Cross Reference: /src/sys/arch/arm/cortex

History log of /src/sys/arch/arm/cortex
Revision	Date	Author	Comments
1.59	18-May-2019	skrll	Convert remaining armv7 kernels to generic start and remove a bunch of code including a9_mpsubr.S. Thanks to Lwazi Dube for testing PANDABOARD and BEAGLEBONE.
1.58	21-Sep-2018	skrll	Centralise defparam CONSADDR, CONSPEED, CONMODE and CONADDR into opt_console.h and adjust.
1.57	27-Jun-2018	ryo	branches: 1.57.2; on evbarm/RPI,RPI2, VERBOSE_INIT_ARM had broken. XPUTC() of evbarm/rpi/rpi_start.S uses bcm283[567]_platform_early_putchar() and it requires stack. fixed to allocate stack when starting from rpi_start.S and a9_mpsubr.S if needed. to work XPUTC(), need to define VERBOSE_INIT_ARM and EARLYCONS option.
1.56	27-Jun-2018	ryo	keep stack pointer even if chainging CPU mode.
1.55	18-Jan-2018	skrll	branches: 1.55.2; Use r0 in the tlbiall instruction to avoid confusion. From Ramakrishna Rao Desetti
1.54	10-Dec-2017	skrll	FDTise RapberryPI support. Thanks for jmcneill for a lot of help with this. The kernel image that the RPI firmware boots is now netbsd.img in the kernel build directory. XXX fdtbus_get_reg needs reworking
1.53	10-Nov-2017	matt	Add #define CPU_CORTEDVIRT to reduce copied complex ifdef. Shrink HYP test
1.52	04-Nov-2017	skrll	Ensure CNTVOFF is 0 before dropping out of Hyp mode CVS ----------------------------------------------------------------------
1.51	22-Sep-2017	skrll	Typo
1.50	06-Sep-2017	jmcneill	Clear TEX Remap Enable in SCTLR. U-Boot with CONFIG_ARMV8_SWITCH_TO_EL1 sets it since it is RES1 when TTBCR.EAE=1, but we are still using the short descriptor format and don't currently support TEX remap. ok skrll@
1.49	24-Jul-2017	joerg	Replace assembler flags with .arch* annotation.
1.48	05-Jul-2017	skrll	Make fp 0 on entry to idle_stack to ensure we mark that we're top of stack
1.47	04-Oct-2016	kiyohara	branches: 1.47.8; Don't touch ACTLR on CORTEX A9, if ACTLR.SMP=1. like Linux. Tested on Gumstix DuoVero(OMAP 4430).
1.46	19-Dec-2015	skrll	branches: 1.46.2; Deal with kernel builds where virtualisation isn't available
1.45	17-Dec-2015	skrll	Check for hypervisor mode in cortex_init and exit if the cpu started there. Needed by latest RPI firmware.
1.44	25-Nov-2015	skrll	G/C TEGRAK1_PMAP_WORKAROUND. Using XN (eXecute Never) properly means speculative reads from devices aren't done. Pretty sure this was the cause of the wedges.
1.43	15-Oct-2015	skrll	Setting actlr.bit15=1 (Force in order issue in the branch execution unit) makes my jetson tk1 stable. Apply this workaround until we figure out what the real problem is.
1.42	09-Jun-2015	skrll	Use TTBR_[UM]PATTR in a9_mpsubr.S as well as cpufunc_asm_armv7 Prompted by matt@
1.41	31-May-2015	matt	Add CALL macro to hide ugliness of calling when KERNEL_BASE_VOFFSET is non-0
1.40	30-May-2015	matt	Call armv7_dcache_l1inv_all in mpstart Make sure ACTRL<31> is set on A15 with 3+ cores.
1.39	28-May-2015	matt	A15 change for > 2 cores.
1.38	17-May-2015	matt	Add a missing defined(CORTEX_A15)
1.37	15-May-2015	skrll	Make sure TLB is invalidated and ACTLR.SMP is set on ARM A15. ACTLR.SMP enables the processor to receive instruction cache, BTB and TLB main- tenance operations from other processors
1.36	03-May-2015	matt	On secondary cores, invalidate the caches to make them clean.
1.35	27-Apr-2015	skrll	Remove unused label
1.34	27-Apr-2015	skrll	ARM spells the System Control Register SCTLR
1.33	26-Apr-2015	jmcneill	isb between TTBCR write and TLBIALL
1.32	20-Apr-2015	jmcneill	Restore "#if !defined(CPU_CORTEXA5)" accidentally removed in previous commit -- hi skrll@
1.31	18-Apr-2015	skrll	Use character constants instead of ascii values for readability
1.30	04-Mar-2015	skrll	Spin up the non-boot CPUs, but don't allow cpu_boot_secondary_processors to see them for now. RPI2 nows works well with only the boot cpu.
1.29	27-Feb-2015	jmcneill	skip a TLBIALL on Cortex-A5 that stops my odroid-c1 from booting, ok matt
1.28	07-Feb-2015	jmcneill	According to the Cortex-A5 TRM, the CBAR register is not implemented and always reads as 0x00000000. Add ARM_CBAR option to set this in kernel config.
1.27	07-Feb-2015	jmcneill	make sure we set ACTLR.SMP=1 for CPU_CORTEXA5 in !MP case, ok matt@
1.26	02-Dec-2014	matt	Fix CORTEXA17 support
1.25	02-Dec-2014	matt	Add Cortex-A17 support
1.24	25-Sep-2014	ryo	branches: 1.24.2; Always set CORTEXA9_AUXCTL_SMP on the CortexA9 as well as A7
1.23	16-Sep-2014	matt	Always set SMP on the A7 since it's needed for ldrex/strex
1.22	16-Sep-2014	matt	Enable L2 prefetch on A9 if MP
1.21	15-Sep-2014	skrll	Don't set CORTEXA9_AUXCTL_FW on A7. It's undefined. Misc. cleanup while I'm here.
1.20	15-Sep-2014	ryo	fix to invalidate all way of own processor
1.19	15-Sep-2014	matt	Make sure to read SCTRL no matter way CPU we are on.
1.18	21-May-2014	ozaki-r	branches: 1.18.2; Fix wrong instruction; mrc => mcr
1.17	11-Apr-2014	matt	whitespace cleanup
1.16	11-Apr-2014	matt	Simplify calls into .text by using KERNEL_BASE_VOFFSET.
1.15	10-Apr-2014	skrll	Fix a typo - it's "#define". Use defined(foo) rather than just foo in preprocessor conditional. ok matt@
1.14	30-Mar-2014	matt	branches: 1.14.2; Improve MP startup code. We now use a two stage startup, after creating the initial L1PT and turning on the MMU/caches, we spinup the secondary CPUs waiting for them to get the same state as the boot processor. Once the real L1PT is initialized and used, the secondary CPUs are kicked so they can use it (and the initial L1PT is discarded). Finally, wait until NetBSD kicks the secondary CPUs then load the stack from the idlelwp and then hatch the cpu and then jump to idle_loop.
1.13	21-Feb-2014	matt	Rework PIC method to be simplier. Change be more cortex neutral.
1.12	24-Jan-2014	matt	branches: 1.12.2; Deal with writing bswapped com registers at COM_MULT register widths.
1.11	26-Dec-2013	joerg	dsb is preferred for post-armv7 CPUs.
1.10	12-Nov-2013	matt	Deal with ARM32_DISABLE_ALIGNMENT_FAULTS
1.9	07-Sep-2013	matt	Remove brain fart with TTBCR
1.8	05-Aug-2013	matt	Turn on CPU_CONTROL_EX_BEND for big endian in exceptions, not CPU_CONTROL_BEND_ENABLE.
1.7	04-Aug-2013	matt	Make sure CPU_CONTROL_BEND_ENABLE is set on BE systems.
1.6	20-Jun-2013	matt	branches: 1.6.2; Set caching bits on the TTBR for ARMv7 Make sure TTCR is 0
1.5	17-Jun-2013	matt	Make this a little more generic. Make sure to turn on branch prediction.
1.4	28-Nov-2012	matt	Make these compile with gcc4.1 and binutils 2.16
1.3	05-Sep-2012	matt	branches: 1.3.2; 1.3.4; 1.3.6; Force TTBCR to 0
1.2	02-Sep-2012	matt	Cleanup and bring forwards from bcm53xx_start.S Use more symbolic names ...
1.1	01-Sep-2012	matt	Add Cortex-A9 support including the ARM Generic Interrupt Controller and the A9 Global Timer / Watchdog.
1.3.6.3	12-Mar-2013	matt	Busy wait in a WFI loop until told to exit.
1.3.6.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.3.6.1	05-Sep-2012	matt	file a9_mpsubr.S was added on branch matt-nb6-plus on 2012-11-28 22:40:25 +0000
1.3.4.4	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.3.4.3	16-Jan-2013	yamt	sync with (a bit old) head
1.3.4.2	30-Oct-2012	yamt	sync with head
1.3.4.1	05-Sep-2012	yamt	file a9_mpsubr.S was added on branch yamt-pagecache on 2012-10-30 17:19:00 +0000
1.3.2.4	03-Dec-2017	jdolecek	update from HEAD
1.3.2.3	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.3.2.2	23-Jun-2013	tls	resync from head
1.3.2.1	25-Feb-2013	tls	resync with head
1.6.2.2	18-May-2014	rmind	sync with head
1.6.2.1	28-Aug-2013	rmind	sync with head
1.12.2.6	27-Mar-2014	matt	Don't = since that isn't BE8 friendly
1.12.2.5	26-Mar-2014	matt	flush the icache after enabling the SCU
1.12.2.4	24-Mar-2014	matt	Allow A7 to use this.
1.12.2.3	20-Feb-2014	matt	Use right register when setting ttbr
1.12.2.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.12.2.1	24-Jan-2014	matt	file a9_mpsubr.S was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.14.2.1	10-Aug-2014	tls	Rebase.
1.18.2.6	03-Dec-2017	snj	Pull up following revision(s) (requested by skrll in ticket #1524): sys/arch/arm/cortex/a9_mpsubr.S: revision 1.52 Ensure CNTVOFF is 0 before dropping out of Hyp mode
1.18.2.5	08-Jul-2017	snj	Pull up following revision(s) (requested by skrll in ticket #1444): sys/arch/arm/cortex/a9_mpsubr.S: revision 1.48 Make fp 0 on entry to idle_stack to ensure we mark that we're top of stack
1.18.2.4	26-Feb-2016	snj	Pull up following revision(s) (requested by skrll in ticket #1107): external/broadcom/rpi-firmware/dist/LICENCE.broadcom: revision 1.2 external/broadcom/rpi-firmware/dist/bootcode.bin: revision 1.8 external/broadcom/rpi-firmware/dist/fixup.dat: revision 1.8 external/broadcom/rpi-firmware/dist/fixup_cd.dat: revision 1.8 external/broadcom/rpi-firmware/dist/start.elf: revision 1.8 external/broadcom/rpi-firmware/dist/start_cd.elf: revision 1.8 sys/arch/arm/broadcom/bcm2835_emmc.c: revision 1.29 sys/arch/arm/broadcom/bcm2835_gpio.c: revision 1.3 sys/arch/arm/broadcom/bcm2835_gpio_subr.c: revision 1.4 sys/arch/arm/broadcom/bcm2835_space.c: revision 1.9, 1.10 sys/arch/arm/broadcom/bcm2835reg.h: patch sys/arch/arm/cortex/a9_mpsubr.S: revisions 1.45, 1.46 sys/arch/evbarm/conf/CUBIEBOARD: revision 1.45 sys/arch/evbarm/conf/std.awin: revision 1.9 sys/arch/evbarm/rpi/rpi2_start.S: revision 1.3 sys/arch/evbarm/rpi/rpi_machdep.c: revision 1.68 Check for hypervisor mode in cortex_init and exit if the cpu started there. Needed by latest RPI firmware. -- Fix up bus_space_map for latest RPI firmware which now passes the FB address in the mailbox properties as a bus address. -- Update RPI firmware to version after the following commit commit 224c75602b8bae1a9e942b4f1c7ed3aa8e0f0ec8 Author: popcornmix<popcornmix@gmail.com> Date: Tue Dec 8 14:48:57 2015 +0000 -- Deal with kernel builds where virtualisation isn't available -- Tweak CPUFLAGS to cover all CPUs -- Fix up bcm283[56] bus_space(4) to really use bus addresses for peripherals, etc Simplifies the code in various places and uses the abstraction in more places. (bcm2835_gpio_subr.c still doesn't)
1.18.2.3	21-Mar-2015	snj	Pull up following revision(s) (requested by jmcneill in ticket #598): sys/arch/arm/amlogic/amlogic_board.c: up to revision 1.9 sys/arch/arm/amlogic/amlogic_canvasreg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_com.c: up to revision 1.4 sys/arch/arm/amlogic/amlogic_comreg.h: up to revision 1.3 sys/arch/arm/amlogic/amlogic_comvar.h: revision 1.1 sys/arch/arm/amlogic/amlogic_cpufreq.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_crureg.h: up to revision 1.7 sys/arch/arm/amlogic/amlogic_dwctwo.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_genfb.c: revision 1.1 sys/arch/arm/amlogic/amlogic_gmac.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_hdmireg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_intr.h: up to revision 1.5 sys/arch/arm/amlogic/amlogic_io.c: up to revision 1.7 sys/arch/arm/amlogic/amlogic_reg.h: up to revision 1.9 sys/arch/arm/amlogic/amlogic_rng.c: revision 1.1 sys/arch/arm/amlogic/amlogic_sdhc.c: up to revision 1.3 sys/arch/arm/amlogic/amlogic_sdhcreg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_space.c: revision 1.1 sys/arch/arm/amlogic/amlogic_var.h: up to revision 1.8 sys/arch/arm/amlogic/amlogic_vpureg.h: revision 1.1 sys/arch/arm/arm/bootconfig.c: revisions 1.7-1.8 sys/arch/arm/conf/files.arm: revision 1.129 sys/arch/arm/cortex/pl310.c: revisions 1.16-1.17 sys/arch/arm/cortex/a9_mpsubr.S: revisions 1.25-1.29 sys/arch/arm/cortex/a9tmr.c: revisions 1.8-1.12 sys/arch/arm/cortex/a9tmr_var.h: revision 1.4 sys/arch/arm/cortex/a9wdt.c: revisions 1.3-1.4 sys/arch/arm/cortex/armperiph.c: revisions 1.5-1.7 sys/arch/arm/arm/cpufunc.c: revision 1.151 sys/arch/arm/include/bootconfig.h: revision 1.7 sys/arch/arm/include/locore.h: revision 1.19 sys/arch/evbarm/amlogic/amlogic_machdep.c: up to revision 1.17 sys/arch/evbarm/amlogic/amlogic_start.S: up to revision 1.2 sys/arch/evbarm/amlogic/genassym.cf: revision 1.1 sys/arch/evbarm/amlogic/platform.h: revision 1.1 sys/arch/evbarm/conf/files.amlogic: up to revision 1.8 sys/arch/evbarm/conf/std.amlogic: up to revision 1.2 sys/arch/evbarm/conf/mk.amlogic: revision 1.1 sys/arch/evbarm/conf/ODROID-C1: up to revision 1.12 sys/arch/evarm/conf/ODROID-C1_INSTALL: revision 1.1 Don't use not as a variable since it's reserved in C++. -- clean the a9 l2 cache before turning it on. -- Add Cortex-A17 support -- Fix CORTEXA17 support -- Let the "cbar" device property override the cbar value, to work around broken bootloaders -- add a helper to update a9tmr frequency -- detach and re-attach timecounter when updating freq, and reinit timer on each cpu -- fix typo -- add BOOTOPT_TYPE_MACADDR for parsing mac address parameters -- make sure we set ACTLR.SMP=1 for CPU_CORTEXA5 in !MP case, ok matt@ -- According to the Cortex-A5 TRM, the CBAR register is not implemented and always reads as 0x00000000. Add ARM_CBAR option to set this in kernel config. -- skip a TLBIALL on Cortex-A5 that stops my odroid-c1 from booting, ok matt -- match on Cortex-A5 -- match on Cortex-A5 -- allow arml2cc to be used on Cortex-A5 if the "offset" property is specified -- print "A5" instead of "A9" at attach time if running on a Cortex-A5 -- Improve inline asm around dsb/dmb/isb: - always use volatile and mark them as memory barrier - use the common version from locore.h in all places not included from userland -- Work-in-progress Odroid-C1 support. -- no need to override ARM_CBAR, remove unused COM_16750 option -- Add basic serial console support. -- add dwctwo and usb devices -- ODROID-C1 SMP support. -- auto-detect RAM size -- ODROID-C1 onboard ethernet support. -- add amlogicrng, add commented-out genfb placeholder -- enable amlogicsdhc -- add ODROID-C1 install kernel -- Add CPUFREQ option to set boot CPU frequency. ODROID-C1 is advertised as quad-core 1.5GHz but boots up at 1.2GHz; add CPUFREQ=1512 to config and make sure to set the correct speed before attaching CPUs. The speed can still be scaled down with machdep.cpu sysctls. -- disable DEBUG, LOCKDEBUG, VERBOSE_INIT_ARM -- Basic framebuffer console support. Work in progress.
1.18.2.2	11-Mar-2015	snj	Pull up following revision(s) (requested by skrll in ticket #582): distrib/utils/embedded/conf/rpi.conf: revision 1.27 etc/etc.evbarm/Makefile.inc: revision 1.70 sys/arch/arm/broadcom/bcm2835_intr.c: revision 1.5-1.7 sys/arch/arm/broadcom/bcm2835_obio.c: revision 1.23, 1.24 sys/arch/arm/broadcom/bcm2835_space.c: revision 1.8 sys/arch/arm/broadcom/bcm2835reg.h: revision 1.14 sys/arch/arm/broadcom/bcm2835var.h: revision 1.2 sys/arch/arm/broadcom/files.bcm2835: revision 1.24 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.30 sys/arch/arm/cortex/armperiph.c: revision 1.8, 1.9 sys/arch/arm/cortex/gtmr.c: revision 1.9 sys/arch/arm/cortex/gtmr_var.h: revision 1.5 sys/arch/arm/cortex/mpcore_var.h: revision 1.3 sys/arch/arm/include/cpu.h: revision 1.84 sys/arch/evbarm/conf/RPI2: revision 1.1, 1.2 sys/arch/evbarm/conf/RPI2_INSTALL: revision 1.1 sys/arch/evbarm/conf/RPI: revision 1.59, 1.60 sys/arch/evbarm/conf/mk.rpi: revision 1.4 sys/arch/evbarm/conf/std.rpi: revisions 1.16-1.19 via patch sys/arch/evbarm/rpi/genassym.cf: revision 1.2 sys/arch/evbarm/rpi/rpi.h: revision 1.4 sys/arch/evbarm/rpi/rpi2_start.S: revision 1.1 sys/arch/evbarm/rpi/rpi_machdep.c: revision 1.57, 1.58 via patch sys/arch/evbarm/rpi/rpi_start.S: revision 1.13 Move some options into std.rpi -- Add __HAVE_MM_MD_CACHE_ALIASING Pull up following revision(s) (requested by skrll in ticket #582): Fix TPIDRPRW_IS_CURLWP builds. -- A MULTIPROCESSOR kernel requires TPIDRPRW_IS_CURCPU. -- Use TPIDRPRW_IS_CURLWP as it's a slight code reduction and performance improvement. Initial RPI2 support - it doesn't work yet. The generic timer gets messed up somehow. This commit changes the KVA layout of the RPI. -- Make this compile where gtmr isn't used. -- Spin up the non-boot CPUs, but don't allow cpu_boot_secondary_processors to see them for now. RPI2 nows works well with only the boot cpu. -- Appease a KASSERT - will be remove when MULTIPROCESSOR RPI2 is fixed. -- Add RPI2 to kernels build for both earmv[67]. Use the earmv6 built kernels to create an image that can be used on both RPI and RPI2 -- Add an RPI2_INSTALL
1.18.2.1	09-Nov-2014	martin	Pull up following revision(s) (requested by skrll in ticket #188): sys/arch/arm/include/arm32/pmap.h: revision 1.136 sys/arch/arm/include/armreg.h: revision 1.100 sys/arch/arm/cortex/gic.c: revision 1.11 sys/arch/arm/arm32/db_interface.c: revision 1.54 sys/arch/arm/include/armreg.h: revision 1.101 sys/arch/arm/cortex/gic.c: revision 1.12 sys/arch/arm/arm32/arm32_machdep.c: revision 1.107 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.19 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.20 sys/arch/evbarm/conf/BPI: revision 1.5 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.21 sys/arch/arm/arm32/pmap.c: revision 1.306 sys/arch/arm/arm32/db_machdep.c: revision 1.22 sys/arch/arm/arm32/arm32_tlb.c: revision 1.3 sys/arch/arm/arm/undefined.c: revision 1.55 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.22 sys/arch/arm/arm32/pmap.c: revision 1.307 sys/arch/arm/arm32/arm32_tlb.c: revision 1.4 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.23 sys/arch/arm/arm32/arm32_tlb.c: revision 1.5 sys/arch/evbarm/conf/BPI: revision 1.8 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.24 sys/arch/arm/arm32/arm32_tlb.c: revision 1.6 sys/arch/arm/arm32/arm32_tlb.c: revision 1.7 sys/arch/evbarm/conf/CUBIETRUCK: revision 1.5 sys/arch/arm/pic/pic.c: revision 1.23 sys/arch/arm/pic/pic.c: revision 1.24 sys/arch/arm/pic/picvar.h: revision 1.11 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.20 sys/arch/arm/mainbus/cpu_mainbus.c: revision 1.16 sys/arch/arm/arm32/pmap.c: revision 1.298 sys/arch/arm/arm/cpufunc_asm_arm11.S: revision 1.17 sys/arch/arm/arm/cpufunc_asm_pj4b.S: revision 1.5 sys/arch/arm/arm32/pmap.c: revision 1.310 sys/arch/arm/arm32/pmap.c: revision 1.311 sys/arch/arm/arm32/arm32_kvminit.c: revision 1.32 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.19 sys/arch/arm/arm32/arm32_boot.c: revision 1.10 sys/arch/arm/arm/ast.c: revision 1.25 sys/arch/arm/include/armreg.h: revision 1.98 sys/uvm/pmap/pmap_tlb.c: revision 1.10 sys/arch/arm/arm32/arm32_boot.c: revision 1.8 sys/arch/arm/arm32/arm32_boot.c: revision 1.9 sys/arch/arm/arm/arm_machdep.c: revision 1.43 Various ARM MP fixes.
1.24.2.6	28-Aug-2017	skrll	Sync with HEAD
1.24.2.5	05-Dec-2016	skrll	Sync with HEAD
1.24.2.4	27-Dec-2015	skrll	Sync with HEAD (as of 26th Dec)
1.24.2.3	22-Sep-2015	skrll	Sync with HEAD
1.24.2.2	06-Jun-2015	skrll	Sync with HEAD
1.24.2.1	06-Apr-2015	skrll	Sync with HEAD
1.46.2.1	04-Nov-2016	pgoyette	Sync with HEAD
1.47.8.3	31-Jul-2023	martin	Pull up following revision(s) (requested by riastradh in ticket #1859): sys/arch/ia64/ia64/vm_machdep.c: revision 1.18 sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67 sys/arch/aarch64/aarch64/locore.S: revision 1.91 sys/arch/mips/include/asm.h: revision 1.74 sys/arch/hppa/include/cpu.h: revision 1.13 sys/arch/arm/arm/armv6_start.S: revision 1.38 (applied also to sys/arch/arm/cortex/a9_mpsubr.S, sys/arch/arm/cortex/a9_mpsubr.S, sys/arch/arm/cortex/cortex_init.S) sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2 sys/arch/mips/mips/locore.S: revision 1.229 sys/arch/alpha/include/asm.h: revision 1.45 (applied to sys/arch/alpha/alpha/multiproc.s) sys/arch/sparc64/sparc64/locore.s: revision 1.432 sys/arch/vax/vax/subr.S: revision 1.42 sys/arch/mips/mips/locore_mips3.S: revision 1.116 sys/arch/ia64/ia64/machdep.c: revision 1.44 sys/arch/arm/arm32/cpuswitch.S: revision 1.106 sys/arch/sparc/sparc/locore.s: revision 1.284 (all via patch) aarch64: Add missing barriers in cpu_switchto. Details in comments. Note: This is a conservative change that inserts a barrier where there was a comment saying none is needed, which is probably correct. The goal of this change is to systematically add barriers to be confident in correctness; subsequent changes may remove some bariers, as an optimization, with an explanation of why each barrier is not needed. PR kern/57240 alpha: Add missing barriers in cpu_switchto. Details in comments. arm32: Add missing barriers in cpu_switchto. Details in comments. hppa: Add missing barriers in cpu_switchto. Not sure hppa has ever had working MULTIPROCESSOR, so maybe no pullups needed? ia64: Add missing barriers in cpu_switchto. (ia64 has never really worked, so no pullups needed, right?) mips: Add missing barriers in cpu_switchto. Details in comments. powerpc: Add missing barriers in cpu_switchto. Details in comments. sparc: Add missing barriers in cpu_switchto. sparc64: Add missing barriers in cpu_switchto. Details in comments. vax: Note where cpu_switchto needs barriers. Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not even sure how to spell store-before-load barriers on VAX, so no functional change for now.
1.47.8.2	17-Nov-2017	martin	Pull up following revision(s) (requested by skrll in ticket #351): sys/arch/arm/cortex/a9_mpsubr.S: revision 1.52 Ensure CNTVOFF is 0 before dropping out of Hyp mode
1.47.8.1	06-Jul-2017	martin	branches: 1.47.8.1.2; Pull up following revision(s) (requested by skrll in ticket #99): sys/arch/arm/cortex/a9_mpsubr.S: revision 1.48 Make fp 0 on entry to idle_stack to ensure we mark that we're top of stack
1.47.8.1.2.1	13-Dec-2017	matt	Add Cortex-A35 and make VIRT support simplier
1.55.2.2	30-Sep-2018	pgoyette	Ssync with HEAD
1.55.2.1	28-Jul-2018	pgoyette	Sync with HEAD
1.57.2.1	10-Jun-2019	christos	Sync with HEAD
1.3	05-Nov-2022	jmcneill	Handle speed change events
1.2	14-Aug-2019	skrll	branches: 1.2.2; 1.2.10; Various fixes / changes - don't use prescaler - improve AB_DEBUG output - fix a9ptmr_delay to work with a decrementing counter! Thanks to jmcneill@ for proving I'm an idiot
1.1	10-Aug-2019	skrll	Add a driver for the A5/A9 Private timer. While here FDTise the Watchdog driver.
1.2.10.2	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.2.10.1	14-Aug-2019	martin	file a9ptmr.c was added on branch phil-wifi on 2020-04-13 08:03:33 +0000
1.2.2.2	15-Aug-2019	martin	Pull up following revision(s) (requested by skrll in ticket #55): sys/arch/arm/cortex/a9wdt.c: revision 1.10 sys/arch/evbarm/conf/HUMMINGBOARD: revision 1.9 sys/arch/evbarm/conf/GENERIC: revision 1.50 sys/arch/evbarm/conf/NITROGEN6X: revision 1.24 sys/arch/arm/cortex/a9tmr_var.h: revision 1.7 sys/arch/arm/fdt/files.fdt: revision 1.29 sys/arch/arm/amlogic/meson_platform.c: revision 1.12 sys/arch/arm/amlogic/meson8b_pinctrl.c: revision 1.2 sys/arch/arm/amlogic/meson_platform.c: revision 1.13 sys/arch/evbarm/conf/BCM5301X: revision 1.34 sys/arch/arm/dts/meson8b.dtsi: revision 1.6 sys/arch/arm/fdt/a9ptmr_fdt.c: revision 1.1 sys/arch/arm/dts/meson8b.dtsi: revision 1.7 sys/arch/arm/cortex/a9ptmr_var.h: revision 1.1 sys/arch/evbarm/conf/PANDABOARD: revision 1.30 sys/arch/evbarm/conf/DUOVERO: revision 1.14 sys/arch/arm/cortex/a9ptmr.c: revision 1.1 sys/arch/arm/cortex/a9ptmr.c: revision 1.2 sys/arch/arm/fdt/a9wdt_fdt.c: revision 1.1 sys/arch/evbarm/conf/BCM56340: revision 1.19 sys/arch/evbarm/conf/CUBOX-I: revision 1.23 sys/arch/arm/amlogic/meson8b_clkc.c: revision 1.4 sys/arch/evbarm/conf/PARALLELLA: revision 1.7 sys/arch/arm/cortex/files.cortex: revision 1.12 sys/arch/arm/dts/meson8b-odroidc1.dts: revision 1.4 sys/arch/arm/cortex/a9wdt.c: revision 1.9 sys/arch/evbarm/conf/ZEDBOARD: revision 1.6 spaces to tab - Add a driver for the A5/A9 Private timer. While here FDTise the Watchdog driver. - Update for recent a9wdt changes - Trailing whitespace - Updates to get Odroid-C1 in better shape since the last DTS import - Various fixes / changes - don't use prescaler - improve AB_DEBUG output - fix a9ptmr_delay to work with a decrementing counter! Thanks to jmcneill@ for proving I'm an idiot - Add eth_rxd3 and eth_rxd2 pinctrl groups - Catch up to recent mainline dts changes
1.2.2.1	14-Aug-2019	martin	file a9ptmr.c was added on branch netbsd-9 on 2019-08-15 09:49:49 +0000
1.2	05-Nov-2022	jmcneill	Handle speed change events
1.1	10-Aug-2019	skrll	branches: 1.1.2; 1.1.10; Add a driver for the A5/A9 Private timer. While here FDTise the Watchdog driver.
1.1.10.2	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.1.10.1	10-Aug-2019	martin	file a9ptmr_var.h was added on branch phil-wifi on 2020-04-13 08:03:33 +0000
1.1.2.2	15-Aug-2019	martin	Pull up following revision(s) (requested by skrll in ticket #55): sys/arch/arm/cortex/a9wdt.c: revision 1.10 sys/arch/evbarm/conf/HUMMINGBOARD: revision 1.9 sys/arch/evbarm/conf/GENERIC: revision 1.50 sys/arch/evbarm/conf/NITROGEN6X: revision 1.24 sys/arch/arm/cortex/a9tmr_var.h: revision 1.7 sys/arch/arm/fdt/files.fdt: revision 1.29 sys/arch/arm/amlogic/meson_platform.c: revision 1.12 sys/arch/arm/amlogic/meson8b_pinctrl.c: revision 1.2 sys/arch/arm/amlogic/meson_platform.c: revision 1.13 sys/arch/evbarm/conf/BCM5301X: revision 1.34 sys/arch/arm/dts/meson8b.dtsi: revision 1.6 sys/arch/arm/fdt/a9ptmr_fdt.c: revision 1.1 sys/arch/arm/dts/meson8b.dtsi: revision 1.7 sys/arch/arm/cortex/a9ptmr_var.h: revision 1.1 sys/arch/evbarm/conf/PANDABOARD: revision 1.30 sys/arch/evbarm/conf/DUOVERO: revision 1.14 sys/arch/arm/cortex/a9ptmr.c: revision 1.1 sys/arch/arm/cortex/a9ptmr.c: revision 1.2 sys/arch/arm/fdt/a9wdt_fdt.c: revision 1.1 sys/arch/evbarm/conf/BCM56340: revision 1.19 sys/arch/evbarm/conf/CUBOX-I: revision 1.23 sys/arch/arm/amlogic/meson8b_clkc.c: revision 1.4 sys/arch/evbarm/conf/PARALLELLA: revision 1.7 sys/arch/arm/cortex/files.cortex: revision 1.12 sys/arch/arm/dts/meson8b-odroidc1.dts: revision 1.4 sys/arch/arm/cortex/a9wdt.c: revision 1.9 sys/arch/evbarm/conf/ZEDBOARD: revision 1.6 spaces to tab - Add a driver for the A5/A9 Private timer. While here FDTise the Watchdog driver. - Update for recent a9wdt changes - Trailing whitespace - Updates to get Odroid-C1 in better shape since the last DTS import - Various fixes / changes - don't use prescaler - improve AB_DEBUG output - fix a9ptmr_delay to work with a decrementing counter! Thanks to jmcneill@ for proving I'm an idiot - Add eth_rxd3 and eth_rxd2 pinctrl groups - Catch up to recent mainline dts changes
1.1.2.1	10-Aug-2019	martin	file a9ptmr_var.h was added on branch netbsd-9 on 2019-08-15 09:49:49 +0000
1.22	03-Mar-2022	riastradh	arm: Use device_set_private for various drivers.
1.21	02-Dec-2020	wiz	comparision -> comparison
1.20	11-Jun-2019	skrll	branches: 1.20.10; Trailing whitespace
1.19	22-Nov-2018	aymeric	Switch the DE0 Nano SoC to the GENERIC kernel.
1.18	28-Oct-2018	aymeric	Enable the global timer at attach time, it ensures that delay() works.
1.17	14-Oct-2018	aymeric	Remove comment that the peripherals clock should be half of the cpu clock. NFC
1.16	20-Jun-2018	hkenken	branches: 1.16.2; Use mpcaa_off1 parameter for mapping subregion.
1.15	05-Jun-2018	hkenken	Rename ARM A9 Global Timer driver name to support fdt. - Rename a9tmr to arma9tmr. - Add a9tmr_fdt.c based gtmr_fdt.c.
1.14	24-Jul-2015	ryo	branches: 1.14.16; KNF
1.13	24-Jul-2015	ryo	- fix sc_ev_missing_ticks over-counting. - don't use 64bit division, because it has expensive cost on gcc/arm whether it is a constant or not. 'delta' is usually taken a value around sc_autoinc depending on timing of read. therefore 'delta / sc->sc_autoinc' would be count too much.
1.12	04-Mar-2015	jmcneill	print "A5" instead of "A9" at attach time if running on a Cortex-A5
1.11	27-Feb-2015	jmcneill	match on Cortex-A5
1.10	08-Jan-2015	hkenken	fix typo
1.9	02-Jan-2015	jmcneill	detach and re-attach timecounter when updating freq, and reinit timer on each cpu
1.8	02-Jan-2015	jmcneill	add a helper to update a9tmr frequency
1.7	28-Mar-2014	matt	branches: 1.7.4; 1.7.6; Mark interrupt as MPSAFE.
1.6	20-Jun-2013	matt	branches: 1.6.2; 1.6.6; Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args. Modify the list of devices to include the offset(s) from PERIPHBASE.
1.5	12-Jun-2013	matt	Don't attach a9tmr if the CPU supports the generic timer.
1.4	29-Nov-2012	matt	Make sure we enable the timer since CFE doesn't enable it by default.
1.3	27-Sep-2012	matt	branches: 1.3.2; 1.3.4; Don't bother dealing with "extra" ticks, just count them.
1.2	14-Sep-2012	matt	Set dv_private, use a9tmr_private.
1.1	01-Sep-2012	matt	branches: 1.1.2; Add Cortex-A9 support including the ARM Generic Interrupt Controller and the A9 Global Timer / Watchdog.
1.1.2.5	03-Dec-2017	jdolecek	update from HEAD
1.1.2.4	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.1.2.3	23-Jun-2013	tls	resync from head
1.1.2.2	25-Feb-2013	tls	resync with head
1.1.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.3.4.3	29-Nov-2012	matt	Sync with HEAD.
1.3.4.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.3.4.1	27-Sep-2012	matt	file a9tmr.c was added on branch matt-nb6-plus on 2012-11-28 22:40:25 +0000
1.3.2.4	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.3.2.3	16-Jan-2013	yamt	sync with (a bit old) head
1.3.2.2	30-Oct-2012	yamt	sync with head
1.3.2.1	27-Sep-2012	yamt	file a9tmr.c was added on branch yamt-pagecache on 2012-10-30 17:19:00 +0000
1.6.6.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.6.6.1	20-Jun-2013	matt	file a9tmr.c was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.6.2.1	18-May-2014	rmind	sync with head
1.7.6.2	22-Sep-2015	skrll	Sync with HEAD
1.7.6.1	06-Apr-2015	skrll	Sync with HEAD
1.7.4.1	21-Mar-2015	snj	Pull up following revision(s) (requested by jmcneill in ticket #598): sys/arch/arm/amlogic/amlogic_board.c: up to revision 1.9 sys/arch/arm/amlogic/amlogic_canvasreg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_com.c: up to revision 1.4 sys/arch/arm/amlogic/amlogic_comreg.h: up to revision 1.3 sys/arch/arm/amlogic/amlogic_comvar.h: revision 1.1 sys/arch/arm/amlogic/amlogic_cpufreq.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_crureg.h: up to revision 1.7 sys/arch/arm/amlogic/amlogic_dwctwo.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_genfb.c: revision 1.1 sys/arch/arm/amlogic/amlogic_gmac.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_hdmireg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_intr.h: up to revision 1.5 sys/arch/arm/amlogic/amlogic_io.c: up to revision 1.7 sys/arch/arm/amlogic/amlogic_reg.h: up to revision 1.9 sys/arch/arm/amlogic/amlogic_rng.c: revision 1.1 sys/arch/arm/amlogic/amlogic_sdhc.c: up to revision 1.3 sys/arch/arm/amlogic/amlogic_sdhcreg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_space.c: revision 1.1 sys/arch/arm/amlogic/amlogic_var.h: up to revision 1.8 sys/arch/arm/amlogic/amlogic_vpureg.h: revision 1.1 sys/arch/arm/arm/bootconfig.c: revisions 1.7-1.8 sys/arch/arm/conf/files.arm: revision 1.129 sys/arch/arm/cortex/pl310.c: revisions 1.16-1.17 sys/arch/arm/cortex/a9_mpsubr.S: revisions 1.25-1.29 sys/arch/arm/cortex/a9tmr.c: revisions 1.8-1.12 sys/arch/arm/cortex/a9tmr_var.h: revision 1.4 sys/arch/arm/cortex/a9wdt.c: revisions 1.3-1.4 sys/arch/arm/cortex/armperiph.c: revisions 1.5-1.7 sys/arch/arm/arm/cpufunc.c: revision 1.151 sys/arch/arm/include/bootconfig.h: revision 1.7 sys/arch/arm/include/locore.h: revision 1.19 sys/arch/evbarm/amlogic/amlogic_machdep.c: up to revision 1.17 sys/arch/evbarm/amlogic/amlogic_start.S: up to revision 1.2 sys/arch/evbarm/amlogic/genassym.cf: revision 1.1 sys/arch/evbarm/amlogic/platform.h: revision 1.1 sys/arch/evbarm/conf/files.amlogic: up to revision 1.8 sys/arch/evbarm/conf/std.amlogic: up to revision 1.2 sys/arch/evbarm/conf/mk.amlogic: revision 1.1 sys/arch/evbarm/conf/ODROID-C1: up to revision 1.12 sys/arch/evarm/conf/ODROID-C1_INSTALL: revision 1.1 Don't use not as a variable since it's reserved in C++. -- clean the a9 l2 cache before turning it on. -- Add Cortex-A17 support -- Fix CORTEXA17 support -- Let the "cbar" device property override the cbar value, to work around broken bootloaders -- add a helper to update a9tmr frequency -- detach and re-attach timecounter when updating freq, and reinit timer on each cpu -- fix typo -- add BOOTOPT_TYPE_MACADDR for parsing mac address parameters -- make sure we set ACTLR.SMP=1 for CPU_CORTEXA5 in !MP case, ok matt@ -- According to the Cortex-A5 TRM, the CBAR register is not implemented and always reads as 0x00000000. Add ARM_CBAR option to set this in kernel config. -- skip a TLBIALL on Cortex-A5 that stops my odroid-c1 from booting, ok matt -- match on Cortex-A5 -- match on Cortex-A5 -- allow arml2cc to be used on Cortex-A5 if the "offset" property is specified -- print "A5" instead of "A9" at attach time if running on a Cortex-A5 -- Improve inline asm around dsb/dmb/isb: - always use volatile and mark them as memory barrier - use the common version from locore.h in all places not included from userland -- Work-in-progress Odroid-C1 support. -- no need to override ARM_CBAR, remove unused COM_16750 option -- Add basic serial console support. -- add dwctwo and usb devices -- ODROID-C1 SMP support. -- auto-detect RAM size -- ODROID-C1 onboard ethernet support. -- add amlogicrng, add commented-out genfb placeholder -- enable amlogicsdhc -- add ODROID-C1 install kernel -- Add CPUFREQ option to set boot CPU frequency. ODROID-C1 is advertised as quad-core 1.5GHz but boots up at 1.2GHz; add CPUFREQ=1512 to config and make sure to set the correct speed before attaching CPUs. The speed can still be scaled down with machdep.cpu sysctls. -- disable DEBUG, LOCKDEBUG, VERBOSE_INIT_ARM -- Basic framebuffer console support. Work in progress.
1.14.16.3	26-Nov-2018	pgoyette	Sync with HEAD, resolve a couple of conflicts
1.14.16.2	20-Oct-2018	pgoyette	Sync with head
1.14.16.1	25-Jun-2018	pgoyette	Sync with HEAD
1.16.2.2	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.16.2.1	10-Jun-2019	christos	Sync with HEAD
1.20.10.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.1	01-Sep-2012	matt	branches: 1.1.4; 1.1.6; 1.1.16; Add Cortex-A9 support including the ARM Generic Interrupt Controller and the A9 Global Timer / Watchdog.
1.1.16.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.1.16.1	01-Sep-2012	matt	file a9tmr_intr.h was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.1.6.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.1.6.1	01-Sep-2012	matt	file a9tmr_intr.h was added on branch matt-nb6-plus on 2012-11-28 22:40:26 +0000
1.1.4.2	30-Oct-2012	yamt	sync with head
1.1.4.1	01-Sep-2012	yamt	file a9tmr_intr.h was added on branch yamt-pagecache on 2012-10-30 17:19:00 +0000
1.3	02-Oct-2021	skrll	Trailing whitespace
1.2	27-Jul-2019	skrll	Rename a register define to make it more obvious it's watchdog only
1.1	01-Sep-2012	matt	branches: 1.1.4; 1.1.6; 1.1.16; 1.1.46; Add Cortex-A9 support including the ARM Generic Interrupt Controller and the A9 Global Timer / Watchdog.
1.1.46.1	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.1.16.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.1.16.1	01-Sep-2012	matt	file a9tmr_reg.h was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.1.6.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.1.6.1	01-Sep-2012	matt	file a9tmr_reg.h was added on branch matt-nb6-plus on 2012-11-28 22:40:26 +0000
1.1.4.2	30-Oct-2012	yamt	sync with head
1.1.4.1	01-Sep-2012	yamt	file a9tmr_reg.h was added on branch yamt-pagecache on 2012-10-30 17:19:00 +0000
1.7	10-Aug-2019	skrll	Add a driver for the A5/A9 Private timer. While here FDTise the Watchdog driver.
1.6	20-Jun-2018	hkenken	branches: 1.6.2; 1.6.6; Use mpcaa_off1 parameter for mapping subregion.
1.5	05-Jun-2018	hkenken	Rename ARM A9 Global Timer driver name to support fdt. - Rename a9tmr to arma9tmr. - Add a9tmr_fdt.c based gtmr_fdt.c.
1.4	02-Jan-2015	jmcneill	branches: 1.4.16; add a helper to update a9tmr frequency
1.3	20-Jun-2013	matt	branches: 1.3.6; 1.3.10; 1.3.12; Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args. Modify the list of devices to include the offset(s) from PERIPHBASE.
1.2	27-Sep-2012	matt	branches: 1.2.2; 1.2.4; Don't bother dealing with "extra" ticks, just count them.
1.1	01-Sep-2012	matt	branches: 1.1.2; Add Cortex-A9 support including the ARM Generic Interrupt Controller and the A9 Global Timer / Watchdog.
1.1.2.3	03-Dec-2017	jdolecek	update from HEAD
1.1.2.2	23-Jun-2013	tls	resync from head
1.1.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.2.4.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.2.4.1	27-Sep-2012	matt	file a9tmr_var.h was added on branch matt-nb6-plus on 2012-11-28 22:40:26 +0000
1.2.2.3	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.2.2.2	30-Oct-2012	yamt	sync with head
1.2.2.1	27-Sep-2012	yamt	file a9tmr_var.h was added on branch yamt-pagecache on 2012-10-30 17:19:00 +0000
1.3.12.1	06-Apr-2015	skrll	Sync with HEAD
1.3.10.1	21-Mar-2015	snj	Pull up following revision(s) (requested by jmcneill in ticket #598): sys/arch/arm/amlogic/amlogic_board.c: up to revision 1.9 sys/arch/arm/amlogic/amlogic_canvasreg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_com.c: up to revision 1.4 sys/arch/arm/amlogic/amlogic_comreg.h: up to revision 1.3 sys/arch/arm/amlogic/amlogic_comvar.h: revision 1.1 sys/arch/arm/amlogic/amlogic_cpufreq.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_crureg.h: up to revision 1.7 sys/arch/arm/amlogic/amlogic_dwctwo.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_genfb.c: revision 1.1 sys/arch/arm/amlogic/amlogic_gmac.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_hdmireg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_intr.h: up to revision 1.5 sys/arch/arm/amlogic/amlogic_io.c: up to revision 1.7 sys/arch/arm/amlogic/amlogic_reg.h: up to revision 1.9 sys/arch/arm/amlogic/amlogic_rng.c: revision 1.1 sys/arch/arm/amlogic/amlogic_sdhc.c: up to revision 1.3 sys/arch/arm/amlogic/amlogic_sdhcreg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_space.c: revision 1.1 sys/arch/arm/amlogic/amlogic_var.h: up to revision 1.8 sys/arch/arm/amlogic/amlogic_vpureg.h: revision 1.1 sys/arch/arm/arm/bootconfig.c: revisions 1.7-1.8 sys/arch/arm/conf/files.arm: revision 1.129 sys/arch/arm/cortex/pl310.c: revisions 1.16-1.17 sys/arch/arm/cortex/a9_mpsubr.S: revisions 1.25-1.29 sys/arch/arm/cortex/a9tmr.c: revisions 1.8-1.12 sys/arch/arm/cortex/a9tmr_var.h: revision 1.4 sys/arch/arm/cortex/a9wdt.c: revisions 1.3-1.4 sys/arch/arm/cortex/armperiph.c: revisions 1.5-1.7 sys/arch/arm/arm/cpufunc.c: revision 1.151 sys/arch/arm/include/bootconfig.h: revision 1.7 sys/arch/arm/include/locore.h: revision 1.19 sys/arch/evbarm/amlogic/amlogic_machdep.c: up to revision 1.17 sys/arch/evbarm/amlogic/amlogic_start.S: up to revision 1.2 sys/arch/evbarm/amlogic/genassym.cf: revision 1.1 sys/arch/evbarm/amlogic/platform.h: revision 1.1 sys/arch/evbarm/conf/files.amlogic: up to revision 1.8 sys/arch/evbarm/conf/std.amlogic: up to revision 1.2 sys/arch/evbarm/conf/mk.amlogic: revision 1.1 sys/arch/evbarm/conf/ODROID-C1: up to revision 1.12 sys/arch/evarm/conf/ODROID-C1_INSTALL: revision 1.1 Don't use not as a variable since it's reserved in C++. -- clean the a9 l2 cache before turning it on. -- Add Cortex-A17 support -- Fix CORTEXA17 support -- Let the "cbar" device property override the cbar value, to work around broken bootloaders -- add a helper to update a9tmr frequency -- detach and re-attach timecounter when updating freq, and reinit timer on each cpu -- fix typo -- add BOOTOPT_TYPE_MACADDR for parsing mac address parameters -- make sure we set ACTLR.SMP=1 for CPU_CORTEXA5 in !MP case, ok matt@ -- According to the Cortex-A5 TRM, the CBAR register is not implemented and always reads as 0x00000000. Add ARM_CBAR option to set this in kernel config. -- skip a TLBIALL on Cortex-A5 that stops my odroid-c1 from booting, ok matt -- match on Cortex-A5 -- match on Cortex-A5 -- allow arml2cc to be used on Cortex-A5 if the "offset" property is specified -- print "A5" instead of "A9" at attach time if running on a Cortex-A5 -- Improve inline asm around dsb/dmb/isb: - always use volatile and mark them as memory barrier - use the common version from locore.h in all places not included from userland -- Work-in-progress Odroid-C1 support. -- no need to override ARM_CBAR, remove unused COM_16750 option -- Add basic serial console support. -- add dwctwo and usb devices -- ODROID-C1 SMP support. -- auto-detect RAM size -- ODROID-C1 onboard ethernet support. -- add amlogicrng, add commented-out genfb placeholder -- enable amlogicsdhc -- add ODROID-C1 install kernel -- Add CPUFREQ option to set boot CPU frequency. ODROID-C1 is advertised as quad-core 1.5GHz but boots up at 1.2GHz; add CPUFREQ=1512 to config and make sure to set the correct speed before attaching CPUs. The speed can still be scaled down with machdep.cpu sysctls. -- disable DEBUG, LOCKDEBUG, VERBOSE_INIT_ARM -- Basic framebuffer console support. Work in progress.
1.3.6.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.3.6.1	20-Jun-2013	matt	file a9tmr_var.h was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.4.16.1	25-Jun-2018	pgoyette	Sync with HEAD
1.6.6.1	15-Aug-2019	martin	Pull up following revision(s) (requested by skrll in ticket #55): sys/arch/arm/cortex/a9wdt.c: revision 1.10 sys/arch/evbarm/conf/HUMMINGBOARD: revision 1.9 sys/arch/evbarm/conf/GENERIC: revision 1.50 sys/arch/evbarm/conf/NITROGEN6X: revision 1.24 sys/arch/arm/cortex/a9tmr_var.h: revision 1.7 sys/arch/arm/fdt/files.fdt: revision 1.29 sys/arch/arm/amlogic/meson_platform.c: revision 1.12 sys/arch/arm/amlogic/meson8b_pinctrl.c: revision 1.2 sys/arch/arm/amlogic/meson_platform.c: revision 1.13 sys/arch/evbarm/conf/BCM5301X: revision 1.34 sys/arch/arm/dts/meson8b.dtsi: revision 1.6 sys/arch/arm/fdt/a9ptmr_fdt.c: revision 1.1 sys/arch/arm/dts/meson8b.dtsi: revision 1.7 sys/arch/arm/cortex/a9ptmr_var.h: revision 1.1 sys/arch/evbarm/conf/PANDABOARD: revision 1.30 sys/arch/evbarm/conf/DUOVERO: revision 1.14 sys/arch/arm/cortex/a9ptmr.c: revision 1.1 sys/arch/arm/cortex/a9ptmr.c: revision 1.2 sys/arch/arm/fdt/a9wdt_fdt.c: revision 1.1 sys/arch/evbarm/conf/BCM56340: revision 1.19 sys/arch/evbarm/conf/CUBOX-I: revision 1.23 sys/arch/arm/amlogic/meson8b_clkc.c: revision 1.4 sys/arch/evbarm/conf/PARALLELLA: revision 1.7 sys/arch/arm/cortex/files.cortex: revision 1.12 sys/arch/arm/dts/meson8b-odroidc1.dts: revision 1.4 sys/arch/arm/cortex/a9wdt.c: revision 1.9 sys/arch/evbarm/conf/ZEDBOARD: revision 1.6 spaces to tab - Add a driver for the A5/A9 Private timer. While here FDTise the Watchdog driver. - Update for recent a9wdt changes - Trailing whitespace - Updates to get Odroid-C1 in better shape since the last DTS import - Various fixes / changes - don't use prescaler - improve AB_DEBUG output - fix a9ptmr_delay to work with a decrementing counter! Thanks to jmcneill@ for proving I'm an idiot - Add eth_rxd3 and eth_rxd2 pinctrl groups - Catch up to recent mainline dts changes
1.6.2.1	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.10	10-Aug-2019	skrll	Add a driver for the A5/A9 Private timer. While here FDTise the Watchdog driver.
1.9	10-Aug-2019	skrll	spaces to tab
1.8	30-Jul-2019	skrll	branches: 1.8.2; Fix loop to calculate prescaler divisor.
1.7	29-Dec-2017	skrll	branches: 1.7.4; Trailing whitespace
1.6	29-Dec-2017	skrll	Set attached to true when attach completes. Reported by Ramakrishna Rao Desetti on port-arm
1.5	04-Oct-2016	kiyohara	Register sysmon_wdog.
1.4	04-Mar-2015	jmcneill	branches: 1.4.2; print "A5" instead of "A9" at attach time if running on a Cortex-A5
1.3	27-Feb-2015	jmcneill	match on Cortex-A5
1.2	13-Apr-2014	matt	branches: 1.2.2; 1.2.4; write correct register.
1.1	01-Sep-2012	matt	branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8; 1.1.16; 1.1.18; Add Cortex-A9 support including the ARM Generic Interrupt Controller and the A9 Global Timer / Watchdog.
1.1.18.1	10-Aug-2014	tls	Rebase.
1.1.16.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.1.16.1	01-Sep-2012	matt	file a9wdt.c was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.1.8.1	18-May-2014	rmind	sync with head
1.1.6.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.1.6.1	01-Sep-2012	matt	file a9wdt.c was added on branch matt-nb6-plus on 2012-11-28 22:40:26 +0000
1.1.4.3	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.1.4.2	30-Oct-2012	yamt	sync with head
1.1.4.1	01-Sep-2012	yamt	file a9wdt.c was added on branch yamt-pagecache on 2012-10-30 17:19:00 +0000
1.1.2.2	03-Dec-2017	jdolecek	update from HEAD
1.1.2.1	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.2.4.2	05-Dec-2016	skrll	Sync with HEAD
1.2.4.1	06-Apr-2015	skrll	Sync with HEAD
1.2.2.1	21-Mar-2015	snj	Pull up following revision(s) (requested by jmcneill in ticket #598): sys/arch/arm/amlogic/amlogic_board.c: up to revision 1.9 sys/arch/arm/amlogic/amlogic_canvasreg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_com.c: up to revision 1.4 sys/arch/arm/amlogic/amlogic_comreg.h: up to revision 1.3 sys/arch/arm/amlogic/amlogic_comvar.h: revision 1.1 sys/arch/arm/amlogic/amlogic_cpufreq.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_crureg.h: up to revision 1.7 sys/arch/arm/amlogic/amlogic_dwctwo.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_genfb.c: revision 1.1 sys/arch/arm/amlogic/amlogic_gmac.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_hdmireg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_intr.h: up to revision 1.5 sys/arch/arm/amlogic/amlogic_io.c: up to revision 1.7 sys/arch/arm/amlogic/amlogic_reg.h: up to revision 1.9 sys/arch/arm/amlogic/amlogic_rng.c: revision 1.1 sys/arch/arm/amlogic/amlogic_sdhc.c: up to revision 1.3 sys/arch/arm/amlogic/amlogic_sdhcreg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_space.c: revision 1.1 sys/arch/arm/amlogic/amlogic_var.h: up to revision 1.8 sys/arch/arm/amlogic/amlogic_vpureg.h: revision 1.1 sys/arch/arm/arm/bootconfig.c: revisions 1.7-1.8 sys/arch/arm/conf/files.arm: revision 1.129 sys/arch/arm/cortex/pl310.c: revisions 1.16-1.17 sys/arch/arm/cortex/a9_mpsubr.S: revisions 1.25-1.29 sys/arch/arm/cortex/a9tmr.c: revisions 1.8-1.12 sys/arch/arm/cortex/a9tmr_var.h: revision 1.4 sys/arch/arm/cortex/a9wdt.c: revisions 1.3-1.4 sys/arch/arm/cortex/armperiph.c: revisions 1.5-1.7 sys/arch/arm/arm/cpufunc.c: revision 1.151 sys/arch/arm/include/bootconfig.h: revision 1.7 sys/arch/arm/include/locore.h: revision 1.19 sys/arch/evbarm/amlogic/amlogic_machdep.c: up to revision 1.17 sys/arch/evbarm/amlogic/amlogic_start.S: up to revision 1.2 sys/arch/evbarm/amlogic/genassym.cf: revision 1.1 sys/arch/evbarm/amlogic/platform.h: revision 1.1 sys/arch/evbarm/conf/files.amlogic: up to revision 1.8 sys/arch/evbarm/conf/std.amlogic: up to revision 1.2 sys/arch/evbarm/conf/mk.amlogic: revision 1.1 sys/arch/evbarm/conf/ODROID-C1: up to revision 1.12 sys/arch/evarm/conf/ODROID-C1_INSTALL: revision 1.1 Don't use not as a variable since it's reserved in C++. -- clean the a9 l2 cache before turning it on. -- Add Cortex-A17 support -- Fix CORTEXA17 support -- Let the "cbar" device property override the cbar value, to work around broken bootloaders -- add a helper to update a9tmr frequency -- detach and re-attach timecounter when updating freq, and reinit timer on each cpu -- fix typo -- add BOOTOPT_TYPE_MACADDR for parsing mac address parameters -- make sure we set ACTLR.SMP=1 for CPU_CORTEXA5 in !MP case, ok matt@ -- According to the Cortex-A5 TRM, the CBAR register is not implemented and always reads as 0x00000000. Add ARM_CBAR option to set this in kernel config. -- skip a TLBIALL on Cortex-A5 that stops my odroid-c1 from booting, ok matt -- match on Cortex-A5 -- match on Cortex-A5 -- allow arml2cc to be used on Cortex-A5 if the "offset" property is specified -- print "A5" instead of "A9" at attach time if running on a Cortex-A5 -- Improve inline asm around dsb/dmb/isb: - always use volatile and mark them as memory barrier - use the common version from locore.h in all places not included from userland -- Work-in-progress Odroid-C1 support. -- no need to override ARM_CBAR, remove unused COM_16750 option -- Add basic serial console support. -- add dwctwo and usb devices -- ODROID-C1 SMP support. -- auto-detect RAM size -- ODROID-C1 onboard ethernet support. -- add amlogicrng, add commented-out genfb placeholder -- enable amlogicsdhc -- add ODROID-C1 install kernel -- Add CPUFREQ option to set boot CPU frequency. ODROID-C1 is advertised as quad-core 1.5GHz but boots up at 1.2GHz; add CPUFREQ=1512 to config and make sure to set the correct speed before attaching CPUs. The speed can still be scaled down with machdep.cpu sysctls. -- disable DEBUG, LOCKDEBUG, VERBOSE_INIT_ARM -- Basic framebuffer console support. Work in progress.
1.4.2.1	04-Nov-2016	pgoyette	Sync with HEAD
1.7.4.1	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.8.2.1	15-Aug-2019	martin	Pull up following revision(s) (requested by skrll in ticket #55): sys/arch/arm/cortex/a9wdt.c: revision 1.10 sys/arch/evbarm/conf/HUMMINGBOARD: revision 1.9 sys/arch/evbarm/conf/GENERIC: revision 1.50 sys/arch/evbarm/conf/NITROGEN6X: revision 1.24 sys/arch/arm/cortex/a9tmr_var.h: revision 1.7 sys/arch/arm/fdt/files.fdt: revision 1.29 sys/arch/arm/amlogic/meson_platform.c: revision 1.12 sys/arch/arm/amlogic/meson8b_pinctrl.c: revision 1.2 sys/arch/arm/amlogic/meson_platform.c: revision 1.13 sys/arch/evbarm/conf/BCM5301X: revision 1.34 sys/arch/arm/dts/meson8b.dtsi: revision 1.6 sys/arch/arm/fdt/a9ptmr_fdt.c: revision 1.1 sys/arch/arm/dts/meson8b.dtsi: revision 1.7 sys/arch/arm/cortex/a9ptmr_var.h: revision 1.1 sys/arch/evbarm/conf/PANDABOARD: revision 1.30 sys/arch/evbarm/conf/DUOVERO: revision 1.14 sys/arch/arm/cortex/a9ptmr.c: revision 1.1 sys/arch/arm/cortex/a9ptmr.c: revision 1.2 sys/arch/arm/fdt/a9wdt_fdt.c: revision 1.1 sys/arch/evbarm/conf/BCM56340: revision 1.19 sys/arch/evbarm/conf/CUBOX-I: revision 1.23 sys/arch/arm/amlogic/meson8b_clkc.c: revision 1.4 sys/arch/evbarm/conf/PARALLELLA: revision 1.7 sys/arch/arm/cortex/files.cortex: revision 1.12 sys/arch/arm/dts/meson8b-odroidc1.dts: revision 1.4 sys/arch/arm/cortex/a9wdt.c: revision 1.9 sys/arch/evbarm/conf/ZEDBOARD: revision 1.6 spaces to tab - Add a driver for the A5/A9 Private timer. While here FDTise the Watchdog driver. - Update for recent a9wdt changes - Trailing whitespace - Updates to get Odroid-C1 in better shape since the last DTS import - Various fixes / changes - don't use prescaler - improve AB_DEBUG output - fix a9ptmr_delay to work with a decrementing counter! Thanks to jmcneill@ for proving I'm an idiot - Add eth_rxd3 and eth_rxd2 pinctrl groups - Catch up to recent mainline dts changes
1.20	19-Jun-2025	andvar	Add missing RCSIDs. Fix typo s/btyes/bytes/ in comment.
1.19	07-Aug-2021	thorpej	branches: 1.19.12; Merge thorpej-cfargs2.
1.18	24-Apr-2021	thorpej	branches: 1.18.8; Merge thorpej-cfargs branch: Simplify and make extensible the config_search() / config_found() / config_attach() interfaces: rather than having different variants for which arguments you want pass along, just have a single call that takes a variadic list of tag-value arguments. Adjust all call sites: - Simplify wherever possible; don't pass along arguments that aren't actually needed. - Don't be explicit about what interface attribute is attaching if the device only has one. (More simplification.) - Add a config_probe() function to be used in indirect configuiration situations, making is visibly easier to see when indirect config is in play, and allowing for future change in semantics. (As of now, this is just a wrapper around config_match(), but that is an implementation detail.) Remove unnecessary or redundant interface attributes where they're not needed. There are currently 5 "cfargs" defined: - CFARG_SUBMATCH (submatch function for direct config) - CFARG_SEARCH (search function for indirect config) - CFARG_IATTR (interface attribte) - CFARG_LOCATORS (locators array) - CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles) ...and a sentinel value CFARG_EOL. Add some extra sanity checking to ensure that interface attributes aren't ambiguous. Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark ports to associate those device handles with device_t instance. This will trickle trough to more places over time (need back-end for pre-OFW Sun OBP; any others?).
1.17	28-Nov-2020	skrll	branches: 1.17.2; Fix build
1.16	29-Sep-2020	jmcneill	branches: 1.16.2; Collapse all CPU_CORTEXA<n> options into CPU_CORTEX and do runtime detection instead of ifdefs where required.
1.15	25-Sep-2018	skrll	Cortex A5 also uses PPI 27 for timer. ODROID-C1 boots again.
1.14	15-Aug-2018	skrll	Sprinkle #include "opt_cputypes.h"
1.13	05-Jun-2018	hkenken	branches: 1.13.2; Rename ARM A9 Global Timer driver name to support fdt. - Rename a9tmr to arma9tmr. - Add a9tmr_fdt.c based gtmr_fdt.c.
1.12	29-Dec-2017	skrll	branches: 1.12.2; Set attached to true when attach completes. Reported by Ramakrishna Rao Desetti on port-arm
1.11	26-May-2017	jmcneill	branches: 1.11.6; Recognize Cortex-A57 FPU, GIC, and Generic Timer.
1.10	02-Apr-2015	matt	need to include <sys/lwp.h>
1.9	28-Feb-2015	skrll	Make this compile where gtmr isn't used.
1.8	28-Feb-2015	skrll	Initial RPI2 support - it doesn't work yet. The generic timer gets messed up somehow. This commit changes the KVA layout of the RPI.
1.7	27-Feb-2015	jmcneill	allow arml2cc to be used on Cortex-A5 if the "offset" property is specified
1.6	27-Feb-2015	jmcneill	match on Cortex-A5
1.5	05-Dec-2014	jmcneill	Let the "cbar" device property override the cbar value, to work around broken bootloaders
1.4	20-Jun-2013	matt	branches: 1.4.6; 1.4.10; 1.4.12; Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args. Modify the list of devices to include the offset(s) from PERIPHBASE.
1.3	16-Jun-2013	matt	Add generic timer support (untested)
1.2	02-Sep-2012	matt	branches: 1.2.2; 1.2.4; 1.2.6; Add driver to attach ARM PL210 L2 Cache Controller arml2cc0 at armperiph0: ARM PL310 L2 r3p2 Cache Controller arml2cc0: 256KB/32B 16-way L2 Unified cache
1.1	01-Sep-2012	matt	Add Cortex-A9 support including the ARM Generic Interrupt Controller and the A9 Global Timer / Watchdog.
1.2.6.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.2.6.1	02-Sep-2012	matt	file armperiph.c was added on branch matt-nb6-plus on 2012-11-28 22:40:26 +0000
1.2.4.3	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.2.4.2	30-Oct-2012	yamt	sync with head
1.2.4.1	02-Sep-2012	yamt	file armperiph.c was added on branch yamt-pagecache on 2012-10-30 17:19:00 +0000
1.2.2.2	03-Dec-2017	jdolecek	update from HEAD
1.2.2.1	23-Jun-2013	tls	resync from head
1.4.12.2	28-Aug-2017	skrll	Sync with HEAD
1.4.12.1	06-Apr-2015	skrll	Sync with HEAD
1.4.10.2	21-Mar-2015	snj	Pull up following revision(s) (requested by jmcneill in ticket #598): sys/arch/arm/amlogic/amlogic_board.c: up to revision 1.9 sys/arch/arm/amlogic/amlogic_canvasreg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_com.c: up to revision 1.4 sys/arch/arm/amlogic/amlogic_comreg.h: up to revision 1.3 sys/arch/arm/amlogic/amlogic_comvar.h: revision 1.1 sys/arch/arm/amlogic/amlogic_cpufreq.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_crureg.h: up to revision 1.7 sys/arch/arm/amlogic/amlogic_dwctwo.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_genfb.c: revision 1.1 sys/arch/arm/amlogic/amlogic_gmac.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_hdmireg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_intr.h: up to revision 1.5 sys/arch/arm/amlogic/amlogic_io.c: up to revision 1.7 sys/arch/arm/amlogic/amlogic_reg.h: up to revision 1.9 sys/arch/arm/amlogic/amlogic_rng.c: revision 1.1 sys/arch/arm/amlogic/amlogic_sdhc.c: up to revision 1.3 sys/arch/arm/amlogic/amlogic_sdhcreg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_space.c: revision 1.1 sys/arch/arm/amlogic/amlogic_var.h: up to revision 1.8 sys/arch/arm/amlogic/amlogic_vpureg.h: revision 1.1 sys/arch/arm/arm/bootconfig.c: revisions 1.7-1.8 sys/arch/arm/conf/files.arm: revision 1.129 sys/arch/arm/cortex/pl310.c: revisions 1.16-1.17 sys/arch/arm/cortex/a9_mpsubr.S: revisions 1.25-1.29 sys/arch/arm/cortex/a9tmr.c: revisions 1.8-1.12 sys/arch/arm/cortex/a9tmr_var.h: revision 1.4 sys/arch/arm/cortex/a9wdt.c: revisions 1.3-1.4 sys/arch/arm/cortex/armperiph.c: revisions 1.5-1.7 sys/arch/arm/arm/cpufunc.c: revision 1.151 sys/arch/arm/include/bootconfig.h: revision 1.7 sys/arch/arm/include/locore.h: revision 1.19 sys/arch/evbarm/amlogic/amlogic_machdep.c: up to revision 1.17 sys/arch/evbarm/amlogic/amlogic_start.S: up to revision 1.2 sys/arch/evbarm/amlogic/genassym.cf: revision 1.1 sys/arch/evbarm/amlogic/platform.h: revision 1.1 sys/arch/evbarm/conf/files.amlogic: up to revision 1.8 sys/arch/evbarm/conf/std.amlogic: up to revision 1.2 sys/arch/evbarm/conf/mk.amlogic: revision 1.1 sys/arch/evbarm/conf/ODROID-C1: up to revision 1.12 sys/arch/evarm/conf/ODROID-C1_INSTALL: revision 1.1 Don't use not as a variable since it's reserved in C++. -- clean the a9 l2 cache before turning it on. -- Add Cortex-A17 support -- Fix CORTEXA17 support -- Let the "cbar" device property override the cbar value, to work around broken bootloaders -- add a helper to update a9tmr frequency -- detach and re-attach timecounter when updating freq, and reinit timer on each cpu -- fix typo -- add BOOTOPT_TYPE_MACADDR for parsing mac address parameters -- make sure we set ACTLR.SMP=1 for CPU_CORTEXA5 in !MP case, ok matt@ -- According to the Cortex-A5 TRM, the CBAR register is not implemented and always reads as 0x00000000. Add ARM_CBAR option to set this in kernel config. -- skip a TLBIALL on Cortex-A5 that stops my odroid-c1 from booting, ok matt -- match on Cortex-A5 -- match on Cortex-A5 -- allow arml2cc to be used on Cortex-A5 if the "offset" property is specified -- print "A5" instead of "A9" at attach time if running on a Cortex-A5 -- Improve inline asm around dsb/dmb/isb: - always use volatile and mark them as memory barrier - use the common version from locore.h in all places not included from userland -- Work-in-progress Odroid-C1 support. -- no need to override ARM_CBAR, remove unused COM_16750 option -- Add basic serial console support. -- add dwctwo and usb devices -- ODROID-C1 SMP support. -- auto-detect RAM size -- ODROID-C1 onboard ethernet support. -- add amlogicrng, add commented-out genfb placeholder -- enable amlogicsdhc -- add ODROID-C1 install kernel -- Add CPUFREQ option to set boot CPU frequency. ODROID-C1 is advertised as quad-core 1.5GHz but boots up at 1.2GHz; add CPUFREQ=1512 to config and make sure to set the correct speed before attaching CPUs. The speed can still be scaled down with machdep.cpu sysctls. -- disable DEBUG, LOCKDEBUG, VERBOSE_INIT_ARM -- Basic framebuffer console support. Work in progress.
1.4.10.1	11-Mar-2015	snj	Pull up following revision(s) (requested by skrll in ticket #582): distrib/utils/embedded/conf/rpi.conf: revision 1.27 etc/etc.evbarm/Makefile.inc: revision 1.70 sys/arch/arm/broadcom/bcm2835_intr.c: revision 1.5-1.7 sys/arch/arm/broadcom/bcm2835_obio.c: revision 1.23, 1.24 sys/arch/arm/broadcom/bcm2835_space.c: revision 1.8 sys/arch/arm/broadcom/bcm2835reg.h: revision 1.14 sys/arch/arm/broadcom/bcm2835var.h: revision 1.2 sys/arch/arm/broadcom/files.bcm2835: revision 1.24 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.30 sys/arch/arm/cortex/armperiph.c: revision 1.8, 1.9 sys/arch/arm/cortex/gtmr.c: revision 1.9 sys/arch/arm/cortex/gtmr_var.h: revision 1.5 sys/arch/arm/cortex/mpcore_var.h: revision 1.3 sys/arch/arm/include/cpu.h: revision 1.84 sys/arch/evbarm/conf/RPI2: revision 1.1, 1.2 sys/arch/evbarm/conf/RPI2_INSTALL: revision 1.1 sys/arch/evbarm/conf/RPI: revision 1.59, 1.60 sys/arch/evbarm/conf/mk.rpi: revision 1.4 sys/arch/evbarm/conf/std.rpi: revisions 1.16-1.19 via patch sys/arch/evbarm/rpi/genassym.cf: revision 1.2 sys/arch/evbarm/rpi/rpi.h: revision 1.4 sys/arch/evbarm/rpi/rpi2_start.S: revision 1.1 sys/arch/evbarm/rpi/rpi_machdep.c: revision 1.57, 1.58 via patch sys/arch/evbarm/rpi/rpi_start.S: revision 1.13 Move some options into std.rpi -- Add __HAVE_MM_MD_CACHE_ALIASING Pull up following revision(s) (requested by skrll in ticket #582): Fix TPIDRPRW_IS_CURLWP builds. -- A MULTIPROCESSOR kernel requires TPIDRPRW_IS_CURCPU. -- Use TPIDRPRW_IS_CURLWP as it's a slight code reduction and performance improvement. Initial RPI2 support - it doesn't work yet. The generic timer gets messed up somehow. This commit changes the KVA layout of the RPI. -- Make this compile where gtmr isn't used. -- Spin up the non-boot CPUs, but don't allow cpu_boot_secondary_processors to see them for now. RPI2 nows works well with only the boot cpu. -- Appease a KASSERT - will be remove when MULTIPROCESSOR RPI2 is fixed. -- Add RPI2 to kernels build for both earmv[67]. Use the earmv6 built kernels to create an image that can be used on both RPI and RPI2 -- Add an RPI2_INSTALL
1.4.6.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.4.6.1	20-Jun-2013	matt	file armperiph.c was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.11.6.1	13-Dec-2017	matt	Add Cortex-A35 devices
1.12.2.3	30-Sep-2018	pgoyette	Ssync with HEAD
1.12.2.2	06-Sep-2018	pgoyette	Sync with HEAD Resolve a couple of conflicts (result of the uimin/uimax changes)
1.12.2.1	25-Jun-2018	pgoyette	Sync with HEAD
1.13.2.1	10-Jun-2019	christos	Sync with HEAD
1.16.2.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.17.2.1	21-Mar-2021	thorpej	Give config_found() the same variadic arguments treatment as config_search(). This commit only adds the CFARG_EOL sentinel to the existing config_found() calls. Conversion of config_found_sm_loc() and config_found_ia() call sites will be in subsequent commits.
1.18.8.1	04-Aug-2021	thorpej	Adapt to CFARGS().
1.19.12.1	02-Aug-2025	perseant	Sync with HEAD
1.2	05-Jun-2017	skrll	Removed unused file
1.1	25-Nov-2015	marty	branches: 1.1.2; 1.1.12; something temporary that will go away once odroid xu4 works
1.1.12.1	31-Jul-2023	martin	Pull up following revision(s) (requested by riastradh in ticket #1859): sys/arch/ia64/ia64/vm_machdep.c: revision 1.18 sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67 sys/arch/aarch64/aarch64/locore.S: revision 1.91 sys/arch/mips/include/asm.h: revision 1.74 sys/arch/hppa/include/cpu.h: revision 1.13 sys/arch/arm/arm/armv6_start.S: revision 1.38 (applied also to sys/arch/arm/cortex/a9_mpsubr.S, sys/arch/arm/cortex/a9_mpsubr.S, sys/arch/arm/cortex/cortex_init.S) sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2 sys/arch/mips/mips/locore.S: revision 1.229 sys/arch/alpha/include/asm.h: revision 1.45 (applied to sys/arch/alpha/alpha/multiproc.s) sys/arch/sparc64/sparc64/locore.s: revision 1.432 sys/arch/vax/vax/subr.S: revision 1.42 sys/arch/mips/mips/locore_mips3.S: revision 1.116 sys/arch/ia64/ia64/machdep.c: revision 1.44 sys/arch/arm/arm32/cpuswitch.S: revision 1.106 sys/arch/sparc/sparc/locore.s: revision 1.284 (all via patch) aarch64: Add missing barriers in cpu_switchto. Details in comments. Note: This is a conservative change that inserts a barrier where there was a comment saying none is needed, which is probably correct. The goal of this change is to systematically add barriers to be confident in correctness; subsequent changes may remove some bariers, as an optimization, with an explanation of why each barrier is not needed. PR kern/57240 alpha: Add missing barriers in cpu_switchto. Details in comments. arm32: Add missing barriers in cpu_switchto. Details in comments. hppa: Add missing barriers in cpu_switchto. Not sure hppa has ever had working MULTIPROCESSOR, so maybe no pullups needed? ia64: Add missing barriers in cpu_switchto. (ia64 has never really worked, so no pullups needed, right?) mips: Add missing barriers in cpu_switchto. Details in comments. powerpc: Add missing barriers in cpu_switchto. Details in comments. sparc: Add missing barriers in cpu_switchto. sparc64: Add missing barriers in cpu_switchto. Details in comments. vax: Note where cpu_switchto needs barriers. Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not even sure how to spell store-before-load barriers on VAX, so no functional change for now.
1.1.2.3	28-Aug-2017	skrll	Sync with HEAD
1.1.2.2	27-Dec-2015	skrll	Sync with HEAD (as of 26th Dec)
1.1.2.1	25-Nov-2015	skrll	file cortex_init.S was added on branch nick-nhusb on 2015-12-27 12:09:30 +0000
1.6	02-Oct-2025	riastradh	cpu_in_cksum_asm_neon.S: Nix trailing whitespace. No functional change intended.
1.5	19-Jun-2025	andvar	Add missing RCSIDs. Fix typo s/btyes/bytes/ in comment.
1.4	02-Oct-2021	skrll	branches: 1.4.10; Trailing whitespace
1.3	22-Dec-2012	matt	branches: 1.3.2; 1.3.6; 1.3.14; Rework considerably. Use alternating sets of registers. (Still not faster than normal ARM code).
1.2	18-Dec-2012	matt	Tighten up cpu_in_cksum_neon_v4hdr by 3 instructions. Swap the doubles on a partial qword load on BE platforms.
1.1	17-Dec-2012	matt	Add preliminary version of a NEON based in_cksum routine.
1.3.14.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.3.14.1	22-Dec-2012	matt	file cpu_in_cksum_asm_neon.S was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.3.6.2	25-Feb-2013	tls	resync with head
1.3.6.1	22-Dec-2012	tls	file cpu_in_cksum_asm_neon.S was added on branch tls-maxphys on 2013-02-25 00:28:26 +0000
1.3.2.2	23-Jan-2013	yamt	sync with head
1.3.2.1	22-Dec-2012	yamt	file cpu_in_cksum_asm_neon.S was added on branch yamt-pagecache on 2013-01-23 00:05:41 +0000
1.4.10.1	02-Aug-2025	perseant	Sync with HEAD
1.2	19-Jun-2025	andvar	Add missing RCSIDs. Fix typo s/btyes/bytes/ in comment.
1.1	17-Dec-2012	matt	branches: 1.1.2; 1.1.6; 1.1.14; 1.1.80; Add preliminary version of a NEON based in_cksum routine.
1.1.80.1	02-Aug-2025	perseant	Sync with HEAD
1.1.14.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.1.14.1	17-Dec-2012	matt	file cpu_in_cksum_neon.c was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.1.6.2	25-Feb-2013	tls	resync with head
1.1.6.1	17-Dec-2012	tls	file cpu_in_cksum_neon.c was added on branch tls-maxphys on 2013-02-25 00:28:26 +0000
1.1.2.2	23-Jan-2013	yamt	sync with head
1.1.2.1	17-Dec-2012	yamt	file cpu_in_cksum_neon.c was added on branch yamt-pagecache on 2013-01-23 00:05:41 +0000
1.17	25-Jun-2022	jmcneill	Remove GIC_SPLFUNCS.
1.16	10-Aug-2021	jmcneill	Make gic_splfuncs optional and disable it by default until it has had more testing.
1.15	10-Aug-2021	jmcneill	Use custom spl funcs for GIC and avoid unnecessary pmr register accesses in splx.
1.14	29-Sep-2020	jmcneill	Collapse all CPU_CORTEXA<n> options into CPU_CORTEX and do runtime detection instead of ifdefs where required.
1.13	14-Oct-2019	jmcneill	Add support for Amazon's Graviton MSI controller. Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of sending messages to a fixed address with the SPI as data, the Graviton's GICv2m uses a different address for each vector with "don't care" as data.
1.12	10-Aug-2019	skrll	Add a driver for the A5/A9 Private timer. While here FDTise the Watchdog driver.
1.11	12-Nov-2018	jmcneill	branches: 1.11.4; Support building kernels with ACPI and no PCI.
1.10	09-Nov-2018	jmcneill	Add support for GICv3 Locality-specific Periphal Interrupts (LPIs) and the Interrupt Translation Service (ITS).
1.9	21-Oct-2018	jmcneill	Add support for PCI MSI using ARM GICv2m.
1.8	08-Aug-2018	jmcneill	Add GICv3 support.
1.7	05-Jun-2018	hkenken	branches: 1.7.2; Rename ARM A9 Global Timer driver name to support fdt. - Rename a9tmr to arma9tmr. - Add a9tmr_fdt.c based gtmr_fdt.c.
1.6	28-May-2017	jmcneill	branches: 1.6.8; Move children of armperiph to the "mpcorebus" interface attribute and have armperiph declare support for it.
1.5	19-Feb-2014	matt	branches: 1.5.6; Add needs-flag to arml2cc
1.4	16-Jun-2013	matt	branches: 1.4.2; 1.4.6; Add generic timer support (untested)
1.3	17-Dec-2012	matt	Add preliminary version of a NEON based in_cksum routine.
1.2	02-Sep-2012	matt	branches: 1.2.2; 1.2.4; 1.2.6; Add driver to attach ARM PL210 L2 Cache Controller arml2cc0 at armperiph0: ARM PL310 L2 r3p2 Cache Controller arml2cc0: 256KB/32B 16-way L2 Unified cache
1.1	01-Sep-2012	matt	Add Cortex-A9 support including the ARM Generic Interrupt Controller and the A9 Global Timer / Watchdog.
1.2.6.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.2.6.1	02-Sep-2012	matt	file files.cortex was added on branch matt-nb6-plus on 2012-11-28 22:40:26 +0000
1.2.4.4	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.2.4.3	23-Jan-2013	yamt	sync with head
1.2.4.2	30-Oct-2012	yamt	sync with head
1.2.4.1	02-Sep-2012	yamt	file files.cortex was added on branch yamt-pagecache on 2012-10-30 17:19:00 +0000
1.2.2.4	03-Dec-2017	jdolecek	update from HEAD
1.2.2.3	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.2.2.2	23-Jun-2013	tls	resync from head
1.2.2.1	25-Feb-2013	tls	resync with head
1.4.6.3	19-Feb-2014	matt	arml2cc -> needs-flag
1.4.6.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.4.6.1	16-Jun-2013	matt	file files.cortex was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.4.2.1	18-May-2014	rmind	sync with head
1.5.6.1	28-Aug-2017	skrll	Sync with HEAD
1.6.8.3	26-Nov-2018	pgoyette	Sync with HEAD, resolve a couple of conflicts
1.6.8.2	06-Sep-2018	pgoyette	Sync with HEAD Resolve a couple of conflicts (result of the uimin/uimax changes)
1.6.8.1	25-Jun-2018	pgoyette	Sync with HEAD
1.7.2.2	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.7.2.1	10-Jun-2019	christos	Sync with HEAD
1.11.4.2	15-Oct-2019	martin	Pull up following revision(s) (requested by jmcneill in ticket #334): sys/arch/arm/cortex/gic_v2m.c: revision 1.7 sys/arch/arm/acpi/gicv3_acpi.c: revision 1.5 sys/arch/arm/acpi/files.acpi: revision 1.8 sys/arch/arm/acpi/gic_acpi.c: revision 1.4 sys/arch/arm/cortex/files.cortex: revision 1.13 sys/arch/arm/acpi/gic_v2m_acpi.c: revision 1.1 sys/arch/arm/acpi/gic_v2m_acpi.h: revision 1.1 sys/arch/arm/cortex/gic_v2m.h: revision 1.2 Add support for Amazon's Graviton MSI controller. Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of sending messages to a fixed address with the SPI as data, the Graviton's GICv2m uses a different address for each vector with "don't care" as data.
1.11.4.1	15-Aug-2019	martin	Pull up following revision(s) (requested by skrll in ticket #55): sys/arch/arm/cortex/a9wdt.c: revision 1.10 sys/arch/evbarm/conf/HUMMINGBOARD: revision 1.9 sys/arch/evbarm/conf/GENERIC: revision 1.50 sys/arch/evbarm/conf/NITROGEN6X: revision 1.24 sys/arch/arm/cortex/a9tmr_var.h: revision 1.7 sys/arch/arm/fdt/files.fdt: revision 1.29 sys/arch/arm/amlogic/meson_platform.c: revision 1.12 sys/arch/arm/amlogic/meson8b_pinctrl.c: revision 1.2 sys/arch/arm/amlogic/meson_platform.c: revision 1.13 sys/arch/evbarm/conf/BCM5301X: revision 1.34 sys/arch/arm/dts/meson8b.dtsi: revision 1.6 sys/arch/arm/fdt/a9ptmr_fdt.c: revision 1.1 sys/arch/arm/dts/meson8b.dtsi: revision 1.7 sys/arch/arm/cortex/a9ptmr_var.h: revision 1.1 sys/arch/evbarm/conf/PANDABOARD: revision 1.30 sys/arch/evbarm/conf/DUOVERO: revision 1.14 sys/arch/arm/cortex/a9ptmr.c: revision 1.1 sys/arch/arm/cortex/a9ptmr.c: revision 1.2 sys/arch/arm/fdt/a9wdt_fdt.c: revision 1.1 sys/arch/evbarm/conf/BCM56340: revision 1.19 sys/arch/evbarm/conf/CUBOX-I: revision 1.23 sys/arch/arm/amlogic/meson8b_clkc.c: revision 1.4 sys/arch/evbarm/conf/PARALLELLA: revision 1.7 sys/arch/arm/cortex/files.cortex: revision 1.12 sys/arch/arm/dts/meson8b-odroidc1.dts: revision 1.4 sys/arch/arm/cortex/a9wdt.c: revision 1.9 sys/arch/evbarm/conf/ZEDBOARD: revision 1.6 spaces to tab - Add a driver for the A5/A9 Private timer. While here FDTise the Watchdog driver. - Update for recent a9wdt changes - Trailing whitespace - Updates to get Odroid-C1 in better shape since the last DTS import - Various fixes / changes - don't use prescaler - improve AB_DEBUG output - fix a9ptmr_delay to work with a decrementing counter! Thanks to jmcneill@ for proving I'm an idiot - Add eth_rxd3 and eth_rxd2 pinctrl groups - Catch up to recent mainline dts changes
1.57	05-Oct-2023	riastradh	arm/gic: Check l_blcnt, not l_biglocks. l_biglocks is a now-defunct temporary storage used only when sleeping; l_blcnt is the number of kernel locks held by the lwp when not sleeping. Should fix arm builds.
1.56	26-Jun-2022	jmcneill	build fix: remove includes of opt_gic.h
1.55	25-Jun-2022	jmcneill	Remove GIC_SPLFUNCS.
1.54	25-Jun-2022	jmcneill	pic: Update ci_cpl in pic_set_priority callback. Not all ICs need interrupts disabled to update the priority. DAIF accesses are not cheap, so push the update of ci_cpl from pic_set_priority to the IC's pic_set_priority callback, and let the IC driver determine whether or not it needs interrupts disabled.
1.53	03-Mar-2022	riastradh	arm: Use device_set_private for various drivers.
1.52	02-Jan-2022	riastradh	arm: Remove #ifdef DIAGNOSTIC now wrong after KASSERT change. Objects in question aren't volatile here so access is flushable.
1.51	21-Oct-2021	skrll	Fix some conditionals to match gicv3 and add some comments to describe what's going on. Fixes PR port-evbarm/56420
1.50	26-Sep-2021	jmcneill	If an SGI or PPI is established after interrupts are enabled, make sure we unblock the source on _all_ CPUs and not just the CPU that is establishing the interrupt.
1.49	10-Aug-2021	jmcneill	Make gic_splfuncs optional and disable it by default until it has had more testing.
1.48	10-Aug-2021	jmcneill	Use custom spl funcs for GIC and avoid unnecessary pmr register accesses in splx.
1.47	28-Mar-2021	skrll	Only target the boot cpu for real with SPI interrupts. I tried to do this back in 2014, but somehow I missed a spot. This is a quick-and-dirty fix for the USB stack which expects transfer completions to be in-order. If interrupts happen across the CPUs then this isn't guaranteed (yet). kern/55243 panic at usb_transfer_complete() on raspberry pi 4
1.46	23-Feb-2021	jmcneill	branches: 1.46.2; If we are committing a deferred splhigh() to hardware, no need to continue.
1.45	21-Feb-2021	jmcneill	Apply PMR optimizations from gicv3
1.44	09-Feb-2021	jakllsch	Avoid an extra daif read when dispatching interrupts by using ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros.
1.43	03-Dec-2020	skrll	Provide and use a sev() macro for the sev instruction. While here use the correct barrier to ensure completion of memory accesses before a couple of the sev() calls.
1.42	26-Sep-2020	skrll	branches: 1.42.2; G/C arm/atomic.h
1.41	27-Jul-2020	jmcneill	Remove CPU ID test in armgic_match. Perfectly normal to have GIC in non-Cortex cores.
1.40	12-Jul-2020	skrll	Avoid undefined behaviour. Detected by KUBSAN.
1.39	13-Apr-2020	jmcneill	Fix "left shift of 255 by 24 places cannot be represented in type 'int'" warning from UBSan.
1.38	16-Nov-2018	jmcneill	branches: 1.38.4; 1.38.10; Use intr_establish_xname
1.37	10-Sep-2018	jmcneill	armgic_ipi_send: use GIC interface number, not CPU index, when setting the target(s) for an IPI.
1.36	10-Sep-2018	jmcneill	Update sc_mptargets atomically, as PEs will be started up in parallel w/o locking here
1.35	15-Jul-2018	jmcneill	Support pic_set_affinity and pic_get_affinity
1.34	28-Apr-2018	jakllsch	branches: 1.34.2; Cover all pic_maxsources lines for armgic_cpu_init_priorities() and armgic_cpu_update_priorities(). Previously only the first 32 lines were covered, which is significantly less than the 1000-some interrupt lines possible. Only relevant to MULTIPROCESSOR configurations.
1.33	01-Apr-2018	ryo	Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@) - sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@) - add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)
1.32	07-Feb-2018	jmcneill	branches: 1.32.2; PR# port-evbarm/49468: Cortex GIC assertion triggered on Allwinner A80 SoC The priority level is changed by writing to GICC_PMR with interrupts disabled. However, interrupts are enabled/disabled downstream of the GICC at the CPU. When raising priority level, there is a window between the time that interrupts are disabled and the GICC_PMR register is written. If an interrupt occurs at a previously allowed priority before GICC_PMR is changed, the CPU will receive the signal when interrupts are re-enabled. At this time, GICC_PMR is now the new priority level, so reads of GICC_IAR will report a spurious IRQ. Move the "old_ipl != IPL_HIGH" test until after we have confirmed that there is at least one pending IRQ.
1.31	14-Jul-2017	skrll	KNF
1.30	29-Jun-2017	jmcneill	ARM Trusted Firmware reserves SGIs 8-15 for secure use. Even without ATF, U-Boot on some platforms may use SGIs in this range for the PSCI implementation. Change ARMGIC_IPI_BASE to 0 from (16 - NIPI) and add a compile-time assert to ensure that we don't end up with a conflict.
1.29	28-Jun-2017	skrll	Revert the KERNHIST for now it causes problems
1.28	22-Jun-2017	skrll	If we see GICC_IAR_IRQ_SSPURIOUS we should also stop looking for irqs
1.27	22-Jun-2017	skrll	Wrap long line
1.26	22-Jun-2017	skrll	Print the GICC_IIDR when AB_DEBUG
1.25	22-Jun-2017	skrll	Add 'armgichist' KERNHIST for (future) debugging.
1.24	18-Jun-2017	jmcneill	Don't assume that CPU index = GIC CPU interface number. We can determine the current CPU interface number by reading from the read-only GICD_ITARGETSR0 through GICD_ITARGETSR7 registers. This gets interrupts working on Exynos 5422, where the boot processor has GIC CPU interface #4.
1.23	05-Jun-2017	skrll	Clean out some #if 0'ed or //'ed code
1.22	04-Jun-2017	skrll	Initialise all the SGI/PPI priorities for all CPUs to mask the interrupts
1.21	30-May-2017	jmcneill	branches: 1.21.2; Use an FDT-based ARM_INTR_IMPL for Tegra.
1.20	29-Jul-2015	matt	Adjust some of IPLs of various IPIs.
1.19	15-Apr-2015	matt	Add separate IPI routines for IPI_AST and IPI_KPREEMPT.
1.18	11-Apr-2015	matt	Add a pic_cpus to the softc which specifies which cpus the pic can send IPIs to. For GIC, initialize pic_cpus to kcpuset_running since it can handle all the cpus.
1.17	09-Apr-2015	matt	All SGIs are MPSAFE so establish them as such.
1.16	20-Mar-2015	skrll	Trailing whitespace
1.15	12-Mar-2015	skrll	G/C armgic_last_priority
1.14	03-Mar-2015	jmcneill	in armgic_establish_irq, make sure to write the new value to GICD_ICFGRn when setting irq type (IST_LEVEL/IST_EDGE)
1.13	02-Mar-2015	jmcneill	sc_gic_lines is the total number of valid lines but pic_sources[] is sparse; when initializing mpsafe targets make sure to go all the way to the end (sc_pic.pic_maxsources) instead
1.12	29-Oct-2014	skrll	branches: 1.12.2; Only target boot cpu for SPIs atm. Fix a couple of bugs in the now disabled code.
1.11	29-Oct-2014	skrll	Sprinkle #include "opt_multiprocessor.h"
1.10	19-May-2014	rmind	branches: 1.10.2; Implement MI IPI interface with cross-call support.
1.9	27-Apr-2014	matt	When dealing with the PMR register, only use non-secure priority values.
1.8	13-Apr-2014	matt	Move aprint to print sooner.
1.7	28-Mar-2014	matt	branches: 1.7.2; Various MP changes.
1.6	04-Mar-2014	matt	Don't byte swap the data, assume the bus_space will do it.
1.5	17-Dec-2013	joerg	branches: 1.5.2; armgic_priority_to_ipl is only used in #if 0'd code, so apply that as well.
1.4	20-Jun-2013	matt	branches: 1.4.2; Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args. Modify the list of devices to include the offset(s) from PERIPHBASE.
1.3	16-Sep-2012	rmind	branches: 1.3.2; 1.3.4; Rename kcpuset_copybits() to kcpuset_export_u32() and thus be more specific about the interface.
1.2	14-Sep-2012	matt	Verify the source isn't a dummy source.
1.1	01-Sep-2012	matt	branches: 1.1.2; Add Cortex-A9 support including the ARM Generic Interrupt Controller and the A9 Global Timer / Watchdog.
1.1.2.4	03-Dec-2017	jdolecek	update from HEAD
1.1.2.3	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.1.2.2	23-Jun-2013	tls	resync from head
1.1.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.3.4.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.3.4.1	16-Sep-2012	matt	file gic.c was added on branch matt-nb6-plus on 2012-11-28 22:40:26 +0000
1.3.2.3	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.3.2.2	30-Oct-2012	yamt	sync with head
1.3.2.1	16-Sep-2012	yamt	file gic.c was added on branch yamt-pagecache on 2012-10-30 17:19:00 +0000
1.4.2.1	18-May-2014	rmind	sync with head
1.5.2.3	26-Mar-2014	matt	Let bus_space so the endian conversion if needed
1.5.2.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.5.2.1	17-Dec-2013	matt	file gic.c was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.7.2.1	10-Aug-2014	tls	Rebase.
1.10.2.5	30-Jul-2015	martin	Pull up following revision(s) (requested by skrll in ticket #890): sys/arch/arm/pic/pic.c: revision 1.27-1.32 sys/arch/arm/omap/omap5430_intr.h: revision 1.3 sys/arch/arm/broadcom/bcm2835_obio.c: revision 1.25 sys/arch/arm/cortex/gic.c: revision 1.18 sys/arch/arm/broadcom/bcm2835reg.h: revision 1.15 sys/arch/evbarm/rpi/rpi_machdep.c: revision 1.61 sys/arch/arm/broadcom/bcm2835_intr.h: revision 1.2 sys/arch/arm/marvell/mvsoc_intr.h: revision 1.5 sys/arch/arm/broadcom/bcm2835_intr.c: revision 1.8-1.10 sys/arch/arm/pic/picvar.h: revision 1.12-1.14 sys/arch/arm/omap/omap4430_intr.h: revision 1.3 Don't clear CI_ASTPENDING in exception return, do it in ast() instead. Add basic support for __HAVE_PREEMPTION. Use atomic ops for ci_astpending if __HAVE_PREEMPTION is defined. Use kpreempt_disable/kpreempt_enable Add __HAVE_PIC_HAVE_PENDING_INTRS and define it if __HAVE_PIC_SET_PRIORITY is undefined (also define in mvsoc_intr.h since their use of the latter is peculiar). This new define controls whether the pending interrupt logic is compiled. The GIC doesn't use pending interrupts since it uses the priority level on the GIC to control delivery of interrupts, thus there can never be a pending interrupt. The kernel shrinks about 4KB with the removal of the pending interupt support, Only if we __HAVE_PIC_PENDING_INTRS do we need the variables to track them. Add #define __HAVE_PIC_PENDING_INTRS for the non-GIC PICs. Add a pic_cpus to the softc which specifies which cpus the pic can send IPIs to. For GIC, initialize pic_cpus to kcpuset_running since it can handle all the cpus. Adapt pic to deal with the BCM2836 interrupts. Move pic_pending_pics, pic_pending_ipls, and pic_blocked_irqs into a structure and make then per-cpu. There is no global interrupt state anymore. Use right kcpuset call. Don't need pic_ipi_sender anymore. Don't send IPIs to ourselves if sending to everyone. RPI2 MP support. Thanks to Matt Thomas for making this possible with his changes to pic.c Use a bit per IPI type in local mailbox 0 registers. Ok matt@ IPIs should be IPL_HIGH according to rmind@ Fix bcm2836mp_pic_{un,}block_irqs to handle timer AND mailbox interrupts if they're both passed. Thanks to nat@ for finding this. Sprinkle some KASSERTs
1.10.2.4	21-Mar-2015	snj	Pull up following revision(s) (requested by skrll in ticket #627): sys/arch/arm/cortex/gic.c: revision 1.16 Trailing whitespace
1.10.2.3	15-Mar-2015	snj	Pull up following revision(s) (requested by skrll in ticket #591): sys/arch/arm/cortex/gic.c: revision 1.15 G/C armgic_last_priority
1.10.2.2	07-Mar-2015	snj	Pull up following revision(s) (requested by jmcneill in ticket #567): sys/arch/arm/cortex/gic.c: revision 1.13, 1.14 in armgic_establish_irq, make sure to write the new value to GICD_ICFGRn when setting irq type (IST_LEVEL/IST_EDGE) -- sc_gic_lines is the total number of valid lines but pic_sources[] is sparse; when initializing mpsafe targets make sure to go all the way to the end (sc_pic.pic_maxsources) instead
1.10.2.1	09-Nov-2014	martin	Pull up following revision(s) (requested by skrll in ticket #188): sys/arch/arm/include/arm32/pmap.h: revision 1.136 sys/arch/arm/include/armreg.h: revision 1.100 sys/arch/arm/cortex/gic.c: revision 1.11 sys/arch/arm/arm32/db_interface.c: revision 1.54 sys/arch/arm/include/armreg.h: revision 1.101 sys/arch/arm/cortex/gic.c: revision 1.12 sys/arch/arm/arm32/arm32_machdep.c: revision 1.107 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.19 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.20 sys/arch/evbarm/conf/BPI: revision 1.5 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.21 sys/arch/arm/arm32/pmap.c: revision 1.306 sys/arch/arm/arm32/db_machdep.c: revision 1.22 sys/arch/arm/arm32/arm32_tlb.c: revision 1.3 sys/arch/arm/arm/undefined.c: revision 1.55 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.22 sys/arch/arm/arm32/pmap.c: revision 1.307 sys/arch/arm/arm32/arm32_tlb.c: revision 1.4 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.23 sys/arch/arm/arm32/arm32_tlb.c: revision 1.5 sys/arch/evbarm/conf/BPI: revision 1.8 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.24 sys/arch/arm/arm32/arm32_tlb.c: revision 1.6 sys/arch/arm/arm32/arm32_tlb.c: revision 1.7 sys/arch/evbarm/conf/CUBIETRUCK: revision 1.5 sys/arch/arm/pic/pic.c: revision 1.23 sys/arch/arm/pic/pic.c: revision 1.24 sys/arch/arm/pic/picvar.h: revision 1.11 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.20 sys/arch/arm/mainbus/cpu_mainbus.c: revision 1.16 sys/arch/arm/arm32/pmap.c: revision 1.298 sys/arch/arm/arm/cpufunc_asm_arm11.S: revision 1.17 sys/arch/arm/arm/cpufunc_asm_pj4b.S: revision 1.5 sys/arch/arm/arm32/pmap.c: revision 1.310 sys/arch/arm/arm32/pmap.c: revision 1.311 sys/arch/arm/arm32/arm32_kvminit.c: revision 1.32 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.19 sys/arch/arm/arm32/arm32_boot.c: revision 1.10 sys/arch/arm/arm/ast.c: revision 1.25 sys/arch/arm/include/armreg.h: revision 1.98 sys/uvm/pmap/pmap_tlb.c: revision 1.10 sys/arch/arm/arm32/arm32_boot.c: revision 1.8 sys/arch/arm/arm32/arm32_boot.c: revision 1.9 sys/arch/arm/arm/arm_machdep.c: revision 1.43 Various ARM MP fixes.
1.12.2.4	28-Aug-2017	skrll	Sync with HEAD
1.12.2.3	22-Sep-2015	skrll	Sync with HEAD
1.12.2.2	06-Jun-2015	skrll	Sync with HEAD
1.12.2.1	06-Apr-2015	skrll	Sync with HEAD
1.21.2.2	18-Jul-2017	snj	Pull up following revision(s) (requested by jmcneill in ticket #114): sys/arch/arm/samsung/exynos_intr.h: revision 1.3 sys/arch/arm/sunxi/sun8i_h3_ccu.c: revision 1.1 sys/arch/arm/sunxi/sun8i_h3_ccu.c: revision 1.2 sys/arch/arm/sunxi/sun8i_h3_ccu.c: revision 1.3 sys/arch/arm/sunxi/sunxi_gates.c: revision 1.1 distrib/utils/embedded/mkimage: revision 1.66 sys/arch/arm/sunxi/sun8i_h3_ccu.c: revision 1.4 sys/arch/arm/sunxi/sunxi_rsb.c: revision 1.1 sys/arch/arm/sunxi/sun8i_h3_ccu.c: revision 1.5 sys/arch/arm/sunxi/sun8i_h3_ccu.c: revision 1.6 sys/arch/arm/sunxi/sun8i_h3_ccu.c: revision 1.7 sys/dev/gpio/gpio.c: revision 1.59 sys/arch/arm/sunxi/sunxi_ccu_prediv.c: revision 1.1 sys/conf/Makefile.kern.inc: revision 1.257 sys/arch/evbarm/conf/ODROID-XU_INSTALL: file removal sys/arch/arm/sunxi/sunxi_ccu_prediv.c: revision 1.2 sys/conf/Makefile.kern.inc: revision 1.258 sys/arch/arm/fdt/psci_fdt.h: revision 1.1 sys/arch/arm/sunxi/sunxi_resets.c: revision 1.1 sys/arch/evbarm/conf/files.sunxi: revision 1.1 sys/arch/evbarm/fdt/fdt_machdep.c: revision 1.8 sys/arch/evbarm/fdt/fdt_machdep.c: revision 1.9 sys/arch/arm/samsung/files.exynos: revision 1.22 distrib/utils/embedded/conf/armv7.conf: revision 1.13 sys/arch/arm/samsung/files.exynos: revision 1.23 sys/arch/evbarm/conf/std.tegra: revision 1.15 distrib/utils/embedded/conf/armv7.conf: revision 1.14 sys/arch/arm/samsung/files.exynos: revision 1.24 distrib/utils/embedded/conf/armv7.conf: revision 1.15 sys/arch/evbarm/sunxi/genassym.cf: revision 1.1 sys/arch/arm/samsung/exynos_fdt.c: file removal sys/dev/fdt/fdt_pinctrl.c: revision 1.4 sys/arch/arm/samsung/exynos_sysmmu.c: revision 1.2 sys/arch/arm/sunxi/sun8i_h3_gpio.c: revision 1.1 sys/arch/arm/sunxi/sunxi_twi.c: revision 1.1 sys/dev/usb/ehci.c: revision 1.255 sys/arch/arm/sunxi/sunxi_twi.c: revision 1.2 sys/arch/arm/sunxi/sun8i_a83t_ccu.h: revision 1.1 sys/dev/ic/dwc_mmc.c: revision 1.11 sys/arch/arm/cortex/gic.c: revision 1.24 distrib/evbarm/instkernel/ramdisk/Makefile: revision 1.17 etc/etc.evbarm/Makefile.inc: revision 1.87 etc/etc.evbarm/Makefile.inc: revision 1.88 sys/arch/arm/fdt/gic_fdt.c: revision 1.5 etc/Makefile: revision 1.429 sys/arch/arm/fdt/gic_fdt.c: revision 1.6 sys/arch/arm/fdt/gic_fdt.c: revision 1.7 sys/arch/arm/sunxi/sunxi_gpio.c: revision 1.1 sys/arch/arm/sunxi/sunxi_gpio.c: revision 1.2 sys/arch/evbarm/conf/std.sunxi: revision 1.1 sys/arch/arm/sunxi/sunxi_gpio.c: revision 1.3 sys/arch/evbarm/conf/std.sunxi: revision 1.2 sys/arch/arm/sunxi/sunxi_gpio.c: revision 1.4 sys/arch/evbarm/conf/std.sunxi: revision 1.3 sys/arch/arm/sunxi/sunxi_gpio.c: revision 1.5 sys/arch/arm/sunxi/sunxi_ccu_div.c: revision 1.1 sys/dev/gpio/gpiovar.h: revision 1.17 sys/arch/arm/sunxi/sunxi_gpio.c: revision 1.6 sys/arch/arm/sunxi/sunxi_gpio.c: revision 1.7 sys/arch/arm/sunxi/sunxi_gpio.c: revision 1.8 sys/arch/arm/sunxi/sunxi_rsb.h: revision 1.1 sys/arch/arm/samsung/exynos_i2c.c: revision 1.12 sys/dev/fdt/fdtvar.h: revision 1.21 sys/arch/evbarm/sunxi/sunxi_start.S: revision 1.1 sys/arch/arm/samsung/exynos_i2c.c: revision 1.13 sys/dev/fdt/fdtvar.h: revision 1.22 sys/arch/evbarm/conf/SUNXI: revision 1.10 sys/dev/fdt/fdtvar.h: revision 1.23 sys/arch/evbarm/conf/SUNXI: revision 1.11 sys/dev/fdt/gpioleds.c: revision 1.1 sys/dev/fdt/fdtvar.h: revision 1.24 sys/arch/evbarm/conf/SUNXI: revision 1.12 sys/arch/evbarm/conf/SUNXI: revision 1.13 sys/arch/arm/cortex/gic.c: revision 1.30 sys/arch/evbarm/conf/SUNXI: revision 1.14 sys/arch/evbarm/conf/SUNXI: revision 1.15 sys/arch/evbarm/conf/SUNXI: revision 1.16 sys/arch/arm/sunxi/sunxi_emac.c: revision 1.1 etc/Makefile: revision 1.430 sys/arch/arm/sunxi/sunxi_emac.c: revision 1.2 etc/Makefile: revision 1.431 sys/arch/evbarm/conf/VEXPRESS_A15: revision 1.17 sys/arch/arm/sunxi/sunxi_emac.c: revision 1.3 sys/arch/arm/sunxi/sunxi_emac.c: revision 1.4 sys/arch/arm/samsung/exynos5422_clock.c: revision 1.6 sys/arch/arm/samsung/exynos_platform.c: revision 1.1 sys/dev/ofw/ofw_subr.c: revision 1.29 sys/arch/arm/samsung/exynos_platform.c: revision 1.2 sys/arch/evbarm/conf/mk.vexpress: revision 1.3 sys/arch/arm/samsung/exynos_platform.c: revision 1.3 sys/arch/evbarm/conf/mk.vexpress: revision 1.4 sys/arch/arm/samsung/exynos_platform.c: revision 1.4 sys/arch/arm/arm/psci.h: revision 1.1 sys/arch/arm/samsung/exynos_platform.c: revision 1.5 sys/arch/arm/samsung/exynos_platform.c: revision 1.6 sys/arch/evbarm/fdt/fdt_machdep.c: revision 1.10 external/bsd/mdocml/bin/mandoc/Makefile: revision 1.12 sys/dev/fdt/files.fdt: revision 1.17 sys/dev/fdt/files.fdt: revision 1.18 sys/dev/fdt/files.fdt: revision 1.19 sys/arch/arm/samsung/exynos_sscom.c: revision 1.8 sys/arch/arm/sunxi/sun8i_a83t_ccu.c: revision 1.1 sys/arch/arm/sunxi/sunxi_mmc.c: revision 1.1 sys/arch/arm/samsung/exynos_sscom.c: revision 1.9 sys/arch/arm/conf/files.arm: revision 1.133 sys/arch/arm/samsung/mct_var.h: revision 1.5 sys/arch/arm/sunxi/sunxi_platform.c: revision 1.1 sys/arch/arm/sunxi/sunxi_platform.c: revision 1.2 sys/arch/evbarm/conf/std.vexpress: revision 1.6 sys/arch/arm/sunxi/sunxi_platform.c: revision 1.3 sys/arch/arm/sunxi/sun6i_a31_gpio.c: revision 1.1 sys/arch/arm/sunxi/sunxi_platform.c: revision 1.4 sys/arch/arm/sunxi/sun6i_a31_gpio.c: revision 1.2 sys/arch/arm/sunxi/files.sunxi: revision 1.1 sys/dev/ofw/ofw_subr.c: revision 1.30 sys/arch/arm/sunxi/files.sunxi: revision 1.2 sys/dev/ofw/openfirm.h: revision 1.35 sys/arch/arm/sunxi/files.sunxi: revision 1.3 sys/dev/ofw/openfirm.h: revision 1.36 sys/arch/arm/sunxi/files.sunxi: revision 1.4 sys/arch/arm/sunxi/files.sunxi: revision 1.5 sys/arch/evbarm/exynos/exynos_machdep.c: file removal sys/arch/arm/sunxi/sunxi_gpio.h: revision 1.1 sys/arch/arm/samsung/sscom.c: revision 1.9 sys/arch/arm/sunxi/files.sunxi: revision 1.6 sys/dev/fdt/ohci_fdt.c: revision 1.1 sys/arch/arm/sunxi/sunxi_usbphy.c: revision 1.1 sys/arch/arm/sunxi/sunxi_gpio.h: revision 1.2 sys/arch/arm/sunxi/files.sunxi: revision 1.7 sys/arch/arm/sunxi/sunxi_usbphy.c: revision 1.2 sys/arch/arm/sunxi/sunxi_gpio.h: revision 1.3 sys/arch/arm/sunxi/files.sunxi: revision 1.8 sys/arch/arm/sunxi/sunxi_usbphy.c: revision 1.3 sys/arch/arm/sunxi/files.sunxi: revision 1.9 sys/arch/arm/samsung/exynos_sscom.c: revision 1.10 sys/arch/evbarm/conf/mk.tegra: revision 1.5 sys/arch/arm/samsung/exynos_dwcmmc.c: revision 1.4 sys/arch/evbarm/conf/mk.tegra: revision 1.6 sys/arch/evbarm/conf/EXYNOS: revision 1.15 sys/arch/evbarm/conf/EXYNOS: revision 1.16 sys/arch/evbarm/conf/EXYNOS: revision 1.17 sys/arch/arm/sunxi/sunxi_ccu.c: revision 1.1 sys/arch/evbarm/conf/EXYNOS: revision 1.19 sys/arch/arm/sunxi/sunxi_ccu.c: revision 1.2 sys/arch/arm/sunxi/sunxi_ccu.c: revision 1.3 sys/arch/arm/sunxi/sunxi_ccu.c: revision 1.4 sys/arch/arm/sunxi/sunxi_ccu.c: revision 1.5 sys/arch/arm/sunxi/sunxi_emac.h: revision 1.1 sys/arch/evbarm/conf/mk.sunxi: revision 1.1 sys/arch/evbarm/include/bootconfig.h: revision 1.7 sys/arch/evbarm/conf/TEGRA: revision 1.24 sys/arch/arm/arm/psci.c: revision 1.1 sys/dev/led.c: revision 1.1 sys/dev/led.c: revision 1.2 sys/arch/arm/arm/psci_arm.S: revision 1.1 sys/arch/arm/sunxi/sunxi_ccu_gate.c: revision 1.1 sys/arch/arm/sunxi/sunxi_ccu_gate.c: revision 1.2 sys/dev/fdt/ehci_fdt.c: revision 1.1 sys/dev/fdt/ehci_fdt.c: revision 1.2 sys/arch/arm/sunxi/sun6i_a31_ccu.h: revision 1.1 sys/arch/evbarm/conf/EXYNOS: revision 1.21 sys/arch/arm/sunxi/files.sunxi: revision 1.10 sys/arch/arm/sunxi/files.sunxi: revision 1.11 sys/dev/fdt/fdtbus.c: revision 1.14 sys/arch/arm/sunxi/sunxi_mmc.h: revision 1.1 sys/arch/arm/samsung/exynos5422_dma.c: file removal usr.bin/config/mkmakefile.c: revision 1.69 sys/conf/files: revision 1.1178 sys/arch/arm/sunxi/sunxi_platform.h: revision 1.1 sys/arch/evbarm/exynos/exynos_start.S: revision 1.4 sys/arch/arm/samsung/exynos_pinctrl.c: revision 1.11 sys/arch/arm/samsung/exynos_pinctrl.c: revision 1.12 sys/arch/arm/sunxi/sunxi_rtc.c: revision 1.1 sys/arch/arm/sunxi/sun8i_h3_ccu.h: revision 1.1 sys/arch/arm/samsung/exynos5410_clock.c: revision 1.1 sys/arch/arm/samsung/exynos5410_clock.c: revision 1.2 sys/arch/evbarm/conf/SUNXI: revision 1.1 external/bsd/elftosb/usr.sbin/elftosb/Makefile: revision 1.5 sys/arch/evbarm/conf/SUNXI: revision 1.2 sys/arch/arm/fdt/psci_fdt.c: revision 1.1 sys/arch/evbarm/conf/SUNXI: revision 1.3 sys/arch/evbarm/conf/SUNXI: revision 1.4 sys/arch/evbarm/conf/files.exynos: revision 1.3 sys/arch/evbarm/conf/SUNXI: revision 1.5 sys/arch/evbarm/conf/SUNXI: revision 1.6 sys/arch/arm/sunxi/sunxi_ccu_nm.c: revision 1.1 sys/dev/fdt/fixedfactorclock.c: revision 1.1 sys/dev/fdt/fdt_subr.c: revision 1.14 sys/arch/evbarm/conf/SUNXI: revision 1.7 sys/arch/arm/sunxi/sunxi_ccu_nm.c: revision 1.2 sys/arch/arm/sunxi/sun8i_a83t_gpio.c: revision 1.1 sys/dev/fdt/fdt_subr.c: revision 1.15 sys/arch/evbarm/conf/SUNXI: revision 1.8 sys/arch/arm/sunxi/sunxi_ccu_nm.c: revision 1.3 sys/dev/ic/dwc_mmc_reg.h: revision 1.6 sys/dev/fdt/fdt_subr.c: revision 1.16 sys/arch/evbarm/conf/SUNXI: revision 1.9 usr.bin/config/mkmakefile.c: revision 1.70 sys/dev/fdt/fdt_phy.c: revision 1.1 sys/arch/evbarm/conf/ODROID-XU: file removal sys/arch/arm/fdt/arm_fdt.c: revision 1.4 sys/arch/arm/samsung/exynos_reg.h: revision 1.14 sys/conf/files: revision 1.1180 sys/arch/arm/samsung/exynos_reg.h: revision 1.15 sys/arch/arm/sunxi/sunxi_ccu.h: revision 1.1 sys/arch/arm/sunxi/sunxi_ccu.h: revision 1.2 sys/arch/arm/sunxi/sunxi_ccu.h: revision 1.3 sys/arch/arm/sunxi/sunxi_ccu.h: revision 1.4 sys/arch/arm/sunxi/sunxi_ccu.h: revision 1.5 sys/arch/arm/sunxi/sunxi_ccu.h: revision 1.6 sys/dev/ic/dwc_mmc_var.h: revision 1.6 sys/arch/arm/samsung/exynos_combiner.c: revision 1.7 sys/arch/evbarm/exynos/platform.h: revision 1.2 sys/arch/arm/fdt/files.fdt: revision 1.12 sys/arch/evbarm/conf/std.exynos: revision 1.2 sys/arch/evbarm/conf/std.exynos: revision 1.3 sys/arch/arm/rockchip/rockchip_dwcmmc.c: revision 1.6 sys/arch/arm/sunxi/sunxi_com.c: revision 1.1 sys/dev/led.h: revision 1.1 sys/arch/evbarm/conf/std.exynos: revision 1.5 sys/arch/arm/sunxi/sunxi_com.c: revision 1.2 sys/arch/evbarm/conf/files.evbarm: revision 1.26 usr.bin/config/defs.h: revision 1.99 sys/arch/arm/fdt/arm_fdtvar.h: revision 1.6 sys/arch/arm/samsung/exynos_soc.c: revision 1.32 sys/arch/arm/sunxi/sun6i_a31_ccu.c: revision 1.1 sys/arch/arm/sunxi/sun6i_a31_ccu.c: revision 1.2 sys/arch/arm/samsung/mct.c: revision 1.11 sys/arch/evbarm/conf/ODROID-U: file removal sys/arch/arm/samsung/mct.c: revision 1.12 sys/arch/arm/sunxi/sunxi_ccu_nkmp.c: revision 1.1 sys/arch/arm/sunxi/sunxi_ccu_nkmp.c: revision 1.2 sys/arch/arm/sunxi/sunxi_ccu_nkmp.c: revision 1.3 sys/arch/arm/sunxi/sunxi_ccu_nkmp.c: revision 1.4 Get the EXYNOS kernel building again with recent FDT changes. Untested. Use arm_fdt_cpu_hatch and add mmu entry for DTB Fix exynos5 devmap, bootstrap, and implement early_putchar. Calculate UART frequency based on bootloader config. Fix KERNEL_BASE_PHYS (how did this ever work?) Avoid divide-by-zero for unconfigured PLLs Correctly initialize i2cbus attach args. Add delay and enable mct timecounter. Fix build w/o VERBOSE_INIT_ARM Remove ODROID-U and ODROID-XU kernel configs as they no longer work. - Replace CONSADDR with SSCOM2CONSOLE in example - Remove gtmr (Exynos5422 uses mct) - cinclude EXYNOS.local instead of TEGRA.local Use fdtbus_intr_establish to hook in block interrupts instead of intr_establish. Simplify MCT; just enable it and then attach an ARMv7 generic timer. Add support for building DTB files during kernel build, from christos. build vexpress-v2p-ca15-tc1.dtb with the kernel build tegra124-apalis-eval.dtb, tegra124-jetson-tk1.dtb, tegra124-nyan-big.dtb, tegra124-nyan-blaze.dtb, and tegra124-venice2.dtb with the kernel Allow multiline makeoptions to work by quoting the newline.. Bump for quoting makeoptions with multiple lines. un-c99 bump required config version for multiline makeoptions feature Set DTS makeoption in kernel config Assign DTB files to a variable so we can make -V DTB put the dtb files with their kernels. no need for debug printing. Don't assume that CPU index = GIC CPU interface number. We can determine the current CPU interface number by reading from the read-only GICD_ITARGETSR0 through GICD_ITARGETSR7 registers. This gets interrupts working on Exynos 5422, where the boot processor has GIC CPU interface #4. use -v to get the expanded variable. Use -v to get the expanded variables. Get baud rate from sclk_uartN instead of uartN. Print IRQ number at attach. Fix PLL con0 register locations and add uart clocks Disable exyortc for now, it doesn't work. More or less a rewrite of dwc_mmc, based on awin_mmc, adding DMA support. Update for new dwc_mmc driver Fix dmesg Add Exynos 5410 clock controller driver. Fix a few typos in clock parent names for mmc clocks. From jmcneill@ Update for new dwc_mmc driver Implement platform reset for exynos5 Attach fdtbus to a /clocks node with no compatible string. Add support for ARM Power State Coordination Interface (PSCI). Support interrupt sharing. Add initial support for Allwinner H3 SoC. ARM Trusted Firmware reserves SGIs 8-15 for secure use. Even without ATF, U-Boot on some platforms may use SGIs in this range for the PSCI implementation. Change ARMGIC_IPI_BASE to 0 from (16 - NIPI) and add a compile-time assert to ensure that we don't end up with a conflict. Add H3 MMC support SD/MMC clock fixes Add FDT PHY interface. Add glue for generic ehci/ohci bindings. Rename a variable, NFC. Support parents in different clock domains. Add USB stuff. Doesn't quite work yet. Synopsys DesignWare APB UART needs "options COM_AWIN" for now. Add i2c glue. Add RTC driver. PHY registers start at index 1. Now USB works. Don't allow sharing edge and level triggered interrupts. Add arm_fdt_memory_dump helper for dumping physical addresses from ddb Print clocks with aprint_debug Remove unused defines Add fdtbus_get_string helper Add of_search_compatible, which searches an array of compat_data structures for a matching "compatible" entry matching the supplied OFW node. This allows us to associate data with compatible strings. Add driver for Allwinner Gigabit Ethernet (EMAC) as found in sun8i and later family SoCs. This is a port of my FreeBSD driver which has been confirmed to work on Allwinner H3, A83T, and A64 SoCs. Fix dmesg Add basic support for Allwinner A31. Add basic FDT GPIO support. Fix the pinctrl api to match the spec. A pinctrl config can have more than one xref, and an xref may have specifier data associated with it. Enable sunxi pinctrl support Adjust to new pinctrl API Add P2WI/RSB driver, based on awin_p2wi.c. Fix typo in a compat string. Configure pin defaults at attach No need to explicitly set pinctrl config 0 now Fix some register definitions. Disallow sharing between MPSAFE and non-MPSAFE handlers. Add of_match_compat_data. This routine searches an array of compat_data structures for a matching "compatible" entry matching the supplied OFW node. Add options __HAVE_CPU_UAREA_ALLOC_IDLELWP Add support for reserved memory and MEMORY_DISK_DYNAMIC for FDT-based kernels. the extent code cannot use the full range of u_long, so ignore the last page before 4GB too. ok jmcneill@ Copy install ramdisk to releasedir. Provide both a raw ffs and Legacy U-Boot version of it. Replace HUMMINGBIRD_A31 with SUNXI kernel on armv7.img and include .dtb files for SUNXI and TEGRA kernels on the MSDOS partition. Let the controller provide a default name for pins. This makes pins easier to locate when we have multiple banks and a variable number of pins per bank. Attach gpio(4) to sunxigpio Test for kernel build directory before reading DTB list Add support for Allwinner A83T SoC. Add A83T files Fixup busdma sync and locking in the RX path. Disable batch RX/TX ints. Fix AHB2 register definition and explicitly set AHB2 parent to PLL_PERIPH0/2 -- this gives us 50% more bus bandwidth for emac Restore TX_INTERVAL_DEFAULT to 64 Drop the sunxi_emac_rx_batch feature. It was originally designed to reduce the amount of mutex unlock/lock cycles during the RX path on FreeBSD and if_input, but it is not required to drop the lock before calling if_percpuq_enqueue on NetBSD. Write back the data value instead of mask in sunxi_gpio_write Add a helper for exposing LED controls via sysctl. Add GPIO LED driver. add gpioleds Add misc. gates and resets driver, and explicitly enable PIO clocks at attach. Add fdtbus_get_string_index helper. Add driver for fixed-factor clocks. Add ffclock Remove the requirement for ehci to attach after companion devices. "go for it" - skrll@ Remove the hack to find companion devices and just assume 1 companion if ETTF flag is not set. Remove pass numbers for ehci/ohci now that the attach order no longer matters Use unsigned char for ctype functions, suggested by christos Add : to body of populate_sunxi to appease bash. port-evbarm/52388: Fix number of args to a debug printf.
1.21.2.1	05-Jun-2017	snj	Pull up following revision(s) (requested by skrll in ticket #8): sys/arch/arm/cortex/gic.c: revision 1.22 Initialise all the SGI/PPI priorities for all CPUs to mask the interrupts
1.32.2.5	26-Nov-2018	pgoyette	Sync with HEAD, resolve a couple of conflicts
1.32.2.4	30-Sep-2018	pgoyette	Ssync with HEAD
1.32.2.3	28-Jul-2018	pgoyette	Sync with HEAD
1.32.2.2	02-May-2018	pgoyette	Synch with HEAD
1.32.2.1	07-Apr-2018	pgoyette	Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
1.34.2.2	21-Apr-2020	martin	Sync with HEAD
1.34.2.1	10-Jun-2019	christos	Sync with HEAD
1.38.10.1	20-Apr-2020	bouyer	Sync with HEAD
1.38.4.1	31-Mar-2021	martin	Pull up following revision(s) (requested by skrll in ticket #1238): sys/arch/arm/cortex/gic.c: revision 1.47 Only target the boot cpu for real with SPI interrupts. I tried to do this back in 2014, but somehow I missed a spot. This is a quick-and-dirty fix for the USB stack which expects transfer completions to be in-order. If interrupts happen across the CPUs then this isn't guaranteed (yet). kern/55243 panic at usb_transfer_complete() on raspberry pi 4
1.42.2.2	03-Apr-2021	thorpej	Sync with HEAD.
1.42.2.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.46.2.1	03-Apr-2021	thorpej	Sync with HEAD.
1.3	30-May-2017	jmcneill	Use an FDT-based ARM_INTR_IMPL for Tegra.
1.2	09-Apr-2014	matt	branches: 1.2.4; add helper macros.
1.1	01-Sep-2012	matt	branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8; 1.1.16; 1.1.18; Add Cortex-A9 support including the ARM Generic Interrupt Controller and the A9 Global Timer / Watchdog.
1.1.18.1	10-Aug-2014	tls	Rebase.
1.1.16.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.1.16.1	01-Sep-2012	matt	file gic_intr.h was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.1.8.1	18-May-2014	rmind	sync with head
1.1.6.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.1.6.1	01-Sep-2012	matt	file gic_intr.h was added on branch matt-nb6-plus on 2012-11-28 22:40:26 +0000
1.1.4.3	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.1.4.2	30-Oct-2012	yamt	sync with head
1.1.4.1	01-Sep-2012	yamt	file gic_intr.h was added on branch yamt-pagecache on 2012-10-30 17:19:00 +0000
1.1.2.2	03-Dec-2017	jdolecek	update from HEAD
1.1.2.1	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.2.4.1	28-Aug-2017	skrll	Sync with HEAD
1.12	22-Nov-2020	jmcneill	Add GICD_CTRL_EnableGrp1S definition.
1.11	02-May-2019	jmcneill	branches: 1.11.10; Fix definition of GICD_IROUTER; the input to this macro is the INTID, which can be a value between 32 and 1019.
1.10	24-Nov-2018	skrll	Handle ThunderX errata
1.9	13-Nov-2018	jmcneill	Update GICD_CTLR reg bit definitions to reflect the layout of the register when either in non-secure state or for a system that only supports a single state.
1.8	09-Nov-2018	jmcneill	Add support for GICv3 Locality-specific Periphal Interrupts (LPIs) and the Interrupt Translation Service (ITS).
1.7	08-Aug-2018	jmcneill	Update for GICv3
1.6	22-Jun-2017	skrll	branches: 1.6.4; 1.6.6; Naming consistency for (as yet) unused register
1.5	09-Jun-2015	skrll	Correct a comment
1.4	05-Jun-2015	skrll	Add an define for spurious interrupt number 1022
1.3	27-Apr-2014	matt	branches: 1.3.4; When dealing with the PMR register, only use non-secure priority values.
1.2	28-Mar-2014	matt	branches: 1.2.2; Various MP changes.
1.1	01-Sep-2012	matt	branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8; 1.1.16; Add Cortex-A9 support including the ARM Generic Interrupt Controller and the A9 Global Timer / Watchdog.
1.1.16.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.1.16.1	01-Sep-2012	matt	file gic_reg.h was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.1.8.1	18-May-2014	rmind	sync with head
1.1.6.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.1.6.1	01-Sep-2012	matt	file gic_reg.h was added on branch matt-nb6-plus on 2012-11-28 22:40:27 +0000
1.1.4.3	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.1.4.2	30-Oct-2012	yamt	sync with head
1.1.4.1	01-Sep-2012	yamt	file gic_reg.h was added on branch yamt-pagecache on 2012-10-30 17:19:00 +0000
1.1.2.2	03-Dec-2017	jdolecek	update from HEAD
1.1.2.1	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.2.2.1	10-Aug-2014	tls	Rebase.
1.3.4.3	28-Aug-2017	skrll	Sync with HEAD
1.3.4.2	22-Sep-2015	skrll	Sync with HEAD
1.3.4.1	06-Jun-2015	skrll	Sync with HEAD
1.6.6.1	10-Jun-2019	christos	Sync with HEAD
1.6.4.2	26-Nov-2018	pgoyette	Sync with HEAD, resolve a couple of conflicts
1.6.4.1	06-Sep-2018	pgoyette	Sync with HEAD Resolve a couple of conflicts (result of the uimin/uimax changes)
1.11.10.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.5	30-Oct-2021	jmcneill	Implement gic_splraise and the gic_splx fast path in asm (armv8).
1.4	26-Sep-2021	jmcneill	Add missing insn barrier
1.3	20-Sep-2021	jmcneill	Make _splraise/_spllower/splx functions available to modules again.
1.2	18-Sep-2021	jmcneill	gic_splx: performance optimizations Avoid any kind of register access (DAIF, PMR, etc), barriers, and atomic operations in the common case where no interrupt fires between spl being raised and lowered. This introduces a per-CPU return address (ci_splx_restart) used by the vector handler to restart a sequence in splx that compares the new ipl with the per-CPU hardware priority state stored in ci_hwpl.
1.1	10-Aug-2021	jmcneill	Use custom spl funcs for GIC and avoid unnecessary pmr register accesses in splx.
1.1	10-Aug-2021	jmcneill	Use custom spl funcs for GIC and avoid unnecessary pmr register accesses in splx.
1.3	31-Oct-2021	jmcneill	Reload tpidr_el1 into x3 and re-test newipl vs cpl on restart.
1.2	30-Oct-2021	jmcneill	Add __HAVE_PREEMPTION support to gic_splfuncs asm funcs. "looks right to me" - thorpej
1.1	30-Oct-2021	jmcneill	Implement gic_splraise and the gic_splx fast path in asm (armv8).
1.11	14-Mar-2021	skrll	Remove an unnecessary if statement in gic_v2m_msi_alloc when finding a 'count' that fits the available.
1.10	11-Dec-2020	jmcneill	Preserve ST Lower and Upper fields when clearing Mask bit in the MSI-X vector control register.
1.9	07-May-2020	jmcneill	branches: 1.9.2; Do not store a pointer to the passed in struct pci_attach_args
1.8	02-Dec-2019	msaitoh	Use PCI_MSIX_"TBL"BIR_MASK instead of PCI_MSIX_"PBA"BIR_MASK for MSI-X table. This is not a real bug because both macros have the same value.
1.7	14-Oct-2019	jmcneill	Add support for Amazon's Graviton MSI controller. Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of sending messages to a fixed address with the SPI as data, the Graviton's GICv2m uses a different address for each vector with "don't care" as data.
1.6	17-Jun-2019	jmcneill	branches: 1.6.2; - Disable MSI/MSI-X when making changes - MSI: Write the vector count to the Multi Message Enable (MME) field - MSI: Set DATA to the first LPI number, not the last
1.5	07-Dec-2018	jakllsch	branches: 1.5.4; fix a paste-o in a panic message
1.4	16-Nov-2018	jmcneill	branches: 1.4.2; Add intr_establish_xname support to arm and expose it to intrctl
1.3	31-Oct-2018	jmcneill	Add MSI-X support.
1.2	30-Oct-2018	jmcneill	Fail gracefully when an attempt to allocate MSI vectors is made on a device without MSI capabilities.
1.1	21-Oct-2018	jmcneill	Add support for PCI MSI using ARM GICv2m.
1.4.2.3	26-Dec-2018	pgoyette	Sync with HEAD, resolve a few conflicts
1.4.2.2	26-Nov-2018	pgoyette	Sync with HEAD, resolve a couple of conflicts
1.4.2.1	16-Nov-2018	pgoyette	file gic_v2m.c was added on branch pgoyette-compat on 2018-11-26 01:52:18 +0000
1.5.4.4	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.5.4.3	08-Apr-2020	martin	Merge changes from current as of 20200406
1.5.4.2	10-Jun-2019	christos	Sync with HEAD
1.5.4.1	07-Dec-2018	christos	file gic_v2m.c was added on branch phil-wifi on 2019-06-10 22:05:52 +0000
1.6.2.2	07-May-2020	martin	Pull up following revision(s) (requested by jmcneill in ticket #895): sys/arch/arm/cortex/gic_v2m.h: revision 1.3 sys/arch/arm/cortex/gic_v2m.c: revision 1.9 Do not store a pointer to the passed in struct pci_attach_args
1.6.2.1	15-Oct-2019	martin	Pull up following revision(s) (requested by jmcneill in ticket #334): sys/arch/arm/cortex/gic_v2m.c: revision 1.7 sys/arch/arm/acpi/gicv3_acpi.c: revision 1.5 sys/arch/arm/acpi/files.acpi: revision 1.8 sys/arch/arm/acpi/gic_acpi.c: revision 1.4 sys/arch/arm/cortex/files.cortex: revision 1.13 sys/arch/arm/acpi/gic_v2m_acpi.c: revision 1.1 sys/arch/arm/acpi/gic_v2m_acpi.h: revision 1.1 sys/arch/arm/cortex/gic_v2m.h: revision 1.2 Add support for Amazon's Graviton MSI controller. Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of sending messages to a fixed address with the SPI as data, the Graviton's GICv2m uses a different address for each vector with "don't care" as data.
1.9.2.2	03-Apr-2021	thorpej	Sync with HEAD.
1.9.2.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.3	07-May-2020	jmcneill	Do not store a pointer to the passed in struct pci_attach_args
1.2	14-Oct-2019	jmcneill	Add support for Amazon's Graviton MSI controller. Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of sending messages to a fixed address with the SPI as data, the Graviton's GICv2m uses a different address for each vector with "don't care" as data.
1.1	21-Oct-2018	jmcneill	branches: 1.1.2; 1.1.6; 1.1.8; Add support for PCI MSI using ARM GICv2m.
1.1.8.2	07-May-2020	martin	Pull up following revision(s) (requested by jmcneill in ticket #895): sys/arch/arm/cortex/gic_v2m.h: revision 1.3 sys/arch/arm/cortex/gic_v2m.c: revision 1.9 Do not store a pointer to the passed in struct pci_attach_args
1.1.8.1	15-Oct-2019	martin	Pull up following revision(s) (requested by jmcneill in ticket #334): sys/arch/arm/cortex/gic_v2m.c: revision 1.7 sys/arch/arm/acpi/gicv3_acpi.c: revision 1.5 sys/arch/arm/acpi/files.acpi: revision 1.8 sys/arch/arm/acpi/gic_acpi.c: revision 1.4 sys/arch/arm/cortex/files.cortex: revision 1.13 sys/arch/arm/acpi/gic_v2m_acpi.c: revision 1.1 sys/arch/arm/acpi/gic_v2m_acpi.h: revision 1.1 sys/arch/arm/cortex/gic_v2m.h: revision 1.2 Add support for Amazon's Graviton MSI controller. Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of sending messages to a fixed address with the SPI as data, the Graviton's GICv2m uses a different address for each vector with "don't care" as data.
1.1.6.3	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.1.6.2	10-Jun-2019	christos	Sync with HEAD
1.1.6.1	21-Oct-2018	christos	file gic_v2m.h was added on branch phil-wifi on 2019-06-10 22:05:52 +0000
1.1.2.2	26-Nov-2018	pgoyette	Sync with HEAD, resolve a couple of conflicts
1.1.2.1	21-Oct-2018	pgoyette	file gic_v2m.h was added on branch pgoyette-compat on 2018-11-26 01:52:18 +0000
1.56	04-Sep-2025	rin	gicv3: Some more left-shift v.s. int fixes Suggested by msaitoh@, thanks!
1.55	04-Sep-2025	rin	gicv3: Appease KUBSAN, otherwise NFC
1.54	26-Jun-2022	jmcneill	branches: 1.54.4; 1.54.12; build fix: remove includes of opt_gic.h
1.53	25-Jun-2022	jmcneill	gicv3: Treat all IPLs below IPL_VM as IPL_NONE for hwpl mappings
1.52	25-Jun-2022	jmcneill	Remove GIC_SPLFUNCS.
1.51	25-Jun-2022	jmcneill	pic: Update ci_cpl in pic_set_priority callback. Not all ICs need interrupts disabled to update the priority. DAIF accesses are not cheap, so push the update of ci_cpl from pic_set_priority to the IC's pic_set_priority callback, and let the IC driver determine whether or not it needs interrupts disabled.
1.50	28-Mar-2022	riastradh	arm/cortex: Use container_of, not bespoke offsetof arithmetic.
1.49	02-Oct-2021	skrll	Trailing whitespace
1.48	26-Sep-2021	jmcneill	If an SGI or PPI is established after interrupts are enabled, make sure we unblock the source on _all_ CPUs and not just the CPU that is establishing the interrupt.
1.47	11-Sep-2021	jmcneill	GIC: Support SPI affinity routing before secondary CPUs have hatched. Instead of reading MPIDR from CPU init to determine a routing target, trust system configuration data (Devicetree or ACPI) to properly fill in ci_cpuid. This allows for SPI affinity routing to work before secondary CPUs are hatched; previously, one of two things would happen: a) If 1ofN distribution is supported, the SPI could be distributed to any participating PE. b) If 1ofN distribution is not supported, the SPI would not be forwarded and would stay pending.
1.46	10-Aug-2021	jmcneill	Make gic_splfuncs optional and disable it by default until it has had more testing.
1.45	10-Aug-2021	jmcneill	Use custom spl funcs for GIC and avoid unnecessary pmr register accesses in splx.
1.44	28-Mar-2021	jmcneill	Disable 1ofN distribution of SPIs by default. This is a workaround for an issue in the USB stack -- signaling transfer complete on multiple PEs can cause transfer completions to be processed out of order.
1.43	23-Feb-2021	jmcneill	branches: 1.43.2; If we are committing a deferred splhigh() to hardware, no need to continue.
1.42	21-Feb-2021	jmcneill	Keep current hardware priority value in struct cpu_info and use it instead of reading icc_pmr_el1 in gicv3_set_priority.
1.41	09-Feb-2021	ryo	fix build without MULTIPROCESSOR
1.40	07-Feb-2021	jmcneill	Optimize hardware priority updates. In gicv3_set_priority, read the current priority mask and only update it if we are lowering the priority. The hardware priority filter is raised only after taking an interrupt. This makes splfoo/splx without an interrupt in between considerably cheaper as PMR writes are relatively expensive compared to reads. While here, avoid an extra daif read when dispatching interrupts by using ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros.
1.39	16-Jan-2021	jmcneill	Remove MAXCPUS dependency.
1.38	22-Dec-2020	jmcneill	When lpiconf flushing is required, make sure to flush to PoC and not PoU. Spotted by nick.
1.37	11-Dec-2020	jmcneill	Fix spelling in comment.
1.36	04-Dec-2020	jmcneill	gicv3: Only use 1 of N SPI distribution when the feature is available. A GICv3+ implementation is not guaranteed to support 1 of N SPI distribution. Support for this feature is indicated in GICD_TYPER.No1N. When No1N=1, route all interrupts to the primary PE by default and only allow a single CPU target when updating affinity.
1.35	24-Nov-2020	jmcneill	Improve detection of NS vs S views of priorities. For PMR, write a 0 to bit7 and see if it sticks. This is only possible from NS EL1 if we have a non-secure view of ICC_PMR_EL1. For int priorities (GICD/GICR interfaces and LPIs), assume that the GICD_CTLR.DS bit is telling us the truth. RK3399 is special here when using the vendor bootloader, so keep the auto-detection from the previous commit but limit the scope to only run on RK3399 SOCs.
1.34	22-Nov-2020	jmcneill	Fix interrupt priorities on N1 SDP. The GICv3 architecture specification is not clear on the NS view of priority registers, and there doesn't seem to be any consistency in how these are implemented in both real and emulated environments. The previous fix for this issue was meant to detect what we thought at the time was a bug on the Rockchip RK3399. At that time the theory was somehow EL1 has a secure view of the hardware, and this is causing us to have the wrong view of IPRIORITYRn based on IHI0069F section 4.8.6 "Software accesses of interrupt priority". But it turns out that this is not the full picture. While I was able to confirm that yes, we do have secure access to the GIC on RK3399 from EL1, the view of IPRIORITYRn differs depending on whether you are using the Rockchip TF-A as included with https://github.com/ayufan-rock64/linux-u-boot (shifted view), or mainline TF-A from pkgsrc (unshifted view). So to detect this quirk, we need three things: A method to detect if we have S access to GIC registers, a method to see how many PMR bits are implemented, and a method to see how many IPRIORITYRn bits are implemented. To detect S access, we can try to toggle GICD_CTRL.EnableGrp1S. This bit is either RES0 (security extensions not implemented), RAZ/WI (non-secure access in two security state systems) or RW (secure access in two security state systems). To read the number of PMR and IPRIORITYRn bits supported, we can write all 1s to the register fields and read them back. For the RK3399 (Rockchip TF-A) quirk, we assume a shifted view of IPRIORITYRn if we have detected S accesses, and the PMR and IPRIORITYRn values differ. The S access test is required because some real hardware implementations (Ampere eMAG) were observed to report different PMR and IPRIORITYRn masks, but present an unshifted view of IPRIORITYRn. During testing, I also discovered that QEMU 5.1 requires this shifted view workaround as well -- as far as I can tell, this is a QEMU bug. We can't detect it the same way as RK3399 because security is disabled in the emulated GIC, and the PMR and IPRIORITYRn tests both return 0xff! So now if the GICv3 driver sees this configuration, it assumes that the shifted view is required. Honestly, this feature is so poorly documented that maybe it is better to give up on HW priorities and preemption and use a single flat model like Linux and FreeBSD does. Tested on Arm N1 SDP, ROCKpro64 (RK3399) with Rockchip and pkgsrc TF-A, Pinebook Pro (RK3399), Lenovo HR330A (Ampere eMAG), QEMU 5.1 (gic-version=3), AWS EC2 a1.medium (Graviton).
1.33	21-Nov-2020	jmcneill	Add a per-CPU event counter that counts every time an interrupt handler is preempted by a higher priority interrupt.
1.32	01-Nov-2020	jmcneill	branches: 1.32.2; sc_enabled_sgippi can be updated from any CPU, so use atomic_or/atomic_and
1.31	01-Nov-2020	jmcneill	Remove unused __HAVE_PIC_FAST_SOFTINTS block. It never would have worked if enabled..
1.30	01-Nov-2020	jmcneill	Add an isb() barrier after ICC_SGI1R_EL1 write to prevent reordering with subsequent wfi/wfe instructions. Haven't seen this in practice but I would rather be safe here.
1.29	01-Nov-2020	jmcneill	gicv3_set_priority: ICC_PMR_EL1 is self-synchronizing so no need for isb() here.
1.28	01-Nov-2020	jmcneill	gicv3_irq_handler: No need to call gicv3_set_priority if we are already at the desired ipl.
1.27	01-Nov-2020	jmcneill	gicv3_ipi_send: simplify logic in kcp != NULL case given that we know that the kcpuset will only ever contain one cpu.
1.26	30-Oct-2020	skrll	Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.
1.25	13-Apr-2020	jmcneill	Apply similar fix from gic.c that fixed "left shift of 255 by 24 places cannot be represented in type 'int'" warnings from UBSan.
1.24	13-Feb-2020	jmcneill	branches: 1.24.4; Make intr affinity work with MSIs again
1.23	13-Feb-2020	jmcneill	Since all ITS instances share a common LPI configuration table, used a shared vmem arena to allocate pic irqs. Idea from FreeBSD.
1.22	24-Dec-2019	skrll	branches: 1.22.2; Traiing whitespace
1.21	05-Sep-2019	jmcneill	- Use pic_do_pending_ints in intr handler - Sprinkle isb - Fix PMR bits detection on eMAG, from OpenBSD
1.20	30-Jun-2019	jmcneill	branches: 1.20.2; Fix size of LPI pending table allocation and enable caching of LPI conf and pending tables where possible.
1.19	26-Jun-2019	jmcneill	Change how we detect secure vs non-secure access. Write 0xff to ICC_PMR_EL1 and read back how many bits are implemented, then do the same with a GICD_IPRIORITYR<n> priority value field. If the values differ, assume we have a shifted view of IPRIORITYR.
1.18	17-Jun-2019	jmcneill	Improve priority handling for cases where access is secure, from OpenBSD.
1.17	12-Jun-2019	mrg	revert rev 1.4: >Adjust priority mappings, NFCI it has some unintended change that makes nvme hangy. ok @jmcneill.
1.16	12-Jun-2019	jmcneill	Revert "Route all interrupts to the primary PE by default"
1.15	12-Jun-2019	jmcneill	Route all interrupts to the primary PE by default
1.14	12-Jun-2019	jmcneill	Adjust priority mappings, NFCI
1.13	23-Nov-2018	jmcneill	branches: 1.13.4; Fix LPI pending table size, use correct LPI conf offset in gicv3_lpi_block_irqs, and set bit[7]=1 for G1NS interrupts when writing to the LPI configuration table.
1.12	21-Nov-2018	jmcneill	kcpuset_ffs returns the cpu number plus one, so make sure to subtract it
1.11	17-Nov-2018	jmcneill	Use intr_establish_xname
1.10	15-Nov-2018	jmcneill	Instead of disabling preemption, set the binary point field to the minimum supported value
1.9	13-Nov-2018	jmcneill	Update GICD_CTLR reg bit definitions to reflect the layout of the register when either in non-secure state or for a system that only supports a single state.
1.8	13-Nov-2018	jmcneill	Save a few pages by only allocating LPI pending tables for "ncpu" instead of "MAXCPU" CPUs.
1.7	10-Nov-2018	jmcneill	Implement pic_get_affinity/pic_set_affinity for LPIs via ITS
1.6	10-Nov-2018	jmcneill	Implement pic_get_affinity/pic_set_affinity for SPIs
1.5	09-Nov-2018	jmcneill	Add support for GICv3 Locality-specific Periphal Interrupts (LPIs) and the Interrupt Translation Service (ITS).
1.4	05-Nov-2018	jmcneill	ICC_PMR_EL1 has different encoding than IPRIORITYR. Not 100% sure that this is correct yet, but it works with both RK3399 and QEMU.
1.3	30-Sep-2018	jmcneill	Set NS access bit when writing ICC_PMR_EL1
1.2	11-Aug-2018	jmcneill	branches: 1.2.2; IPI and priority fixes. My RK3399 board boots multiuser now.
1.1	08-Aug-2018	jmcneill	Add GICv3 support.
1.2.2.4	26-Nov-2018	pgoyette	Sync with HEAD, resolve a couple of conflicts
1.2.2.3	20-Oct-2018	pgoyette	Sync with head
1.2.2.2	06-Sep-2018	pgoyette	Sync with HEAD Resolve a couple of conflicts (result of the uimin/uimax changes)
1.2.2.1	11-Aug-2018	pgoyette	file gicv3.c was added on branch pgoyette-compat on 2018-09-06 06:55:26 +0000
1.13.4.5	21-Apr-2020	martin	Sync with HEAD
1.13.4.4	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.13.4.3	08-Apr-2020	martin	Merge changes from current as of 20200406
1.13.4.2	10-Jun-2019	christos	Sync with HEAD
1.13.4.1	23-Nov-2018	christos	file gicv3.c was added on branch phil-wifi on 2019-06-10 22:05:52 +0000
1.20.2.1	22-Sep-2019	martin	Pull up following revision(s) (requested by jmcneill in ticket #222): sys/arch/arm/cortex/gicv3.c: revision 1.21 - Use pic_do_pending_ints in intr handler - Sprinkle isb - Fix PMR bits detection on eMAG, from OpenBSD
1.22.2.1	29-Feb-2020	ad	Sync with head.
1.24.4.1	20-Apr-2020	bouyer	Sync with HEAD
1.32.2.3	03-Apr-2021	thorpej	Sync with HEAD.
1.32.2.2	03-Jan-2021	thorpej	Sync w/ HEAD.
1.32.2.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.43.2.1	03-Apr-2021	thorpej	Sync with HEAD.
1.54.12.1	05-Sep-2025	martin	Pull up following revision(s) (requested by rin in ticket #25): sys/arch/arm/cortex/gicv3.c: revision 1.55 sys/arch/arm/cortex/gicv3.c: revision 1.56 gicv3: Appease KUBSAN, otherwise NFC gicv3: Some more left-shift v.s. int fixes Suggested by msaitoh@, thanks!
1.54.4.1	05-Sep-2025	martin	Pull up following revision(s) (requested by rin in ticket #1156): sys/arch/arm/cortex/gicv3.c: revision 1.55 sys/arch/arm/cortex/gicv3.c: revision 1.56 gicv3: Appease KUBSAN, otherwise NFC gicv3: Some more left-shift v.s. int fixes Suggested by msaitoh@, thanks!
1.11	16-Jan-2021	jmcneill	Remove MAXCPUS dependency.
1.10	04-Dec-2020	jmcneill	gicv3: Only use 1 of N SPI distribution when the feature is available. A GICv3+ implementation is not guaranteed to support 1 of N SPI distribution. Support for this feature is indicated in GICD_TYPER.No1N. When No1N=1, route all interrupts to the primary PE by default and only allow a single CPU target when updating affinity.
1.9	24-Nov-2020	jmcneill	Improve detection of NS vs S views of priorities. For PMR, write a 0 to bit7 and see if it sticks. This is only possible from NS EL1 if we have a non-secure view of ICC_PMR_EL1. For int priorities (GICD/GICR interfaces and LPIs), assume that the GICD_CTLR.DS bit is telling us the truth. RK3399 is special here when using the vendor bootloader, so keep the auto-detection from the previous commit but limit the scope to only run on RK3399 SOCs.
1.8	13-Feb-2020	jmcneill	branches: 1.8.6; Since all ITS instances share a common LPI configuration table, used a shared vmem arena to allocate pic irqs. Idea from FreeBSD.
1.7	30-Jun-2019	jmcneill	branches: 1.7.4; Fix size of LPI pending table allocation and enable caching of LPI conf and pending tables where possible.
1.6	26-Jun-2019	jmcneill	Remove unused field
1.5	17-Jun-2019	jmcneill	Improve priority handling for cases where access is secure, from OpenBSD.
1.4	10-Nov-2018	jmcneill	branches: 1.4.4; Implement pic_get_affinity/pic_set_affinity for LPIs via ITS
1.3	10-Nov-2018	jmcneill	Implement pic_get_affinity/pic_set_affinity for SPIs
1.2	09-Nov-2018	jmcneill	Add support for GICv3 Locality-specific Periphal Interrupts (LPIs) and the Interrupt Translation Service (ITS).
1.1	08-Aug-2018	jmcneill	branches: 1.1.2; Add GICv3 support.
1.1.2.3	26-Nov-2018	pgoyette	Sync with HEAD, resolve a couple of conflicts
1.1.2.2	06-Sep-2018	pgoyette	Sync with HEAD Resolve a couple of conflicts (result of the uimin/uimax changes)
1.1.2.1	08-Aug-2018	pgoyette	file gicv3.h was added on branch pgoyette-compat on 2018-09-06 06:55:26 +0000
1.4.4.4	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.4.4.3	08-Apr-2020	martin	Merge changes from current as of 20200406
1.4.4.2	10-Jun-2019	christos	Sync with HEAD
1.4.4.1	10-Nov-2018	christos	file gicv3.h was added on branch phil-wifi on 2019-06-10 22:05:52 +0000
1.7.4.1	29-Feb-2020	ad	Sync with head.
1.8.6.2	03-Apr-2021	thorpej	Sync with HEAD.
1.8.6.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.41	28-Jan-2025	jmcneill	gicv3_its: Fix indirect L2 device table allocation.
1.40	15-Dec-2024	jmcneill	gicv3: its: Fix regression on LX2K. Page size probing and device ID width changes broke LX2K, revert these parts of the last set of changes as they are not required on X1E.
1.39	12-Dec-2024	skrll	gicv3: log the ITS command table information
1.38	10-Dec-2024	jmcneill	fixup! Restore a line accidentally removed in my previous change
1.37	08-Dec-2024	riastradh	gicv3_its.c: Do-nothing macros must expand to `__nothing', not empty. No functional change intended -- unless this was accidentally broken before.
1.36	07-Dec-2024	jmcneill	gicv3: ITS: Add support for indirect device tables. When devbits is too large to fit into the first level of device table, some hardware supports the concept of indirect tables. Add support for this and use it when supported. This is required for MSIs to work properly on Snapdragon X Elite platforms (otherwise, MAPD command fails and stalls the ITS command queue).
1.35	11-Nov-2023	tnn	branches: 1.35.2; gicv3_its: assorted minor improvements - KASSERT that the command queue is not stalled due to async error before issuing more commands. - implement gits_command_int under #if 0 (useful for troubleshooting) - protect command queue with its_lock consistently - KASSERT for 32-bit MSI that upper bits are 0 - KASSERT return value of gicv3_its_msi_alloc_lpi - KASSERT that safe conditions for writing to CBASER are met - move CWRITER initialization to before CBASER - fix alignment of tables for the 16KB page size case
1.34	31-Oct-2021	skrll	Fix non-DIAGNOSTIC builds (hopefully). No idea why this didn't fail to build for me without DIAGNOSTIC.
1.33	31-Oct-2021	skrll	Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep. The AP initialisation code in cpu_init_secondary_processor will read and initialise the required system registers and state for the BP to attach and report. Rework the interrupt handler code for this new sequence. Thankfully, this removes a bunch of code for bcm2836mp. The VFP detection handler on <= armv7 relies on the global undefined handler being in place until the BP attaches vfp. That is, after the APs have been spun up. gicv3_its.c has a serialisation issue which is protected against in the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin lock. The serialisation issue needs addressing more completely. Tested on RPI3, Apple M1, QEMU, and lx2k Fixes PR port-arm/56264: diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3
1.32	16-Jan-2021	jmcneill	Remove MAXCPUS dependency.
1.31	24-Dec-2020	jmcneill	trailing whitespace
1.30	11-Dec-2020	jmcneill	Simplify gits_command by getting rid of the _BYTE_ORDER test and just always use the loop + htole64 path.
1.29	11-Dec-2020	jmcneill	Preserve ST Lower and Upper fields when clearing Mask bit in the MSI-X vector control register.
1.28	24-Sep-2020	ryo	branches: 1.28.2; need to swap on big endian machines. "The ITS command queue uses a little endian memory order model." (GIC Architecture Specification)
1.27	13-Feb-2020	jmcneill	Make intr affinity work with MSIs again
1.26	13-Feb-2020	jmcneill	Since all ITS instances share a common LPI configuration table, used a shared vmem arena to allocate pic irqs. Idea from FreeBSD.
1.25	01-Feb-2020	jmcneill	Use kmem_zalloc for its state, fixes possible crash if a driver tries to set affinity before a CPU is online.
1.24	17-Jan-2020	jmcneill	Set msi_id to its_id
1.23	24-Dec-2019	skrll	branches: 1.23.2; Traiing whitespace
1.22	02-Dec-2019	msaitoh	Use PCI_MSIX_"TBL"BIR_MASK instead of PCI_MSIX_"PBA"BIR_MASK for MSI-X table. This is not a real bug because both macros have the same value.
1.21	30-Jun-2019	jmcneill	branches: 1.21.2; Cleanup ThunderX quirk and print cache / shareability details for ITT tables
1.20	30-Jun-2019	jmcneill	Enable caching of ITS tables when possible
1.19	29-Jun-2019	jmcneill	Restore original size calculation for MAPD and don't disable MSI/MSIX on devices before making changes
1.18	29-Jun-2019	jmcneill	Rename lpi pic to gicv3-its when an ITS is found
1.17	23-Jun-2019	jmcneill	Pass correct EventID to MOVI and INV commands
1.16	23-Jun-2019	jmcneill	Remove unused variable (build fix)
1.15	23-Jun-2019	jmcneill	Ensure that the "size" parameter of MAPD matches the size of the ITT being mapped and subtract the LPI base from EventID. Fixes multi-vector MSI/MSI-X on RK3399.
1.14	16-Jun-2019	jmcneill	Pass correct event ID with MOVI commands
1.13	16-Jun-2019	jmcneill	- Disable MSI/MSI-X when making changes - MSI: Write the vector count to the Multi Message Enable (MME) field - MSI: Set DATA to the first LPI number, not the last
1.12	12-Jun-2019	jmcneill	Allow set_affinity calls before PEs are brought online. We store the desired target PE if set_affinity is called early and restore the routes when the PE comes alive.
1.11	12-Jun-2019	jmcneill	Fail gracefully if gicv3_its_set_affinity is called before a cpu is brought online.
1.10	08-Dec-2018	jmcneill	branches: 1.10.4; Add support for decoding PCI ID mappings using IO remapping tables (IORT).
1.9	28-Nov-2018	jmcneill	Allow non-power of 2 counts, and support alloc/release/alloc patterns for a device as long as the ITT size is sufficient
1.8	24-Nov-2018	skrll	branches: 1.8.2; Handle ThunderX errata
1.7	23-Nov-2018	jmcneill	Only allocate what we need for ITT tables
1.6	23-Nov-2018	jmcneill	Fix ITT size, only need to MAPD once per device.
1.5	22-Nov-2018	jakllsch	use correct interrupt index fixes intrctl list from jmcneill@
1.4	21-Nov-2018	jmcneill	kcpuset_ffs returns the cpu number plus one, so make sure to subtract it
1.3	16-Nov-2018	jmcneill	Add intr_establish_xname support to arm and expose it to intrctl
1.2	10-Nov-2018	jmcneill	Implement pic_get_affinity/pic_set_affinity for LPIs via ITS
1.1	09-Nov-2018	jmcneill	Add support for GICv3 Locality-specific Periphal Interrupts (LPIs) and the Interrupt Translation Service (ITS).
1.8.2.3	26-Dec-2018	pgoyette	Sync with HEAD, resolve a few conflicts
1.8.2.2	26-Nov-2018	pgoyette	Sync with HEAD, resolve a couple of conflicts
1.8.2.1	24-Nov-2018	pgoyette	file gicv3_its.c was added on branch pgoyette-compat on 2018-11-26 01:52:18 +0000
1.10.4.3	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.10.4.2	10-Jun-2019	christos	Sync with HEAD
1.10.4.1	08-Dec-2018	christos	file gicv3_its.c was added on branch phil-wifi on 2019-06-10 22:05:52 +0000
1.21.2.1	10-Feb-2020	martin	Pull up following revision(s) (requested by jmcneill in ticket #680): sys/arch/arm/cortex/gicv3_its.c: revision 1.25 Use kmem_zalloc for its state, fixes possible crash if a driver tries to set affinity before a CPU is online.
1.23.2.2	29-Feb-2020	ad	Sync with head.
1.23.2.1	17-Jan-2020	ad	Sync with head.
1.28.2.3	03-Apr-2021	thorpej	Sync with HEAD.
1.28.2.2	03-Jan-2021	thorpej	Sync w/ HEAD.
1.28.2.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.35.2.1	02-Aug-2025	perseant	Sync with HEAD
1.10	28-Jan-2025	jmcneill	gicv3_its: rename pt_dev_id to pt_index
1.9	07-Dec-2024	jmcneill	gicv3: ITS: Add support for indirect device tables. When devbits is too large to fit into the first level of device table, some hardware supports the concept of indirect tables. Add support for this and use it when supported. This is required for MSIs to work properly on Snapdragon X Elite platforms (otherwise, MAPD command fails and stalls the ITS command queue).
1.8	31-Oct-2021	skrll	branches: 1.8.10; Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep. The AP initialisation code in cpu_init_secondary_processor will read and initialise the required system registers and state for the BP to attach and report. Rework the interrupt handler code for this new sequence. Thankfully, this removes a bunch of code for bcm2836mp. The VFP detection handler on <= armv7 relies on the global undefined handler being in place until the BP attaches vfp. That is, after the APs have been spun up. gicv3_its.c has a serialisation issue which is protected against in the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin lock. The serialisation issue needs addressing more completely. Tested on RPI3, Apple M1, QEMU, and lx2k Fixes PR port-arm/56264: diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3
1.7	16-Jan-2021	jmcneill	Remove MAXCPUS dependency.
1.6	12-Jun-2019	jmcneill	branches: 1.6.10; Allow set_affinity calls before PEs are brought online. We store the desired target PE if set_affinity is called early and restore the routes when the PE comes alive.
1.5	12-Jun-2019	jmcneill	Fail gracefully if gicv3_its_set_affinity is called before a cpu is brought online.
1.4	28-Nov-2018	jmcneill	branches: 1.4.4; Allow non-power of 2 counts, and support alloc/release/alloc patterns for a device as long as the ITT size is sufficient
1.3	24-Nov-2018	jakllsch	branches: 1.3.2; include dev/pci/pcivar.h, we use pci_attach_args directly
1.2	10-Nov-2018	jmcneill	Implement pic_get_affinity/pic_set_affinity for LPIs via ITS
1.1	09-Nov-2018	jmcneill	Add support for GICv3 Locality-specific Periphal Interrupts (LPIs) and the Interrupt Translation Service (ITS).
1.3.2.3	26-Dec-2018	pgoyette	Sync with HEAD, resolve a few conflicts
1.3.2.2	26-Nov-2018	pgoyette	Sync with HEAD, resolve a couple of conflicts
1.3.2.1	24-Nov-2018	pgoyette	file gicv3_its.h was added on branch pgoyette-compat on 2018-11-26 01:52:18 +0000
1.4.4.3	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.4.4.2	10-Jun-2019	christos	Sync with HEAD
1.4.4.1	28-Nov-2018	christos	file gicv3_its.h was added on branch phil-wifi on 2019-06-10 22:05:52 +0000
1.6.10.1	03-Apr-2021	thorpej	Sync with HEAD.
1.8.10.1	02-Aug-2025	perseant	Sync with HEAD
1.50	09-Jan-2025	rin	gtmr_delay: Put SPINLOCK_BACKOFF_HOOK in busy loop It is expanded as a `yield` instruction for aarch64. This slightly improves peak performance for some drivers on MP environments, as tested by msaitoh@ (thanks!). XXX This is what OpenBSD does, while FreeBSD just busy-spins. However, unfortunately, benefits from `yield` should be limited, as we still read count register quite frequently. For long-duration delays, Linux uses `wfit` and `wfet` insns if provided, and falls back to `wfe` otherwise: https://github.com/torvalds/linux/blob/master/arch/arm64/lib/delay.c#L26-L51 Event streams should be configured for this purpose.
1.49	03-Mar-2022	riastradh	branches: 1.49.10; arm: Use device_set_private for various drivers.
1.48	13-Nov-2021	jakllsch	fix aarch64 build
1.47	12-Nov-2021	jmcneill	gtmr: Add support for arm,cpu-registers-not-fw-configured property. On armv7, arm,cpu-registers-not-fw-configured means that firmware hasn't bothered to configure any generic timer registers and we need to initialize cntfrq ourselves.
1.46	31-Oct-2021	skrll	Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep. The AP initialisation code in cpu_init_secondary_processor will read and initialise the required system registers and state for the BP to attach and report. Rework the interrupt handler code for this new sequence. Thankfully, this removes a bunch of code for bcm2836mp. The VFP detection handler on <= armv7 relies on the global undefined handler being in place until the BP attaches vfp. That is, after the APs have been spun up. gicv3_its.c has a serialisation issue which is protected against in the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin lock. The serialisation issue needs addressing more completely. Tested on RPI3, Apple M1, QEMU, and lx2k Fixes PR port-arm/56264: diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3
1.45	09-Sep-2021	jmcneill	If we get a spurious interrupt, log a debug message and ignore it. Otherwise we risk tripping an assertion later on due to an interrupt firing before it is scheduled.
1.44	30-Aug-2021	jmcneill	- Add an isb before cnt[pv]_ctl read - cntk_ctl is 64-bits - Do not toggle CNTCTL_IMASK in intr handler, as this may be needed elsewhere.
1.43	18-Jan-2021	jmcneill	Fix a comment
1.42	30-Oct-2020	skrll	branches: 1.42.2; Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.
1.41	12-Aug-2019	jmcneill	Add support for physical timers and sprinkle isb where needed.
1.40	16-Jun-2019	jmcneill	branches: 1.40.2; Disable counter before updating cval/tval
1.39	30-Jan-2019	jmcneill	Fix bitmask in A64 errata workaround and write cval instead of tval on A64
1.38	15-Nov-2018	jmcneill	A64 timer errata can cause the timer to fire too soon, so skip KASSERT here too.
1.37	30-Oct-2018	jmcneill	Disable diagnostic assertions around timer jitter on Allwinner A64. It seems the instability of CNTVCT can cause issues with the compare value, and rather than applying a heavy workaround just skip the panics.
1.36	30-Sep-2018	skrll	If we're going to allow pl0 to access virtual and physical counters then we should allow it from all CPUs. kern/53630 (openssl fallout on arm)
1.35	16-Sep-2018	jmcneill	port-evbarm/53308: evbarm-earmv7hf performance regression under qemu Revert gtmr.c r1.27 and apply a workaround for Allwinner A64 SoCs based on analysis of the issue from LKML: https://lkml.org/lkml/2018/5/10/774 Since this bug is specific to the Allwinner A64 SoC, only apply the workaround when the root ("/") node of the device tree is compatible with "allwinner,sun50i-a64".
1.34	10-Sep-2018	skrll	Typo in comment from Joerg's gtmr diff
1.33	01-Sep-2018	tnn	fix non-DIAGNOSTIC build
1.32	30-Jun-2018	jmcneill	ARM ARM refers to this as "ARM Generic Timer", so adjust printf at attach to match.
1.31	24-Jun-2018	ryo	branches: 1.31.2; fixed a case of gtmr_cntvct_stable_read() is returning the same value as before.
1.30	17-Jun-2018	jmcneill	Simplify gtmr_delay and don't mix and match usage of the physical and virtual timers (always use the virtual timer).
1.29	09-Jun-2018	jakllsch	Avoid unnecessarily touching CNTP_CTL. We may not have the privilege of accessing CNTP_CTL if running as a virtualized guest, and we're not using the Physical Timer for interupt generation anyway.
1.28	21-May-2018	jmcneill	Replace stable_read/write debug printfs with event counters
1.27	14-May-2018	joerg	Workaround A-008585 errata in GTMR. Register reads and writes may provide unstable results if the counter hardware is active at the same time. This results in non-monotonic counters seen by both the gtmr interrupt and time counter. The loops are currently applied unconditionally, restricting them to appropiate FDT markers can be applied later.
1.26	14-May-2018	joerg	Remove a number of debug #if 0s.
1.25	14-May-2018	joerg	Remove unused gtmr_bootdelay.
1.24	01-Apr-2018	ryo	Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@) - sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@) - add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)
1.23	30-Nov-2017	skrll	branches: 1.23.2; When attaching gtmr at fdt use fdtbus_intr_establish to establish the gtmr interrupt.
1.22	25-Oct-2017	skrll	Improve delay to be better than 1.3 innaccurate by default and handle the unlikely wrap
1.21	25-Oct-2017	skrll	Trailing whitespace
1.20	09-Sep-2017	jmcneill	gtmr_intr: If the ISTATUS bit is 0, timer condition is not met. In this case, just return 0.
1.19	24-Aug-2017	jmcneill	Add __HAVE_GENERIC_CPU_INITCLOCKS option. If set, don't export cpu_initclocks from device drivers as common code (in this case FDT) will provide its own copy.
1.18	17-Jun-2017	jmcneill	Interrupts are enabled before the timer is configured. Ensure that the timer is disabled when attaching so it doesn't go crazy between the time interrupts are enabled and clocks are initialized. My RPI3 makes it multi-user now.
1.17	28-May-2017	jmcneill	branches: 1.17.2; If the "frequency" property is not specified, try to use the value in CNTFRQ. Firmware should have already set this for us.
1.16	20-Apr-2015	matt	Use physical timer for gtmr_delay();
1.15	12-Apr-2015	matt	Don't adjust interval if we are too far into the next tick.
1.14	27-Mar-2015	skrll	Whitespace
1.13	26-Mar-2015	skrll	Trailing whitespace.
1.12	24-Mar-2015	matt	Move isb's to before reading count. Change interrupt to level.
1.11	24-Mar-2015	matt	Sprinkle some arm_isb() to force execution of the mcrr instructions to get more accurate values. (Given that the generic timer is usually running at a 64th or less of the cpu clock, this only settle to a tick or so.)
1.10	23-Mar-2015	jmcneill	port-arm/49737: armgtmr0 timer broken Use physical timer instead of virtual timer for timecounter. For platforms that implement virtualization extensions, the CNTVOFF register defines a virtual offset between the physical count and virtual count. Unfortunately, the CNTVOFF register is only accessible in secure mode and the value is per-CPU, so we may end up in a scenario where virtual count reads from CPU A -> B -> A are not monotonic. No offset applied to physical timer, so physical count reads are guaranteed to be monotonic.
1.9	28-Feb-2015	skrll	Initial RPI2 support - it doesn't work yet. The generic timer gets messed up somehow. This commit changes the KVA layout of the RPI.
1.8	11-Jun-2014	matt	branches: 1.8.2; 1.8.4; Add a KASSERT to make sure the counter is running.
1.7	13-Apr-2014	matt	branches: 1.7.2; Make sure freq is not 0.
1.6	28-Mar-2014	matt	branches: 1.6.2; Add gtmr_bootdelay. rename clockhandler to gtmr_intr
1.5	17-Dec-2013	joerg	branches: 1.5.2; delta can't be negative. Wrapped value is seen as large positive, so covered already.
1.4	12-Sep-2013	matt	Cleanup some diagnostic code.
1.3	07-Sep-2013	matt	Fix some bugs.
1.2	20-Jun-2013	matt	branches: 1.2.2; 1.2.4; Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args. Modify the list of devices to include the offset(s) from PERIPHBASE.
1.1	16-Jun-2013	matt	Add generic timer support (untested)
1.2.4.1	18-May-2014	rmind	sync with head
1.2.2.4	03-Dec-2017	jdolecek	update from HEAD
1.2.2.3	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.2.2.2	23-Jun-2013	tls	resync from head
1.2.2.1	20-Jun-2013	tls	file gtmr.c was added on branch tls-maxphys on 2013-06-23 06:20:00 +0000
1.5.2.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.5.2.1	17-Dec-2013	matt	file gtmr.c was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.6.2.1	10-Aug-2014	tls	Rebase.
1.7.2.2	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.7.2.1	13-Apr-2014	yamt	file gtmr.c was added on branch yamt-pagecache on 2014-05-22 11:39:32 +0000
1.8.4.3	28-Aug-2017	skrll	Sync with HEAD
1.8.4.2	06-Jun-2015	skrll	Sync with HEAD
1.8.4.1	06-Apr-2015	skrll	Sync with HEAD
1.8.2.3	26-Jul-2017	snj	Pull up following revision(s) (requested by jmcneill in ticket #1435): sys/arch/arm/arm32/cpu.c: 1.113 via patch sys/arch/arm/broadcom/bcm2835_bsc.c: 1.6 via patch sys/arch/arm/broadcom/bcm2835_plcom.c: 1.4 via patch sys/arch/arm/cortex/gtmr.c: 1.18 via patch sys/arch/arm/include/armreg.h: 1.110 via patch sys/arch/arm/include/vfpreg.h: 1.15 via patch sys/arch/arm/vfp/vfp_init.c: 1.50 via patch sys/arch/evbarm/rpi/rpi_machdep.c: 1.59, 1.70-1.72 via patch sys/arch/evbarm/rpi/vcprop.h: 1.16 Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs. While I'm here add some A57/A72 info as well. My RPI3 works with FB console - the uart needs some help with its clocks. -- Do invalidate the cache as RPI2 build with Clang can't fetch the memory config otherwise. -- Use the VC property mailbox to request the UART clock rate and use it appropriately Newer firmwares use 48MHz -- Disable BSC0 on Raspberry Pi 3 and Zero W boards. -- Interrupts are enabled before the timer is configured. Ensure that the timer is disabled when attaching so it doesn't go crazy between the time interrupts are enabled and clocks are initialized. My RPI3 makes it multi-user now. -- Enable UART0 (PL011) on GPIO header for Raspberry Pi 3 / Zero W
1.8.2.2	06-Apr-2015	snj	Pull up following revision(s) (requested by skrll in ticket #662): sys/arch/arm/cortex/gtmr.c: revision 1.10-1.14 port-arm/49737: armgtmr0 timer broken Use physical timer instead of virtual timer for timecounter. For platforms that implement virtualization extensions, the CNTVOFF register defines a virtual offset between the physical count and virtual count. Unfortunately, the CNTVOFF register is only accessible in secure mode and the value is per-CPU, so we may end up in a scenario where virtual count reads from CPU A -> B -> A are not monotonic. No offset applied to physical timer, so physical count reads are guaranteed to be monotonic. -- Sprinkle some arm_isb() to force execution of the mcrr instructions to get more accurate values. (Given that the generic timer is usually running at a 64th or less of the cpu clock, this only settle to a tick or so.) -- Move isb's to before reading count. Change interrupt to level. -- Trailing whitespace. -- Whitespace
1.8.2.1	11-Mar-2015	snj	Pull up following revision(s) (requested by skrll in ticket #582): distrib/utils/embedded/conf/rpi.conf: revision 1.27 etc/etc.evbarm/Makefile.inc: revision 1.70 sys/arch/arm/broadcom/bcm2835_intr.c: revision 1.5-1.7 sys/arch/arm/broadcom/bcm2835_obio.c: revision 1.23, 1.24 sys/arch/arm/broadcom/bcm2835_space.c: revision 1.8 sys/arch/arm/broadcom/bcm2835reg.h: revision 1.14 sys/arch/arm/broadcom/bcm2835var.h: revision 1.2 sys/arch/arm/broadcom/files.bcm2835: revision 1.24 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.30 sys/arch/arm/cortex/armperiph.c: revision 1.8, 1.9 sys/arch/arm/cortex/gtmr.c: revision 1.9 sys/arch/arm/cortex/gtmr_var.h: revision 1.5 sys/arch/arm/cortex/mpcore_var.h: revision 1.3 sys/arch/arm/include/cpu.h: revision 1.84 sys/arch/evbarm/conf/RPI2: revision 1.1, 1.2 sys/arch/evbarm/conf/RPI2_INSTALL: revision 1.1 sys/arch/evbarm/conf/RPI: revision 1.59, 1.60 sys/arch/evbarm/conf/mk.rpi: revision 1.4 sys/arch/evbarm/conf/std.rpi: revisions 1.16-1.19 via patch sys/arch/evbarm/rpi/genassym.cf: revision 1.2 sys/arch/evbarm/rpi/rpi.h: revision 1.4 sys/arch/evbarm/rpi/rpi2_start.S: revision 1.1 sys/arch/evbarm/rpi/rpi_machdep.c: revision 1.57, 1.58 via patch sys/arch/evbarm/rpi/rpi_start.S: revision 1.13 Move some options into std.rpi -- Add __HAVE_MM_MD_CACHE_ALIASING Pull up following revision(s) (requested by skrll in ticket #582): Fix TPIDRPRW_IS_CURLWP builds. -- A MULTIPROCESSOR kernel requires TPIDRPRW_IS_CURCPU. -- Use TPIDRPRW_IS_CURLWP as it's a slight code reduction and performance improvement. Initial RPI2 support - it doesn't work yet. The generic timer gets messed up somehow. This commit changes the KVA layout of the RPI. -- Make this compile where gtmr isn't used. -- Spin up the non-boot CPUs, but don't allow cpu_boot_secondary_processors to see them for now. RPI2 nows works well with only the boot cpu. -- Appease a KASSERT - will be remove when MULTIPROCESSOR RPI2 is fixed. -- Add RPI2 to kernels build for both earmv[67]. Use the earmv6 built kernels to create an image that can be used on both RPI and RPI2 -- Add an RPI2_INSTALL
1.17.2.2	11-Sep-2017	snj	Pull up following revision(s) (requested by jmcneill in ticket #271): sys/arch/arm/cortex/gtmr.c: revision 1.20 gtmr_intr: If the ISTATUS bit is 0, timer condition is not met. In this case, just return 0.
1.17.2.1	21-Jun-2017	snj	Pull up following revision(s) (requested by jmcneill in ticket #45): sys/arch/arm/cortex/gtmr.c: revision 1.18 Interrupts are enabled before the timer is configured. Ensure that the timer is disabled when attaching so it doesn't go crazy between the time interrupts are enabled and clocks are initialized. My RPI3 makes it multi-user now.
1.23.2.8	26-Nov-2018	pgoyette	Sync with HEAD, resolve a couple of conflicts
1.23.2.7	20-Oct-2018	pgoyette	Sync with head
1.23.2.6	30-Sep-2018	pgoyette	Ssync with HEAD
1.23.2.5	06-Sep-2018	pgoyette	Sync with HEAD Resolve a couple of conflicts (result of the uimin/uimax changes)
1.23.2.4	28-Jul-2018	pgoyette	Sync with HEAD
1.23.2.3	25-Jun-2018	pgoyette	Sync with HEAD
1.23.2.2	21-May-2018	pgoyette	Sync with HEAD
1.23.2.1	07-Apr-2018	pgoyette	Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
1.31.2.2	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.31.2.1	10-Jun-2019	christos	Sync with HEAD
1.40.2.1	13-Aug-2019	martin	Pull up following revision(s) (requested by jmcneill in ticket #54): sys/arch/aarch64/include/armreg.h: revision 1.26 sys/arch/arm/cortex/gtmr.c: revision 1.41 sys/arch/arm/include/armreg.h: revision 1.128 sys/arch/arm/cortex/gtmr_var.h: revision 1.12 Add support for physical timers and sprinkle isb where needed.
1.42.2.1	03-Apr-2021	thorpej	Sync with HEAD.
1.49.10.1	02-Aug-2025	perseant	Sync with HEAD
1.1	16-Jun-2013	matt	branches: 1.1.2; 1.1.8; 1.1.12; Add generic timer support (untested)
1.1.12.2	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.1.12.1	16-Jun-2013	yamt	file gtmr_intr.h was added on branch yamt-pagecache on 2014-05-22 11:39:32 +0000
1.1.8.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.1.8.1	16-Jun-2013	matt	file gtmr_intr.h was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.1.2.2	23-Jun-2013	tls	resync from head
1.1.2.1	16-Jun-2013	tls	file gtmr_intr.h was added on branch tls-maxphys on 2013-06-23 06:20:00 +0000
1.16	19-Nov-2022	skrll	G/C gtmr_init function declaration
1.15	12-Nov-2021	jmcneill	gtmr: Add support for arm,cpu-registers-not-fw-configured property. On armv7, arm,cpu-registers-not-fw-configured means that firmware hasn't bothered to configure any generic timer registers and we need to initialize cntfrq ourselves.
1.14	05-Mar-2020	riastradh	Revert "Include opt_diagnostic.h for DIAGNOSTIC." This did not do what I thought it did. opt_diagnostic.h is only for the unused _DIAGNOSTIC, which seems like an abortive attempt to incrementally convert DIAGNOSTIC to an opt_*.h option rather than a command-line option.
1.13	05-Mar-2020	riastradh	Include opt_diagnostic.h for DIAGNOSTIC. ...at least, in header files, which may not have already included libkern.h.
1.12	12-Aug-2019	jmcneill	Add support for physical timers and sprinkle isb where needed.
1.11	16-Sep-2018	jmcneill	branches: 1.11.4; port-evbarm/53308: evbarm-earmv7hf performance regression under qemu Revert gtmr.c r1.27 and apply a workaround for Allwinner A64 SoCs based on analysis of the issue from LKML: https://lkml.org/lkml/2018/5/10/774 Since this bug is specific to the Allwinner A64 SoC, only apply the workaround when the root ("/") node of the device tree is compatible with "allwinner,sun50i-a64".
1.10	14-May-2018	joerg	branches: 1.10.2; Remove unused gtmr_bootdelay.
1.9	30-Nov-2017	skrll	branches: 1.9.2; When attaching gtmr at fdt use fdtbus_intr_establish to establish the gtmr interrupt.
1.8	09-Nov-2017	skrll	Trailing whitespace
1.7	24-Aug-2017	jmcneill	Add __HAVE_GENERIC_CPU_INITCLOCKS option. If set, don't export cpu_initclocks from device drivers as common code (in this case FDT) will provide its own copy.
1.6	02-Apr-2015	matt	#include <sys/percpu.h>
1.5	28-Feb-2015	skrll	Initial RPI2 support - it doesn't work yet. The generic timer gets messed up somehow. This commit changes the KVA layout of the RPI.
1.4	28-Mar-2014	matt	branches: 1.4.4; 1.4.6; 1.4.8; Add gtmr_bootdelay. rename clockhandler to gtmr_intr
1.3	12-Sep-2013	matt	branches: 1.3.2; Cleanup some diagnostic code.
1.2	20-Jun-2013	matt	branches: 1.2.2; 1.2.4; Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args. Modify the list of devices to include the offset(s) from PERIPHBASE.
1.1	16-Jun-2013	matt	Add generic timer support (untested)
1.2.4.1	18-May-2014	rmind	sync with head
1.2.2.4	03-Dec-2017	jdolecek	update from HEAD
1.2.2.3	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.2.2.2	23-Jun-2013	tls	resync from head
1.2.2.1	20-Jun-2013	tls	file gtmr_var.h was added on branch tls-maxphys on 2013-06-23 06:20:00 +0000
1.3.2.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.3.2.1	12-Sep-2013	matt	file gtmr_var.h was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.4.8.2	28-Aug-2017	skrll	Sync with HEAD
1.4.8.1	06-Apr-2015	skrll	Sync with HEAD
1.4.6.1	11-Mar-2015	snj	Pull up following revision(s) (requested by skrll in ticket #582): distrib/utils/embedded/conf/rpi.conf: revision 1.27 etc/etc.evbarm/Makefile.inc: revision 1.70 sys/arch/arm/broadcom/bcm2835_intr.c: revision 1.5-1.7 sys/arch/arm/broadcom/bcm2835_obio.c: revision 1.23, 1.24 sys/arch/arm/broadcom/bcm2835_space.c: revision 1.8 sys/arch/arm/broadcom/bcm2835reg.h: revision 1.14 sys/arch/arm/broadcom/bcm2835var.h: revision 1.2 sys/arch/arm/broadcom/files.bcm2835: revision 1.24 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.30 sys/arch/arm/cortex/armperiph.c: revision 1.8, 1.9 sys/arch/arm/cortex/gtmr.c: revision 1.9 sys/arch/arm/cortex/gtmr_var.h: revision 1.5 sys/arch/arm/cortex/mpcore_var.h: revision 1.3 sys/arch/arm/include/cpu.h: revision 1.84 sys/arch/evbarm/conf/RPI2: revision 1.1, 1.2 sys/arch/evbarm/conf/RPI2_INSTALL: revision 1.1 sys/arch/evbarm/conf/RPI: revision 1.59, 1.60 sys/arch/evbarm/conf/mk.rpi: revision 1.4 sys/arch/evbarm/conf/std.rpi: revisions 1.16-1.19 via patch sys/arch/evbarm/rpi/genassym.cf: revision 1.2 sys/arch/evbarm/rpi/rpi.h: revision 1.4 sys/arch/evbarm/rpi/rpi2_start.S: revision 1.1 sys/arch/evbarm/rpi/rpi_machdep.c: revision 1.57, 1.58 via patch sys/arch/evbarm/rpi/rpi_start.S: revision 1.13 Move some options into std.rpi -- Add __HAVE_MM_MD_CACHE_ALIASING Pull up following revision(s) (requested by skrll in ticket #582): Fix TPIDRPRW_IS_CURLWP builds. -- A MULTIPROCESSOR kernel requires TPIDRPRW_IS_CURCPU. -- Use TPIDRPRW_IS_CURLWP as it's a slight code reduction and performance improvement. Initial RPI2 support - it doesn't work yet. The generic timer gets messed up somehow. This commit changes the KVA layout of the RPI. -- Make this compile where gtmr isn't used. -- Spin up the non-boot CPUs, but don't allow cpu_boot_secondary_processors to see them for now. RPI2 nows works well with only the boot cpu. -- Appease a KASSERT - will be remove when MULTIPROCESSOR RPI2 is fixed. -- Add RPI2 to kernels build for both earmv[67]. Use the earmv6 built kernels to create an image that can be used on both RPI and RPI2 -- Add an RPI2_INSTALL
1.4.4.2	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.4.4.1	28-Mar-2014	yamt	file gtmr_var.h was added on branch yamt-pagecache on 2014-05-22 11:39:32 +0000
1.9.2.2	30-Sep-2018	pgoyette	Ssync with HEAD
1.9.2.1	21-May-2018	pgoyette	Sync with HEAD
1.10.2.2	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.10.2.1	10-Jun-2019	christos	Sync with HEAD
1.11.4.1	13-Aug-2019	martin	Pull up following revision(s) (requested by jmcneill in ticket #54): sys/arch/aarch64/include/armreg.h: revision 1.26 sys/arch/arm/cortex/gtmr.c: revision 1.41 sys/arch/arm/include/armreg.h: revision 1.128 sys/arch/arm/cortex/gtmr_var.h: revision 1.12 Add support for physical timers and sprinkle isb where needed.
1.3	28-Feb-2015	skrll	Initial RPI2 support - it doesn't work yet. The generic timer gets messed up somehow. This commit changes the KVA layout of the RPI.
1.2	20-Jun-2013	matt	branches: 1.2.6; 1.2.10; 1.2.12; Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args. Modify the list of devices to include the offset(s) from PERIPHBASE.
1.1	01-Sep-2012	matt	branches: 1.1.2; 1.1.4; 1.1.6; Add Cortex-A9 support including the ARM Generic Interrupt Controller and the A9 Global Timer / Watchdog.
1.1.6.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.1.6.1	01-Sep-2012	matt	file mpcore_var.h was added on branch matt-nb6-plus on 2012-11-28 22:40:27 +0000
1.1.4.3	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.1.4.2	30-Oct-2012	yamt	sync with head
1.1.4.1	01-Sep-2012	yamt	file mpcore_var.h was added on branch yamt-pagecache on 2012-10-30 17:19:00 +0000
1.1.2.2	03-Dec-2017	jdolecek	update from HEAD
1.1.2.1	23-Jun-2013	tls	resync from head
1.2.12.1	06-Apr-2015	skrll	Sync with HEAD
1.2.10.1	11-Mar-2015	snj	Pull up following revision(s) (requested by skrll in ticket #582): distrib/utils/embedded/conf/rpi.conf: revision 1.27 etc/etc.evbarm/Makefile.inc: revision 1.70 sys/arch/arm/broadcom/bcm2835_intr.c: revision 1.5-1.7 sys/arch/arm/broadcom/bcm2835_obio.c: revision 1.23, 1.24 sys/arch/arm/broadcom/bcm2835_space.c: revision 1.8 sys/arch/arm/broadcom/bcm2835reg.h: revision 1.14 sys/arch/arm/broadcom/bcm2835var.h: revision 1.2 sys/arch/arm/broadcom/files.bcm2835: revision 1.24 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.30 sys/arch/arm/cortex/armperiph.c: revision 1.8, 1.9 sys/arch/arm/cortex/gtmr.c: revision 1.9 sys/arch/arm/cortex/gtmr_var.h: revision 1.5 sys/arch/arm/cortex/mpcore_var.h: revision 1.3 sys/arch/arm/include/cpu.h: revision 1.84 sys/arch/evbarm/conf/RPI2: revision 1.1, 1.2 sys/arch/evbarm/conf/RPI2_INSTALL: revision 1.1 sys/arch/evbarm/conf/RPI: revision 1.59, 1.60 sys/arch/evbarm/conf/mk.rpi: revision 1.4 sys/arch/evbarm/conf/std.rpi: revisions 1.16-1.19 via patch sys/arch/evbarm/rpi/genassym.cf: revision 1.2 sys/arch/evbarm/rpi/rpi.h: revision 1.4 sys/arch/evbarm/rpi/rpi2_start.S: revision 1.1 sys/arch/evbarm/rpi/rpi_machdep.c: revision 1.57, 1.58 via patch sys/arch/evbarm/rpi/rpi_start.S: revision 1.13 Move some options into std.rpi -- Add __HAVE_MM_MD_CACHE_ALIASING Pull up following revision(s) (requested by skrll in ticket #582): Fix TPIDRPRW_IS_CURLWP builds. -- A MULTIPROCESSOR kernel requires TPIDRPRW_IS_CURCPU. -- Use TPIDRPRW_IS_CURLWP as it's a slight code reduction and performance improvement. Initial RPI2 support - it doesn't work yet. The generic timer gets messed up somehow. This commit changes the KVA layout of the RPI. -- Make this compile where gtmr isn't used. -- Spin up the non-boot CPUs, but don't allow cpu_boot_secondary_processors to see them for now. RPI2 nows works well with only the boot cpu. -- Appease a KASSERT - will be remove when MULTIPROCESSOR RPI2 is fixed. -- Add RPI2 to kernels build for both earmv[67]. Use the earmv6 built kernels to create an image that can be used on both RPI and RPI2 -- Add an RPI2_INSTALL
1.2.6.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.2.6.1	20-Jun-2013	matt	file mpcore_var.h was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.20	02-Oct-2021	skrll	Trailing whitespace
1.19	19-Jan-2019	jmcneill	Remove hard requirement for "offset" property on Cortex-A5. This is not required w/ FDT.
1.18	20-Jun-2018	hkenken	branches: 1.18.2; Add l2cc support.
1.17	27-Feb-2015	jmcneill	branches: 1.17.16; allow arml2cc to be used on Cortex-A5 if the "offset" property is specified
1.16	01-Dec-2014	matt	clean the a9 l2 cache before turning it on.
1.15	16-Apr-2014	matt	branches: 1.15.2; 1.15.4; Allow l2cc base to gotten from device properties.
1.14	20-Mar-2014	matt	branches: 1.14.2; pl310 cache is PIPT
1.13	23-Feb-2014	matt	#include <arm/locore.h>
1.12	17-Jun-2013	matt	branches: 1.12.2; 1.12.6; KASSERT -> KASSERTMSG
1.11	13-Feb-2013	matt	simplify cache range op
1.10	22-Jan-2013	matt	Don't "sync" atomic ops. Do sync after each range op.
1.9	28-Nov-2012	matt	Make these compile with gcc4.1 and binutils 2.16
1.8	01-Nov-2012	matt	branches: 1.8.2; Invalidate the L2 cache before enabling it.
1.7	17-Oct-2012	matt	branches: 1.7.2; Add a missing mutex exit.
1.6	22-Sep-2012	matt	Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead but add a second argument to it to indicate whether the TLB/caches need to be flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field to see if the fixed can be skipped. Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1) or enabeld (bit = 0). With these changes, the A9 MMU can use traverse caches to do MMU tablewalks Also, make sure all memory has the shareable bit for the A9.
1.5	14-Sep-2012	matt	Add L2 cache flush routines. (not yet enabled).
1.4	07-Sep-2012	matt	branches: 1.4.2; Don't disable the L2C is it isn't enabled.
1.3	07-Sep-2012	matt	Switch cortex_a9 back to need_ptesync = 1 Add code to disable the L2 cache on cortex-a9 (for now). Add evcnt for all the fault types. Move cache info in a structure and have one for the pcache and one for scache. Probe L1/L2 caches properly for ARMv7
1.2	02-Sep-2012	matt	Add "write-back" before Unified
1.1	02-Sep-2012	matt	Add driver to attach ARM PL210 L2 Cache Controller arml2cc0 at armperiph0: ARM PL310 L2 r3p2 Cache Controller arml2cc0: 256KB/32B 16-way L2 Unified cache
1.4.2.5	03-Dec-2017	jdolecek	update from HEAD
1.4.2.4	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.4.2.3	23-Jun-2013	tls	resync from head
1.4.2.2	25-Feb-2013	tls	resync with head
1.4.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.7.2.5	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.7.2.4	23-Jan-2013	yamt	sync with head
1.7.2.3	16-Jan-2013	yamt	sync with (a bit old) head
1.7.2.2	30-Oct-2012	yamt	sync with head
1.7.2.1	17-Oct-2012	yamt	file pl310.c was added on branch yamt-pagecache on 2012-10-30 17:19:00 +0000
1.8.2.3	07-Feb-2013	matt	Sync with HEAD
1.8.2.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.8.2.1	01-Nov-2012	matt	file pl310.c was added on branch matt-nb6-plus on 2012-11-28 22:40:27 +0000
1.12.6.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.12.6.1	17-Jun-2013	matt	file pl310.c was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.12.2.1	18-May-2014	rmind	sync with head
1.14.2.1	10-Aug-2014	tls	Rebase.
1.15.4.1	06-Apr-2015	skrll	Sync with HEAD
1.15.2.1	21-Mar-2015	snj	Pull up following revision(s) (requested by jmcneill in ticket #598): sys/arch/arm/amlogic/amlogic_board.c: up to revision 1.9 sys/arch/arm/amlogic/amlogic_canvasreg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_com.c: up to revision 1.4 sys/arch/arm/amlogic/amlogic_comreg.h: up to revision 1.3 sys/arch/arm/amlogic/amlogic_comvar.h: revision 1.1 sys/arch/arm/amlogic/amlogic_cpufreq.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_crureg.h: up to revision 1.7 sys/arch/arm/amlogic/amlogic_dwctwo.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_genfb.c: revision 1.1 sys/arch/arm/amlogic/amlogic_gmac.c: up to revision 1.2 sys/arch/arm/amlogic/amlogic_hdmireg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_intr.h: up to revision 1.5 sys/arch/arm/amlogic/amlogic_io.c: up to revision 1.7 sys/arch/arm/amlogic/amlogic_reg.h: up to revision 1.9 sys/arch/arm/amlogic/amlogic_rng.c: revision 1.1 sys/arch/arm/amlogic/amlogic_sdhc.c: up to revision 1.3 sys/arch/arm/amlogic/amlogic_sdhcreg.h: revision 1.1 sys/arch/arm/amlogic/amlogic_space.c: revision 1.1 sys/arch/arm/amlogic/amlogic_var.h: up to revision 1.8 sys/arch/arm/amlogic/amlogic_vpureg.h: revision 1.1 sys/arch/arm/arm/bootconfig.c: revisions 1.7-1.8 sys/arch/arm/conf/files.arm: revision 1.129 sys/arch/arm/cortex/pl310.c: revisions 1.16-1.17 sys/arch/arm/cortex/a9_mpsubr.S: revisions 1.25-1.29 sys/arch/arm/cortex/a9tmr.c: revisions 1.8-1.12 sys/arch/arm/cortex/a9tmr_var.h: revision 1.4 sys/arch/arm/cortex/a9wdt.c: revisions 1.3-1.4 sys/arch/arm/cortex/armperiph.c: revisions 1.5-1.7 sys/arch/arm/arm/cpufunc.c: revision 1.151 sys/arch/arm/include/bootconfig.h: revision 1.7 sys/arch/arm/include/locore.h: revision 1.19 sys/arch/evbarm/amlogic/amlogic_machdep.c: up to revision 1.17 sys/arch/evbarm/amlogic/amlogic_start.S: up to revision 1.2 sys/arch/evbarm/amlogic/genassym.cf: revision 1.1 sys/arch/evbarm/amlogic/platform.h: revision 1.1 sys/arch/evbarm/conf/files.amlogic: up to revision 1.8 sys/arch/evbarm/conf/std.amlogic: up to revision 1.2 sys/arch/evbarm/conf/mk.amlogic: revision 1.1 sys/arch/evbarm/conf/ODROID-C1: up to revision 1.12 sys/arch/evarm/conf/ODROID-C1_INSTALL: revision 1.1 Don't use not as a variable since it's reserved in C++. -- clean the a9 l2 cache before turning it on. -- Add Cortex-A17 support -- Fix CORTEXA17 support -- Let the "cbar" device property override the cbar value, to work around broken bootloaders -- add a helper to update a9tmr frequency -- detach and re-attach timecounter when updating freq, and reinit timer on each cpu -- fix typo -- add BOOTOPT_TYPE_MACADDR for parsing mac address parameters -- make sure we set ACTLR.SMP=1 for CPU_CORTEXA5 in !MP case, ok matt@ -- According to the Cortex-A5 TRM, the CBAR register is not implemented and always reads as 0x00000000. Add ARM_CBAR option to set this in kernel config. -- skip a TLBIALL on Cortex-A5 that stops my odroid-c1 from booting, ok matt -- match on Cortex-A5 -- match on Cortex-A5 -- allow arml2cc to be used on Cortex-A5 if the "offset" property is specified -- print "A5" instead of "A9" at attach time if running on a Cortex-A5 -- Improve inline asm around dsb/dmb/isb: - always use volatile and mark them as memory barrier - use the common version from locore.h in all places not included from userland -- Work-in-progress Odroid-C1 support. -- no need to override ARM_CBAR, remove unused COM_16750 option -- Add basic serial console support. -- add dwctwo and usb devices -- ODROID-C1 SMP support. -- auto-detect RAM size -- ODROID-C1 onboard ethernet support. -- add amlogicrng, add commented-out genfb placeholder -- enable amlogicsdhc -- add ODROID-C1 install kernel -- Add CPUFREQ option to set boot CPU frequency. ODROID-C1 is advertised as quad-core 1.5GHz but boots up at 1.2GHz; add CPUFREQ=1512 to config and make sure to set the correct speed before attaching CPUs. The speed can still be scaled down with machdep.cpu sysctls. -- disable DEBUG, LOCKDEBUG, VERBOSE_INIT_ARM -- Basic framebuffer console support. Work in progress.
1.17.16.2	26-Jan-2019	pgoyette	Sync with HEAD
1.17.16.1	25-Jun-2018	pgoyette	Sync with HEAD
1.18.2.1	10-Jun-2019	christos	Sync with HEAD
1.4	22-Mar-2014	reinoud	Add constant for a reserved bit 31 for the L2C_AUXCTL register for use in masks
1.3	22-Mar-2014	reinoud	Add defines for the PL310's L2C_PREFETCH_CTL and L2C_POWER_CTL registers as per r3p2 spec.
1.2	07-Sep-2012	matt	branches: 1.2.2; 1.2.4; 1.2.6; 1.2.8; 1.2.16; Switch cortex_a9 back to need_ptesync = 1 Add code to disable the L2 cache on cortex-a9 (for now). Add evcnt for all the fault types. Move cache info in a structure and have one for the pcache and one for scache. Probe L1/L2 caches properly for ARMv7
1.1	02-Sep-2012	matt	Add driver to attach ARM PL210 L2 Cache Controller arml2cc0 at armperiph0: ARM PL310 L2 r3p2 Cache Controller arml2cc0: 256KB/32B 16-way L2 Unified cache
1.2.16.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.2.16.1	07-Sep-2012	matt	file pl310_reg.h was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.2.8.1	18-May-2014	rmind	sync with head
1.2.6.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.2.6.1	07-Sep-2012	matt	file pl310_reg.h was added on branch matt-nb6-plus on 2012-11-28 22:40:27 +0000
1.2.4.3	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.2.4.2	30-Oct-2012	yamt	sync with head
1.2.4.1	07-Sep-2012	yamt	file pl310_reg.h was added on branch yamt-pagecache on 2012-10-30 17:19:01 +0000
1.2.2.1	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.1	07-Sep-2012	matt	branches: 1.1.4; 1.1.6; 1.1.16; Switch cortex_a9 back to need_ptesync = 1 Add code to disable the L2 cache on cortex-a9 (for now). Add evcnt for all the fault types. Move cache info in a structure and have one for the pcache and one for scache. Probe L1/L2 caches properly for ARMv7
1.1.16.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.1.16.1	07-Sep-2012	matt	file pl310_var.h was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.1.6.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.1.6.1	07-Sep-2012	matt	file pl310_var.h was added on branch matt-nb6-plus on 2012-11-28 22:40:27 +0000
1.1.4.2	30-Oct-2012	yamt	sync with head
1.1.4.1	07-Sep-2012	yamt	file pl310_var.h was added on branch yamt-pagecache on 2012-10-30 17:19:01 +0000
1.3	16-Dec-2018	skrll	Move register definiton to header
1.2	04-Oct-2016	kiyohara	branches: 1.2.14; 1.2.16; Add SCU_SIZE.
1.1	01-Sep-2012	matt	branches: 1.1.2; 1.1.4; 1.1.6; 1.1.16; 1.1.22; 1.1.26; Add Cortex-A9 support including the ARM Generic Interrupt Controller and the A9 Global Timer / Watchdog.
1.1.26.1	04-Nov-2016	pgoyette	Sync with HEAD
1.1.22.1	05-Dec-2016	skrll	Sync with HEAD
1.1.16.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.1.16.1	01-Sep-2012	matt	file scu_reg.h was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.1.6.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.1.6.1	01-Sep-2012	matt	file scu_reg.h was added on branch matt-nb6-plus on 2012-11-28 22:40:27 +0000
1.1.4.2	30-Oct-2012	yamt	sync with head
1.1.4.1	01-Sep-2012	yamt	file scu_reg.h was added on branch yamt-pagecache on 2012-10-30 17:19:01 +0000
1.1.2.1	03-Dec-2017	jdolecek	update from HEAD
1.2.16.1	10-Jun-2019	christos	Sync with HEAD
1.2.14.1	26-Dec-2018	pgoyette	Sync with HEAD, resolve a few conflicts

OpenGrok