Create a new header lwp_private.h to contain _lwp_getprivate_fast,
_lwp_gettcb_fast, _lwp_settcb and remove them from mcontext.h, so that:
1. we don't need special hacks to hide them
2. we can include <lwp.h> where needed to get the necessary prototypes
without redefining them locally.

Undo previous lwp.h change.

Split __lwp_getprivate_fast and __lwp_*tcb from mcontext.h into a separate
lwp.h file.

branches: 1.52.26;
G/C arm/atomic.h

Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.

branches: 1.50.2;
separate cputypes.h for CPU_ID_* from armreg.h,
and add some implementor IDs, CortexA55,73,75 IDs.

(preliminary changes for merging aarch64)

branches: 1.49.26;
Rename sljitarch.h to sljit_machdep.h.

Add sljit support to arm.

branches: 1.47.8;
This change arm, armeb, earm, earmeb, earmhf, earmhfeb so all builds that
share a MACHINE_ARCH for userland so that except for etc, will produce
identical sets.

usr/include/machine now points to usr/include/arm

Add a default arm32 vmparam.h

Install fenv.h

Don't install fp.h anymore

branches: 1.43.2;
Export <arm/vfpreg.h>

Add aeabi.h header which descibes the C portion of the EABI run time API.

Added cpuconf.h needed by libkvm build.

branches: 1.40.2; 1.40.6; 1.40.10;
Do not install bus.h.

Retire varargs.h support. Move machine/stdarg.h logic into MI
sys/stdarg.h and expect compiler to provide proper builtins, defaulting
to the GCC interface. lint still has a special fallback.
Reduce abuse of _BSD_VA_LIST_ by defining __va_list by default and
derive va_list as required by standards.

Revert last change and just use .WAIT

Fix a race condition -j. Don't do SUBDIRS= include/arm include/arm/...
since the latter might be done before the former which mtree doesn't like.
Instead have arm recurse into its own subdirs.

branches: 1.36.14;
Remove arm support for IPKDB.

It hasn't worked since arm was broken out from arm32 in Jan 2001, and
no-one has noticed or cared to fix it.

Add support for kcore headers to arm32 kernel core dumps.

The kcore code is based on i386's kcore header handling.

Having an asm stub for dumpsys, to dump the registers onto the stack, and
then call the C code to do the memory dump is based on amd64's core dump
code.

This allows a successful core dump on cats.

Part of fixing PR cats/18026.

branches: 1.34.10; 1.34.18; 1.34.22; 1.34.24; 1.34.30; 1.34.36;
Install atomic.h, as needed by the installed rwlock.h.

Add <arm/mutex.h> and <arm/rwlock.h>
Add atomic_cas to <arm/atomic.h> for use by <rwlock.h>

branches: 1.32.2;
Merge newlock2 to head.

branches: 1.31.4;
don't install <machine/db_machdep.h>, this is kernel only

branches: 1.30.4; 1.30.8;
merge ktrace-lwp.

branches: 1.29.12;
Factor out W{CHAR,INT}_{MAX,MIN} into their own header file.

branches: 1.28.2;
Merge the nathanw_sa branch.

Remove KDIR=, since SYS_INCLUDE=symlinks and KDIR are not supported any more.

Byte-swapping optimizations, enabled if compiling with GCC:
* Byte-swap 16-bit and 32-bit constants at compile-time.
* Inline 16-bit and 32-bit variable byte-swaps. These take 3 and 4
insns, respectively, and inlining saves the minimum 6 cycle penalty
to call/return from the byte swap function.

Implement pmc(9) -- An interface to hardware performance monitoring
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.

branches: 1.24.8; 1.24.10;
Add an <arm/swi.h>, containing symbolic names for SWI ranges.

Don't install includes which userland doesn't need.

- Move more contents of various <machine/vmparam.h> files into
<arm/arm32/vmparam.h> (mostly the stuff that's tied to the pmap
implementation).
- Since the MMU definitions in pte.h are specific to ARM processors
that support 32-bit mode, move pte.h to <arm/arm32/pte.h>.
- Make the Netwinder startup file build again (use PT_B|PT_C, rather
than PT_CACHEABLE, since the latter expands to a variable these days).

branches: 1.21.6;
Add a merged <pcb.h> for arm26/arm32.

PR 13581
Add empty pmap.h and vmparam.h to make userland happier.

Make <sysarch.h> valid for all arm platforms. Adjust/remove port-specific
includes as required.

branches: 1.18.2;
Add a common <arm/param.h>, containing those few things that are obviously
common across all ARM systems.

Add <arm/endian.h> and remove the cats, dnard and netwinder versions, since
they're all the same (a redirect to <sys/endian.h>).

Move <arm/arm32/bus.h> to <arm/bus.h>, since it looks like it's going to be
necessary on arm26 as well.

Add definitions of C99 integer format conversion macros.
XXX Fastest minimum-width integer types haven't been decided upon yet.

Add definitions of C99 specified-width integer type limits.
XXX Fastest minimum-width integer types haven't been decided upon yet.

Add definitions of C99 integer constant macros.
Tidy Makefiles up a little.

Add definitions of C99 minimum-width and greatest-width integer types.
XXX Fastest minimum-width integer types haven't been decided upon yet.

branches: 1.11.2;
some include files added newly write into Makefile.

Install <arm/endian_machdep.h>.

Fix typo in header filename.

branches: 1.8.2;
Shared ARM ptrace(2) implementation. Mostly the same as the arm32
version, but with some #ifdefs for arm26.

Also, don't define PT_STEP, since we don't implement it. This should
reduce code size a little.

Common <arm/reg.h> (and hence common struct reg) for ARM.
This is theoretically backward-incompatible on arm26, but GDB doesn't work there
yet anyway.

Initial potentially sharable <arm/armreg.h>. Used by all arm26 code.

Add <arm/frame.h>, for shared stack frame structures. Currently, only sigframes
are common.

Move <machine/signal.h> into shared directory.

Share <machine/elf_machdep.h> between arm26 and arm32.

Install all the headers (arm32 does).

Skeleton ARM include infrastructure.

Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.

branches: 1.2.4; 1.2.12; 1.2.38; 1.2.40;
This change arm, armeb, earm, earmeb, earmhf, earmhfeb so all builds that
share a MACHINE_ARCH for userland so that except for etc, will produce
identical sets.

usr/include/machine now points to usr/include/arm

Pickup fenv.h from a common location since it's only used from userland
and the kernel will never include it.

branches: 1.2.2; 1.2.18;
Make -mfloat-abi=soft a native kernel only option. Fixes rump build.

ok justin@

Don't build modules with float instructions.

Add acpi_intr_mask() and acpi_intr_unmask() which, following the pre-existing
ACPI software layering model, are wrappers around acpi_md_intr_mask() and
acpi_md_intr_unmask(), which in turn are wrappers around intr_mask() and
intr_unmask().

XXX ARM and IA64 implementations of acpi_md_intr_mask() and
acpi_md_intr_unmask() are just stubs for now.

branches: 1.2.4;
Add MD functions for establishing and disestablishing interrupt handlers.

branches: 1.1.2;
Add ARM MD ACPI implementation.

More trailing whitespace

All floating point related rtabi (__aeabi) are called using the aapcs
calling standard, not aapcs-vfp. This fixes lots of problems on earmhf

branches: 1.4.4;
Handle _STANDALONE case.

OK from matt@

Allow this to be included in libkern

branches: 1.2.2; 1.2.4; 1.2.6;
#include <stddef.h>

Add aeabi.h header which descibes the C portion of the EABI run time API.

Switch all users (except ia64) of custom machine/ansi.h to common_ansi.h

Deduplicate the code among ports and poll definitions of types
directly from a compiler.

This fixes miscompilation of certain programs that instruct compilers
to generate code for different types. This bug has been detected with
-fshort-wchar in EFI firmware.

Proposed and discussed on a mailing list (twice).

Itanium uses custom !ELF fallback switch, temporarily leave it as it is.

branches: 1.17.30;
consistency in include protection

change include protection from _ANSI_H_ to _ARM_ANSI_H_

branches: 1.15.2;
Change _BSD_SSIZE_T_ so it's not dependent of _BSD_PTRDIFF_T_

Use __{PTRDIFF,SIZE,WCHAR,WINT}_TYPE__ is they are defined.

branches: 1.13.2; 1.13.12;
Retire varargs.h support. Move machine/stdarg.h logic into MI
sys/stdarg.h and expect compiler to provide proper builtins, defaulting
to the GCC interface. lint still has a special fallback.
Reduce abuse of _BSD_VA_LIST_ by defining __va_list by default and
derive va_list as required by standards.

1. {wctype,wctrans,mbstate}_t: switch MD to MI like other
libc implementation (such as *BSD and glibc2).

2. don't typedef void * wc{type,trans}_t, suggested by soda@-san.
it may pass through compiler type check, it's harmful.
so i introduce dummy struct __tag_wc{type,trans}_t(iconv_t already does).

no ABI change was made.

branches: 1.11.4; 1.11.6;
merge christos-time_t

branches: 1.10.2;
Remove non-__ELF__ snippets.

branches: 1.9.16; 1.9.18; 1.9.22; 1.9.24; 1.9.28;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

clean up some definitions around rune_t which are not needed anymore

branches: 1.7.8; 1.7.16; 1.7.22; 1.7.24; 1.7.26; 1.7.28; 1.7.30;
fix gcc -Werror -Wmissing-braces problem
mbstate_t(this is opaque object)'s initializer should be ``{ 0 }'',
so changed 1st field of union from character array to integer.

branches: 1.6.20; 1.6.22;
merge ktrace-lwp.

branches: 1.5.16;
Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

branches: 1.4.2;
add some ISO C 1995 I18N functions and types:
btowc, wctrans, towctrans, wcscoll, wcsxfrm, wctype_t and wctrans_t.

Adjust stdargs/varargs for GCC 3.x.

branches: 1.2.6; 1.2.16; 1.2.18;
Change ARM-ELF to LP64 friendly types.

branches: 1.1.2; 1.1.6;
Header files which don't differ between arm32 and arm26 and can thus be
shared.

whitespace

branches: 1.7.28;
consistency in include protection

Make multiple inclusion symbols always start with _ARM_ (not _ARM32_ or
_MACHINE_).

branches: 1.5.114; 1.5.124; 1.5.130;
merge ktrace-lwp.

Put this back to a #define after he patched sys/exec_aout.h. Otherwise errno.h
has to be pulled in for ENOEXEC definition.

Make cpu_exec_aout_makecmds() a static inline instead of just #define'ed to
ENOEXEC. Broken on ARM build from the de-__P'ing, this is the fix.

branches: 1.2.6; 1.2.14;
Rename __LDPGSZ to AOUT_LDPGSZ, to accurately reflect what it is.

branches: 1.1.2; 1.1.10;
Header files which don't differ between arm32 and arm26 and can thus be
shared.

branches: 1.2.4;
consistency in include protection

branches: 1.1.4; 1.1.6;
This change arm, armeb, earm, earmeb, earmhf, earmhfeb so all builds that
share a MACHINE_ARCH for userland so that except for etc, will produce
identical sets.

usr/include/machine now points to usr/include/arm

branches: 1.1.2;
file arm_intr.h was initially added on branch chris-arm-intr-rework.

move ARMv7 PMC register definitions to armreg.h from tprof_armv7.c

s/auxillary/auxiliary/ in comments.

Add the Cortex A17 Diagnostic control registers

Set ACTLR.SMP=1 on Cortex-A17

Add a placeholder for PRRR

fix typos in comments, mainly s/extention/extension/ and s/sufficent/sufficient/

Fix (unused) PRRR_NOSn #define

branches: 1.129.8;
Explicitly annotate FPU requirements for LLVM MC.

When using GCC, this annotations change the global state, but there is
no push/pop functionality for .fpu to avoid this problem. The state is
local to each inline assembler block with LLVM MC.

Add support for physical timers and sprinkle isb where needed.

branches: 1.127.2;
It's the Normal Memory Remap Register (not Normal Region Remap Register)

Fix Normal Region Remap Register bitmask names

add gtmr_cntv_cval_write

Some CPU specific ACTLR bit definitions

Provide and use cpu_mpidr_aff_read in psci_fdt_bootstrap

Add some PMC event registers

branches: 1.121.2;
Workaround A-008585 errata in GTMR.

Register reads and writes may provide unstable results if the counter
hardware is active at the same time. This results in non-monotonic
counters seen by both the gtmr interrupt and time counter.

The loops are currently applied unconditionally, restricting them to
appropiate FDT markers can be applied later.

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

separate cputypes.h for CPU_ID_* from armreg.h,
and add some implementor IDs, CortexA55,73,75 IDs.

(preliminary changes for merging aarch64)

branches: 1.118.2;
insert a couple of .fpu directives when we access the vfp registers while
is softvpf fpu mode for gcc 6. XXX: there is no .fpu push/pop...

Remove port-acorn26

OK core@

One copy of the generic timer register defines is enough for anyone. The
ARM_ prefixed copies are prefered (at this point) and the comments from
the non-ARM_ prefixed versions are copied over.

Correct ARM_CNTKCTL_PL0[VP]CTEN values. NFC as nothing uses them.

Typo in comment
cvS: ----------------------------------------------------------------------

Some more registers

Add Cortex-A35 CPU ID.

branches: 1.111.14;
Fix CORTEXA9Rx definitions.

Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs.
While I'm here add some A57/A72 info as well.

My RPI3 works with FB console - the uart needs some help with its clocks.

No need to shout

Setting actlr.bit15=1 (Force in order issue in the branch execution unit)
makes my jetson tk1 stable. Apply this workaround until we figure out
what the real problem is.

Use TTBR_[UM]PATTR in a9_mpsubr.S as well as cpufunc_asm_armv7

Prompted by matt@

Add Revision ID register

move register accessor macros for MPIDR and AUXFMC0 to armreg.h

Trailing whitespace

ARM spells the System Control Register SCTLR

branches: 1.102.2;
Add Cortex-A17 ID

Fix dccmvau. Add bpimva.

Fix bpiall and the comment against bpiallis

Minor amendment/corrections.

Remove redundant CORTEXA9_AUXCTL defines

branches: 1.97.2;
Support (untested) SHEEVA_L2_CACHE and SHEEVA_L2_CACHE_WT options.
Move prototypes out to <arm/cpufunc.h> to their own file.
Add sdcache routines to cpufunc_asm_sheeva.S
Add code sheeve_setup to init the sdcache and sdcache info.

Add tpidruro and tpidrurw inlines

branches: 1.95.2;
Add scr inline

Add NSACR

Restrict arm_cond_ok_p to when !__ASSEMBLER && _KERNEL is true.

Avoid a gcc4.8 bogon.

Define all the instruction conditions.
Use __SHIFTOUT to get the condition.
Add bool arm_cond_ok_p(uint32_t insn, uint32_t psr) inline
Add tlbtr inline

More control bits.
SYNCHPRIM defines.

Fix typos

defines/inlines for cortex a5/a7 tlbdata ops

Add more MMU registers

Add more inlines. Default FSR ARMv6+ bits. Add A7/A15 L2CTRL defs.

Flush out the PSR definitions.

Switch to using FP instructions instead of cp10/11 instructions.

fix CPU_ID_CORTEXA7R0

Add MVFR (Media & VFP Features) definitions.

Add TTBCR definitions

branches: 1.80.2;
Improve generic timer inlines to be cnt*_* consistently

Fix VBAR inlines

Fix ARM_PRF1_SEC_MASK value.

Add defines for ARM Generic Timer
Add defines for PFR1 GTIMER and SEC extensions.
Add VBAR inlines

Add Armada XP specific IDs and registers.

Obtained from Marvell, Semihalf.

Fix ID ARM710a for CL PS-711x.

Add c16 c8 (tlb) inlines.
Add CPUID of Cortex-A7 r0

Add inlines for cp10 (vfp) registers

Don't define CP15 inlines when compiling for a _RUMPKERNEL

Add CP15 Generic Timer definitions.
Add cortex PMUSERENR inlines

Add inlines for SCTRL

Add PSR_HYP32_MODE (hypervisor mode).

Only use CPACR register for ARM11 and CORTEX cores.
Add VFP ids for other CORTEX CPUs.

Before testing for VFP, make sure CP10 is enabled. (And CP11 for Neon too).

Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.

branches: 1.65.2;
Add more c7 register inlines. Add some more CT4 defintions

Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7

Add ttbr/ttbr1/ttbcr registers

Use __ASSEMBLER__ to control inline definitions

Don't do inlines if _STANDALONE

Use new armv7 CP15 register to print out cache types.
If the cpu_cc_freq is set, report it.
Add macros to make inlines for reading/writing co-processor registers.

Add SWP enable bit to system control register (Cortex-A9).

Add __HAVE_CPU_COUNTER support for ARM11 and Cortex CPUs

Add MON32 mode (just for completeness).

Make auxiliary register naming consistent for the 1136.

Fix spelling mistake in comments.

Add the documented ARM11[37]6 Auxiliary control register defines.

Fix CPU_ID_CORTEX_P and add CPU_ID_CORTEX_A8_P

Begin support for Cortex A5, A7, A15 and expand A8 and A9 definitions.
Instead of testing all possible CPUids for a cortex, we know what range
a cortex will be so mask out the insignificant parts and do a single test.

Remove the ARM1156T2 bloat - it only has an MPU. Prompted by matt@

Add the ARM1156T2-S

Add the 'Z' to the 1176 cpu product name.

ok matt@

branches: 1.48.2; 1.48.6; 1.48.8;
dependant -> dependent

Preliminary ARM11 MPCore support.

I have confirmed this commit doesn't affect existing evbarm kernels by
comparing binaries.

branches: 1.46.2;
fix XP bit and U bit definitions of CP15 control register.
These constants are not used in our source tree for now,
so this won't change any kernel bianries.

Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Fix cache probing on Cortex. Add missing CORTEX dependency in cpu.c

Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb
instructions.

Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.

PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt

branches: 1.41.12; 1.41.14; 1.41.16;
Add new CPU Cache register definitions for Cortex-A8.

Define IF32_bits as the union of I32_bit|F32_bit

Implement workaround for:
arm11 Errata 364296:Possible Cache Data Corruption with Hit-Under-Miss

Remove hack in userret which is redundant with workaround.

workaround code from <imre.deak@teleca.com>

branches: 1.38.2; 1.38.4; 1.38.6;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.37.26; 1.37.46; 1.37.48; 1.37.50;
Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E

branches: 1.36.2;
The ARM7500 ID is no longer a guess -- I've confirmed it on a real ARM7500.

branches: 1.35.8; 1.35.10;
Added FARADAY FA526 ID.

branches: 1.34.4; 1.34.6; 1.34.8; 1.34.10; 1.34.12;
merge ktrace-lwp.

Added i80219.

branches: 1.32.2;
Add CPU_ID_ARCH_V5TEJ and CPU_ID_ARCH_V6.
Add CPU_IDs for ARM1136J-s and ARM1136J-S R1.

Add CPU-id for arm1026ej-s.

Define THUMB_INSN_SIZE.

add CPU ID for Bulverde

Overhaul arm32's abort handlers:

- Assume a permission fault is always the result of an attempted
write, so no need to disassemble the opcode.
(as discussed with Richard Earnshaw/Jason Thorpe a week or two ago)

- Split out non-MMU data aborts into separate functions, and deal
correctly with XScale imprecise aborts. Specifically, the old code
made no attempt to handle the double abort faults which can occur
as a result of two consecutive external (imprecise) aborts. This
was easy to provoke by read(2)ing from a /dev/mem offset which caused
an external abort. With the old code, this would bring the system
down instantly, with little clue as to why. (hint: tf_spsr held
PSR_ABT32_MODE...)

- Re-write badaddr_read() to use pcb_onfault instead of adding extra
overhead to data_abort_handler(). A side effect of this is that it
now benefits from the XScale double abort recovery.

- Invoke the cpu-specific prefetch/data abort fixup routines only if
the host cpu actually needs it. On other cpus, the code is optimised
away.

- Sprinkle __predict_{false,true} in all the right places.

- G/C some excess debugging baggage.

Add arm1020E cpu id

Recognize some TI processors -- not that you'd want to use them.

branches: 1.25.2;
add CPU types
IXP425 xscale-core NetworkProcessor

later, Ill commit codes for IXP425-evaluation board

Make the ARM_VECTORS_* unsigned.

fix XScale core revision mask, and add masks for core generation and
product number.

Add CPU IDs for PXA B2 and C0 steppings.

Handle i80200 step D0 and i80321 step B0

add cpu id for "PXA250/210 3rd version CPUcore".

for using many PDA/xscale-core.

Add the CPU ID for the 600MHz i80321 part.

branches: 1.18.2; 1.18.4;
add CPU ID of IXP1200 network processor

Fix a typo and an omission in last.

Add bits for the XScale Auxillary Control Register.

Define the two possible addresses for the ARM vector page.

Add a comment summarizing the post-ARM3 CP15 registers.

The 80321 manual lies; it does have a CPU ID distinct from the 80200.
Add that CPU ID, and add a case for it.

Restructure a few things in order to support other XScale core
I/O processors:
* The i80200 and the i80321 have the same CPU ID, so split the
CPU_XSCALE option into CPU_XSCALE_80200 and CPU_XSCALE_80321
options, and don't let them both be defined at the same time.
XXX May want to revisit this in the future.
* Split some registers common between the i80200 and i80321 into
<arm/xscale/xscalereg.h>.
* Rename a few existing functions.

Add CPU ID for the ARM1022ES.
Also add a CPU class for ARM10E processors in general.

Add Cotulla CPU IDs.

Fetch cache info from the Cache Type register on ARM7TDMI and "greater"
processors. Report this when the processor is attached.

branches: 1.8.6;
Add Jazelle mode flag.

branches: 1.7.2;
Correct CPU_ID_ISOLD() and CPU_ID_IS7().

branches: 1.6.2;
Add CPU ID for ARM7500FE (determined empirically from two I've got here).

ARM7100 -> ARM710A, following information from reinoud.

Guess a CPU ID for the ARM700 as well.

Add possible CPU ID for ARM7500 (based on arm/cpu.h).
Add macros to distinguish the three formats of CPU ID.

Add CPU_ID_CPU_MASK. Different, but (I hope) more useful definition than
arm32 currently uses.

branches: 1.1.2;
Initial potentially sharable <arm/armreg.h>. Used by all arm26 code.

Update to support EFI runtime outside the kernel virtual address space
by creating an EFI RT pmap that can be activated / deactivated when
required.

Adds support for EFI RT to ARM_MMU_EXTENDED (ASID) 32-bit Arm machines.

On Arm64 the usage of pmapboot_enter is reduced and the mappings are
created much later in the boot process -- now in cpu_startup_hook.
Backward compatiblity for KVA mapped RT from old bootaa64.efi is
maintained.

Adding support to other platforms should be easier as a result.

Style. NFCI.

branches: 1.6.2;
kasan: fix the copyright notices

Round of uvm.h cleanup.

The poorly named uvm.h is generally supposed to be for uvm-internal
users only.

- Narrow it to files that actually need it -- mostly files that need
to query whether curlwp is the pagedaemon, which should maybe be
exposed by an external header.

- Use uvm_extern.h where feasible and uvm_*.h for things not exposed
by it. We should split up uvm_extern.h but this will serve for now
to reduce the uvm.h dependencies.

- Use uvm_stat.h and #ifdef UVMHIST uvm.h for files that use
UVMHIST(ubchist), since ubchist is declared in uvm.h but the
reference evaporates if UVMHIST is not defined, so we reduce header
file dependencies.

- Make uvm_device.h and uvm_swap.h independently includable while
here.

ok chs@

Some KASAN fixes and tweaks

- don't access BSS variables when __md_early
- centralise the INIT_ARM_STACK_{SHIFT,SIZE} defines and create a new
INIT_ARM_TOTAL_STACK
- Only create L1PT entries in kasan_md_shadow_map_page if
arm32_kernel_vm_init hasn't created the L2PTs (and their L1PT entries)
- Add some comments to explain what's going on

Fix RPI boot which needs more early stack

XXX centralise INIT_ARM_STACK_{SHIFT,SIZE}
XXX how to protect against this breaking again?

Oops... deal with a last minute #define name change. KASAN support now
builds.

Add support for KASAN on ARMv[67]

Thanks to maxv for many pointers and reviews.

arm: asm.h - change GOT_INIT to take the normal asm label

Don't pass the label to use for the "current address" as the macro
parameter. It obscures its purpose and makes the use of local labels
extremely unobvious, so you are forced to invent a name that is mostly
useless otherwise:

GOT_INIT(r3, .Lgot.execsp_start, .Lpc.execsp_start)
GOT_INITSYM(.Lgot.execsp_start, .Lpc.execsp_start)
vs.
0: GOT_INIT(r3, .Lgot.execsp_start)
GOT_INITSYM(.Lgot.execsp_start, 0b)

Same object code is generated.

arm: asm.h - no ## at token boundaries

For the ## "if the result is not a valid preprocessing token, the
behavior is undefined", so you 1) don't need to 2) must not use it to
concatenate a token with a non-token, like .arg or arg()

The point is kinda moot, as traditionally asm with cpp uses traditional
cpp, not ANSI cpp (many assemblers use # for literals, which conflicts
with the ANSI CPP # stringization and requires awkward workarounds),
but don't set a bad example even if it never gets called out by the
compiler.

arm/asm.h: revert PCREL_GET &c in previous (ok riastradh)

This change needs to be redone and re-verified. I have detailed some
issues in the PR, and it also turns out that some of the changes were
in the !_REENTRANT branch of #ifdef and thus not checked at all.
riastradh asked to back out the changes for now.

PR lib/59391: unnecessary __PIC__ conditionals clutter .S files

arm: Nix most __PIC__ conditionals in .S files.

New macros PCREL_GET(rN,label,pclabel) and PCREL_SYM(label,pclabel)
to enable this by the pattern:

ldr rN, label
#ifdef __PIC__
pclabel:
add rN, rN, pc
#endif
...
label:
#ifdef __PIC__
.word (label - (pclabel + 2*sizeof(instruction)))
#else
.word label
#endif

(sizeof(instruction) = 2 for thumb, 4 for non-thumb.)

No binary change in libc with MKPIE=no (i.e., testing both for
changes to the PIC build and changes to the non-PIC build).

In principle, assembly routines could improve instruction scheduling
by splitting up the ldr and add instructions. But in practice, the
maintenance and auditing burden likely makes this worthwhile by
improving legibility vs a tangle of in-line #ifdefs.

brk.S does things a little differently making it harder to unify.
Could redo it but I don't want to make changes without testing them
first.

PR lib/59391: unnecessary __PIC__ conditionals clutter .S files

branches: 1.35.2;
arm/asm.h: Respect NETBSD_REVISIONID.

Fix userland gprof profiling on aarch64.

Adjusts _PROF_PROLOGUE to match OpenBSD; reworks our MCOUNT to retrieve
frompc placed on stack by the prologue, and to streamline sp manipulation
when preserving argument registers.

LLVM is a bit stricter and wants the ARM variant of %progbits.

Mark the .ident section as mergable string section to avoid redundant
entries.

Add support for Branch Target Identification (BTI).

On the executable pages that have the GP (Guarded Page) bit, the semantic
of the "br" and "blr" instructions is changed: the CPU expects the first
instruction of the jump/call target to be "bti", and faults if it isn't.

We add the GP bit on the kernel .text pages (and incidentally the .rodata
pages, but we don't care). The compiler adds a "bti c" instruction at the
beginning of each C function. We modify the ENTRY() macros to manually add
"bti c" in the asm functions.

cpuswitch.S needs a specific change: with "br x27" the CPU expects "bti j",
which is bad because the functions begin with "bti c"; switch to "br x16",
for the CPU to accept "bti c".

BTI helps defend against JOP/COP. Tested on Qemu.

branches: 1.30.10;
fix duplicated chunk from merge

Merge the [pgoyette-compat] branch

branches: 1.28.2;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.27.28;
Remove duplicate END(y) macro

Make multiple inclusion symbols always start with _ARM_ (not _ARM32_ or
_MACHINE_).

arm doesn't need to use (PLT) anymore.

Pass PICFLAGS down to cc-as-as and use __PIC__ to decide if it is small
vs big PIC mode. Retire -DPIC and -DBIGPIC.

Do alternative text sections better, add a _TEXT_SECTION which defaults to
.text but can be overridden before <arm/asm.h> gets included.

remove __thumb__ PIC specifics. no different from ARM except being pc+4 not
pc+8

Don't define RETc if Thumb1
Add REL_SYM(a, b)
Make GOT_INIT* thumb aware.

Add _THUMB_ENTRY and _ARM_ENTRY which do the appropriate things including
switching instruction sets.
Use __thumb__ to decide which _ENTRY gets defined as

Switch to unified syntax
use it to get condition return on thumb

Add KMODTRAMPOLINE(name)
There are 3 variations:
one for armv7 using movw ip,#:lower16:func; movt ip,#:upper16:func; bx ip
one for armv4t+ using ldr ip, pc; bx ip; .word func
one for everything else using ldr pc, [pc, #-4]; .word func

branches: 1.17.2;
Add a RETr(r) macro (indirect return through register r).

branches: 1.16.2;
Add __BITS to asm.h (remove from imxuartreg.h)
Add L1_S_AP_KR to genassym.h
Use L1_S_AP_* in omap_start.S and don't include pmap.h

Add __BIT(n) macro

branches: 1.14.2; 1.14.10;
dependant -> dependent

Consistently use .gnu.warning with .pushsectio and .popsection on all
architectures instead of obsolete STABS frames for linker warnings.

branches: 1.12.12; 1.12.16;
Remove non-__ELF__ support. Use .pushsection/.popsection for RCSID.

branches: 1.11.2; 1.11.6;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.10.16; 1.10.18; 1.10.20;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.9.2;
Move _ARM_ARCH_* from asm.h to cdefs.h so everyone can use them.
Add _END/END/ASEND which every port's asm.h should have.
Add GET_CPUFINO(rX). Reserved for future use. :)
Use %foo instead of #foo

branches: 1.8.28; 1.8.36; 1.8.42; 1.8.44; 1.8.46; 1.8.48;
Add a STRONG_ALIAS macro

branches: 1.7.2;
merge ktrace-lwp.

branches: 1.6.12;
Define _ARM_ARCH_6, _ARM_ARCH_5 and _ARM_ARCH_4T, based on
architecture defines passed from the compiler.

Define RET and RETc macros for return and conditional return. If BX is
available in the current instruction set then make use of it.

Note: these really are from the compiler's -march/-mcpu flags, not
from the kernel config, so they can be relied on in user space.

Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

branches: 1.4.6; 1.4.24;
Change way PIC stuff is emitted for ELF to be more flexible.

Add a GOTSYM which emits the right stuff to GOT symbols under ELF and/or
a.out.

branches: 1.2.2;
Add ELF version of _PROF_PROLOGUE.

branches: 1.1.2; 1.1.4;
Header files which don't differ between arm32 and arm26 and can thus be
shared.

G/C arm/atomic.h

This is not longer needed since atomic_{set|clear}_bit are now dead.
So temporarily this has no contents.

branches: 1.10.6; 1.10.10; 1.10.16; 1.10.18;
When manipulating the interrupt status for atomic ops use cpsr_c rather
than cpsr_all, this avoids updating unnecessary fields in the cpsr.

As a side effect, the inline versions no longer clobber the condition
codes.

branches: 1.9.8; 1.9.16; 1.9.20; 1.9.22; 1.9.28; 1.9.34;
Don't export to userland functions that will only be used in the kernel.

PROG26 version of __with_interrupts_disabled(), and hence of the various
functions in this file.

Fix a typo, spotted by martin (I stared myself blind on that one...).

Add <arm/mutex.h> and <arm/rwlock.h>
Add atomic_cas to <arm/atomic.h> for use by <rwlock.h>

branches: 1.5.26;
inline -> __inline

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.2.16;
fix typo pointed out by Olivier Houchard. thanks.

branches: 1.1.2; 1.1.4; 1.1.10;
make atomic_{set,clear}_bit() inline for arm32 ports, and
add <machine/atomic.h> for them.

More trailing whitespace

branches: 1.2.2; 1.2.10;
Add write_multi_1().

Move the declarations of blockio.S functions from katelib.h to a new, exciting
<arm/blockio.h>. katelib.h includes it for compatibility.

Trailing whitespace

Multiple inclusion protection

Add a few bootconfig helpers:
- get_bootconf_string: returns a copy of the "value" part of a k=v pair
as a string.
- match_bootconf_option: returns true if the "value" part of a k=v pair
exists and the supplied val param is present in the beginning of the
k=v pair's value.

add BOOTOPT_TYPE_MACADDR for parsing mac address parameters

branches: 1.6.2; 1.6.14; 1.6.16;
Make cpu_reset, most of initarm and the kvm init code common.
Add MP hooks for cpu_need_resced
Add idlestck which is allocated in arm32_kvminit

branches: 1.5.12; 1.5.20;
Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.

branches: 1.4.58; 1.4.66; 1.4.72; 1.4.76;
boot_file is not used by generic NetBSD/arm code, and its type varies by
MACHINE. Thus, move it out of <arm/bootconfig.h> and put it into
<machine/bootconfig.h> on those MACHINEs (cats, hpcarm, and shark) where
it's used outside the file in which it's defined.

branches: 1.3.20; 1.3.22;
merge ktrace-lwp.

branches: 1.2.2;
Adapt to shadowing and qualifier-cast warnings.

branches: 1.1.2; 1.1.10; 1.1.28;
Add <machine/bootconfig.h> on arm26, and add an <arm/bootconfig.h> for it to
include (since all the contents are MI).

Add latent AArch64 support.

Make multiple inclusion symbols always start with _ARM_ (not _ARM32_ or
_MACHINE_).

branches: 1.4.112; 1.4.122; 1.4.128;
Change sys/arch/xxx/include/bswap.h to #include machine/byte_swap.h then
sys/bswap.h in order to pick up the MD inline routines and the constant
folding definitions in the right order.
Code can include either sys/bswap.h or machine/bswap.h with the same effect.

branches: 1.3.24; 1.3.36;
* Rename "word" -> 16, and "long" -> 32, as suggested by Ben Harris.
* Replace __byte_swap_32_variable() with a C version from Richard
Earnshaw that generates nearly identical assembly (and it would be
exactly identical with the addition of another peephole to GCC ARM
back-end).

Byte-swapping optimizations, enabled if compiling with GCC:
* Byte-swap 16-bit and 32-bit constants at compile-time.
* Inline 16-bit and 32-bit variable byte-swaps. These take 3 and 4
insns, respectively, and inlining saves the minimum 6 cycle penalty
to call/return from the byte swap function.

branches: 1.1.2; 1.1.6; 1.1.10; 1.1.18; 1.1.20;
Header files which don't differ between arm32 and arm26 and can thus be
shared.

On ARM-ish ports having PCI support, use new-style <sys/bus.h>. Do not
install <machine/bus.h>. Remove various <machine/bus.h> sources.

branches: 1.20.2;
Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.

branches: 1.19.8; 1.19.14; 1.19.18;
Remove clause 3 and 4 from TNF licenses

branches: 1.18.42; 1.18.44; 1.18.46;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

add a pair of new bus_dma(9) functions:
int _bus_dmatag_subregion(bus_dma_tag_t tag,
bus_addr_t min_addr,
bus_addr_t max_addr,
bus_dma_tag_t *newtag,
int flags)
void _bus_dmatag_destroy(bus_dma_tag_t tag)

that allow a (normally broken/limited) device to restrict the bus address
range it can talk to. this is used by bce(4) to limit DMA addresses to
1GB range, the maximum the chip can address.

all this is from Yorick Hardy <yhardy@uj.ac.za> with input from several
people on tech-kern.

XXX: bus_dma(9) needs an update still.

branches: 1.16.20;
merge yamt-uio_vmspace branch.

- use vmspace rather than proc or lwp where appropriate.
the latter is more natural to specify an address space.
(and less likely to be abused for random purposes.)
- fix a swdmover race.

branches: 1.15.2; 1.15.4; 1.15.6;
merge ktrace-lwp.

branches: 1.14.4;
Add a dm_maxsegsz public member to bus_dmamap_t. This allows a user of the API
to select the maximum segment size for each bus_dmamap_load (up to the maxsegsz
supplied to bus_dmamap_create). dm_maxsegsz is reset to the value supplied to
bus_dmamap_create when the dmamap is unloaded.

branches: 1.13.8; 1.13.10;
Use #if defined(_KERNEL_OPT) to protect #include "opt_xxx.h"
from building LKM etc. Suggested by mrg.

Add a defflag for __BUS_SPACE_HAS_STREAM_METHODS, and add the
appropriate glue in bus.h, contingent on the option being defined.

This allows stream methods to be available on a port-by-port basis.

Add an opaque cookie field to the bus dma tag.

branches: 1.10.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Introduce BUS_DMA_NOCACHE, and bus_dmamem_map() of i386 supports it.

Use separate function pointers for dmamap_sync pre- vs post- operations.
Change the bus_dmamap_sync() macro to test the ops argument against pre-
and post- constants. The compiler will optimize out dead code because
of the constants. Since post- operations are not needed on ARM (except
for ISA bounce buffers), this eliminate a large number of function calls
which are noops, each of which cost at least 6 cycles just in the call
and return overhead (not to mention whatever other useless work the
compiler decides to do in the callee).

* Add an ARM32_DMAMAP_COHERENT flag to indicate that a loaded DMA
map contains "coherent" (non-cached in ARM-land) mappings.
* Set ARM32_DMAMAP_COHERENT in the map at the start of a load operation,
and clear it in _bus_dmamap_load_buffer() if we encounter any cacheable
mappings.
* In _bus_dmamap_sync(), if the map is marked COHERENT, skip any cache
flushing.

Overhaul how DMA ranges work in the ARM bus_dma implementation.

A new "arm32_dma_range" structure now describes a DMA window, with
a system address base, bus address base, and length. In addition to
providing info about which memory regions are legal for DMA, the new
structure provides address translation support, as well.

As before, if a tag does not list any ranges, then all addresses are
considered valid, and no DMA address translation is performed.

This allows us to remove a large chunk of code which was duplicated and
tweaked slightly (to do the address translation) from the stock ARM
bus_dma in the XScale IOP and ARM Integrator ports.

Test compiled on all ARM platforms, test booted on Intel IQ80321 and Shark.

Change the way that DMA map syncs are done. Instead of remembering
the virtual address for each DMA segment, just cache a pointer to the
original buffer/buftype used to load the DMA map, and use that. This
lets us shrink the bus_dma_segment_t down from 12 bytes to 8, and the
cache flushing is also more efficient.

Tested on an i80321 -- changes to others are mechanical.

branches: 1.4.8; 1.4.10;
Overhaul bus_dmamap_sync for the ARM:
* Track which process (XXX really, vmspace) owns the mapping. When
we sync the map, if the mapping doesn't belong to the kernel or to
the current process (XXX really, vmspace), then no cache fobbing
is necessary, since the cache is Wb-Inv'd on context switch (XXX need
to revisit this when we support FCSE).
* Be smarter about which cache operation we do when sync'ing the map:
- PREREAD -- Invalidate D$ (XXX right now, we actually do Wb-Inv)
- PREWRITE -- Write-back D$ (note, we do NOT invalidate here)
- PREREAD|PREWRITE -- Wb-Inv D$

More work is needed here. In particular, a version for CPUs
with write-through caches should be provided, to eliminate
the write-back steps (which are noops on such CPUs, but skipping
two branches would be nice).

branches: 1.3.4;
Initial commitment of the bus_space_mmap() functions as proposed by Jason R
Thorpe as an extension to the bus_space(9) API.

Only the mainbus has a working mmap... iomd, podulebus and isa dont have
one yet. Its trivial to add the iomd and isa's memory part but am a bit
hessistant to add it without knowing its implications by heart.

Podulebus might be implemented in 32 bits EASI but otherwise its not really
transparent since there is AFAIK no function to explicitly read one byte or
so .. or is this implemented in a higher level ?

ARM26 and arch/arm32/dnard (Shark) kernels compile and RiscPC and Shark
kernels are tested and function OK.

Implications of other ARM systems like hpcarm and ebarm are propably
minimal or solved trivially.

branches: 1.2.2;
Add BUS_DMA_READ and BUS_DMA_WRITE flags, that hint the back-end
at dmamap load time that the mapping will be used for a unidirectional
transfer of the specified direction.

branches: 1.1.2; 1.1.4;
Move <arm/arm32/bus.h> to <arm/bus.h>, since it looks like it's going to be
necessary on arm26 as well.

Use "non-posted" instead of "strongly ordered" to describe nGnRnE mappings

Rename the following defines:
- _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED to BUS_SPACE_MAP_NONPOSTED
- PMAP_DEV_SO to PMAP_DEV_NP
- LX_BLKPAG_ATTR_DEVICE_MEM_SO to LX_BLKPAG_ATTR_DEVICE_MEM_NP
Rename the following option:
- AARCH64_DEVICE_MEM_STRONGLY_ORDERED to AARCH64_DEVICE_MEM_NONPOSTED

Ensure bus_dmatag_subregion is called with an inclusive max_addr
everywhere.

Add storage for an iommu cookie in bus_dmamap_t and store untranslated CPU
address in bus_dma_segment_t.

Trialing whitespace

Add KASAN-DMA support on aarch64, same as amd64. Discussed with skrll@.

branches: 1.14.6;
Do not use Early Write Acknowledge for PCIe I/O and config space.

branches: 1.13.4;
On second thought, get rid of "bs_base" from struct bus_space and use a
custom bs_map for acpipchb instead.

Add a "bs_base" field to struct bus_space. If present, use it to translate
mappings by appending the value to the pa passed to bus_space_map.

branches: 1.11.2;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.10.28;
Make multiple inclusion symbols always start with _ARM_ (not _ARM32_ or
_MACHINE_).

branches: 1.9.2;
Add PRIxBUSADDR, etal

Get rid of _BUS_DMAMAP_MEM_XLATE

Add a _BUS_DMAMAP_NOALLOC which tells bus_dmamem_alloc to skip that
dmarange when allocating memory.
Add a second dmarange to bcm23xx obio to allow it to map coherently mapped
memory.

Add a flag to make bus_dmamem_map use the bus/sys transation table when
mapping bus addresses. Make bcm2835 obio use it.

C99 types

Make IS_BOUNCING a map flag and use it to simplify code and to avoid calling
the sync routines if (COHERENT|IS_BOUNCING) == COHERENT. (this eeks out a
little bit more performance).

Add per-segment and per-ragne flag (to store _BUS_DMAMAP_COHERENT).
Use the per-range flag to set the per-segment flag.
This allows bus_dma to skip flushing for known coherent memory regions.

Add bounce buffer support for ARM bus_dma(9). Add macros to help initialize
bus_dma_tag structures.

branches: 1.1.2; 1.1.10; 1.1.12;
Per discussion at
<http://mail-index.netbsd.org/tech-kern/2010/04/02/msg007941.html>,
divide each machine's bus.h into bus_defs.h (constants & data types)
and bus_funcs.h (macro implementations of bus_space(9) routines and MD
prototypes).

Note that some bus_space(9) routines' implementation will move to .c
files from inline subroutines or macros in .h files.

I've only made the split for machine architectures where there is PCI.
All of the non-PCI-having architectures will require a similar split.

These #include files are not referenced by any (committed) Makefiles or
header files, yet. Changes to Makefiles, to <sys/bus.h>, and to some
more machine-dependent files will dribble in before I throw the switch.

G/C unnecessary

extern paddr_t physical_start, physical_end;

Fix _bus_dmamem_alloc_range function declaration - low and high are
paddr_t

Obey __HAVE_BUS_SPACE_8

branches: 1.10.2;
Add missing prototypes for __bs_c(f,_bs_sm_?_swap)

(implementations of these already exist for aarch64)

Add KASAN-DMA support on aarch64, same as amd64. Discussed with skrll@.

branches: 1.8.8;
Remove the _BUS_DMAMAP_COHERENT optimisation in the bus_dmamap_sync macro
as the real function performs memory barriers now.

branches: 1.7.2;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.6.28;
Make multiple inclusion symbols always start with _ARM_ (not _ARM32_ or
_MACHINE_).

branches: 1.5.2;
Cortex needs ._dmamap_sync_post for BUS_DMASYNC_POSTREAD

Make IS_BOUNCING a map flag and use it to simplify code and to avoid calling
the sync routines if (COHERENT|IS_BOUNCING) == COHERENT. (this eeks out a
little bit more performance).

Add bounce buffer support for ARM bus_dma(9). Add macros to help initialize
bus_dma_tag structures.

branches: 1.2.2;
s/u_int*_t/ -> uint_*_t
Add swap variants for many accessors.

branches: 1.1.2; 1.1.10;
Per discussion at
<http://mail-index.netbsd.org/tech-kern/2010/04/02/msg007941.html>,
divide each machine's bus.h into bus_defs.h (constants & data types)
and bus_funcs.h (macro implementations of bus_space(9) routines and MD
prototypes).

Note that some bus_space(9) routines' implementation will move to .c
files from inline subroutines or macros in .h files.

I've only made the split for machine architectures where there is PCI.
All of the non-PCI-having architectures will require a similar split.

These #include files are not referenced by any (committed) Makefiles or
header files, yet. Changes to Makefiles, to <sys/bus.h>, and to some
more machine-dependent files will dribble in before I throw the switch.

remove unnecessary cast, KNF

branches: 1.15.2;
Avoid gcc warnings

elide conversion warning.

branches: 1.13.14; 1.13.18;
Use uint32_t for __asm to appease clang.

branches: 1.12.2;
Disable arm32 __asm for _byte_swap_u16_variable since gcc4.5 produces
decent code for it. Fixes PR/46898.

Use defined(_ARM_ARCH_[67])

Add BSWAP16 and BSWAP32 macros for use in assembly.

Use __builtin_constant_p so that we only emit asm when
the expression is not a constant.

branches: 1.8.18; 1.8.34; 1.8.40; 1.8.42;
Remove clause 3 and 4 from TNF licenses

Merge kernel changes in matt-armv6 to HEAD.

branches: 1.6.50; 1.6.74; 1.6.76; 1.6.78;
Move all the stuff that detects bswapxx(constant) into the MI sys/bswap.h
Put the minimum to define the required inline assembler or C into the MD files.
NB: there may be some fallout from this!

branches: 1.5.2;
inline -> __inline

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

branches: 1.3.2; 1.3.24;
Ensure that some integer constants are always unsigned.

branches: 1.2.2; 1.2.4; 1.2.6; 1.2.8;
* Rename "word" -> 16, and "long" -> 32, as suggested by Ben Harris.
* Replace __byte_swap_32_variable() with a C version from Richard
Earnshaw that generates nearly identical assembly (and it would be
exactly identical with the addition of another peephole to GCC ARM
back-end).

Byte-swapping optimizations, enabled if compiling with GCC:
* Byte-swap 16-bit and 32-bit constants at compile-time.
* Inline 16-bit and 32-bit variable byte-swaps. These take 3 and 4
insns, respectively, and inlining saves the minimum 6 cycle penalty
to call/return from the byte swap function.

Switch earmv6{,hf}eb to BE8 in kernel side.

My strategy here is to define _ARM_ARCH_BE8 macro in arm/cdefs.h, if
__ARMEB__ && _ARM_ARCH_6.

Use this macro to determine whether system is compiled for and running on
BE8 mode or not.

Note that, for __ARMEB__, some conditions become compile-time constants
determined by _ARM_ARCH_BE8 macro, e.g., whether BE8 or BE32 are accepted
as a userland binary, or unaligned memory access is possible or not.

The ARM C Language Extenstion document defines __ARCH_ARM as the integer
macro indicating the current ARM instruction set. Let's use it.

PR/55778: evbarm64 GENERIC64 kernel fails to build with clang

XXX Handle the fact that for an ARM architecture ARMvX.Y then,
XXX __ARM_ARCH= X * 100 + Y. E.g. for ARMv8.1 __ARM_ARCH = 801.

branches: 1.17.2;
Define _ARM_ARCH_8 when __ARM_ARCH_8A (no trailing double underscore) as
it is defined by gcc.

__ARM_ARCH_8A__ (with trailing double underscore) seems to be a typo (or
maybe historical)

ARMv6KZ has been misspelled by GCC since forever, but clang only
provides the correct name. Support both.

branches: 1.15.28;
unbreak lint

branches: 1.14.2;
Use sizeof(__int128_t) for aarch64 and sizeof(long long) for ARM EABI

Make all __ALIGNBYTES macros return the same type (size_t)

Fix inverted GCC version test

Add a check for minimum compiler compatible with gcc 4.1
__ARM_PCS_AAPCS64 also requires __ALIGNBYTES to be 7

Deal with __ARM_ARCH_8A__

Add _ARM_ARCH_5T (needed for blx <reg> support)

Add _ARM_ARCH_T2 to indicate Thumb2 support
Don't define _ARM_ARCH_DWORD_OK disappear if compiling for Thumb1

branches: 1.7.2; 1.7.4;
Add a macro for determining whether we can use LDRD/STRD instructions

If we are using EABI (aapcs-linux), then ALIGNBYTES needs to deal with
8-byte long types.

Add more arm7 and arm6 variants.

branches: 1.4.4;
Change CMSG_SPACE and CMSG_LEN to provide Integer Constant Expressions
again. This was changed in sys/socket.h r1.51 to work around fallout
from the IPv6 aux data migration. It broke the historic ABI on some
platforms. This commit restores compatibility for netbsd32 code on such
platforms and provides a template for future changes to the CMSG_*
alignment. Revert PCC/Clang workarounds in postfix and tmux.

branches: 1.3.38; 1.3.54; 1.3.58;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Move _ARM_ARCH_* from asm.h to cdefs.h so everyone can use them.
Add _END/END/ASEND which every port's asm.h should have.
Add GET_CPUFINO(rX). Reserved for future use. :)
Use %foo instead of #foo

branches: 1.1.2; 1.1.44; 1.1.86; 1.1.94; 1.1.100; 1.1.102; 1.1.104; 1.1.106;
Header files which don't differ between arm32 and arm26 and can thus be
shared.

Merge the gehenna-devsw branch into the trunk.

This merge changes the device switch tables from static array to
dynamically generated by config(8).

- All device switches is defined as a constant structure in device drivers.

- The new grammer ``device-major'' is introduced to ``files''.

device-major <prefix> char <num> [block <num>] [<rules>]

- All device major numbers must be listed up in port dependent majors.<arch>
by using this grammer.

- Added the new naming convention.
The name of the device switch must be <prefix>_[bc]devsw for auto-generation
of device switch tables.

- The backward compatibility of loading block/character device
switch by LKM framework is broken. This is necessary to convert
from block/character device major to device name in runtime and vice versa.

- The restriction to assign device major by LKM is completely removed.
We don't need to reserve LKM entries for dynamic loading of device switch.

- In compile time, device major numbers list is packed into the kernel and
the LKM framework will refer it to assign device major number dynamically.

add ixpcom to cdevsw

branches: 1.7.2;
Complete renaming of opms to opms (was partly named pms, externally and
internally). Move arm/iomd/pms* to arm/iomd/opms*. Mechanical change,
tested by cross-compiling a kernel from i386.

Approved by christos.

XXX: What are arm/arm32/conf.c and arm/include/conf.h good for?

Use "#define<tab>".

- define other DEV_ constants that the local port uses.
- delete cdev_decl(mm) since <sys/conf.h> does it.

branches: 1.4.2;
Declare the plcom device.

branches: 1.3.2;
Add cdev_decl for new devices in conf.c

branches: 1.2.2;
Readd sacom to cdevsw.

branches: 1.1.2;
Switch netwinder to use a common conf.c for the arm ports.

arm/cpu.h: Need sys/param.h for COHERENCY_UNIT.

Nix machine/param.h -- not meant to be used directly, pulled in by
sys/param.h.

G/C an unused struct cpu_info member

branches: 1.123.4;
pic: Update ci_cpl in pic_set_priority callback.

Not all ICs need interrupts disabled to update the priority. DAIF accesses
are not cheap, so push the update of ci_cpl from pic_set_priority to the
IC's pic_set_priority callback, and let the IC driver determine whether
or not it needs interrupts disabled.

arm: Forward-declare `struct proc' before using in prototype.

Move arm_cache_info from cpufunc.h to cpu.h

Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.

The AP initialisation code in cpu_init_secondary_processor will read and
initialise the required system registers and state for the BP to attach
and report.

Rework the interrupt handler code for this new sequence. Thankfully,
this removes a bunch of code for bcm2836mp.

The VFP detection handler on <= armv7 relies on the global undefined
handler being in place until the BP attaches vfp. That is, after the
APs have been spun up.

gicv3_its.c has a serialisation issue which is protected against in
the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin
lock. The serialisation issue needs addressing more completely.

Tested on RPI3, Apple M1, QEMU, and lx2k

Fixes PR port-arm/56264:
diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3

Improved the performance of kernel profiling on MULTIPROCESSOR, and possible to get profiling data for each CPU.

In the current implementation, locks are acquired at the entrance of the mcount
internal function, so the higher the number of cores, the more lock conflict
occurs, making profiling performance in a MULTIPROCESSOR environment unusable
and slow. Profiling buffers has been changed to be reserved for each CPU,
improving profiling performance in MP by several to several dozen times.

- Eliminated cpu_simple_lock in mcount internal function, using per-CPU buffers.
- Add ci_gmon member to struct cpu_info of each MP arch.
- Add kern.profiling.percpu node in sysctl tree.
- Add new -c <cpuid> option to kgmon(8) to specify the cpuid, like openbsd.
For compatibility, if the -c option is not specified, the entire system can be
operated as before, and the -p option will get the total profiling data for
all CPUs.

Re-apply

Move 'struct pic_pending' from percpu to struct cpu_info. Saves a few
instructions in splx.

There is(/was) no need to use atomic operations on the percpu / cpu_info
members, so don't.

Finally removng the use of percpu should help avoid problems with "late"
attaching cpus.

Revert recent pic optimizations until I have more time to work on this.

branches: 1.116.2;
Keep current hardware priority value in struct cpu_info and use it instead
of reading icc_pmr_el1 in gicv3_set_priority.

Move 'struct pic_pending' from percpu to struct cpu_info. Saves a few
instructions in splx.

branches: 1.114.2;
swap sys/param.h for machine/param.h. this still obtains the
wanted COHERENCY_UNIT, while avoiding have a cascade of
failures where sys/mutex.h ends up including arm/cpu.h which
ends up including sys/resourcevar.h and then sys/mutex.h,
but as the first includer of sys/mutex.h has defined the
idempotent header define, the second one is empty, and as
kmutex_t isn't defined by the first attempt yet the kmutex_t
used in resourcevar.h generates an error.

should fix evbarm v5/v5eb, hpcarm, iyonix and zaurus builds.

tested building iyonix, zaurus and evbarmv7hf.

G/C MP_CPU_INFO_MEMBERS

Mirror the changes to aarch64 and

- Switch to TPIDRPRW_IS_CURLWP, because curlwp is accessed much more often
by MI code. It also makes curlwp preemption safe,

- Make ASTs operate per-LWP rather than per-CPU, otherwise sometimes LWPs
can see spurious ASTs (which doesn't cause a problem, it just means some
time may be wasted).

- Make sure ASTs are always set on the same CPU as the target LWP, and
delivered via IPI if posted from a remote CPU so that they are resolved
quickly.

- Add some cache line padding to struct cpu_info.

- Add a memory barrier in a couple of places where ci_curlwp is set. This
is needed whenever an LWP that is resuming on the CPU could hold an
adaptive mutex. The barrier needs to drain the CPU's store buffer, so
that the update to ci_curlwp becomes globally visible before the LWP can
resume and call mutex_exit().

Implement fpu_kern_enter/leave for arm32.

Provide a curpcb

Don't expose curproc/curlwp and other random kernel macros/functions/variables
du-jour.

Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}

#ifdef whack-a-mole for the pmap_maxproc_set functionality

s/_ARM_ARCH_6/ARM_MMU_EXTENDED/ in the #ifdef for the recent 4k pages
change

Use 4K pages on ARM_MMU_EXTENDED platforms (all armv[67] except RPI) by
creating a new pool l1ttpl for the userland L1 translation table which
needs to be 8KB and 8KB aligned.

Limit the pool to maxproc and add hooks to allow the sysctl changing of
maxproc to adjust the pool.

This comes at a 5% performance penalty for build.sh -j8 kernel on a
Tegra TK1.

port the arm64 cpu topology setup for big.little to arm.

rename arm64 cpu_do_topology() to arm_cpu_do_topology() and
call it from both arm cpu_attach().

replace both aarch64_set_topology() inline code in arm
cpu_attach() with new arm_cpu_do_topology(), which is called
by the arm64 locore as well (possibly not needed, which would
allow it to become static.)

not yet tested on a real big.little armv7 system. tested
on rockpro64 and pinebook pro.

branches: 1.103.2;
Fix false sharing problems with cpu_info. Identified with tprof(8).
This was a very nice win in my tests on a 48 CPU box.

- Reorganise cpu_data slightly according to usage.
- Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc).
- On x86, put some items in their own cache lines according to usage, like
the IPI bitmask and ci_want_resched.

mi_userret(): take care of calling preempt(), set spc_curpriority directly,
and remove MD code that does the same.

Increase aarch64 MAXCPUS to 256.

branches: 1.100.4;
Start CPUs more like aarch64 by using a cpu_mpidr array (if populated)
to map MPIDRs to an index for each CPU.

Towards big.LITTLE support.

Align struct cpu_info member names. NFC.

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

- Cleanup for dynamic sysctl:
- Remove unused *_NAMES macros for sysctl.
- Remove unused *_MAXID for sysctls.
- Move CTL_MACHDEP sysctl definitions for m68k into m68k/include/cpu.h and
use them on all m68k machines.

branches: 1.96.2;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.95.2;
Remove port-acorn26

OK core@

CPU_INFO_FOREACH() must always iterate at least the boot cpu.
document this in sys/cpu.h and fix the arm and mips versions
to check ncpu is non zero before using it as an iterator max.

this should fix the new assert in init_main.c.

branches: 1.93.6;
Fix rcs tag.

Expose correct cpu_number(), CPU_IS_PRIMARY() and CPU_INFO_FOREACH() for
modules so that the dtrace module works on an MP system.

Trailing whitespace

branches: 1.90.2; 1.90.4;
Make setsoftast take a cpu_info *

__HAVE_PREEEMPTION -> __HAVE_PREEMPTION

Make sure TPIDRPRw_IS_CURLWP is being used when __HAVE_PREEEMPTION is defined.

Add basic support for __HAVE_PREEMPTION.
Use atomic ops for ci_astpending if __HAVE_PREEMPTION is defined.

Add an agnostic version of curlwp and curcpu() for modules since they won't
know if the kernel was built with TPIDRPRW_IS_CUR{LWP,CPU} or not.

Allow TPIDRPRW_IS_CURLWP to be used with MULTIPROCESSOR kernels

branches: 1.84.2;
Fix TPIDRPRW_IS_CURLWP builds.

A MULTIPROCESSOR kernel requires TPIDRPRW_IS_CURCPU.

branches: 1.83.4;
Make ddb_regs, undefined & vfp evcnt's per cpu.

Move some static/global variables to here.

use cii

Fix CLKF_INTR for EABI to (void) its argument so it isn't mark unused by the
optimizer.

<arm/locore.h> fallout (fixes some include ordering errors)

If _KMEMUSER, include <sys/intr.h>

There are only 16 faults.

Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>

branches: 1.75.2;
Add a machdep.fpu_present sysctl for ld.elf_so to use in ld.so.conf to load
libc_vfp.so.

Add vfp_kernel_acquire and vfp_kernel_release prototypes.

branches: 1.73.2;
Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7

Don't use locations in .data to store exception temporaries, use decidicated
space in cpu_info instead. This also moves undefined_handler_address into
cpu_info as well.
Use the new armreg* inlines for getting TPIDRPRW register.
Add MULTIPROCESSOR version of CPU_INFO_FOREACH

Remove undeeded struct device;

Use new armv7 CP15 register to print out cache types.
If the cpu_cc_freq is set, report it.
Add macros to make inlines for reading/writing co-processor registers.

Rename ARM options PROCESS_ID_IS_CUR{CPU,LWP} to TPIDRPRW_IS_CUR{CPU,LWP}
since TPIDRPRW is the cp15 register name.
Initialize it early in start along with CI_ARM_CPUID.
Remove other initializations.
We alays have ci_curlwp.
Enable TIPRPRW_IS_CURCPU in std.beagle.
[tested on a beaglboard (cortex-a8)]

small rototill.
pcb_flags is dead. PCB_NOALIGNFLT is now in stored l_md.md_flags as
MDLWP_NOALIGNFLT. This avoids a few loads of the PCB in exception handling.
pcb_tf has been moved to l_md.md_tf. Again this avoids a lot of pcb
references just to access or set this. It also means that pcb doesn't
need to accessed by MI code.
Move pcb_onfault to after the pcb union.
Add pcb_sp macro to make code prettier.
Add lwp_settrapframe(l, tf) to set the l_md.md_tf field.
Use lwp_trapframe to access it (was process_frame but that name was changed
in a previous commit).
Kill off curpcb in acorn26.
Kill the checks for curlwp being NULL.
Move TRAP_USERMODE from arm32/fault.c to frame.h and a __PROG26 version.
Replace tests for usermode with that macro.

Kill curpcb/ci_curpcb. Use device_t in cpu_info.
Add ci_softc (where ci_curpcb was so cpu_info doesn't change).

Rework VFP support to use PCU.
Add emulation of instruction which save/restore the VFP FPSCR.
Add a sysarch hook to VFP FPSCR manipulation.

[The emulation will be used by libc to store/fetch exception modes and
rounding mode on a per-thread basis.]

Remove irqframe and replace with identical trapframe.

Fix racy softint dispatch that lead to KASSERT(si->si_active) in
softint_execute

Discussed with matt@. "Looks good to me"

expose cpu structures to kmemuser and prevent opt_*.h from being included
if kmemuser

branches: 1.62.8; 1.62.12; 1.62.14;
Include sys/device_if.h instead of sys/device.h. machine/cpu.h is
one of the lower-most definitions. Relying on the huge sys/device.h
is not a good idea.

Include sys/evcnt.h for struct evcnt.

implement ucas_* for arm.

branches: 1.59.2; 1.59.4;
Rename L_ADDR to L_PCB and amend some comments accordingly.

Use lwp_getpcb() on ARM (and acorn26/32), clean from struct user usage.

Define a version of GET_CURCPU, GET_CURLWP, and GET_CURPCB for use on
old uniprocessor ARMs, and re-arrange the ifdefs so that it gets
used on 26-bit systems as well. This allows us to uniformly use these
macros everywhere.

branches: 1.56.2; 1.56.10;
Only call dosoftints() is ci_intr_depth == 0

Do fast softint processing in DO_AST_AND_RESTORE_ALIGNMENT_FAULTS.
Redo the softint mask so ci_softints >> ci_cpl != 0 becomes an easy
test for work to be done.

branches: 1.54.2; 1.54.6;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.53.2; 1.53.4;
VFP support.

Remove CTL_MACHDEP_NAMES, it's not used anywhere.

Ok by martin@.

branches: 1.51.2; 1.51.6;
revert previous; as yamt pointed out, these bits are in <sys/cpu.h>.

cargo-cult CPU_INFOITERATOR and _FOREACH to make kern_prf.c build again.
These should probably be abstracted out to sys/cpu.h at some point, since
they don't really change from arch to arch.

current_intr_depth is dead. Make sure we don't use it anymore.

Add cpu_intr_p().

branches: 1.47.2; 1.47.4; 1.47.6; 1.47.8;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Make want_resched a member of cpu_info.

branches: 1.45.2; 1.45.4; 1.45.6;
Add ci_cpuid where it's missing.

branches: 1.44.2; 1.44.4; 1.44.6; 1.44.8;
Another missed changed for acorn26 idlelwp. Provide IRQenable/IRQdisable
macros.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.42.4; 1.42.6; 1.42.10; 1.42.12;
Changes for newlock2.

branches: 1.41.2;
Remove spllowersoftclock() and CLKF_BASEPRI(), and always dispatch callouts
via a soft interrupt. In the near future, softclock will be run from process
context.

Centralize the various checks for validity of a CPU context in one macro,
so we don't have to get it right in lots of different places.

Don't define, just declare want_resched here.

branches: 1.38.4; 1.38.6; 1.38.8; 1.38.10; 1.38.12;
merge ktrace-lwp.

Change all archs that did:

#define clockframe somethingelse

to:

struct clockframe {
struct somethingelse cf_se;
};

and change access macros accordingly.

That means that, at least for that very issue, things will not go
ka-boomy if you don't have the actual definition of struct clockframe
before including systm.h.

branches: 1.36.12;
move some per-cpu data definitions to MI place so that they can be modified
without touching all ports. discussed on tech-kern@.

Rearrange process exit path to avoid need to free resources from different
process context ('reaper').

From within the exiting process context:
* deactivate pmap and free vmspace while we can still block
* introduce MD cpu_lwp_free() - this cleans all MD-specific context (such
as FPU state), and is the last potentially blocking operation;
all of cpu_wait(), and most of cpu_exit(), is now folded into cpu_lwp_free()
* process is now immediatelly marked as zombie and made available for pickup
by parent; the remaining last lwp continues the exit as fully detached
* MI (rather than MD) code bumps uvmexp.swtch, cpu_exit() is now same
for both 'process' and 'lwp' exit

uvm_lwp_exit() is modified to never block; the u-area memory is now
always just linked to the list of available u-areas. Introduce (blocking)
uvm_uarea_drain(), which is called to release the excessive u-area memory;
this is called by parent within wait4(), or by pagedaemon on memory shortage.
uvm_uarea_free() is now private function within uvm_glue.c.

MD process/lwp exit code now always calls lwp_exit2() immediatelly after
switching away from the exiting lwp.

g/c now unneeded routines and variables, including the reaper kernel thread

branches: 1.34.2;
Make sure to include opt_foo.h if a defflag option FOO is used.

Merge the nathanw_sa branch.

It appears that MI code requires ci_cpuid to be the CPU number of the CPU
in question, whereas the ARM code was using it to hold the model
identification. To fix this, rename:

ci_cpuid -> ci_arm_cpuid
ci_cputype -> ci_arm_cputype (for consistency)
ci_cpurev -> ci_arm_cpurev (ditto)
ci_cpunum -> ci_cpuid

This makes top(1) give correct CPU numbers in its "STATE" column (all 0 for
now).

Remember the location of each CPU's idle PCB in struct cpu_info.
Move allocation of the idle PCB from hydra.c to cpu.c and add some
extra initialisation from cpu_fork().

Minimal changes to allow a kernel with "options MULTIPROCESSOR" to compile
and boot multi-user on a single-processor machine. Many of these changes
are wildly inappropriate for actual multi-processor operation, and correcting
this will be my next task.

* Add a new machdep.powersave sysctl, which controls the use of
the CPU's "sleep" function in the idle loop.
* Default all CPUs to not use powersave, except for the PDA processors
(SA11x0 and PXA2x0).

This significantly reduces inteterrupt latency in high-performance
applications (and was good to squeeze another ~10% out of an XScale
IOP on a Gig-E benchmark).

Inline SetCPSR calls where it seems prudent to do so. This avoids two
branches and allows the compiler to better utilize registers around
calls to disable/enable/restore_interrupts().

branches: 1.27.2;
Hard-wire CLKF_BASEPRI() to 0 on the ARM, since spllowersoftclock() might
not actually be able to unblock the interrupt, which would cause us
to run the softclock interrupts with hardclock blocked.

Per discussion w/ Charles Hannum.

Centralize ARM CPU configuration information by adding a new header
file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines
the following:
* CPU_NTYPES -- now many CPU types are configured into the kernel. What
you really want to know is "== 1" or "> 1".
* Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending
on which ARM architecture versions are configured (based on CPU_*
options). Also defines ARM_NARCH to determins how many architecture
versions are configured.
* Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on
which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS
to determine how many MMU classes are configured.

Remove the needless inclusion of "opt_cputypes.h" in several places.
Convert remaining users to <arm/cpuconf.h>.

Clean up handling of the vector page on 32-bit ARM systems:
* Don't refer to VA 0, instead refer to a new variable: vector_page
* Delete the old zero_page_*() functions, replacing them with a new
one: vector_page_setprot().
* When manipulating vector page mappings in user pmaps, only do so if
the vector page is below KERNEL_BASE (if it's above KERNEL_BASE, the
vector page is mapped by the kernel pmap).
* Add a new function, arm32_vector_init(), which takes the virtual
address of the vector page (which MUST be valid when the function
is called) and a bitmask of vectors the kernel is going to take
over, and performs all vector page initialization, including setting
the V bit in the CPU Control register ("relocate vectors to high
address"), if necessary.

Cache the cpu type and cpu revision in cpu_info.

arm26->acorn26 transition.

Add a ci_dev element to struct cpu_info, pointing to the device that
corresponds to the CPU.

Replace cpu_id and cpu_ctrl in struct _cpu with ci_cpuid and ci_ctrl in
struct cpu_info. Also kill the cpuctrl global while we're here, and make
identify_arm_cpu() take a struct cpu_info * as an argument alongside the CPU
number.

Move arm700bugcount into stuct cpu_info, and attach it in
identify_master_cpu().

Some prototype cleanup.

Merge ast() and userret() between arm32 and arm26. The implementation used
is the arm32 one.

Add 26-bit and 32-bit types.h files, which indicate the programming
model in use for a given platform (__PROG26 vs __PROG32), then pulls
in <arm/types.h>. Change each ARM port to pull in <arm/arm26/types.h>
or <arm/arm32/types.h> as appropriate. Change all references to PROG26
and PROG32 to __PROG26 and __PROG32. Eliminate the opt_progmode.h
header file.

branches: 1.16.2;
Implement a badaddr_read() routine which performs a load of the
specified size for the caller, and returns true or false indicating
whether or not a Data Abort occurred (i.e. the address was "bad").

branches: 1.15.4;
Purge CPU_ARM7500. Thanks to Reinoud's work, it's no longer needed.

branches: 1.14.2;
Initial commit for merging A7000/NC with the RISCPC in order to get _one_
bootable GENERAL kernel for the 3 machines.

This is done by integrating the ARM7500 in a better way. In various places
the IOMD ID is checked and action is taken at runtime compared to
compiletime.

The small piece of assembler that is changed now uses the flag
`arm7500_ioc_found' that is set up by iomd.c at startup. When this chip
isnt found at startup it will skip reading the ARM7500 extended IRQ
registers and wont clear them either.

The next step will be getting the mode-definition files to the bootloader.
Currently they are compiled in.

Don't need to prototype child_return() here, it's in <sys/proc.h>.

strstr() is no longer used in the kernel. G/C it.

Rather large overhaul. Mostly cosmetic, but also:

Provide PROC_PC on arm26.
Provide working CLKF_INTR on arm26.
Make setsoftast a macro everywhere.

Split cpu from mainbus so that cpu can attached to other buses (like ofbus).

branches: 1.9.2; 1.9.4;
PCB convergence, part the first:
Move the pointer to the current user trapframe from struct mdproc to struct
pcb (as on arm26). Only tested by compiling kernels on arm32 and
hpcarm (dnard seems to be incomplete anyway). Someone should try running one.

Large overhaul for arm26 compatibility. This file is now even more of a mess
than it was.

Tidy up ARM7500 restrictions.
Also insist on precisely one of PROG32 and PROG26's being turned on.

cpu_number() macro has no args

Rollback of patch ... there was a bug in the proc.h

Due to changes in ../sys/proc.h ``cpu_wait(p)'' is now a function due to the
prototype defined it in ... added it to arm/vm_machdep.c since all ARM machines
are still single processor anyway

Move arm32 ports over to using <arm/armreg.h>, so <cpu.h> mostly contains
NetBSD-specific definitions.

This also entails some changes to the way CPU identification is done. I hope
I've got it right.

COPY_SIGCODE is never referenced in the kernel, and the comment attached to it
is out of date. Assume it's obsolete and g/c it.

Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.

ci_cpu_id -> ci_arm_cpuid

branches: 1.2.2; 1.2.4; 1.2.6; 1.2.8; 1.2.16;
Use ci->ci_data.cpu_cc_freq.
Use new armreg_* macros.

Add __HAVE_CPU_COUNTER support for ARM11 and Cortex CPUs

remove clause 3 from all my licenses that aren't conflicting with
another copyright claim line. again. (i did this in 2008 and then
did not update all of my personal templates.)

branches: 1.2.4;
Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}

branches: 1.1.2;
port the arm64 cpu topology setup for big.little to arm.

rename arm64 cpu_do_topology() to arm_cpu_do_topology() and
call it from both arm cpu_attach().

replace both aarch64_set_topology() inline code in arm
cpu_attach() with new arm_cpu_do_topology(), which is called
by the arm64 locore as well (possibly not needed, which would
allow it to become static.)

not yet tested on a real big.little armv7 system. tested
on rockpro64 and pinebook pro.

Collapse all CPU_CORTEXA<n> options into CPU_CORTEX and do runtime
detection instead of ifdefs where required.

Retire CPU_ARM2, CPU_ARM250 and CPU_ARM3, they are all leftovers of
acorn26.

ok jmcneill@ skrll@

branches: 1.26.2;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.25.16;
Remove CPU_CORTEXA8 from a conditional - it doesn't believe there.

branches: 1.24.4;
Support (untested) SHEEVA_L2_CACHE and SHEEVA_L2_CACHE_WT options.
Move prototypes out to <arm/cpufunc.h> to their own file.
Add sdcache routines to cpufunc_asm_sheeva.S
Add code sheeve_setup to init the sdcache and sdcache info.