Remove katelib.h and references to it.

{Read,Write}{Word,Byte} macros are provided in the files that still use
them. Someone(tm) should convert them to bus_space(9)

branches: 1.9.158;
Remove KDIR=, since SYS_INCLUDE=symlinks and KDIR are not supported any more.

- Move more contents of various <machine/vmparam.h> files into
<arm/arm32/vmparam.h> (mostly the stuff that's tied to the pmap
implementation).
- Since the MMU definitions in pte.h are specific to ARM processors
that support 32-bit mode, move pte.h to <arm/arm32/pte.h>.
- Make the Netwinder startup file build again (use PT_B|PT_C, rather
than PT_CACHEABLE, since the latter expands to a variable these days).

Add 26-bit and 32-bit types.h files, which indicate the programming
model in use for a given platform (__PROG26 vs __PROG32), then pulls
in <arm/types.h>. Change each ARM port to pull in <arm/arm26/types.h>
or <arm/arm32/types.h> as appropriate. Change all references to PROG26
and PROG32 to __PROG26 and __PROG32. Eliminate the opt_progmode.h
header file.

branches: 1.6.6;
Add a merged <pcb.h> for arm26/arm32.

Make <sysarch.h> valid for all arm platforms. Adjust/remove port-specific
includes as required.

branches: 1.4.2;
Move <arm/arm32/bus.h> to <arm/bus.h>, since it looks like it's going to be
necessary on arm26 as well.

branches: 1.3.2;
Add param.h to INCS.

branches: 1.2.2;
Putting the param.h back into the arm32 resp. hpcarm include directories

Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.

branches: 1.1.2;
file arm1136_pmc.h was initially added on branch matt-nb4-arm.

branches: 1.4.8;
Move <arm/arm32/bus.h> to <arm/bus.h>, since it looks like it's going to be
necessary on arm26 as well.

branches: 1.3.2;
Add the BUS_DMA_STREAMING flag.

branches: 1.2.2;
s/vm_offset_t/vaddr_t/g

Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.

Move db_reset_cmd prototype to db_machdep.h (forgot to commit this file)

Make ddb_registers per-cpu. All switching of CPUs (xxx doesn't work yet).

Add db_show_tlb_cmd prototype

branches: 1.7.2;
remove show panic cmd

Add a 'mach fault' command to print DFAR/DFSR/IFAR/IFSR/TTBR

branches: 1.5.12; 1.5.20; 1.5.22;
Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.

branches: 1.4.48; 1.4.56; 1.4.62; 1.4.66;
Fix lossage from boolean_t -> bool and updated x86 bus_dma.

branches: 1.3.26;
merge ktrace-lwp.

branches: 1.2.2;
Catch up with constification.

branches: 1.1.2; 1.1.4; 1.1.22;
Make some of the arm32 files build with LOOSE_PROTOTYPES not set in the makefile. Turned up a few mismatched functions. Note that this isn't all of the arm32 files. Aim will be to get arm32 kernels built with LOOSE_PROTOTYPES not set.

Mirror the changes to aarch64 and

- Switch to TPIDRPRW_IS_CURLWP, because curlwp is accessed much more often
by MI code. It also makes curlwp preemption safe,

- Make ASTs operate per-LWP rather than per-CPU, otherwise sometimes LWPs
can see spurious ASTs (which doesn't cause a problem, it just means some
time may be wasted).

- Make sure ASTs are always set on the same CPU as the target LWP, and
delivered via IPI if posted from a remote CPU so that they are resolved
quickly.

- Add some cache line padding to struct cpu_info.

- Add a memory barrier in a couple of places where ci_curlwp is set. This
is needed whenever an LWP that is resuming on the CPU could hold an
adaptive mutex. The barrier needs to drain the CPU's store buffer, so
that the update to ci_curlwp becomes globally visible before the LWP can
resume and call mutex_exit().

Consistency - NFC

Remove magic number

branches: 1.45.4; 1.45.6;
Fixup the non-KDTRACE_HOOKS case of PUSHDTRACEGAP - we need to copy the
stack pointer to r2.

split PUSHFRAMEINSVC into two pieces so that we can insert some additional
instructions in the middle in undefinedinstruction_bounce, namely to add
some additional space on the stack before the trapframe for undefineds from
SVC mode. this extra space allows dtrace to emulate a "push" instruction.
the initial version was from me and some improvements were from nick.

Trailing whitespace

Put the clearing of ci_astpending back in frame.h while interrupts are
disabled.

Don't clear CI_ASTPENDING in exception return, do it in ast() instead.
Add basic support for __HAVE_PREEMPTION.
Use atomic ops for ci_astpending if __HAVE_PREEMPTION is defined.
Use kpreempt_disable/kpreempt_enable

CI_ASTPENDING is now a bitfield and low bit is for user ASTs.

branches: 1.39.6;
Remove KERNEL_LOCK/KERNEL_UNLOCK

When restoring SPRSR, use spsr_fsxc not spsr_all so bits[23-8] are restored.
This should fix use of simd instructions that rely on the GE bits.

Don't use cpsr_all/spsr_all with mrs, it doesn't take a mask.

Use blx ip if _ARM_ARCH_5
prepare to get of switchframe

branches: 1.35.2;
Change to use symbolic constants from assym.h and fix a typo in a comment.

Implement a "fast" path for IRQ handling out of the idle loop. Since we
are in SVC32 already we only need to save a few registers. Processing is
also simplified since we know we can't return to user-mode.

branches: 1.33.2;
Use ARMV6+ cpsi{d,f} instructions whenever possible. Use r7 to hold previous
mode and avoid recomputing it. Add support for obtaining kernel_lock on
exception entry and exit.

Fix typo.

small rototill.
pcb_flags is dead. PCB_NOALIGNFLT is now in stored l_md.md_flags as
MDLWP_NOALIGNFLT. This avoids a few loads of the PCB in exception handling.
pcb_tf has been moved to l_md.md_tf. Again this avoids a lot of pcb
references just to access or set this. It also means that pcb doesn't
need to accessed by MI code.
Move pcb_onfault to after the pcb union.
Add pcb_sp macro to make code prettier.
Add lwp_settrapframe(l, tf) to set the l_md.md_tf field.
Use lwp_trapframe to access it (was process_frame but that name was changed
in a previous commit).
Kill off curpcb in acorn26.
Kill the checks for curlwp being NULL.
Move TRAP_USERMODE from arm32/fault.c to frame.h and a __PROG26 version.
Replace tests for usermode with that macro.

Remove irqframe and replace with identical trapframe.

Move fill to between spsr and r0 so that the registers will be dword aligned.
Adjust PUSH/PULL macros accordingly.

Shrink PUSHFRAMEINSVC by 4 more instructions.

Add code to make sure the trapframe is aligned to a doubleword boundary.

Only do the SA110 user register save workaround on kernel using SA110s.

Make trapframe/irqframe an even number of words (make adjustments for
the filler word).
Improve the comments in PUSH/PULL macros.
Use the armv6+ CPS instruction if we can.

whitespace cleanup

branches: 1.23.14; 1.23.22;
Now that GET_CURPCB and GET_CURCPU are generally available, use them
unconditionally rather than rolling our own (often badly) all over the
place.

Clear out the vestigial support for the Simtec Hydra board. Now that we're
getting support for proper SMP ARMs, keeping non-functional support for
a seriously crippled not-really-SMP system is likely to cause more problems
than it's worth, even if it was fun for a while.

Fix __HAVE_FAST_SOFTINTS (boolean dyslexia strikes again).
Add some KASSERTS to make sure assumptions are valid.

branches: 1.20.2; 1.20.8;
Fix DO_PENDING_SOFTINTS (remove pasto, remove a branch, use movs)
pasto spotted by mjf

Only call dosoftints() is ci_intr_depth == 0

Do fast softint processing in DO_AST_AND_RESTORE_ALIGNMENT_FAULTS.
Redo the softint mask so ci_softints >> ci_cpl != 0 becomes an easy
test for work to be done.

branches: 1.17.2; 1.17.6;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.16.6; 1.16.8; 1.16.10;
Push a switchframe in dumpsys and cpu_switchto, but as dumpsys calls
other funcs a switchframe needs to be a multiple of 8 bytes. Stash sp as
well in the switchframe to bump it to 24bytes.

Setup the switchframe appropriately in cpu_lwp_fork.

Remove savectx - nothing uses it.

All of this make gdb's life much easier when dealing with crash dumps and
live kernels.

Reviewd by chris.

branches: 1.15.8; 1.15.16; 1.15.20; 1.15.22; 1.15.28; 1.15.34;
Rewrite the ARM mutex implementation to be of the simple-mutex variety.
Because pre-v6 ARM lacks support for an atomic compare-and-swap, we
implement _lock_cas() as a restartable atomic squence that is checked
in the IRQ handler right before AST processing. (This is safe because,
for all practical purposes, there are no SMP pre-v6 ARM systems.)

This can serve as a model for other non-MP platforms that lack the
necessary atomic operations for mutexes (SuperH, for example).

Upshots of this change:
- kmutex_t is now down to 8 bytes on ARM; about as good as we can get.
- ARM2 systems don't have to trap and emulate SWP or SWPB for mutexes.

The acorn26 port is not updated by this commit to do the LOCK_CAS_CHECK.
That is left as an exercise for the port maintainer.

Reviewed and tested by Matt Thomas.

branches: 1.14.4;
- Document COMPAT_15 as doing nothing
- Add COMPAT_15 to all the kernel that had COMPAT_14, for the sake of coherency
- Remove the only occurences of #ifdef COMPAT_15 in the tree: for the ARM
ports, COMPAT_15 was always used in conjunction with EXEC_AOUT. Only EXEC_AOUT
matters here.

This address kern/18407

branches: 1.13.20; 1.13.22;
merge ktrace-lwp.

Change all archs that did:

#define clockframe somethingelse

to:

struct clockframe {
struct somethingelse cf_se;
};

and change access macros accordingly.

That means that, at least for that very issue, things will not go
ka-boomy if you don't have the actual definition of struct clockframe
before including systm.h.

branches: 1.11.12;
Always disable interrupts at the start of DO_AST_AND_RESTORE_ALIGNMENT_FAULTS.
This addresses #2 of port-arm/23581 by Richard Earnshaw.

Many thanks to Richard for spotting the cause of this problem.

branches: 1.10.2;
The last cpsr_all change was misguided. Just use cpsr_c wherever possible.

- For consistency, use cpsr_all instead of cpsr.
- Make sure IRQs are enabled before handling ASTs.

Slight re-org of the alignment/ast exit macro to better mimic the
original behaviour WRT cpsr/I32_bit handling.

Move the alignment fault enable/disable code into macroes to avoid
needless duplication.

Additionally, merge AST handling into the same code.

exception.S and the generic irq_dispatch.S routines have been updated
to use the macroes.

XXX: I have patches for the non-generic IRQ dispatch routines, but they
need testing by someone with hardware.

Don't drop to spl0 in cpu_switch/cpu_switchto. Do it in the idle loop
instead.

With this change, we no longer need to save the current interrupt level
in the switchframe. This is no great loss since both cpu_switch and
cpu_switchto are always called at splsched, so the process' spl is
effectively saved somewhere in the callstack.

This fixes an evbarm problem reported by Allen Briggs:

lwp gets into sa_switch -> mi_switch with newl != NULL
when it's the last element on the runqueue, so it
hits the second bit of:
if (newl == NULL) {
retval = cpu_switch(l, NULL);
} else {
remrunqueue(newl);
cpu_switchto(l, newl);
retval = 0;
}

mi_switch calls remrunqueue() and cpu_switchto()

cpu_switchto unlocks the sched lock
cpu_switchto drops CPU priority
softclock is received
schedcpu is called from softclock
schedcpu hits the first if () {} block here:
if (l->l_priority >= PUSER) {
if (l->l_stat == LSRUN &&
(l->l_flag & L_INMEM) &&
(l->l_priority / PPQ) != (l->l_usrpri / PPQ)) {
remrunqueue(l);
l->l_priority = l->l_usrpri;
setrunqueue(l);
} else
l->l_priority = l->l_usrpri;
}

Since mi_switch has already run remrunqueue, the LWP has been
removed, but it's not been put back on any queue, so the
remrunqueue panics.

branches: 1.5.2; 1.5.8;
Undo recent cpu_switch register usage changes in order to decrease nathanw_sa
merge pain.

In cpu_switch(), stack more registers at the start of the function,
and hence save fewer into the PCB. This should give me enough free
registers in cpu_switch to tidy things up and support MULTIPROCESSOR
properly. While we're here, make the stacked registers into an
APCS stack frame, so that DDB backtraces through cpu_switch() will
work.

This also affects cpu_fork(), which has to fabricate a switchframe and
PCB for the new process.

Use cpsr_c rather then cpsr_all where appropriate.

branches: 1.2.6; 1.2.14;
Use comments around the token after a #endif.

branches: 1.1.4; 1.1.6;
Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.

Remove katelib.h and references to it.

{Read,Write}{Word,Byte} macros are provided in the files that still use
them. Someone(tm) should convert them to bus_space(9)

branches: 1.3.170;
Use <arm/cpufunc.h>, not <machine/cpufunc.h>.

branches: 1.2.2; 1.2.8;
Move the declarations of blockio.S functions from katelib.h to a new, exciting
<arm/blockio.h>. katelib.h includes it for compatibility.

branches: 1.1.2; 1.1.4;
Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.

Update to support EFI runtime outside the kernel virtual address space
by creating an EFI RT pmap that can be activated / deactivated when
required.

Adds support for EFI RT to ARM_MMU_EXTENDED (ASID) 32-bit Arm machines.

On Arm64 the usage of pmapboot_enter is reduced and the mappings are
created much later in the boot process -- now in cpu_startup_hook.
Backward compatiblity for KVA mapped RT from old bootaa64.efi is
maintained.

Adding support to other platforms should be easier as a result.

Some KASAN fixes and tweaks

- don't access BSS variables when __md_early
- centralise the INIT_ARM_STACK_{SHIFT,SIZE} defines and create a new
INIT_ARM_TOTAL_STACK
- Only create L1PT entries in kasan_md_shadow_map_page if
arm32_kernel_vm_init hasn't created the L2PTs (and their L1PT entries)
- Add some comments to explain what's going on

Protect with #ifdef _KERNEL

Revert "Include opt_diagnostic.h for DIAGNOSTIC."

This did not do what I thought it did. opt_diagnostic.h is only for
the unused _DIAGNOSTIC, which seems like an abortive attempt to
incrementally convert DIAGNOSTIC to an opt_*.h option rather than a
command-line option.

Include opt_diagnostic.h for DIAGNOSTIC.

...at least, in header files, which may not have already included
libkern.h.

Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}

branches: 1.30.2;
New function cpu_startup_hook on arm.

Called at end of cpu_startup. Can be defined in, e.g., evbarm to do
additional stuff after cpu_startup. Defined as a weak alias to a
function that does nothing, so optional.

ok jmcneill

branches: 1.29.2;
Consistently use vaddr_t as initarm and friends return type.

Makes no difference to binaries except for aarch64 where it's required

Start CPUs more like aarch64 by using a cpu_mpidr array (if populated)
to map MPIDRs to an index for each CPU.

Towards big.LITTLE support.

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

Refactor code to split aarch{32,64} kernel page tables and VM setup. This
will help re-build the kernel page tables on aarch64 with correct section
mappings.

Expose kern_vtopdiff

Provide and use kern_vtopdiff in KERN_{VTOPHYS,PHYSTOV}. A step towards
generic arm.

s/_ARM32_BOOT_MACHDEP_H_/_ARM32_MACHDEP_H_/ in multiple inclusion
protection.

Retire ipkdb entirely. The option was removed from the config files
yesterday.

ok kamil christos

branches: 1.21.12; 1.21.14;
Whitespace in comment

Trailing whitespace

branches: 1.19.2; 1.19.4;
add support for optional RB_POWERDOWN handler

branches: 1.18.6;
Change arm_cpu_mbox to volatile

branches: 1.17.2;
Increase l2pts to accomodate large memory disks.

branches: 1.16.2;
Backout previous, Matt fixed it differently

Move struct pv_addr next to struct bootmem_info into machdep.h and have
pmap.h include that.
Seems to be the least intrusive build fix; Matt: feel free to revamp.

Make cpu_reset, most of initarm and the kvm init code common.
Add MP hooks for cpu_need_resced
Add idlestck which is allocated in arm32_kvminit

Don't use locations in .data to store exception temporaries, use decidicated
space in cpu_info instead. This also moves undefined_handler_address into
cpu_info as well.
Use the new armreg* inlines for getting TPIDRPRW register.
Add MULTIPROCESSOR version of CPU_INFO_FOREACH

Since the PMC cycle counter is started in cpufunc no reason to do so here.
Use curcpu()->ci_data.cpu_cc_freq and new armreg* inlines.

Move the standard definitions of the {UND,IRQ,FIQ,ABT}_STACK_SIZE to
<arm32/machdep.h>
Move the extern for cpu_reset_address to the same file.
Add cpu_reset_address_paddr.
Kill cpu_reset_v4_MMU_disable.
if cpu_reset_address is NULL, then the MMU will be disabled.

Fix more -fno-common fallout.
Move more variables to common locations.

branches: 1.9.12; 1.9.20;
Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.

branches: 1.8.46; 1.8.54; 1.8.60; 1.8.64;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.7.34; 1.7.72;
map_chunk() -> pmap_map_chunk(), and move it to pmap.c

map_pagetable() -> pmap_link_l2pt(), and move it to pmap.c

Collapse map_entry{,ro,nc}() into a single pmap_map_entry() that
takes a prot and a "cacheable" indicator.

Rename map_section() to pmap_map_section(), move it to pmap.c, and give it
an extra argument (prot - specifies protection of the mapping).

Some prototype cleanup.

branches: 1.2.2; 1.2.4;
Finish up the changes to get LOOSE_PROTOTYPES working for cats.
Note that this leaves a few inconsistencies (no more than we already had though) eg initarm is now prototyped in arm32/machdep.h, however only cats currently makes use of that header.

Make some of the arm32 files build with LOOSE_PROTOTYPES not set in the makefile. Turned up a few mismatched functions. Note that this isn't all of the arm32 files. Aim will be to get arm32 kernels built with LOOSE_PROTOTYPES not set.

Include opt_param.h for MSGBUFSIZE ifdef _KERNEL_OPT.

branches: 1.33.6; 1.33.8;
Add support for KASAN on ARMv[67]

Thanks to maxv for many pointers and reviews.

Define USPACE in terms of UPAGES (not the other way around) now that
NBPG is fixed at 4K

Whitespace

Bump the amount of KMEM allowed to 1/3rd of KVM. _ARCH_ARM_6 has a split
of 2:2 and others have a split of 3:1.

Tested by martin@ Thanks

G/C

Use 4K pages on ARM_MMU_EXTENDED platforms (all armv[67] except RPI) by
creating a new pool l1ttpl for the userland L1 translation table which
needs to be 8KB and 8KB aligned.

Limit the pool to maxproc and add hooks to allow the sysctl changing of
maxproc to adjust the pool.

This comes at a 5% performance penalty for build.sh -j8 kernel on a
Tegra TK1.

branches: 1.27.2; 1.27.4;
KNF and add a comment

Trailing whitespace

branches: 1.25.6;
if __HIDE_DELAY is defined, do not define delay() or DELAY().
needed by dtrace and ZFS.

Don't include <machine/cpu.h>

branches: 1.23.6;
On second thoughts don't do the RPI hack for everyone.

Drop down to 4KB pages on armv6 for now.

Make the ARM pmap use ASIDs, split TTBRs, and MP safe. This only happens for
ARMv6 or later CPUs. This means that on context switch that the TLBs and
caches no longer to cleaned/flushed. Also, eXecute Never (XN) protection has
been added so non-exec pages can not be run. Change the page size for ARMv6+
to be 8KB while allows a L1PT to be a normal page. This means that the L1PT
is not special. Use the XN support to only sync pages that are executed from.

branches: 1.20.2;
Explicitely cast to unsigned. Avoid bugs caused by misintepreting the result as
signed.

riastradh@ suggested to change these macros into static inline functions.
But I'm still not convinced...

Obtained from Marvell, Semihalf.

Bump MSGBUFSIZE on arm ports to 16KB.

OK matt@

FPCONTEXTSIZE is dead.

branches: 1.17.6;
improve sizing of kmem_arena now that more allocations are made from it
don't enforce limits if not required

ok: riz@

branches: 1.16.8; 1.16.12;
Retire struct user, remove sys/user.h inclusions. Note sys/user.h header
as obsolete. Remove USER_TO_UAREA/UAREA_TO_USER macros.

Various #include fixes and review by matt@.

branches: 1.15.2;
Remove separate mb_map. The nmbclusters is computed at boot time based
on the amount of physical memory and limited by NMBCLUSTERS if present.
Architectures without direct mapping also limit it based on the kmem_map
size, which is used as backing store. On i386 and ARM, the maximum KVA
used for mbuf clusters is limited to 64MB by default.

The old default limits and limits based on GATEWAY have been removed.
key_registered_sb_max is hard-wired to a value derived from 2048
clusters.

branches: 1.14.2;
Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.

branches: 1.13.10; 1.13.18; 1.13.24;
With the removal of IPKDB on arm, the undefined stack is only used to
bounce into SVC32 mode, there is no per-process data stored on it.

We can therefore use the undefined stack setup by the platform machdep.c
as a system wide undefined stack.

This removes the need for a per-process undefined stack, and the processor
mode switching overhead it causes in cpu_switchto.

The space freed in the USPACE is used to increase the per process kernel
stack size.

branches: 1.12.46; 1.12.50; 1.12.52; 1.12.58; 1.12.66;
merge ktrace-lwp.

branches: 1.11.10;
Bump UPAGES back down to 8KB now that real issue was found with ep93xx intr handling

bump default U-area size from 8KB to 64KB, 8KB is too little to even successfully boot a tsarm SBC

branches: 1.9.12;
* arm_byte_to_page() -> arm_btop()
* arm_page_to_byte() -> arm_ptob()

Purge CLSIZE, CLSIZELOG2 and MCLOFSET.
Be consistant in the way that MSIZE, MCLSHIFT, MCLBYTES and NMBCLUSTERS
are defined.
Remove old VM constants from cesfic port.
Bump MSIZE to 256 on mipsco (the only one that wasn't already 256).

Bumb NMBCLUSTER defaults to 2048 for GATEWAY and 1024 otherwise. These
match current powerpc defaults and are more reasonable for the current era.

branches: 1.6.6;
Add arm_trunc_page, similair to trunc_page but using a hardcoded PGOFSET.

Use <arm/param.h> to get shared definitions.

branches: 1.4.2;
use _KERNEL_OPT

branches: 1.3.2; 1.3.4;
Only define MACHINE & MACHINE_ARCH in port-dependent param.h.
Everything else (since it's common) is from <arm/arm32/param.h>

Make hpcarm kernel compile again.

Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.

branches: 1.4.6;
Add a merged <pcb.h> for arm26/arm32.

Remove unused entries from the pcb. This is with a long term view of merging the arm26 and arm32 pcb's.

branches: 1.2.4; 1.2.6;
PCB convergence, part the first:
Move the pointer to the current user trapframe from struct mdproc to struct
pcb (as on arm26). Only tested by compiling kernels on arm32 and
hpcarm (dnard seems to be incomplete anyway). Someone should try running one.

Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.

Add the beginnings of a GENERIC_V5 kernel that targets armv5 boards and
uses FDT.

In this first iteration some support is added for OLinuXino boards.

Thanks to Yuri Honegger for doing the vast majority of the work.

Fix non-DIAGNOSTIC builds

No need to define cpu_{,set}_tlb_info here - just use the
sys/uvm/pmap/pmap_tlb.h versions.

Fix DEVMAP_FLAGS, patch from Nick.

Provide a shared pmap_devmap implementation and convert all pmap_devmap
arrays to use DEVMAP_ENTRY{,_END}

branches: 1.173.4;
Update to support EFI runtime outside the kernel virtual address space
by creating an EFI RT pmap that can be activated / deactivated when
required.

Adds support for EFI RT to ARM_MMU_EXTENDED (ASID) 32-bit Arm machines.

On Arm64 the usage of pmapboot_enter is reduced and the mappings are
created much later in the boot process -- now in cpu_startup_hook.
Backward compatiblity for KVA mapped RT from old bootaa64.efi is
maintained.

Adding support to other platforms should be easier as a result.

Remove unnecessary brackets

pm_remove_all is a shared field so move it out the #ifdefs

Provide pte_{value,valid_p}

branches: 1.169.6;
Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Consistency...#define<tab>

PMAP_DEBUG has been deleted on arm

branches: 1.166.2;
Don't define pt_entry_t if _LOCORE

Reported by Patrick Welche

Provide a pt_entry_t and PRIxPTE

pmap_remove_all(): Return a boolean value to indicate the behaviour. If
true, all mappings have been removed, the pmap is totally cleared out, and
UVM can then avoid doing the work to call pmap_remove() for each map entry.
If false, either nothing has been done, or some helpful arch-specific voodoo
has taken place.

Adjust for UVM locking changes

G/C l1pte_pgindex

Fix the armv[67] memory attributes for uncached memory. Previously it was
mapped as strongly-ordered which meant that unaligned accesses would fault.

armv7_generic_bs_map now maps pages with PMAP_DEV which is treated as SO

bus_dma continues to use PMAP_NOCACHE as appropriate, but this now get
mapped to the correct memory attribute bits for armv[67]

DEVMAP_ENTRY usees a new flag PTE_DEV.

The workaround for the unaligned access faults is now removed.

XXX Other armv[67] boards bus_space implementations should be checked.
XXX There is scope to reduce the difference to aarch64

s/_ARM_ARCH_6/ARM_MMU_EXTENDED/ in the #ifdef for the recent 4k pages
change

Use 4K pages on ARM_MMU_EXTENDED platforms (all armv[67] except RPI) by
creating a new pool l1ttpl for the userland L1 translation table which
needs to be 8KB and 8KB aligned.

Limit the pool to maxproc and add hooks to allow the sysctl changing of
maxproc to adjust the pool.

This comes at a 5% performance penalty for build.sh -j8 kernel on a
Tegra TK1.

fix -Wsign-compare because module tests trigger it.

branches: 1.157.2;
pg->phys_addr -> VM_PAGE_TO_PHYS(pg)

branches: 1.156.4;
Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

branches: 1.155.2;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.154.2;
Remove port-acorn26

OK core@

Centralise defines for DEVMAP_{ALIGN,SIZE,ENTRY,ENTRY_END}

Revert the *_PROT_RO_* define changes and do all the work in the *_PROT()
macros for RO kernel pages.

cats boots again - no idea how it slipped through my testing previously

Fix up L{1_S,2_L,2_S}_PROT for recent changes to the
L{1_S,2_L,2_S}_PROT_RO* values.

KNF two comments

Re-define the L*_PROT_RO for MMUs that don't really support RO mapping
and adjust l2pte_set_{writeable,readony} to the new values.

This allows RO mappings for MMUs that actually support them.

Trailing whitespace

Use the define name PMAP_HWPAGEWALKER and not PMAP_TLB_HWPAGEWALKER

Spell ARM_MMU_EXTENDED correctly

Fixup the compile time decisions around PMAP_{INCLUDE,NEEDS}_PTE_SYNC and
fix the options for xscale boards which require the code in
pmap_l2ptp_ctor marked as #ifndef PMAP_INCLUDE_PTE_SYNC.

Fix the typo (pte -> opte) in this code block and consistently use opte
elsewhere.

PR/51990: Regression data_abort_handler: data_aborts fsr=0x406 far=0xbfffeff5 on copyout in init

branches: 1.144.2; 1.144.4;
Spell PMAP_TLB_NEED_SHOOTDOWN correctly

Support pmap_pv_track and friends

Make L2_S_CACHE_MASK_armv6n consistent with other *_CACHE_MASK_armv6n

pmap_directbase is a failed experiment, nuke it.

Support directmapped systems with >1GB that start memory at 0x80000000.

Add some KASSERTs to catch similar bugs to the cnptes/nptes one

Improve inline asm around dsb/dmb/isb:
- always use volatile and mark them as memory barrier
- use the common version from locore.h in all places not included from
userland

branches: 1.137.2;
Whitespace

Sprinkle #include "opt_multiprocessor.h"

branches: 1.135.2;
Trailing whitespace

More fixes as a step towards ARM_MMU_EXTENDED on RPI.

- don't set CPU_CONTROL_SYST_ENABLE in arm11x6_setup for ARM_MMU_EXTENDED

- Use the new MMU defines for V6N

- pull in arm/cpuconf.h in vmparam s that VM_MAXUSER_ADDRESS gets set
correctly.

Fix macro name; PMAP_TLB_NEED_SHOOTDOWN => PMAP_NEED_TLB_SHOOTDOWN

Make to flush the secondary cache when syncing PTEs when the Sheeva L2 cache
is used.

Add a kernel for the CUBIETRUCK (CUBIEBOARD3). Allow direct mapping of all
memory (but for now allow the memory mapped above KERNEL_BASE to used for
poolpages).

branches: 1.130.2;
For ARM_MMU_V6C enable supersections

Deal with large page mappings in l2pte_set.

Now the RPI can get passed setting the new TTB.

ok matt@

For ARM_MMU_EXTENDED, a KERNEL_BASE >= 0x80000000 is ok but a
VM_USER_MAXADDRESS can not be more than 0x80000000 - PAGE_SIZE.

Add a missing 0 to an #error

Make the ARM pmap use ASIDs, split TTBRs, and MP safe. This only happens for
ARMv6 or later CPUs. This means that on context switch that the TLBs and
caches no longer to cleaned/flushed. Also, eXecute Never (XN) protection has
been added so non-exec pages can not be run. Change the page size for ARMv6+
to be 8KB while allows a L1PT to be a normal page. This means that the L1PT
is not special. Use the XN support to only sync pages that are executed from.

Remove duplicate PMAP_PTE

Replace 1000 with PAGE_SIZE

Add PMAP_PTE flag. (map page so it can be used as a PDE or PTE page)

struct pcb; for a function prototype.

Add l2pte_set and l2pte_reset inlines to set/reset a pte. These will be
used to support > 4KB pages sizes.
Don't use >> L1_S_SHIFT, use L1_IDX() instead.

branches: 1.120.2;
Add a ARM_HAS_VBAR option which forces the use of the VBAR register. This
allows much code to deal with vector_page mappings to be eliminated. On a
BEAGLEBONE kernel, this saves 8KB of text and instructions that never have
to be executed. (The PJ4B has VBAR but doesn't implement the security
extensions it is part of so a method was needed to allow it use VBAR with
relying on the default test for the security extensions.)

Protect more definitions with #ifndef _LOCORE

Enable direct-mapped poolpages if __HAVE_MM_MD_DIRECT_MAPPED_PHYS is defined.

Add b{zero,copy}_page{,_vfp} and physical_end

Add pmap_{copy,zero}_page_vfp

C99 types

Add PMAP_MAP_POOLPAGE / PMAP_UNMAP_POOLPAGE if PMAP_NEED_ALLOC_POOLPAGE is
defined.

Add a PMAP_NEEDS_ALLOC_POOLPAGE / PMAP_ALLOC_POOLPAGE hook so systems can
allocate pool pages from a specific VM freelist.

Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.

branches: 1.111.2;
Fix the CACHE_MASKs for armv6 to include TEX and S bits.
Fix a comment in pte.h

Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7

Alas, Cortex-A8 can't TLB walk out of their caches so they need to sync each PTE.

Enable "shareable" access to the page table for armv7. PTE_SYNC only does
a DSB now on an armv7 cpu and no longer needs to flush the cache line to ram.

Make bus_dma understand supersections.

Backout previous, Matt fixed it differently

Move struct pv_addr next to struct bootmem_info into machdep.h and have
pmap.h include that.
Seems to be the least intrusive build fix; Matt: feel free to revamp.

Add a l1pte_supersection_p macro.

Add support for mapping SuperSection on armv6 and armv7. These always
a domain of 0 so move the kernel from domain 15 to domain 0.

Fix more -fno-common fallout.
Move more variables to common locations.

branches: 1.101.4;
Nuke the simplelock from vm_page_md

branches: 1.100.2; 1.100.6;
Welcome to 5.99.53! Merge rmind-uvmplock branch:

- Reorganize locking in UVM and provide extra serialisation for pmap(9).
New lock order: [vmpage-owner-lock] -> pmap-lock.

- Simplify locking in some pmap(9) modules by removing P->V locking.

- Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share
the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs).

- Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner.
Add TLBSTATS option for x86 to collect statistics about TLB shootdowns.

- Unify /dev/mem et al in MI code and provide required locking (removes
kernel-lock on some ports). Also, avoid cache-aliasing issues.

Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches
formed the core changes of this branch.

branches: 1.99.2;
Preliminary ARM11 MPCore support.

I have confirmed this commit doesn't affect existing evbarm kernels by
comparing binaries.

implement arm32_pmap_flags() to allow mappings with write buffering enabled,
mostly for video memory
Tested on shark

branches: 1.97.2; 1.97.4;
Move struct vm_page_md definition from vmparam.h to pmap.h, because
it's used only by pmap. vmparam.h has definitions for wider
audience.

All GENERIC kernels build tested, except ia64.

powerpc/include/booke/vmparam.h has one too, but it has no pmap.h,
so it's left as is.

Fix build of evbarm.

PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt

branches: 1.94.2; 1.94.4;
Add write-through cache work-around for ARM11 as well as ARM9/ARM10. Analyzed
& tested on i.MX35 with help from Tsubai Masanari.

Simplify pmap_remove() a little by avoiding pmap_do_remove() layer, since
possibility to skip wired mappings is not needed anymore. Apart from that,
no functional differences are intended.

Use PMAP_ENABLE_PMAP_KMPAGE to enable PMAP_KMPAGE. We still want the bit
defined in the MI space, not in an MD header.

Rationalize the definition of PMAP_KMPAGE.

Reclaim PVF_KNC in VIPT to be PVF_MULTCLR (page has multiple colors).
Track when a page is mapping in multiple colors and deal with the ramifications.
When a page's MOD attribute is cleared, clean it from the cache.
Fix a logic inversion.

With these changes, the TI SDP2420 H4 board can successfully natively build a
TISDP2420 kernel.

Make pmap_kernel() a MI macro for struct pmap *kernel_pmap_ptr,
which is now the "API" provided by the pmap module. pmap_kernel()
remains as the syntactic sugar.

Bonus cosmetics round: move all the pmap_t pointer typedefs into
uvm_pmap.h.

Thanks to Greg Oster for providing cpu muscle for doing test builds.

branches: 1.88.2; 1.88.10;
Fix a few more corner cases. Always KMPAGE or pages with unmanaged writeable
kernel mappings as modified. Only ever set DIRTY bit is DMOD is true and
NC is false. Don't modify unmanaged mappings in pmap_clearbit.

Add PMAP_KMPAGE defintion (forgotten commit). Also add PVF_DIRTY which will
be used by an update pmap.c shortly (to note what pages may have dirty
cache lines).

Revamp bookkeeping for pages entered by pmap_kenter_pa. Keep track of them
on pvlists so that the cacheability can be properly tracked.

branches: 1.85.2; 1.85.4; 1.85.6;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.84.6; 1.84.8; 1.84.10;
Add support for kcore headers to arm32 kernel core dumps.

The kcore code is based on i386's kcore header handling.

Having an asm stub for dumpsys, to dump the registers onto the stack, and
then call the C code to do the memory dump is based on amd64's core dump
code.

This allows a successful core dump on cats.

Part of fixing PR cats/18026.

branches: 1.83.2; 1.83.8;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

ARM cpu_switchto() has been partially broken since yamt-idlelwp was merged
as its cache/tlb management smarts relied too heavily on pre-merge context-
switch behaviour. See PR kern/36548 for one manifestation of the breakage.

To address this:
- Ditch the shadow pmap variables in the PCB (pagedir, l1vec, dacr, cstate)
as it was too easy for them to get out of sync with the pmap.
- Re-write (and fix) the convoluted cpuswitch.S cache/tlb ASM code in C.
It's only slightly less efficient, but is much more readable/maintainable.
- Document cpufuncs.cf_context_switch() as being C-callable.
- pmap_activate() becomes a no-op if the lwp's vmspace is already active.
(Good performance win, since pmap_activate() is now invoked on every
context-switch, even though ARM's cpu_switchto() already does all the
grunt work)

XXX: Some CPU-specific armXX_context_switch() implementations (arm67,
arm7tdmi, arm8) always flush the I+D caches. This should not be necessary.
Someone with access to hardware (acorn32?) needs to deal with this.

branches: 1.81.4; 1.81.12; 1.81.18; 1.81.20; 1.81.22; 1.81.24;
TRUE -> true, FALSE -> false

Replace the Mach-derived boolean_t type with the C99 bool type. A
future commit will replace use of TRUE and FALSE with true and false.

branches: 1.79.26; 1.79.30;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

Implement pmap_collect() for arm32.

branches: 1.77.16;
On Xscale, define PMAP_UAREA() and use it to tweak uarea mappings so
they use the mini D$.

This results in a small performance boost on xscale platforms, since
flushing the main cache on a context switch won't affect the kernel
stack/pcb.

Add support for ARM10 class processors.

branches: 1.75.2;
protect with #ifndef _LOCORE so that assembler codes can share
definitions in this file such as PMAP_DOMAIN_KERNEL.

Add another devmap routine that allows bootstrap code to register
a devmap reflecting mappings that are created by really early
bootstrap code before pmap_devmap_bootstrap() is called.

Replace the ad-hoc "section mapping table" for static device mappings
with a more generic "devmap" structure that can also handle mappings
made with large and small pages. Add new pmap routines to enter these
mappings during bootstrap (and "remember" the devmap), and routines to
look up the static mappings once the kernel is running.

Remove #ifdefs supporting the old pmap, switching fully to the new.

Reduce differences between ARM32_NEW_VM_LAYOUT and not; always pass
the start and end of the kernel managed virtual address space to
pmap_bootstrap() in the new pmap.

Fix the bug reported by Richard Earnshaw in port-arm32/21349.

Make sure to check the access permissions before doing
ref/mod/domain fixups. This is particularly important
on machines with ARM_VECTORS_LOW.

Some ARM32_PMAP_NEW-related cleanup:
* Define a new "MMU type", ARM_MMU_SA1. While the SA-1's MMU is basically
compatible with the generic, the SA-1 cache does not have a write-through
mode, and it is useful to know have an indication of this.
* Add a new PMAP_NEEDS_PTE_SYNC indicator, and try to evaluate it at
compile time. We evaluate it like so:
- If SA-1-style MMU is the only type configured -> 1
- If SA-1-style MMU is not configured -> 0
- Otherwise, defer to a run-time variable.
If PMAP_NEEDS_PTE_SYNC might evaluate to true (SA-1 only or run-time
check), then we also define PMAP_INCLUDE_PTE_SYNC so that e.g. assembly
code can include the necessary run-time support. PMAP_INCLUDE_PTE_SYNC
largely replaces the ARM32_PMAP_NEEDS_PTE_SYNC manual setting Steve
included with the original new pmap.
* In the new pmap, make pmap_pte_init_generic() check to see if the CPU
has a write-back cache. If so, init the PT cache mode to C=1,B=0 to get
write-through mode. Otherwise, init the PT cache mode to C=1,B=1.
* Add a new pmap_pte_init_arm8(). Old pmap, same as generic. New pmap,
sets page table cacheability to 0 (ARM8 has a write-back cache, but
flushing it is quite expensive).
* In the new pmap, make pmap_pte_init_arm9() reset the PT cache mode to
C=1,B=0, since the write-back check in generic gets it wrong for ARM9,
since we use write-through mode all the time on ARM9 right now. (What
this really tells me is that the test for write-through cache is less
than perfect, but we can fix that later.)
* Add a new pmap_pte_init_sa1(). Old pmap, same as generic. New pmap,
does generic initialization, then resets page table cache mode to
C=1,B=1, since C=1,B=0 does not produce write-through on the SA-1.

Gah, fix *another* typo.

Oops, fix typo.

Define two new macros to test if a mapping is mappable with an L1 Section
mapping or an L2 Large Page mapping.

Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems.

Some features of the new pmap are:

- It allows L1 descriptor tables to be shared efficiently between
multiple processes. A typical "maxusers 32" kernel, where NPROC is set
to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily
with just 4 L1s. This completely solves the problem of running out
of contiguous physical memory for allocating new L1s at runtime on a
busy system.

- Much improved cache/TLB management "smarts". This change ripples
out to encompass the low-level context switch code, which is also
much smarter about when to flush the cache/TLB, and when not to.

- Faster allocation of L2 page tables and associated metadata thanks,
in part, to the pool_cache enhancements recently contributed to
NetBSD by Wasabi Systems.

- Faster VM space teardown due to accurate referenced tracking of L2
page tables.

- Better/faster cache-alias tracking.

The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel
config file, and making the necessary changes to the port-specific
initarm() function. Several ports have already been converted and will
be committed shortly.

Add the ability for pool caches to cache the physical address of
objects. Clients of the pool_cache API must consistently use
the "paddr" variants or not, otherwise behavior is undefined.

Enable this on Alpha, ARM, MIPS, and x86. Other platforms must
define POOL_VTOPHYS() in the appropriate manner in order to enable
the feature.

Part 1 of a series of simple patches contributed by Wasabi Systems
to improve network performance.

Garbage collect pmap_map, the last (and only?) use has been removed.

Fix PTE_FLUSH_RANGE macro, it should have had a cnt parameter.

it really helps to get the stub right before cutting + pasting it 27 times.
alas, I did not. doh.

add pmap_remove_all() hook (empty on most platforms so far).

Define macros describing the 4M super-sections that our pmap
actually uses (since we allocate PT pages in 4K chunks, rather
than 1K chunks).

Enable caching on kernel and user page tables. This saves having
to do uncached memory access during VM operations (which can be
quite expensive on some CPUs).

We currently write-back PTEs as soon as they're modified; there is
some room for optimization (to write them back in larger chunks).
For PTEs in the APTE space (i.e. PTEs for pmaps that describe another
process's address space), PTEs must also be evicted from the cache
complete (PTEs in PTE space will be evicted durint a context switch).

* Add PTE_SYNC() and PTE_SYNC_RANGE() macros. These don't actually do
anything yet.
* Use PTE_SYNC() and PTE_SYNC_RANGE() in some obvious places, i.e.
where vtopte() is used.

Add a PVF_EXEC -- we don't use it yet, though.

Overhaul how DMA ranges work in the ARM bus_dma implementation.

A new "arm32_dma_range" structure now describes a DMA window, with
a system address base, bus address base, and length. In addition to
providing info about which memory regions are legal for DMA, the new
structure provides address translation support, as well.

As before, if a tag does not list any ranges, then all addresses are
considered valid, and no DMA address translation is performed.

This allows us to remove a large chunk of code which was duplicated and
tweaked slightly (to do the address translation) from the stock ARM
bus_dma in the XScale IOP and ARM Integrator ports.

Test compiled on all ARM platforms, test booted on Intel IQ80321 and Shark.

Move the calls to uvm_page_physload() out of pmap_bootstrap() and
into platform-specific initialization code, giving platform-specific
code control over which free list a given chunk of memory gets put
onto.

Changes are essentially mechanical. Test compiled for all ARM
platforms, test booted on Intel IQ80321 and Shark.

Discussed some time ago on port-arm.

branches: 1.53.2;
Default all XScale core processors to the read/write-allocate write-back
cache mode. Add a new XSCALE_CACHE_WRITE_THROUGH option for people who
are paranoid about the cache-related errata (you *do* have to line up
the planets correctly to trip them, but having the option is useful).

Centralize ARM CPU configuration information by adding a new header
file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines
the following:
* CPU_NTYPES -- now many CPU types are configured into the kernel. What
you really want to know is "== 1" or "> 1".
* Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending
on which ARM architecture versions are configured (based on CPU_*
options). Also defines ARM_NARCH to determins how many architecture
versions are configured.
* Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on
which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS
to determine how many MMU classes are configured.

Remove the needless inclusion of "opt_cputypes.h" in several places.
Convert remaining users to <arm/cpuconf.h>.

Add separate pmap_{zero,copy}_page() functions for generic ARM
vs. XScale. Use the mini-data cache for the destination on XScale,
thus saving tossing out 4K of possible-useful data from the main
data cache each time.

This significantly improves every test in lmbench.

* Move the code that cleans the XScale mini-data cache into its
own function.
* Add a new function which sets up the mini-data cache clean area
properly.

* Split pte_cache_mode into pte_l1_s_cache_mode, pte_l2_l_cache_mode,
and pte_l2_s_cache_mode. The cache-meaningful bits are different
for these descriptor types on some processor models.
* Add pte_*_cache_mask, corresponding to each above, which has a mask
of the cache-meangful bits, and define those for generic and XScale
MMU classes. Note, the L2_S_CACHE_MASK_xscale definition requires
use of the Extended Small Page L2 descriptor (the "X" bit overlaps
with AP bits otherwise).

Use the "Extended Small Page" L2 descriptor type on XScale (note
this means that there are no 1K sub-pages on XScale, but we don't
use them anyway).

Remove the implementation-defined bits from L1_S_PROTO_xscale and
L1_C_PROTO_xscale; while they are supposed to be set to 1 on generic
ARM MMUs (according to the SA-110 and ARM920T manuals), they are listed
as "should be zero" in the i80200 manual.

Define 2 classes of ARM MMUs:
1. Generic (compatible with ARM6)
1. XScale (can be used as generic, but also has certainly nifty extensions).

Define abstract PTE bit defintions for each MMU class. If only one MMU
class is configured into the kernel (based on CPU_* options), then we
get the constants for that MMU class. Otherwise we indirect through
varaibles set up via set_cpufuncs().

XXX The XScale bits are currently the same as the generic bits. Baby steps.

Use abstract names for the protection and PTE type bits in
L1 and L2 descriptors. This will allow us to support different
PTE layouts that enable the use of extensions on different
processor models.

* Rewrite the 32-bit ARM pte.h based on the ARM architecture manual.
Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h. While
doing this, two bugs (as a result of typos) were fixed in

arm/arm32/bus_dma.c
evbarm/integrator/int_bus_dma.c

Rename flags that are really part of the pv_entry/mdpage into
pmap.h and give them more descriptive names and better comments:
* PT_M -> PVF_MOD (page is modified)
* PT_H -> PVF_REF (page is referenced)
* PT_W -> PVF_WIRED (mapping is wired)
* PT_Wr -> PVF_WRITE (mapping is writable)
* PT_NC -> PVF_NC (mapping is non-cacheable; multiple mappings)

Clean up handling of the vector page on 32-bit ARM systems:
* Don't refer to VA 0, instead refer to a new variable: vector_page
* Delete the old zero_page_*() functions, replacing them with a new
one: vector_page_setprot().
* When manipulating vector page mappings in user pmaps, only do so if
the vector page is below KERNEL_BASE (if it's above KERNEL_BASE, the
vector page is mapped by the kernel pmap).
* Add a new function, arm32_vector_init(), which takes the virtual
address of the vector page (which MUST be valid when the function
is called) and a bitmask of vectors the kernel is going to take
over, and performs all vector page initialization, including setting
the V bit in the CPU Control register ("relocate vectors to high
address"), if necessary.

* Some cleanup.
* Delete the call to pmap_copy() in pmap.h

Move some private pmap data structures into pmap.c

Tidy a few things up.

Correct the comment describing the layout of the VM space. In
particular, don't describe a recursive PTE mapping, since the ARM
port doesn't (and can't) use one.

Remove exported pmap_pte() prototype.

Clean up PTE access macros a bit.

* arm_byte_to_page() -> arm_btop()
* arm_page_to_byte() -> arm_ptob()

Garbage-collect the "pagehook" stuff.

* Rename PROCESS_PAGE_TBLS_BASE -> PTE_BASE
* Rename ALT_PAGE_TBLS_BASE -> APTE_BASE
* Garbage-collect PAGE_TABLE_SPACE_START

Remove redundant #ifdef _KERNEL

* Make pmap_is_{modified,referenced}() macros in pmap.h that just
test the attributes in the vm_page_md directly.
* Clean up pmap_clear_{modified,referenced}().
* Delete now-unused pmap_testbit().

Switch back to using vm_page_md (thanks chuq for finding the bug
in the code that made it unstable before!)

Implement pmap_growkernel for arm32 based ports.
Note that this has been compiled on some systems, cats, IQ80310, IPAQ, netwinder and shark (note that shark's build is currently broken due to other reasons), but only actually run on cats.
Shark doesn't make use of the functionality as I believe there has to be a correlation between OFW and the kernel tables so that calls into OFW work.

Keep track of which kernel PTs are available during bootstrap,
and let pmap_map_chunk() lookup the correct one to use for the
current VA. Eliminate the "l2table" argument to pmap_map_chunk().

Add a second L2 table for mapping kernel text/data/bss on the
IQ80310 (fixes booting kernels with ramdisks).

map_chunk() -> pmap_map_chunk(), and move it to pmap.c

map_pagetable() -> pmap_link_l2pt(), and move it to pmap.c

Collapse map_entry{,ro,nc}() into a single pmap_map_entry() that
takes a prot and a "cacheable" indicator.

Rename map_section() to pmap_map_section(), move it to pmap.c, and give it
an extra argument (prot - specifies protection of the mapping).

Back out all the vm_page_md changes. They are causing some
mysterious problems (a similar change to the i386 pmap causes
mysterious problems there, as well), and the issue needs to
be investigated more.

Efficiency tweaks, some made possible by vm_page_md.

Use vm_page_md rather than pmap_physseg. Saves lots of cycles in
common operations.

add a new flag PMAP_CACHE_VIVT for the pmap to inform the MI code that
that the cache is virtually-indexed and virtually-tagged (such as on the ARM),
and use this flag in the UBC code to be more friendly to those caches.

Use <arm/cpufunc.h>, not <machine/cpufunc.h>.

- Move more contents of various <machine/vmparam.h> files into
<arm/arm32/vmparam.h> (mostly the stuff that's tied to the pmap
implementation).
- Since the MMU definitions in pte.h are specific to ARM processors
that support 32-bit mode, move pte.h to <arm/arm32/pte.h>.
- Make the Netwinder startup file build again (use PT_B|PT_C, rather
than PT_CACHEABLE, since the latter expands to a variable these days).

Implement pmap_update(). Currently it just calls cpu_cpwait(),
which ensures that TLB/cache operations have completed.

branches: 1.16.2;
Define boolean predicates pmap_pde_page, pmap_pde_section & pmap_pde_fpage,
which return true if their pde argument is a coarse page, section or
fine page respectively.

branches: 1.15.2;
Sprinkle some static and inline into a couple of functions. Remove dead entries from pmap.h.

Update pmap_update to now take the updated pmap as an argument.
This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.

Currently this is a no-op on most platforms, so they should see no difference.

Reviewed by Jason.

branches: 1.13.2;
Checking a whole host of pmap changes:
Improved locking (not that we actually use it on a uniprocessor, but one day :)
Removed unneeded splvm's
tweaked pmap_clean_page code to only flush the cache if the page is mapped in the current pmap (based on diff from richard E)
Adopted pv entry allocation mechanism from i386.
Laid framework for returning ptp's when we've finished with them rather than holding onto them till the process exits.
ptp's are now allocated with a uvm object for the pmap, means that we can walk a list to free them off in pmap_release, until they get freed off by pmap_remove.

Also implemented a page zeroing function when the processor is idling. Note that hpcarm may wish to disable this.

I believe this code to be stable, if anyone has any problems please shout up.

Rework the pmap_release code to not have to walk the ptpt, it now uses a uvm_object to track the allocated vm_pages, this means it can free off the entries in the uvm_object.

Testing shows that it's about 5% faster on the make configure step for gmake.

A couple of tidy ups to pmap:
pmap_t -> struct pmap * in pmap.c and pmap.h
kernel_pmap -> pmap_kernel() everywhere.

Compiled and booted on riscpc and cats.

branches: 1.10.2;
GC a couple of unused entries in the pmap struct

replace vm_page_t with struct vm_page *.

replace {simple_,}lock{_data,}_t with struct {simple,}lock {,*}.

Undo a misguided previous change to the pmap_update() API.

Give pmap_update() an argument (a pmap_t) so that it knows which
pmap it should be updating.

Update the comment for pmap_update().

branches: 1.4.2; 1.4.4;
more vm_offset_t/vm_size_t -> {p,v}{addr,size}_t changes
move pmap_* declarations to pmap.h. fix conflicts this
exposed (e.g different definitions for pmap_bootstrap).

Convert some vm_size_t to vsize_t/psize_t. Change vaddr_t to paddr_t
where appropriate.

s/vm_offset_t/vaddr_t/g

Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.

Rename the cpu_id() define to cpu_idnum() so that it does not conflict with
dtrace and friends.

branches: 1.20.6;
_setsoftintr is long dead. reap any leftovers from arm.

branches: 1.19.2; 1.19.4;
Remove safepri and use IPL_SAFEPRI instead. This may be defined in a MD
header file (if not, a value of 0 is assmued).

branches: 1.18.14; 1.18.22;
fix splx() function prototype.

branches: 1.17.4; 1.17.12;
Let the shark boot again. Fixes port-shark/38929. While I'm here fix the
splsoft... macros to always raise the IPL (oops!).

branches: 1.16.2; 1.16.4;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.15.6; 1.15.8; 1.15.10;
Cleanup softint lossage.

branches: 1.14.6;
Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

branches: 1.13.2;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.12.2; 1.12.4;
Remove obsolete spllowersoftclock(9).

branches: 1.11.4; 1.11.6; 1.11.8;
Quick and dirty fix for hpcarm build failure, using hpcarm specific
softintr code for now.

branches: 1.10.2; 1.10.4; 1.10.10;
Make ipl_t and ipl_cookie_t 8-bit values. kmutex is now down to 12 bytes
(from 20) on ARM.

Approved by Matt Thomas.

Don't export spl_smasks or soft_interrupts. They are local to intr.c
Make sure that softintr_init() is called when needed.
Assume __HAVE_GENERIC_SOFT_INTERRUPTS is defined (since newlock2 requires it).

Add __HAVE_GENERIC_SOFT_INTERRUPTS support for shark. This was done by
extenting the current arm generic intrs to support softintrs. Add
IPL_SOFTCLOCK, IPL_SOFTNET, IPL_SOFTSERIAL.

branches: 1.7.2;
merge yamt-splraiseipl branch.

- finish implementing splraiseipl (and makeiplcookie).
http://mail-index.NetBSD.org/tech-kern/2006/07/01/0000.html
- complete workqueue(9) and fix its ipl problem, which is reported
to cause audio skipping.
- fix netbt (at least compilation problems) for some ports.
- fix PR/33218.

branches: 1.6.18; 1.6.48; 1.6.50;
Rename IPL_IMP -> IPL_VM.

branches: 1.5.2;
Add new spl level -- _SPL_STATCLOCK.

branches: 1.4.2; 1.4.6;
Multiple-inclusion protection.

Remove the use of splimp() from the NetBSD kernel. splnet()
and only splnet() is allowed for the protection of data structures
used by network devices.

Increase spl_masks[] size by one and set the extra element to 0.
irq_entry accesses here.

branches: 1.1.2; 1.1.4;
Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.

Prevent double definition of pt_entry_t from machine/param.h

G/C L1_TABLE_SIZE_REAL

Use 4K pages on ARM_MMU_EXTENDED platforms (all armv[67] except RPI) by
creating a new pool l1ttpl for the userland L1 translation table which
needs to be 8KB and 8KB aligned.

Limit the pool to maxproc and add hooks to allow the sysctl changing of
maxproc to adjust the pool.

This comes at a 5% performance penalty for build.sh -j8 kernel on a
Tegra TK1.

branches: 1.20.4;
Whitespace

branches: 1.19.20;
Update a comment to reflect ARM ARMv7

Comment whitespace.

Spell user with an e.

Trailing whitespace

branches: 1.15.2;
Add XN bit L2 large pages.

Add L1_TABLE_SIZE_REAL

branches: 1.13.2; 1.13.4;
Fix the CACHE_MASKs for armv6 to include TEX and S bits.
Fix a comment in pte.h

Add support for mapping SuperSection on armv6 and armv7. These always
a domain of 0 so move the kernel from domain 15 to domain 0.

Add L2_S_SEGSIZE which is the number of bytes that a L2 page table will map.

branches: 1.10.4; 1.10.10; 1.10.12;
Preliminary ARM11 MPCore support.

I have confirmed this commit doesn't affect existing evbarm kernels by
comparing binaries.

branches: 1.9.2;
PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt

branches: 1.8.18; 1.8.20; 1.8.22;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.7.82; 1.7.106; 1.7.108; 1.7.110;
Remove #ifdefs supporting the old pmap, switching fully to the new.

Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems.

Some features of the new pmap are:

- It allows L1 descriptor tables to be shared efficiently between
multiple processes. A typical "maxusers 32" kernel, where NPROC is set
to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily
with just 4 L1s. This completely solves the problem of running out
of contiguous physical memory for allocating new L1s at runtime on a
busy system.

- Much improved cache/TLB management "smarts". This change ripples
out to encompass the low-level context switch code, which is also
much smarter about when to flush the cache/TLB, and when not to.

- Faster allocation of L2 page tables and associated metadata thanks,
in part, to the pool_cache enhancements recently contributed to
NetBSD by Wasabi Systems.

- Faster VM space teardown due to accurate referenced tracking of L2
page tables.

- Better/faster cache-alias tracking.

The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel
config file, and making the necessary changes to the port-specific
initarm() function. Several ports have already been converted and will
be committed shortly.

* Rewrite the 32-bit ARM pte.h based on the ARM architecture manual.
Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h. While
doing this, two bugs (as a result of typos) were fixed in

arm/arm32/bus_dma.c
evbarm/integrator/int_bus_dma.c

Rename flags that are really part of the pv_entry/mdpage into
pmap.h and give them more descriptive names and better comments:
* PT_M -> PVF_MOD (page is modified)
* PT_H -> PVF_REF (page is referenced)
* PT_W -> PVF_WIRED (mapping is wired)
* PT_Wr -> PVF_WRITE (mapping is writable)
* PT_NC -> PVF_NC (mapping is non-cacheable; multiple mappings)

In analogy to L2_LPAGE_SIZE add L2_SPAGE_SIZE ....

Update the types, pt_entry and pd_entry should be unsigned, and fixed at 32 bits.

branches: 1.1.2; 1.1.4;
- Move more contents of various <machine/vmparam.h> files into
<arm/arm32/vmparam.h> (mostly the stuff that's tied to the pmap
implementation).
- Since the MMU definitions in pte.h are specific to ARM processors
that support 32-bit mode, move pte.h to <arm/arm32/pte.h>.
- Make the Netwinder startup file build again (use PT_B|PT_C, rather
than PT_CACHEABLE, since the latter expands to a variable these days).

Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.

branches: 1.1.4; 1.1.136; 1.1.144; 1.1.150;
Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.

branches: 1.2.6;
Make <sysarch.h> valid for all arm platforms. Adjust/remove port-specific
includes as required.

branches: 1.1.4; 1.1.6;
Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.

G/C

branches: 1.12.4; 1.12.10;
Remove port-acorn26

OK core@

Move #define __HAVE_OLD_DISKLABEL to <arm/types.h>

Make all ports use a common disklabel.h with MAXPARTITIONS set to 16.
Only RAW_PART varies between ports.

implement cpu_lwp_setprivate() on several platforms.

branches: 1.8.110; 1.8.130; 1.8.132;
Remove #ifdefs supporting the old pmap, switching fully to the new.

Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems.

Some features of the new pmap are:

- It allows L1 descriptor tables to be shared efficiently between
multiple processes. A typical "maxusers 32" kernel, where NPROC is set
to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily
with just 4 L1s. This completely solves the problem of running out
of contiguous physical memory for allocating new L1s at runtime on a
busy system.

- Much improved cache/TLB management "smarts". This change ripples
out to encompass the low-level context switch code, which is also
much smarter about when to flush the cache/TLB, and when not to.

- Faster allocation of L2 page tables and associated metadata thanks,
in part, to the pool_cache enhancements recently contributed to
NetBSD by Wasabi Systems.

- Faster VM space teardown due to accurate referenced tracking of L2
page tables.

- Better/faster cache-alias tracking.

The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel
config file, and making the necessary changes to the port-specific
initarm() function. Several ports have already been converted and will
be committed shortly.

Switch to using the MI C versions of setrunqueue() and remrunqueue().
GCC produces almost exactly the same instructions as the hand-assembled
versions, albeit in a different order. It even found one place where it
could shave one off. Its insistence on creating a stack frame might slow
things down marginally, but not, I think, enough to matter.

Add support for restartable atomic sequences on 26-bit ARM. Compile
tested only.

Now that all ARM systems have RAS, move __HAVE_RAS from arm/arm32/types.h
to arm/types.h.

Only need to define __HAVE_MD_RUNQUEUE once here...

Add __HAVE_MD_RUNQUEUE flag for MD code to override MI run queue primitives.

Add machine-dependent bits of RAS for arm32.

branches: 1.1.2; 1.1.4; 1.1.12;
Add 26-bit and 32-bit types.h files, which indicate the programming
model in use for a given platform (__PROG26 vs __PROG32), then pulls
in <arm/types.h>. Change each ARM port to pull in <arm/arm26/types.h>
or <arm/arm32/types.h> as appropriate. Change all references to PROG26
and PROG32 to __PROG26 and __PROG32. Eliminate the opt_progmode.h
header file.

branches: 1.1.2;
file vmpagemd.h was initially added on branch matt-nb5-mips64.

spelling and grammar fixes, mainly in comments.

branches: 1.57.6;
Rename VM_KERNEL_IO_ADDRESS to VM_KERNEL_IO_BASE to match RISC-V

It's less letters, matches other similar variables and will help with
sharing code between the two architectures.

NFCI.

Bump MAXDSIZ from 1536 to 1836.
1836 is 2048-128(MAXTSIZ)-64(MAXSSIZ).
Gives us a fighting chance to build rust natively.
OK'ed by skrll@

Cover the full kernel address range in KASAN

Fix ARM builds

Remove stray #else / #endif block in KASAN support commit

Oops... deal with a last minute #define name change. KASAN support now
builds.

Add support for KASAN on ARMv[67]

Thanks to maxv for many pointers and reviews.

Do previous differently for now

Provide some KVA layout #defines in arm32/vmparam.h and simplify
fdt/platform.h as a nice side effect

Remove an unnecessary #ifdef

Revert previous; we don't want arm to have variable page size. Instead
nick@ is fixing the cache pages issue to use a separate pool.

Define the min and max page size supported for the benefit of jemalloc

branches: 1.45.2; 1.45.4;
Update a comment

Need to include <sys/cdefs.h> so that the _ARM_CPU* macros get defined
so that we always select the correct page size (8K for armv6+).

- expose vmparams to userland on arm, like other archs do.
- remove unneeded includes

Trailing whitespace

branches: 1.41.12; 1.41.14;
G/C VM_MAX_KERNEL_BUF

branches: 1.40.2; 1.40.4;
pull in arm/arm32/param.h

__USE_TOPDOWN_VM

Fixes PR/49974: mmap(2) of large anonymous regions is broken

"go for it" from matt@

Back off MAXDSIZ to 1.5GB to avoid some virtual memory exhausted messages.

ARM systems are no longer small, increase MAXTSIZ/MAXDSIZ/MAXSSIZ.

Restore PAGER_MAP_DEFAULT_SIZE for ARMv4, they typically have only 256MB
KVA.

branches: 1.35.4;
More fixes as a step towards ARM_MMU_EXTENDED on RPI.

- don't set CPU_CONTROL_SYST_ENABLE in arm11x6_setup for ARM_MMU_EXTENDED

- Use the new MMU defines for V6N

- pull in arm/cpuconf.h in vmparam s that VM_MAXUSER_ADDRESS gets set
correctly.

branches: 1.34.2;
For ARM_MMU_EXTENDED, a KERNEL_BASE >= 0x80000000 is ok but a
VM_USER_MAXADDRESS can not be more than 0x80000000 - PAGE_SIZE.

Revert previous - will fix userland with new sysctls for VM_MIN_ADDRESS/
VM_MAXADDESS.

Include param.h here - userland expects VM_* defines to work with just
this include, but PAGE_SIZE relies on PGSHIFT now, which is not defined
here.

Matt: please rearrange/cleanup differently if you prefer (but test build
src/tests/lib/libc/sys/t_mlock for example.)

Use PAGE_SIZE instead of 1000

Remove unnecessary include of sys/simplelock.h

branches: 1.29.6;
Define PAGESHIFT using PGSHIFT

Bump max text/data/stack sizes to more reasonable values.

branches: 1.27.2;
Tweak max addresses a bit so that [r1, #off] can't overflow them.

expose stuff that crash needs to kmemuser

branches: 1.25.8; 1.25.12; 1.25.16;
Move struct vm_page_md definition from vmparam.h to pmap.h, because
it's used only by pmap. vmparam.h has definitions for wider
audience.

All GENERIC kernels build tested, except ia64.

powerpc/include/booke/vmparam.h has one too, but it has no pmap.h,
so it's left as is.

branches: 1.24.2; 1.24.4;
Remove SHMMAXPGS from all kernel configs. Dynamically compute the
initial limit as 1/4 of the physical memory. Ensure the limit is at
least 1024 pages, the old default on most platforms.

branches: 1.23.2; 1.23.8; 1.23.12;
Change pv_entries to use SLIST.

For VIPT caches, keep track of when pages are dirty so that their content
can be flushed back to main memory. This is done when the page is
read-only mapped by more than 1 color. Pages become when either their
modified bit gets set or an unmanaged writeable page is mapped. When
a page in unmapped or changed to read-only, run pmap_vac_me_harder in
case the page can be mapped read-only.

Thanks are given to Imre Deak for giving me the idea to assert for PVF_DIRTY.

branches: 1.22.2; 1.22.6;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.21.6; 1.21.8; 1.21.10;
Header cleanup.

branches: 1.20.20; 1.20.24; 1.20.26; 1.20.32; 1.20.38;
From Scott Alan in http://mail-index.netbsd.org/port-arm/2006/07/26/0000.html

This one is really simple. I wanted to use KERNEL_BASE in an assembly source,
but arch/arm/include/arm32/vmparam.h wasn't protected by #ifndef
__ASSEMBLER__. The patch adds the protection.

branches: 1.19.18; 1.19.48; 1.19.54;
Use virtual_avail and virtual_end to compute the size of the available
kernel VM space for VM_MAX_KERNEL_BUF, and move the definition into
generic ARM code.

Remove #ifdefs supporting the old pmap, switching fully to the new.

VM_{MIN,MAX}* are now the same for ARM32_PMAP_NEW with both new and
old VM layout, so merge the two cases.

Don't expose KERNEL_TEXT_BASE outside of board-specific code. This gives
individual board start-up code more flexibility about where the kernel
starts in the kernel address space.

Don't need to reserve a page of space before KERNEL_BASE in the
ARM32_NEW_VM_LAYOUT case.

Eliminate PTE_BASE and the PT-PT completely in the ARM32_PMAP_NEW case.
Also in the ARM32_PMAP_NEW case, reclaim the USPACE-bytes of wasted space
at the top of the user address that hasn't been needed for a very very
long time.

Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems.

Some features of the new pmap are:

- It allows L1 descriptor tables to be shared efficiently between
multiple processes. A typical "maxusers 32" kernel, where NPROC is set
to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily
with just 4 L1s. This completely solves the problem of running out
of contiguous physical memory for allocating new L1s at runtime on a
busy system.

- Much improved cache/TLB management "smarts". This change ripples
out to encompass the low-level context switch code, which is also
much smarter about when to flush the cache/TLB, and when not to.

- Faster allocation of L2 page tables and associated metadata thanks,
in part, to the pool_cache enhancements recently contributed to
NetBSD by Wasabi Systems.

- Faster VM space teardown due to accurate referenced tracking of L2
page tables.

- Better/faster cache-alias tracking.

The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel
config file, and making the necessary changes to the port-specific
initarm() function. Several ports have already been converted and will
be committed shortly.

Use PAGE_SIZE rather than NBPG.

Use __LDPGSZ (which must be == USRTEXT) as the text address for a.out
executables, and eliminate the USRTEXT constant, which was only used
by the a.out exec code.

Add some code, conditional on PMAP_ALIAS_DEBUG, that can be used to
hunt for virtual aliases between managed (pmap_enter) and non-managed
(pmap_kenter_pa) mappings.

branches: 1.9.2; 1.9.4;
KERNEL_SPACE_START -> KERNEL_BASE

* Rename PROCESS_PAGE_TBLS_BASE -> PTE_BASE
* Rename ALT_PAGE_TBLS_BASE -> APTE_BASE
* Garbage-collect PAGE_TABLE_SPACE_START

Switch back to using vm_page_md (thanks chuq for finding the bug
in the code that made it unstable before!)

Implement pmap_growkernel for arm32 based ports.
Note that this has been compiled on some systems, cats, IQ80310, IPAQ, netwinder and shark (note that shark's build is currently broken due to other reasons), but only actually run on cats.
Shark doesn't make use of the functionality as I believe there has to be a correlation between OFW and the kernel tables so that calls into OFW work.

Back out all the vm_page_md changes. They are causing some
mysterious problems (a similar change to the i386 pmap causes
mysterious problems there, as well), and the issue needs to
be investigated more.

Use vm_page_md rather than pmap_physseg. Saves lots of cycles in
common operations.

branches: 1.3.2;
Move even more constants into the shared 32-bit vmparam.h header.
Cleanup elsewhere will have to be done before we can sanitize this
header any further.

- Move more contents of various <machine/vmparam.h> files into
<arm/arm32/vmparam.h> (mostly the stuff that's tied to the pmap
implementation).
- Since the MMU definitions in pte.h are specific to ARM processors
that support 32-bit mode, move pte.h to <arm/arm32/pte.h>.
- Make the Netwinder startup file build again (use PT_B|PT_C, rather
than PT_CACHEABLE, since the latter expands to a variable these days).

branches: 1.1.2; 1.1.4;
Even though the ARM architecture defines large, standard, and small
pages, we use the standard (4K) page size as PAGE_SIZE. Make the
PAGE_SIZE related variables compile-time constants that reflect this.

Results in a bit over 2K worth of .text savings, and visibly better
code in the places that use PAGE_SIZE, etc.