| History log of /src/sys/arch/arm/include/isa_machdep.h |
| Revision | | Date | Author | Comments |
| 1.13 |
| 12-Dec-2021 |
andvar | s/Miscellanous/Miscellaneous/ in copypasta comments.
|
| 1.12 |
| 18-Oct-2016 |
jdolecek | add isa_intr_establish_xname() to MD isa headers so that it can be used
by MI drivers
|
| 1.11 |
| 29-Jan-2014 |
matt | branches: 1.11.6; 1.11.10;
Make multiple inclusion symbols always start with _ARM_ (not _ARM32_ or
_MACHINE_).
|
| 1.10 |
| 27-Oct-2012 |
chs | branches: 1.10.2;
split device_t/softc for all remaining drivers.
replace "struct device *" with "device_t".
use device_xname(), device_unit(), etc.
|
| 1.9 |
| 21-Sep-2012 |
matt | Switch to the generic bounce buffer support.
|
| 1.8 |
| 01-Jul-2011 |
dyoung | branches: 1.8.2; 1.8.10; 1.8.12;
#include <sys/bus.h> instead of <machine/bus.h>.
|
| 1.7 |
| 19-Aug-2009 |
dyoung | isa_detach_hook() needs two arguments, the first an isa_chipset_tag_t.
|
| 1.6 |
| 19-Aug-2009 |
dyoung | Define isa_dmadestroy(). Declare isa_detach_hook().
|
| 1.5 |
| 28-Apr-2008 |
martin | Remove clause 3 and 4 from TNF licenses
|
| 1.4 |
| 09-May-2003 |
fvdl | branches: 1.4.80; 1.4.106; 1.4.108; 1.4.110;
A few ISA sound drivers like to share dma channels, and hence deferred
isa_dmamap_create() calls to their open/close entrypoints. This worked
with some luck, but broke on i386 when _bus_dmamap_create started
to allocate bounce buffers upfront, since memory below 16M may well
not be available when the sound devices is opened for the Nth time.
To fix this, create a new simple interface, isa_drq_alloc/isa_drq_free,
wrappers around already existing bitmask macros. These are expected
to be used before an isa_dmamap_create call, and after an
isa_dmamap_destroy call, respectively. For the sb and ad1848 drivers,
they're deferred until open/close.
All isa_dmamap_create calls can now use BUS_DMA_ALLOCNOW and be done
at attach time.
|
| 1.3 |
| 07-Jan-2002 |
chris | Finish up the changes to get LOOSE_PROTOTYPES working for cats.
Note that this leaves a few inconsistencies (no more than we already had though) eg initarm is now prototyped in arm32/machdep.h, however only cats currently makes use of that header.
|
| 1.2 |
| 04-Mar-2001 |
matt | branches: 1.2.4; 1.2.6; 1.2.10;
s/vm_offset_t/vaddr_t/g
|
| 1.1 |
| 23-Feb-2001 |
reinoud | Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.
|
| 1.2.10.2 |
| 28-Feb-2002 |
nathanw | Catch up to -current.
|
| 1.2.10.1 |
| 11-Jan-2002 |
nathanw | More catchup.
|
| 1.2.6.1 |
| 10-Jan-2002 |
thorpej | Sync kqueue branch with -current.
|
| 1.2.4.2 |
| 12-Mar-2001 |
bouyer | Sync with HEAD.
|
| 1.2.4.1 |
| 04-Mar-2001 |
bouyer | file isa_machdep.h was added on branch thorpej_scsipi on 2001-03-12 13:27:22 +0000
|
| 1.4.110.2 |
| 19-Aug-2009 |
yamt | sync with head.
|
| 1.4.110.1 |
| 16-May-2008 |
yamt | sync with head.
|
| 1.4.108.1 |
| 18-May-2008 |
yamt | sync with head.
|
| 1.4.106.1 |
| 02-Jun-2008 |
mjf | Sync with HEAD.
|
| 1.4.80.2 |
| 09-Feb-2008 |
chris | Add initial reworking of acorn32 to use new interrupt code.
Note that cats probably won't work currently as acorn32 changed the way
that the pic is registered, it has to provide the irq lines as on acorn32
we attach the iomd after we need to register irqs for the pioc. So we
setup the irqs for iomd before malloc etc are available. This needs
to be fixed.
More work is still needed to update most of the podulebus drivers.
First I need to add podulebus wrapper for interrupts that handles the
maskaddr and maskbits. Exposing them to the common irq code is wrong.
|
| 1.4.80.1 |
| 11-Aug-2007 |
chris | Initial check-in of reworked arm interrupt routines.
Main things to note on this branch:
* spl routines are inlined, less complex, and small (kernel drops in size)
* interrupts are handled in priority order (for most things it doesn't
matter, but pending ipls are used to determine if there is any work to do)
* arm_irqhandler.c is derived from footbridge_irqhandler.c, which was based
on work by thorpej.
* The code tries to touch hardware as little as possible.
* spl masks are no longer tracked, as the system is based on pending ipls
The shared code uses global ipl lists to track which interrupt handlers
are attached to which ipl (arm_iplq[]).
Interrupt sources register with the common code to indicate:
* how many irq lines they have
* a function to set the hardware mask.
* call arm_intr_claim and arm_intr_disestablish to setup handlers
When an interrupt occurs the ipl is flagged as pending, in ipls_pending.
If it can be handled at the current_ipl_level the code does so.
If it can't be handled it's left until the current_ipl_level drops.
As the ipl level changes down a quick test is made of the new ipl level
against the ipls_pending value. If an ipl is pending arm_intr_splx_lifter
is called to handle the pending ipls.
It should be noted that all interrupts are left enabled at the hardware
level, interrupts are only masked when they occur. They are only
re-enabled after it's interrupt handler is called. Hardware masks are not
changed at any other time.
Soft interrupts are treated the same as hardware interrupts, they
register as a provider, and do not get treated specially. All the soft
interrupt handlers are placed onto the relevant global ipl queue, the same
as hard interrupts handlers.
At the moment only footbridge within a cats has been updated to use the new
handling.
Todo:
* change the handling of interrupts, so that the hardware doesn't register
a routine to fetch the hardware status. Instead is makes a call which
provides the mask. This removes the primary flag when registering an
interrupt provider. It also makes more sense with multiple interrupt
sources.
* Arm v5 has the clz asm, which could be used instead of the carefully
hand rolled arm_intr_fls function.
* switch cats isa support to use this framework.
* switch iomd and acorn32 to use this framework.
* switch shark to use this framework.
* port any other arm platforms that are interested
* examine overlaps between this code and ppcoea-renovation branch.
* add support for different trigger types (Edge, level, pulse, etc)
(note that iomd and shark currently touch hardware on every spl change,
hence why they're targets to port)
|
| 1.8.12.3 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.8.12.2 |
| 20-Aug-2014 |
tls | Rebase to HEAD as of a few days ago.
|
| 1.8.12.1 |
| 20-Nov-2012 |
tls | Resync to 2012-11-19 00:00:00 UTC
|
| 1.8.10.1 |
| 06-Dec-2012 |
matt | Merge changes from -current.
|
| 1.8.2.2 |
| 22-May-2014 |
yamt | sync with head.
for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.
this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
|
| 1.8.2.1 |
| 30-Oct-2012 |
yamt | sync with head
|
| 1.10.2.1 |
| 18-May-2014 |
rmind | sync with head
|
| 1.11.10.1 |
| 04-Nov-2016 |
pgoyette | Sync with HEAD
|
| 1.11.6.1 |
| 05-Dec-2016 |
skrll | Sync with HEAD
|
