pic: Update ci_cpl in pic_set_priority callback.

Not all ICs need interrupts disabled to update the priority. DAIF accesses
are not cheap, so push the update of ci_cpl from pic_set_priority to the
IC's pic_set_priority callback, and let the IC driver determine whether
or not it needs interrupts disabled.

s/disbale/disable/ and s/enbale/enable/ in comments. also one more typo fix.

Add ARMEB support to {evb,}arm/marvell.

Combined with upcoming commit to dev/marvell, all peripheral devices
seem to work just fine for KUROBOX_PRO in big-endian mode.

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Remove extra semicolon.

Trailing whitespace

Use PEX numbers consistently. No functional change.

Typo in comment

branches: 1.18.2;
also fix this other off by one.

fix off by one.

ok riastradh

Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.

branches: 1.15.2;
add ARMADA XP's Soc internal bus(Mbus) address decoder initialization function.
some versions of u-boot initializes the address decoder incorrectly(probably
these values are come from Kirkwood SoC or older.) the codes generates
SoC's default address spaces and some modifications for NetBSD's assumption.

add error interrupt definitions, interrupt name strings for 'vmstat -e',
verbose output of Mbus settings for such low-level debugging of SoC.

fix Marvell Coherency Barrier register address.
configure coherency bus maintance broadcast using MPIDR. we need to configure
this regardless of 'options MULTIPROCESSOR.'

add synchronization barrier for AURORA_IO_CACHE_COHERENCY.
cleanup MARVELL L2 cache code.

write back unaligned boundary of L2 cache even if invalidate operation
is requested.

sync L2 cache on the tail of region.

add L2 cache write eviction buffer sync barrier

implement L2 cache maintenance operations of ARMADA XP.
the L2 cahce maintenance operations are defined on SoC internal registers.

branches: 1.8.2; 1.8.6;
Initialize cpu_cc_freq with our CPU speed.

branches: 1.7.2;
Add armada370_getclks().
Remove some white spaces.

Support to check the clock gating for Armada XP in armadaxp.c.
Also move the checking for clock gate of Kirkwood into kirkwood.c.

Move Misc Registers from mvsocreg.h to armadaxpreg.h. These registers only
Armada XP. The misc_base initializes in initarm() instead of mvsoc_bootstrap().

Support __HAVE_PIC_SET_PRIORITY for Armada XP.

Change argument for some functions.

branches: 1.2.2; 1.2.4;
Add CVS IDs where appropriate.

Add support for Armada XP PIC.

Obtained from Marvell, Semihalf.

fix typos in comments.

fix various typos, mainly in comments.

Initialise the windows and allow access to PCI Express port 1 first lane.

Allows xhci(4) to attach in the MV78230 based Lenovo ix4-300d

mvpex1 at mvsoc0 unit 4 offset 0x80000-0x81fff irq 62: Marvell PCI Express Interface
pci1 at mvpex1
xhci0 at pci1 dev 1 function 0: vendor 1033 product 0194 (rev. 0x04)
xhci0: interrupting at interrupt pin INTA#
usb3 at xhci0: USB revision 3.0
usb4 at xhci0: USB revision 2.0

branches: 1.7.2;
Add register macros.
And reorder registers.
Also remove white-spaces.

branches: 1.6.2;
Add mvsocts to mvsoc_periph for Armada XP.

add ARMADA XP's Soc internal bus(Mbus) address decoder initialization function.
some versions of u-boot initializes the address decoder incorrectly(probably
these values are come from Kirkwood SoC or older.) the codes generates
SoC's default address spaces and some modifications for NetBSD's assumption.

add error interrupt definitions, interrupt name strings for 'vmstat -e',
verbose output of Mbus settings for such low-level debugging of SoC.

add synchronization barrier for AURORA_IO_CACHE_COHERENCY.
cleanup MARVELL L2 cache code.

implement L2 cache maintenance operations of ARMADA XP.
the L2 cahce maintenance operations are defined on SoC internal registers.

branches: 1.2.4; 1.2.6; 1.2.10; 1.2.12;
Move Misc Registers from mvsocreg.h to armadaxpreg.h. These registers only
Armada XP. The misc_base initializes in initarm() instead of mvsoc_bootstrap().

Move armadaxpreg.h into arm/marvell.
And add some defines and reorder.

Fix various typos in comments.

branches: 1.3.14; 1.3.54;
Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.

branches: 1.2.2; 1.2.4;
add ARMADA XP's Soc internal bus(Mbus) address decoder initialization function.
some versions of u-boot initializes the address decoder incorrectly(probably
these values are come from Kirkwood SoC or older.) the codes generates
SoC's default address spaces and some modifications for NetBSD's assumption.

add error interrupt definitions, interrupt name strings for 'vmstat -e',
verbose output of Mbus settings for such low-level debugging of SoC.

implement L2 cache maintenance operations of ARMADA XP.
the L2 cahce maintenance operations are defined on SoC internal registers.

Fix various typos in comments and log message.

Drive-by KNF

Add ARMEB support to {evb,}arm/marvell.

Combined with upcoming commit to dev/marvell, all peripheral devices
seem to work just fine for KUROBOX_PRO in big-endian mode.

branches: 1.1.4; 1.1.6; 1.1.18;
Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.

s/interrut/interrupt/ and s/accelelerator/accelerator/ in comments.

branches: 1.1.4; 1.1.6; 1.1.18;
Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.

Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.

branches: 1.17.2;
add new cryptographic accelerator driver 'mvxpsec.'

this driver controls CESA unit as same as mvcesa, but uses DMA engines and
does CBC operations, HMAC operations by hardware. about 2 kbytes of data
are processed at one. supported algorithms are:

- DES-CBC, 3DES-CBC, AES-CBC
- HMAC-SHA1, HMAC-MD5

non-CBC algorithm such as AES-GCM is not supported by CESA's acceleration
engine. mvcesa is still useful to implement such algorithms as combination of
accelerated block cipher and software chaining.

separate buffer management codes 'mvxpbm.c' from if_mvxpe.c.

the buffer management(ex. fill the rx descriptors/buffers) is done by H/W in
ARMADA XP/380, and is done by S/W in ARMADA 370. the H/W BM support is not yet
implemented, so all devices use the S/W management mode at this time.

move Marvell ARMADA SoC's device driver definitions from arm/marvell
to dev/marvell.

add new ethernet driver mvxpe for recent MARVELL's SoC after ARMADA/XP.
this driver supports 'counter mode', and is disabled by default.

ARMADA SoC family has new ethernet controller acceleration mode called
'enhanced mode' or 'counter mode.' it seems that backward compatibility mode
used by if_mvgbe is still working, but the specification of the old mode
is completely disappeared from SoC's reference manual.

I tested the driver using MIRABOX(ARMADA/370).

branches: 1.13.6;
defflag MVSOC_CONSOLE_EARLY

Add MEMSIZE to opt_mvsoc.h

Move defparam opt_mvsoc.h to more appropriate place.

Add ARMADAXP into opt_mvsoc.h.
And add mv78xx0.c. However not test long time.

Fix build failed with ofppc.
Move 'attach mvspi at mvsoc' to arch/arm/marvell/files.marvell.

branches: 1.8.2;
Add support for Armada XP PIC.

Obtained from Marvell, Semihalf.

branches: 1.7.2;
Add mvsocts.

Add mvcesa.

Add support for the watchdog timer in mvsoctmr.
Tested on DreamPlug system.

branches: 1.4.4; 1.4.10;
mvsoc needs pic_splfuncs.

branches: 1.3.2;
Add contributed Marvell Kirkwood RTC driver from Brett Slager
Fixes PR 44004

branches: 1.2.2; 1.2.4; 1.2.6;
Comment-out mvcesa. It not exists now.

Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Add ARMEB support to {evb,}arm/marvell.

Combined with upcoming commit to dev/marvell, all peripheral devices
seem to work just fine for KUROBOX_PRO in big-endian mode.

Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.

branches: 1.9.6; 1.9.10;
Mark a diagnostic only variable

Support to check the clock gating for Armada XP in armadaxp.c.
Also move the checking for clock gate of Kirkwood into kirkwood.c.

branches: 1.7.2; 1.7.4;
Add missing ','
It will fix a bug that "vmstat -e" shows the incorrect counts in wrong entries.

Add 88F6282.
Also fix/add some clock parameters.

Fix always check high. macro KIRKWOOD_IRQ_* means bit number. HIGH is bit0.

branches: 1.4.4; 1.4.10;
Merge in the patch in PR/44965 with some improvements (removing ifs when
possible).

Add support for Dreamplug CPU clock speed detection.

branches: 1.2.2; 1.2.6;
Fix mvPclk. Need 'break' each 'case'.

branches: 1.1.2; 1.1.4;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

s/interrut/interrupt/ and s/accelelerator/accelerator/ in comments.

Fixup model value for Kirkwood 88F6192.
Thanks for lwazidub at gmail com.
Add some KIRKWOOD_MISC_* Registers.
s/AUDIOSDIO/AUDIO/.

Change address/size of CESA Registers.

branches: 1.4.2; 1.4.4;
Add Thermal Sensor for Kirkwood(88F6282). tested only OpenBlockS A6.

Add some comments of 88F6282 and TWSI column.
Add IRQ and BASE for TWSI1.

Add attributes, irqs and base-address for PEX1.

branches: 1.1.2; 1.1.4; 1.1.10; 1.1.14;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Add ARMEB support to {evb,}arm/marvell.

Combined with upcoming commit to dev/marvell, all peripheral devices
seem to work just fine for KUROBOX_PRO in big-endian mode.

Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.

branches: 1.1.4; 1.1.6; 1.1.10; 1.1.12; 1.1.16;
Add mv78xx0 support. However not test long time.

s/interrut/interrupt/ and s/accelelerator/accelerator/ in comments.

Change some defines.

branches: 1.1.2; 1.1.4; 1.1.10; 1.1.14; 1.1.24; 1.1.28;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Fix typo. unknwon -> unknown

Add ARMEB support to {evb,}arm/marvell.

Combined with upcoming commit to dev/marvell, all peripheral devices
seem to work just fine for KUROBOX_PRO in big-endian mode.

Merge thorpej-cfargs2.

branches: 1.30.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.29.28;
Initialise the windows and allow access to PCI Express port 1 first lane.

Allows xhci(4) to attach in the MV78230 based Lenovo ix4-300d

mvpex1 at mvsoc0 unit 4 offset 0x80000-0x81fff irq 62: Marvell PCI Express Interface
pci1 at mvpex1
xhci0 at pci1 dev 1 function 0: vendor 1033 product 0194 (rev. 0x04)
xhci0: interrupting at interrupt pin INTA#
usb3 at xhci0: USB revision 3.0
usb4 at xhci0: USB revision 2.0

Typo in a model string

branches: 1.27.2;
Remove no-need #ifdef MARVELL_ATTR_AXI_DDR. It has defined.

make this compile (but not work) XXX

Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.

branches: 1.24.2;
Add mvsocts to mvsoc_periph for Armada XP.

add new cryptographic accelerator driver 'mvxpsec.'

this driver controls CESA unit as same as mvcesa, but uses DMA engines and
does CBC operations, HMAC operations by hardware. about 2 kbytes of data
are processed at one. supported algorithms are:

- DES-CBC, 3DES-CBC, AES-CBC
- HMAC-SHA1, HMAC-MD5

non-CBC algorithm such as AES-GCM is not supported by CESA's acceleration
engine. mvcesa is still useful to implement such algorithms as combination of
accelerated block cipher and software chaining.

separate buffer management codes 'mvxpbm.c' from if_mvxpe.c.

the buffer management(ex. fill the rx descriptors/buffers) is done by H/W in
ARMADA XP/380, and is done by S/W in ARMADA 370. the H/W BM support is not yet
implemented, so all devices use the S/W management mode at this time.

dump Mbus settins on boot if AV_VERBOSE or AV_DEBUG is enabled.

add MARVELL Armada XP MV78260 B0(rev.2)
recent OpenBlocks AX3 uses it.

add new ethernet driver mvxpe for recent MARVELL's SoC after ARMADA/XP.
this driver supports 'counter mode', and is disabled by default.

ARMADA SoC family has new ethernet controller acceleration mode called
'enhanced mode' or 'counter mode.' it seems that backward compatibility mode
used by if_mvgbe is still working, but the specification of the old mode
is completely disappeared from SoC's reference manual.

I tested the driver using MIRABOX(ARMADA/370).

branches: 1.18.6;
Support Armada 370.

Support MARVELL_TAG_DDR3_CS[0-3].

Support to check the clock gating for Armada XP in armadaxp.c.
Also move the checking for clock gate of Kirkwood into kirkwood.c.

Move Misc Registers from mvsocreg.h to armadaxpreg.h. These registers only
Armada XP. The misc_base initializes in initarm() instead of mvsoc_bootstrap().

Fixup model value for Kirkwood 88F6192.
Thanks for lwazidub at gmail com.
Add some KIRKWOOD_MISC_* Registers.
s/AUDIOSDIO/AUDIO/.

Remove #ifdef ARMADAXP. It is OK !ARMADAXP.
Add some ARMADAXP devices to peripheral list.
And sort and reorder list.

branches: 1.12.2;
Add support for SDIO on Armada XP.

Add support for mvsoc-based Armada XP peripherals.

Obtained from Marvell, Semihalf.

Add CLKGATING_BIT for some devices. This change prevent some boards
that a device's clock is stopped from hangup.

branches: 1.9.2;
Add MVSOC_CONSOLE_EARLY option to get a com console as soon as initarm
is entered.

Add Thermal Sensor for Kirkwood(88F6282). tested only OpenBlockS A6.

Enable idmac.

Add 88F6282 parameters.
Use MVSOC_UNITID_PEX instead of {ORION,KIRKWOOD}_UNITID_PEX. This PEX UNITID is generic UNITID for MVSoC maybe.

branches: 1.5.2;
Change old-style function defintions to C89 prototypes.

Approved by releng.

branches: 1.4.2; 1.4.6;
Add revision 3/A1 of the KIRKWOOD

{ KIRKWOOD(88F6192), 3, "88F619x", "A1", "Kirkwood" },

Add interrupt info for 88F5182 gtidmac(4) and uncomment.

branches: 1.2.2;
Add contributed Marvell Kirkwood RTC driver from Brett Slager
Fixes PR 44004

branches: 1.1.2; 1.1.4; 1.1.6;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Add bounce buffer support for ARM bus_dma(9). Add macros to help initialize
bus_dma_tag structures.

branches: 1.2.2; 1.2.12;
#include <sys/bus.h> instead of <machine/bus.h>.

branches: 1.1.2; 1.1.4; 1.1.10;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Explicitly include armreg.h (for the interrupt enable bit)

Support __HAVE_PIC_SET_PRIORITY for Armada XP.

Reorder include opt_mvsoc.h.

branches: 1.6.2;
Add support for mvsoc-based Armada XP peripherals.

Obtained from Marvell, Semihalf.

branches: 1.5.2;
Fix more -fno-common fallout.
Move more variables to common locations.

Use IST_LEVEL_HIGH for the ist argument to intr_establish() (as is done in
marvell_intr_establish() and other relevant places) instead of 0 in
mvsoc_bridge_intr_establish(). This IST argument isn't used anywhere,
but it looks better this way.

branches: 1.3.2;
In *find_pending_irqs() return the value of pic_mark_pending_sources() instead
of 1. Changed to match other ARM PIC code.

branches: 1.2.6;
Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits. Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

branches: 1.1.2; 1.1.4;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

marvell: Reconcile arm vs powerpc marvell_intr_establish.

If there's a better way to do this without #ifdef __powerpc__, please
have at it!

branches: 1.8.4;
Remove GIC_SPLFUNCS.

Catch up with spl changes.

It's 2021 and ugly is in (with apologies to PWEI)

dump Mbus settins on boot if AV_VERBOSE or AV_DEBUG is enabled.

Add __HAVE_PIC_HAVE_PENDING_INTRS and define it if __HAVE_PIC_SET_PRIORITY
is undefined (also define in mvsoc_intr.h since their use of the latter is
peculiar). This new define controls whether the pending interrupt logic is
compiled. The GIC doesn't use pending interrupts since it uses the priority
level on the GIC to control delivery of interrupts, thus there can never
be a pending interrupt. The kernel shrinks about 4KB with the removal of
the pending interupt support,

branches: 1.4.4; 1.4.6;
Only include "opt_mvsoc.h" if _INTR_PRIVATE is defined.

Support __HAVE_PIC_SET_PRIORITY for Armada XP.

branches: 1.2.2; 1.2.4;
Fix more -fno-common fallout.
Move more variables to common locations.

branches: 1.1.2; 1.1.4; 1.1.10; 1.1.14;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

malloc(9) -> kmem(9)

branches: 1.1.4; 1.1.6; 1.1.18; 1.1.34;
Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.

s/controll/control/ in comments.

Add ARMEB support to {evb,}arm/marvell.

Combined with upcoming commit to dev/marvell, all peripheral devices
seem to work just fine for KUROBOX_PRO in big-endian mode.

use designated initializer to make adaptability and flexibility for changing struct bus_space.
no functional change.

branches: 1.9.12;
Initialise the windows and allow access to PCI Express port 1 first lane.

Allows xhci(4) to attach in the MV78230 based Lenovo ix4-300d

mvpex1 at mvsoc0 unit 4 offset 0x80000-0x81fff irq 62: Marvell PCI Express Interface
pci1 at mvpex1
xhci0 at pci1 dev 1 function 0: vendor 1033 product 0194 (rev. 0x04)
xhci0: interrupting at interrupt pin INTA#
usb3 at xhci0: USB revision 3.0
usb4 at xhci0: USB revision 2.0

branches: 1.8.2;
Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.

branches: 1.7.6; 1.7.10;
Don't manipulate the pte to get uncached memory, use PMAP_NOCACHE instead.
Convert footbring to kenter_pa/kremove

branches: 1.6.2;
Add support for mvsoc-based Armada XP peripherals.

Obtained from Marvell, Semihalf.

branches: 1.5.2;
Add a few missing commas.

Add bus-space-tags for PEX1 of Kirkwood. But not test.

Add stream methods

branches: 1.2.2;
#include <sys/bus.h> instead of <machine/bus.h>.

branches: 1.1.2; 1.1.4; 1.1.10;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Fix typo. unknwon -> unknown

Merge thorpej-cfargs2.

branches: 1.7.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.6.44;
Remove an unused variable

branches: 1.5.2;
Fix a uvm_fault panic that memory is not allocated for the last few GPIO bits.

branches: 1.4.2;
Fix a bug that the irq_masks of GPIO are incorrectly set on Marvell SoCs.

branches: 1.3.2; 1.3.8;
In *find_pending_irqs() return the value of pic_mark_pending_sources() instead
of 1. Changed to match other ARM PIC code.

branches: 1.2.2;
Capture more initial GPIO state.
Also, fix behaviour if the number of GPIOs exceed 32.

branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

branches: 1.1.2; 1.1.4; 1.1.10;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

branches: 1.1.2; 1.1.4; 1.1.10;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

branches: 1.1.4; 1.1.6; 1.1.18;
Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.

branches: 1.1.4; 1.1.6; 1.1.18;
Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.

Fix typos in the word 'Control' in comments.

branches: 1.13.52;
Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.

branches: 1.12.2;
dump Mbus settins on boot if AV_VERBOSE or AV_DEBUG is enabled.

fix Marvell Coherency Barrier register address.
configure coherency bus maintance broadcast using MPIDR. we need to configure
this regardless of 'options MULTIPROCESSOR.'

add synchronization barrier for AURORA_IO_CACHE_COHERENCY.
cleanup MARVELL L2 cache code.

branches: 1.9.6;
Add some MVSOC_MLMB_ definitions for supporting DDR3.

Support to check the clock gating for Armada XP in armadaxp.c.
Also move the checking for clock gate of Kirkwood into kirkwood.c.

Move Misc Registers from mvsocreg.h to armadaxpreg.h. These registers only
Armada XP. The misc_base initializes in initarm() instead of mvsoc_bootstrap().

Add defines for MISC registers.

Remove #ifdef ARMADAXP. It is OK !ARMADAXP.

branches: 1.4.2;
Add support for mvsoc-based Armada XP peripherals.

Obtained from Marvell, Semihalf.

Add CLKGATING_BIT for some devices. This change prevent some boards
that a device's clock is stopped from hangup.

branches: 1.2.2; 1.2.6; 1.2.12; 1.2.16;
Address 3rd issue in PR#43990.
Different implementation but same method as suggested.

branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Change todr_chip_handle::cookie -> todr_chip_handle::todr_dev, and
make it a device_t. Upcoming functional changes will require the
device_t associated with a TODR device.

Change todr_chip_handle::bus_cookie -> todr_chip_handle::todr_devaux.
Nothing was using the old field, but I decided to keep it around just
in cause something needs it in the future.

And with these largely mechanical yet semantically meaningful changes,
thus spake the Oracle: "Welcome to NetBSD 11.99.2."

Remove unnecessary NULL-initialization of TODR handle fields.

use the inline bcdtobin and bintobcd directly instead through a macro.

branches: 1.2.12;
#include <sys/bus.h> instead of <machine/bus.h>.

branches: 1.1.2; 1.1.6;
Add contributed Marvell Kirkwood RTC driver from Brett Slager
Fixes PR 44004

branches: 1.1.2; 1.1.6;
Add contributed Marvell Kirkwood RTC driver from Brett Slager
Fixes PR 44004

For struct timecounter, use C99 initializers.
Compile tested. No functional changes intended.

Change to a tab from white-spaces.

branches: 1.13.6; 1.13.10;
Support Armada 370. tested on MiraBox.

Initialize mvsoctmr_freq earlier (in mvsoctmr_attach) to avoid division
by zero in calculation of the watchdog parameters.

Remove TMR_FLAGS_ARMADAXP and Add flags NOBRIDGE, 25MHZ, SYSCLK.
- NOBRIDGE does not go via a bridge.
- 25MHZ is always counted with the cycle of 25 MHz.
- SYSCLK is counted with the cycle of sysClk. This is used in a few days
for Armada 370.
And please use not mvTclk but variable mvsoctmr_freq for calculation of a clock.
(e.g. in delay())

Remove some #ifdef ARMADAXP. We can enable simultaneously both ARMADAXP and
other SoC options.

branches: 1.9.4;
Add support for timers on Armada XP.

Obtained from Marvell, Semihalf.

branches: 1.8.2;
Actually, the WDT-expired bit in the ICR needs to be cleared before enabling
watchdog reset.

The maximum watchdog period is dependant on mvTclk; calculate at runtime.
This gets the maximum period up to 25 seconds at 166⅔MHz mvTclk.

Remove duplicate global variable.

When disabling watchdog timer, do not set the counter to 0.
Having the watchdog counter at 0 and having WDRstOutEn set to 1 causes
immediate watchdog reset on my 88F5182 A2.

Add support for the watchdog timer in mvsoctmr.
Tested on DreamPlug system.

branches: 1.3.2;
Change old-style function defintions to C89 prototypes.

Approved by releng.

branches: 1.2.2; 1.2.6;
Rework mvsoctmr(4), improving timekeeping accuracy

Inconveniently the Marvell hardware only counts down.
We need to reverse this for timecounter(9), and we need
to do it in a very lightweight way.

- use Timer0 for the clock interrupt
- use Timer1 for timecounter(9) and delay(9)
- drop statclock due to lack of timers (does anyone actually use this?)

branches: 1.1.2; 1.1.4; 1.1.10; 1.1.12;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Add comment 'Armada XP only' to 25MHz bit. Also it is documented to errata?

Add timer 2 and 3 for Discovery Innovation.

branches: 1.2.4;
Add support for timers on Armada XP.

Obtained from Marvell, Semihalf.

branches: 1.1.2; 1.1.4; 1.1.10; 1.1.14; 1.1.24;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Fix typo. unknwon -> unknown

Support Armada XP.

branches: 1.1.2; 1.1.4; 1.1.18;
Add Thermal Sensor for Kirkwood(88F6282). tested only OpenBlockS A6.

Add ARMEB support to {evb,}arm/marvell.

Combined with upcoming commit to dev/marvell, all peripheral devices
seem to work just fine for KUROBOX_PRO in big-endian mode.

Initialise the windows and allow access to PCI Express port 1 first lane.

Allows xhci(4) to attach in the MV78230 based Lenovo ix4-300d

mvpex1 at mvsoc0 unit 4 offset 0x80000-0x81fff irq 62: Marvell PCI Express Interface
pci1 at mvpex1
xhci0 at pci1 dev 1 function 0: vendor 1033 product 0194 (rev. 0x04)
xhci0: interrupting at interrupt pin INTA#
usb3 at xhci0: USB revision 3.0
usb4 at xhci0: USB revision 2.0

branches: 1.11.2;
Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.

branches: 1.10.2;
add new cryptographic accelerator driver 'mvxpsec.'

this driver controls CESA unit as same as mvcesa, but uses DMA engines and
does CBC operations, HMAC operations by hardware. about 2 kbytes of data
are processed at one. supported algorithms are:

- DES-CBC, 3DES-CBC, AES-CBC
- HMAC-SHA1, HMAC-MD5

non-CBC algorithm such as AES-GCM is not supported by CESA's acceleration
engine. mvcesa is still useful to implement such algorithms as combination of
accelerated block cipher and software chaining.

dump Mbus settins on boot if AV_VERBOSE or AV_DEBUG is enabled.

branches: 1.8.6;
Add armada370_getclks().
Remove some white spaces.

Support to check the clock gating for Armada XP in armadaxp.c.
Also move the checking for clock gate of Kirkwood into kirkwood.c.

Move Misc Registers from mvsocreg.h to armadaxpreg.h. These registers only
Armada XP. The misc_base initializes in initarm() instead of mvsoc_bootstrap().

Remove #ifdef ARMADAXP. It is OK !ARMADAXP.
Change argument for armadaxp functions.
Add some MV78xx0 definitions.
Add mv78xx0 functions.

branches: 1.4.2;
Add support for mvsoc-based Armada XP peripherals.

Obtained from Marvell, Semihalf.

branches: 1.3.2;
Add tags for PEX1 of Kirkwood.
Remove unneccesary white-space.
Reorder function prototypes.

branches: 1.2.2;
#include <sys/bus.h> instead of <machine/bus.h>.

branches: 1.1.2; 1.1.4; 1.1.10;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Add ARMEB support to {evb,}arm/marvell.

Combined with upcoming commit to dev/marvell, all peripheral devices
seem to work just fine for KUROBOX_PRO in big-endian mode.

Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.

branches: 1.5.6; 1.5.10;
Mark a diagnostic-only variable

branches: 1.4.6; 1.4.10;
Change old-style function defintions to C89 prototypes.

Approved by releng.

I have a feeling 133333334 was off-by-one.

Constify sysclktbl and use __arraycount thereon.

branches: 1.1.2; 1.1.4; 1.1.10; 1.1.14; 1.1.18;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Change address/size of CESA Registers.

branches: 1.1.2; 1.1.4; 1.1.10; 1.1.14; 1.1.24; 1.1.28;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Remove extra semicolon.

Switch to designated initializers

Add intr_establish_xname support to arm and expose it to intrctl

Fix build

branches: 1.12.10; 1.12.12;
Initialize intr_setattr of arm32_pci_chipset

Initialise the windows and allow access to PCI Express port 1 first lane.

Allows xhci(4) to attach in the MV78230 based Lenovo ix4-300d

mvpex1 at mvsoc0 unit 4 offset 0x80000-0x81fff irq 62: Marvell PCI Express Interface
pci1 at mvpex1
xhci0 at pci1 dev 1 function 0: vendor 1033 product 0194 (rev. 0x04)
xhci0: interrupting at interrupt pin INTA#
usb3 at xhci0: USB revision 3.0
usb4 at xhci0: USB revision 2.0

branches: 1.10.2; 1.10.4;
Fix intr_establish. PCI interrupt is LEVEL LOW.

PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific

branches: 1.8.6;
wrap a few lines

make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

kill sprintf

branches: 1.5.4;
Handle situations where we can have more pexes, like Armada XP.

Obtained from Marvell, Semihalf.

branches: 1.4.2;
Fix pci_conf_hook/interrupt for ARM.

Fix more pci_conf_interrupt/pci_conf_hook problems

branches: 1.2.4;
Neither pci_dma64_available(), pci_probe_device(), pci_mapreg_map(9),
pci_find_rom(), pci_intr_map(9), pci_enumerate_bus(), nor the match
predicate passed to pciide_compat_intr_establish() should ever modify
their pci_attach_args argument, so make their pci_attach_args arguments
const and deal with the fallout throughout the kernel.

For the most part, these changes add a 'const' where there was no
'const' before, however, some drivers and MD code used to modify
pci_attach_args. Now those drivers either copy their pci_attach_args
and modify the copy, or refrain from modifying pci_attach_args:

Xen: according to Manuel Bouyer, writing to pci_attach_args in
pci_intr_map() was a leftover from Xen 2. Probably a bug. I
stopped writing it. I have not tested this change.

siside(4): sis_hostbr_match() needlessly wrote to pci_attach_args.
Probably a bug. I use a temporary variable. I have not tested this
change.

slide(4): sl82c105_chip_map() overwrote the caller's pci_attach_args.
Probably a bug. Use a local pci_attach_args. I have not tested
this change.

viaide(4): via_sata_chip_map() and via_sata_chip_map_new() overwrote the
caller's pci_attach_args. Probably a bug. Make a local copy of the
caller's pci_attach_args and modify the copy. I have not tested
this change.

While I'm here, make pci_mapreg_submap() static.

With these changes in place, I have tested the compilation of these
kernels:

alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-eb NSLU2
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE GUMSTIX
HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321 IXDP425 IXM1200
KUROBOX_PRO LUBBOCK MARVELL_NAS NAPPI SHEEVAPLUG SMDK2800 TEAMASA_NPWR
TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sgimips GENERIC32_IP2x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

As of Sun Apr 3 15:26:26 CDT 2011, I could not compile these kernels
with or without my patches in place:

### evbmips-el GDIUM

nbmake: nbmake: don't know how to make /home/dyoung/pristine-nbsd/src/sys/arch/mips/mips/softintr.c. Stop

### evbarm-el MPCSA_GENERIC
src/sys/arch/evbarm/conf/MPCSA_GENERIC:318: ds1672rtc*: unknown device `ds1672rtc'

### ia64 GENERIC

/tmp/genassym.28085/assym.c: In function 'f111':
/tmp/genassym.28085/assym.c:67: error: invalid application of 'sizeof' to incomplete type 'struct pcb'
/tmp/genassym.28085/assym.c:76: error: dereferencing pointer to incomplete type

### sgimips GENERIC32_IP3x

crmfb.o: In function `crmfb_attach':
crmfb.c:(.text+0x2304): undefined reference to `ddc_read_edid'
crmfb.c:(.text+0x2304): relocation truncated to fit: R_MIPS_26 against `ddc_read_edid'
crmfb.c:(.text+0x234c): undefined reference to `edid_parse'
crmfb.c:(.text+0x234c): relocation truncated to fit: R_MIPS_26 against `edid_parse'
crmfb.c:(.text+0x2354): undefined reference to `edid_print'
crmfb.c:(.text+0x2354): relocation truncated to fit: R_MIPS_26 against `edid_print'

branches: 1.1.2; 1.1.4; 1.1.6; 1.1.10;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.