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History log of /src/sys/arch/arm/pic/picvar.h
RevisionDateAuthorComments
 1.38  25-Jun-2022  jmcneill Remove GIC_SPLFUNCS.
 1.37  26-Sep-2021  jmcneill If an SGI or PPI is established after interrupts are enabled, make sure
we unblock the source on _all_ CPUs and not just the CPU that is
establishing the interrupt.
 1.36  20-Sep-2021  jmcneill Make _splraise/_spllower/splx functions available to modules again.
 1.35  10-Aug-2021  jmcneill arm: pic: allow overriding _splraise/_spllower/splx
 1.34  27-Mar-2021  jmcneill Revert recent pic optimizations until I have more time to work on this.
 1.33  27-Feb-2021  jmcneill branches: 1.33.2;
machine/cpufunc.h -> arm/cpufunc.h for the benefit of non-evbarm ports
 1.32  26-Feb-2021  jmcneill Unfortunately we need to disable interrupts in pic_set_priority to keep
hardware and ci_cpl in sync.
 1.31  21-Feb-2021  jmcneill Inline pic_set_priority and use cpu_dosoftints_ci when available.
 1.30  20-Feb-2021  jmcneill Inline "pic_do_pending_ints" in splx and check ci_pending_ipls to optimize
the common case (hw priority, no cascaded interrupts pending).

This also removes the need for the "pic_pending_used" flag, and should fix
booting on Raspberry Pi 3.
 1.29  20-Feb-2021  jmcneill remove "pic_do_pending_int() prototype; no matching function
 1.28  16-Feb-2021  skrll Provide a pic_set_priority_psw in the case that __HAVE_PIC_SET_PRIORITY
is not defined.
 1.27  15-Feb-2021  jmcneill splx: use pic_set_priority_psw in interrupts disabled case to skip a few
more daif accesses.
 1.26  24-Dec-2019  skrll branches: 1.26.8;
Update pic_add to allocate and return an irqbase if passed
PIC_IRQBASE_ALLOC.
 1.25  23-Dec-2019  jmcneill Add reference counts to intr_mask/intr_unmask as calls can be nested, spotted by thorpej
 1.24  23-Dec-2019  jmcneill Implement acpi_md_intr_mask and acpi_md_intr_unmask
 1.23  27-Mar-2019  ryo enlarge pic_name[] from 14 to 16. bcm2835_intr.c@1.20 used to the limit.
(sizeof struct pic_softc was not changed. it's just same as padding)
 1.22  16-Nov-2018  jmcneill Add intr_establish_xname support to arm and expose it to intrctl
 1.21  09-Nov-2018  jmcneill Increase size of is_irq and pic_irqbase
 1.20  12-Oct-2018  jmcneill Implement intr_string(9)
 1.19  08-Sep-2018  jmcneill Increase the size of is_irq from 8- to 16-bits to allow for > 256 IRQs per pic.
 1.18  16-Jul-2018  jmcneill I added is_affinity to intrsource in the previous commit but it is not used. Remove it.
 1.17  15-Jul-2018  jmcneill Add support for setting and getting interrupt affinity.
 1.16  07-Jul-2015  matt branches: 1.16.16; 1.16.18;
Protect #include "opt_multiprocessor.h" with _KERNEL_OPT
 1.15  15-Apr-2015  matt Add separate IPI routines for IPI_AST and IPI_KPREEMPT.
 1.14  11-Apr-2015  matt Add a pic_cpus to the softc which specifies which cpus the pic can send
IPIs to. For GIC, initialize pic_cpus to kcpuset_running since it can handle
all the cpus.
 1.13  09-Apr-2015  matt Only if we __HAVE_PIC_PENDING_INTRS do we need the variables to track them.
 1.12  08-Apr-2015  matt Add __HAVE_PIC_HAVE_PENDING_INTRS and define it if __HAVE_PIC_SET_PRIORITY
is undefined (also define in mvsoc_intr.h since their use of the latter is
peculiar). This new define controls whether the pending interrupt logic is
compiled. The GIC doesn't use pending interrupts since it uses the priority
level on the GIC to control delivery of interrupts, thus there can never
be a pending interrupt. The kernel shrinks about 4KB with the removal of
the pending interupt support,
 1.11  29-Oct-2014  skrll branches: 1.11.2;
Sprinkle #include "opt_multiprocessor.h"
 1.10  19-May-2014  rmind branches: 1.10.2;
Implement MI IPI interface with cross-call support.
 1.9  13-Mar-2014  matt branches: 1.9.2;
Support MPSAFE interrupts.
 1.8  03-Mar-2014  matt Add a mpsafe flag to the intrsource
 1.7  01-Sep-2012  matt branches: 1.7.2; 1.7.4; 1.7.8;
Add PIC hooks for MP and for the ARM Generic Interrupt Controller.
 1.6  14-Jul-2012  matt Add hooks for __HAVE_PIC_SET_PRIORITY which allows updating of a hardware
(PIC) priority based on current IPL.
 1.5  15-Nov-2010  bsh branches: 1.5.8; 1.5.16;
fix compile error about missing evcnt definition.
picvar.h is now included very early because of uebayashi's change to sys/param.h.
 1.4  30-Dec-2008  matt branches: 1.4.4; 1.4.6;
Use atomic ops to manipulate the bitmasks.
 1.3  28-Apr-2008  martin branches: 1.3.8; 1.3.16;
Remove clause 3 and 4 from TNF licenses
 1.2  27-Apr-2008  matt Merge kernel changes in matt-armv6 to HEAD.
 1.1  29-Aug-2007  matt branches: 1.1.2; 1.1.20; 1.1.22; 1.1.24;
file picvar.h was initially added on branch matt-armv6.
 1.1.24.2  04-May-2009  yamt sync with head.
 1.1.24.1  16-May-2008  yamt sync with head.
 1.1.22.1  18-May-2008  yamt sync with head.
 1.1.20.2  17-Jan-2009  mjf Sync with HEAD.
 1.1.20.1  02-Jun-2008  mjf Sync with HEAD.
 1.1.2.6  29-Feb-2008  matt Rework establish_irq to take an intrsource.
Enable an interrupt after establishing it.
 1.1.2.5  28-Jan-2008  matt Update to new vmlocking world.
 1.1.2.4  06-Nov-2007  matt add spl* routines and prototypes.
add intr_establish/intr_disestablish
 1.1.2.3  11-Sep-2007  matt Another round of pic code. Includes spl* code.
 1.1.2.2  30-Aug-2007  matt More W-I-P
 1.1.2.1  29-Aug-2007  matt Commit W-I-P new generic interrupt controller code similar in idea
to the one in ppcoea-renovation.
 1.3.16.1  15-Feb-2014  matt Merge armv7 support from HEAD, specifically support for the BCM5301X
and BCM56340 evbarm kernels.
 1.3.8.1  19-Jan-2009  skrll Sync with HEAD.
 1.4.6.1  05-Mar-2011  rmind sync with head
 1.4.4.1  15-Nov-2010  uebayasi Sync with HEAD.
 1.5.16.1  28-Nov-2012  matt Merge improved arm support (especially Cortex) from HEAD
including OMAP and BCM53xx support.
 1.5.8.2  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.5.8.1  30-Oct-2012  yamt sync with head
 1.7.8.1  10-May-2013  khorben Allow interrupt handlers to be temporarily disabled or enabled again,
including from within interrupt context: returning non-zero keeps the
handler enabled (as previously), while returning zero disables the
interrupt until a call to intr_enable().

This is necessary with the TPS65950 companion chip because:
- it interrupts on the main code (via IRQ_SYS_nIRQ0)
- interrupt handling requires I2C traffic (to access registers)
- interrupt-based interaction is necessary with this chip (keypad, GPIO...)

XXX Affects other ARM devices using the ARM PIC code, additional code
review is required to address them.
 1.7.4.1  18-May-2014  rmind sync with head
 1.7.2.2  03-Dec-2017  jdolecek update from HEAD
 1.7.2.1  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.9.2.1  10-Aug-2014  tls Rebase.
 1.10.2.2  30-Jul-2015  martin Pull up following revision(s) (requested by skrll in ticket #890):
sys/arch/arm/pic/pic.c: revision 1.27-1.32
sys/arch/arm/omap/omap5430_intr.h: revision 1.3
sys/arch/arm/broadcom/bcm2835_obio.c: revision 1.25
sys/arch/arm/cortex/gic.c: revision 1.18
sys/arch/arm/broadcom/bcm2835reg.h: revision 1.15
sys/arch/evbarm/rpi/rpi_machdep.c: revision 1.61
sys/arch/arm/broadcom/bcm2835_intr.h: revision 1.2
sys/arch/arm/marvell/mvsoc_intr.h: revision 1.5
sys/arch/arm/broadcom/bcm2835_intr.c: revision 1.8-1.10
sys/arch/arm/pic/picvar.h: revision 1.12-1.14
sys/arch/arm/omap/omap4430_intr.h: revision 1.3

Don't clear CI_ASTPENDING in exception return, do it in ast() instead.
Add basic support for __HAVE_PREEMPTION.
Use atomic ops for ci_astpending if __HAVE_PREEMPTION is defined.
Use kpreempt_disable/kpreempt_enable
Add __HAVE_PIC_HAVE_PENDING_INTRS and define it if __HAVE_PIC_SET_PRIORITY
is undefined (also define in mvsoc_intr.h since their use of the latter is
peculiar). This new define controls whether the pending interrupt logic is
compiled. The GIC doesn't use pending interrupts since it uses the priority
level on the GIC to control delivery of interrupts, thus there can never
be a pending interrupt. The kernel shrinks about 4KB with the removal of
the pending interupt support,
Only if we __HAVE_PIC_PENDING_INTRS do we need the variables to track them.
Add #define __HAVE_PIC_PENDING_INTRS for the non-GIC PICs.
Add a pic_cpus to the softc which specifies which cpus the pic can send
IPIs to. For GIC, initialize pic_cpus to kcpuset_running since it can handle
all the cpus.
Adapt pic to deal with the BCM2836 interrupts.
Move pic_pending_pics, pic_pending_ipls, and pic_blocked_irqs into a
structure and make then per-cpu. There is no global interrupt state anymore.
Use right kcpuset call.
Don't need pic_ipi_sender anymore.
Don't send IPIs to ourselves if sending to everyone.
RPI2 MP support.
Thanks to Matt Thomas for making this possible with his changes to pic.c
Use a bit per IPI type in local mailbox 0 registers. Ok matt@
IPIs should be IPL_HIGH according to rmind@
Fix bcm2836mp_pic_{un,}block_irqs to handle timer AND mailbox interrupts
if they're both passed. Thanks to nat@ for finding this.
Sprinkle some KASSERTs
 1.10.2.1  09-Nov-2014  martin Pull up following revision(s) (requested by skrll in ticket #188):
sys/arch/arm/include/arm32/pmap.h: revision 1.136
sys/arch/arm/include/armreg.h: revision 1.100
sys/arch/arm/cortex/gic.c: revision 1.11
sys/arch/arm/arm32/db_interface.c: revision 1.54
sys/arch/arm/include/armreg.h: revision 1.101
sys/arch/arm/cortex/gic.c: revision 1.12
sys/arch/arm/arm32/arm32_machdep.c: revision 1.107
sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.19
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.20
sys/arch/evbarm/conf/BPI: revision 1.5
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.21
sys/arch/arm/arm32/pmap.c: revision 1.306
sys/arch/arm/arm32/db_machdep.c: revision 1.22
sys/arch/arm/arm32/arm32_tlb.c: revision 1.3
sys/arch/arm/arm/undefined.c: revision 1.55
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.22
sys/arch/arm/arm32/pmap.c: revision 1.307
sys/arch/arm/arm32/arm32_tlb.c: revision 1.4
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.23
sys/arch/arm/arm32/arm32_tlb.c: revision 1.5
sys/arch/evbarm/conf/BPI: revision 1.8
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.24
sys/arch/arm/arm32/arm32_tlb.c: revision 1.6
sys/arch/arm/arm32/arm32_tlb.c: revision 1.7
sys/arch/evbarm/conf/CUBIETRUCK: revision 1.5
sys/arch/arm/pic/pic.c: revision 1.23
sys/arch/arm/pic/pic.c: revision 1.24
sys/arch/arm/pic/picvar.h: revision 1.11
sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.20
sys/arch/arm/mainbus/cpu_mainbus.c: revision 1.16
sys/arch/arm/arm32/pmap.c: revision 1.298
sys/arch/arm/arm/cpufunc_asm_arm11.S: revision 1.17
sys/arch/arm/arm/cpufunc_asm_pj4b.S: revision 1.5
sys/arch/arm/arm32/pmap.c: revision 1.310
sys/arch/arm/arm32/pmap.c: revision 1.311
sys/arch/arm/arm32/arm32_kvminit.c: revision 1.32
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.19
sys/arch/arm/arm32/arm32_boot.c: revision 1.10
sys/arch/arm/arm/ast.c: revision 1.25
sys/arch/arm/include/armreg.h: revision 1.98
sys/uvm/pmap/pmap_tlb.c: revision 1.10
sys/arch/arm/arm32/arm32_boot.c: revision 1.8
sys/arch/arm/arm32/arm32_boot.c: revision 1.9
sys/arch/arm/arm/arm_machdep.c: revision 1.43
Various ARM MP fixes.
 1.11.2.2  22-Sep-2015  skrll Sync with HEAD
 1.11.2.1  06-Jun-2015  skrll Sync with HEAD
 1.16.18.2  08-Apr-2020  martin Merge changes from current as of 20200406
 1.16.18.1  10-Jun-2019  christos Sync with HEAD
 1.16.16.4  26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.16.16.3  20-Oct-2018  pgoyette Sync with head
 1.16.16.2  30-Sep-2018  pgoyette Ssync with HEAD
 1.16.16.1  28-Jul-2018  pgoyette Sync with HEAD
 1.26.8.1  03-Apr-2021  thorpej Sync with HEAD.
 1.33.2.1  03-Apr-2021  thorpej Sync with HEAD.

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