Merge thorpej-cfargs2.

branches: 1.17.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.16.52;
struct device * -> device_t for IXP4xx (and nslu2).
Tested with my NSLU2.

Add bounce buffer support for ARM bus_dma(9). Add macros to help initialize
bus_dma_tag structures.

branches: 1.14.2; 1.14.12;
#include <sys/bus.h> instead of <machine/bus.h>.

PCI_FLAGS_IO_ENABLED and PCI_FLAGS_MEM_ENABLED changed their functional
role in NetBSD (drivers are no longer supposed to write these to
pa_flags) without changing name. Correct that.

Rename PCI_FLAGS_IO_ENABLED to PCI_FLAGS_IO_OKAY and
PCI_FLAGS_MEM_ENABLED to PCI_FLAGS_MEM_OKAY, thus making their names
consistent with the other PCI flags and poisoning 3rd-party driver
sources that use the flags in the old bad way.

This patch produces no binary changes in this set of PCI kernels when
they are compiled w/o 'options DIAGNOSTIC' and w/ -V MKREPRO=yes:

algor P4032 P5064 P6032
alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE
evbarm-el GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321
evbarm-el IXDP425 IXM1200 KUROBOX_PRO
evbarm-el LUBBOCK MARVELL_NAS NAPPI NSLU2 SHEEVAPLUG SMDK2800 TEAMASA_NPWR
evbarm-el TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
evbppc OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
iyonix GENERIC
landisk GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sbmips-el GENERIC
sgimips GENERIC32_IP2x GENERIC32_IP3x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

branches: 1.12.102; 1.12.108;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

s/locdesc_t/int/g

branches: 1.9.2;
adaptions to config_search() change, and minor autoconf fixes, mostly from Havard Eidnes

Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

__KERNEL_RCSID()

branches: 1.6.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Make big-endian mode a little closer to working on the BRH. I can talk
to both the EEPROM *and* the PHY on the Ethernet interface now, at least,
though it is still not completely working.

Many thanks to Stephen Goadhouse at ADI for some hints.

Sprinkle a few aprint_normal()s in place of printf().

Fix a typo that prevented the large inbound PCI memory window from
being programmed (guess RedBoot allowed us to get lucky).

Add support for attaching on-chip peripherals to the BECC using
indirect configuration (because the BECC is a soft-core, it could
have a variety of peripherals in the FPGA). Also add support for
local untranslated DMA.

Support for ADI Engineering's Big Endian Companion Chip for the
Intel i80200 XScale processor. Despite its name, the BECC can
run in both big- and little-endian modes.

Change old-stlye-defintions to C89 prototypes.
Switch to CFATTACH_DECL_NEW/device_t/cfdata_t
Defer attaching interrupt evcnts.

Approved by releng.

branches: 1.3.114; 1.3.118;
merge ktrace-lwp.

__KERNEL_RCSID()

branches: 1.1.2;
Add a driver for the reset button on the ADI BECC.

Merge kernel changes in matt-armv6 to HEAD.

branches: 1.2.52; 1.2.76; 1.2.78; 1.2.80;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

branches: 1.1.18;
Support for ADI Engineering's Big Endian Companion Chip for the
Intel i80200 XScale processor. Despite its name, the BECC can
run in both big- and little-endian modes.

malloc(9) -> kmem(9)

branches: 1.14.8;
in many device attach paths, allocate memory with M_WAITOK instead of M_NOWAIT
and remove code to handle failures that can no longer happen.

branches: 1.13.40;
Remove irqframe and replace with identical trapframe.

branches: 1.12.8;
Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits. Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

branches: 1.11.22;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.10.6; 1.10.8; 1.10.10;
Cleanup softint lossage.

And you, be ye fruitful, and multiply; bring forth abundantly in the earth,
and multiply therein. (Genesis 9:6-8)

Make it compile.

branches: 1.7.24; 1.7.28; 1.7.30; 1.7.36; 1.7.40; 1.7.42; 1.7.44;
s/heirarchy/hierarchy/, from Zafer.

branches: 1.6.20; 1.6.22;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

Follow up the type change of i80200_extirq_dispatch which now takes
an irqframe* and not a clockframe* as argument.

branches: 1.3.16;
__KERNEL_RCSID()

branches: 1.2.2;
Rename IPL_IMP -> IPL_VM.

Support for ADI Engineering's Big Endian Companion Chip for the
Intel i80200 XScale processor. Despite its name, the BECC can
run in both big- and little-endian modes.

Remove port-acorn26

OK core@

put back line accidentally deleted before (hi matt)

_setsoftintr is long dead. reap any leftovers from arm.

branches: 1.4.34; 1.4.44; 1.4.50;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.3.6; 1.3.8; 1.3.10;
Cleanup softint lossage.

branches: 1.2.46; 1.2.50; 1.2.52; 1.2.58; 1.2.66;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

branches: 1.1.18;
Support for ADI Engineering's Big Endian Companion Chip for the
Intel i80200 XScale processor. Despite its name, the BECC can
run in both big- and little-endian modes.

Remove unnecessary sys/malloc.h include

Overhaul the interface to pci_configure_bus():
- Don't expose how PCI bus configuration resource management is implemented.
Provide a new resource provider API:

==> pciconf_resource_init() -- Initialize a PCI configuration resources
container.
==> pciconf_resource_add() -- Add a PCI configuration resource to the
container (I/O, MEM, or prefetchable MEM). Multiple resources of
each type may be added.
==> pciconf_resource_fini() -- Tear down the PCI configurtation resources
container once the bus has been configured.

This is much easier to use than the previous method of providing an
extent map for each kind of resource, and works better for e.g. ACPI
platforms that provide potentially multiple PCI resources in tables
provided by firmware.

- Re-implement PCI configuration resource management using vmem arenas,
rather than extent maps.

replace EX_NOWAIT with EX_WAITOK in device attach methods.
remove checks for failures that can no longer occur.

Add intr_establish_xname support to arm and expose it to intrctl

branches: 1.18.16; 1.18.18;
PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific

branches: 1.17.6;
Fix typo.

wrap a few lines

make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

<arm/locore.h> fallout (fixes some include ordering errors)

branches: 1.13.2;
struct device * -> device_t for IXP4xx (and nslu2).
Tested with my NSLU2.

branches: 1.12.2;
Fix pci_conf_interrupt fallout.

converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

branches: 1.10.2; 1.10.6;
#include <sys/bus.h> instead of <machine/bus.h>.

Neither pci_dma64_available(), pci_probe_device(), pci_mapreg_map(9),
pci_find_rom(), pci_intr_map(9), pci_enumerate_bus(), nor the match
predicate passed to pciide_compat_intr_establish() should ever modify
their pci_attach_args argument, so make their pci_attach_args arguments
const and deal with the fallout throughout the kernel.

For the most part, these changes add a 'const' where there was no
'const' before, however, some drivers and MD code used to modify
pci_attach_args. Now those drivers either copy their pci_attach_args
and modify the copy, or refrain from modifying pci_attach_args:

Xen: according to Manuel Bouyer, writing to pci_attach_args in
pci_intr_map() was a leftover from Xen 2. Probably a bug. I
stopped writing it. I have not tested this change.

siside(4): sis_hostbr_match() needlessly wrote to pci_attach_args.
Probably a bug. I use a temporary variable. I have not tested this
change.

slide(4): sl82c105_chip_map() overwrote the caller's pci_attach_args.
Probably a bug. Use a local pci_attach_args. I have not tested
this change.

viaide(4): via_sata_chip_map() and via_sata_chip_map_new() overwrote the
caller's pci_attach_args. Probably a bug. Make a local copy of the
caller's pci_attach_args and modify the copy. I have not tested
this change.

While I'm here, make pci_mapreg_submap() static.

With these changes in place, I have tested the compilation of these
kernels:

alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-eb NSLU2
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE GUMSTIX
HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321 IXDP425 IXM1200
KUROBOX_PRO LUBBOCK MARVELL_NAS NAPPI SHEEVAPLUG SMDK2800 TEAMASA_NPWR
TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sgimips GENERIC32_IP2x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

As of Sun Apr 3 15:26:26 CDT 2011, I could not compile these kernels
with or without my patches in place:

### evbmips-el GDIUM

nbmake: nbmake: don't know how to make /home/dyoung/pristine-nbsd/src/sys/arch/mips/mips/softintr.c. Stop

### evbarm-el MPCSA_GENERIC
src/sys/arch/evbarm/conf/MPCSA_GENERIC:318: ds1672rtc*: unknown device `ds1672rtc'

### ia64 GENERIC

/tmp/genassym.28085/assym.c: In function 'f111':
/tmp/genassym.28085/assym.c:67: error: invalid application of 'sizeof' to incomplete type 'struct pcb'
/tmp/genassym.28085/assym.c:76: error: dereferencing pointer to incomplete type

### sgimips GENERIC32_IP3x

crmfb.o: In function `crmfb_attach':
crmfb.c:(.text+0x2304): undefined reference to `ddc_read_edid'
crmfb.c:(.text+0x2304): relocation truncated to fit: R_MIPS_26 against `ddc_read_edid'
crmfb.c:(.text+0x234c): undefined reference to `edid_parse'
crmfb.c:(.text+0x234c): relocation truncated to fit: R_MIPS_26 against `edid_parse'
crmfb.c:(.text+0x2354): undefined reference to `edid_print'
crmfb.c:(.text+0x2354): relocation truncated to fit: R_MIPS_26 against `edid_print'

branches: 1.8.102; 1.8.108;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.6.16;
"bogus pin" -> "bogus device" in last change.

Fix (real) uninitialized error. (Someone familiar with this should see
if is really an error).

__KERNEL_RCSID()

branches: 1.3.2;
Sprinkle a few aprint_normal()s in place of printf().

Get the interrupt mappings right for the slot.

Support for ADI Engineering's Big Endian Companion Chip for the
Intel i80200 XScale processor. Despite its name, the BECC can
run in both big- and little-endian modes.

Make big-endian mode a little closer to working on the BRH. I can talk
to both the EEPROM *and* the PHY on the Ethernet interface now, at least,
though it is still not completely working.

Many thanks to Stephen Goadhouse at ADI for some hints.

use designated initializer to make adaptability and flexibility for changing struct bus_space.
no functional change.

branches: 1.5.52;
#include <sys/bus.h> instead of <machine/bus.h>.

merge ktrace-lwp.

__KERNEL_RCSID()

branches: 1.2.2;
Make big-endian mode a little closer to working on the BRH. I can talk
to both the EEPROM *and* the PHY on the Ethernet interface now, at least,
though it is still not completely working.

Many thanks to Stephen Goadhouse at ADI for some hints.

Support for ADI Engineering's Big Endian Companion Chip for the
Intel i80200 XScale processor. Despite its name, the BECC can
run in both big- and little-endian modes.

For struct timecounter, use C99 initializers.
Compile tested. No functional changes intended.

#include <sys/bus.h> instead of <machine/bus.h>.

Convert evbarm to timecounter. Only one of the systems was tested, the
rest of the patch is compile-time tested only.

Cleanup softint lossage.

Make it compile.

branches: 1.11.20; 1.11.24; 1.11.26; 1.11.32; 1.11.34; 1.11.36; 1.11.38;
Add generic TOD support. From Bucky Katz.

branches: 1.10.4;
First pass at enabling a lot of ARM ports to convert swiftly to
__HAVE_GENERIC_TODR. Just put #define __HAVE_GENERIC_TODR in types.h
if your port uses one of these files.

branches: 1.9.8; 1.9.20;
merge ktrace-lwp.

branches: 1.8.2;
Fix the various todr_gettime() and todr_settime() fallouts from
-Wcast-qual differently, by instead changing the signatore of those
"functions" to take a "volatile struct timeval*" instead of a
"struct timeval*". Many places, these functions are called with
&time, and time is declared as volatile in <sys/kernel.h>. This
way we can get rid of all the ugly casts which now also triggered
warnings, and caused more code to be added to work around the
problem.

Reviewed by thorpej.

Fix shadowed use of hz, and attempts to cast away volatile on time.

Watch out for those unexpected tains.

branches: 1.5.8; 1.5.10;
Fix think'o in last. Pointed out by Izumi Tsutsui.

Flesh out inittodr() and resettodr().

__KERNEL_RCSID()

branches: 1.2.2;
Sprinkle a few aprint_normal()s in place of printf().

Support for ADI Engineering's Big Endian Companion Chip for the
Intel i80200 XScale processor. Despite its name, the BECC can
run in both big- and little-endian modes.

Channel active is bit 10, not 9.

Support for ADI Engineering's Big Endian Companion Chip for the
Intel i80200 XScale processor. Despite its name, the BECC can
run in both big- and little-endian modes.

struct device * -> device_t for IXP4xx (and nslu2).
Tested with my NSLU2.

branches: 1.3.144; 1.3.154;
Bump copyright date for last.

Add support for attaching on-chip peripherals to the BECC using
indirect configuration (because the BECC is a soft-core, it could
have a variety of peripherals in the FPGA). Also add support for
local untranslated DMA.

Support for ADI Engineering's Big Endian Companion Chip for the
Intel i80200 XScale processor. Despite its name, the BECC can
run in both big- and little-endian modes.

Make big-endian mode a little closer to working on the BRH. I can talk
to both the EEPROM *and* the PHY on the Ethernet interface now, at least,
though it is still not completely working.

Many thanks to Stephen Goadhouse at ADI for some hints.

Add a driver for the reset button on the ADI BECC.

Support for ADI Engineering's Big Endian Companion Chip for the
Intel i80200 XScale processor. Despite its name, the BECC can
run in both big- and little-endian modes.

Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.

branches: 1.4.200; 1.4.202;
Implement pmc(9) -- An interface to hardware performance monitoring
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.

branches: 1.3.2; 1.3.4; 1.3.12;
New interrupt framework for NetBSD/evbarm, and accompanying new
interrupt code for the IQ80310 board support package.

XXX The Integrator board support package still uses the old-style
arm32 interrupt code, so some compatibility hacks have been added
for it. When the Integrator uses new-style interrupts, those hacks
can go away.

Fix a typo (thanks Allen).

Add generic code to manipulate the i80200 ICU.

merge ktrace-lwp.

Add support for the i80312 and i80321 I2C controllers.

branches: 1.6.8;
Move the DMA tag initialization functions into i80312.c.

branches: 1.5.2;
Use the bus_space_generic bus space ops.

branches: 1.4.2;
Add routines for accessing the general purpose I/O facility of
the i80312 Companion I/O chip.

branches: 1.3.2; 1.3.4;
Add support for PCI DMA on the i80312. We currently just do
DMA via the Secondary Inbound window, for now. Will probably
need to revisit this at some point.

Require that the board-specific i80312 front-end slice off a
subregion for the memory controller before calling i80312_attach(),
and fix a bug in the IQ80310 front-end that caused the Secondary
Inbound window to be configured incorrectly.

Snapshot of work-in-progress for Intel i80312 Companion I/O chip;
just basic Inbound and Outbound window setup is done, PCI configuration
space access (not quite working yet), and I/O and Memory space routines
so far.

Config info for the i80312 XScale companion I/O chip.

Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.

branches: 1.16.106; 1.16.108;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.15.10; 1.15.12;
Implement ATU Direct Window in order to increase available PCI address
space.

branches: 1.14.26; 1.14.30; 1.14.32; 1.14.38;
merge ktrace-lwp.

branches: 1.13.6;
Permit the counter frequency to be overridden by a board configuration

branches: 1.12.8; 1.12.10;
Add support for the i80312 and i80321 I2C controllers.

branches: 1.11.2;
Back out unintentional commit.

Support for ADI Engineering's Big Endian Companion Chip for the
Intel i80200 XScale processor. Despite its name, the BECC can
run in both big- and little-endian modes.

Use the generic irq_dispatch.S

Implement pmc(9) -- An interface to hardware performance monitoring
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.

Add support for the Intel i80321 I/O Processor's Application Accelerator
Unit. The AAU provides block fill, block copy, XOR, and XOR-parity-check
operations. We currently provide dmover(9) functions for "zero", "fill8",
and "copy".

Much of this code can be shared with the i80312 Companion I/O AAU, and
will be when support for the older chip is implemented.

Move the DMA tag initialization functions into i80321.c.

Add support for the i80321 watchdog timer.

Add support for attaching IOP built-in sub-devices (aau, dma, ssp,
watchdog, etc.)

Add support for DMA to/from the on-chip devices of the i80321 (no
PCI window translation).

XXX This would be better done by overhauling the shared ARM bus_dma code.

branches: 1.2.2; 1.2.4; 1.2.6;
Use the bus_space_generic bus space ops.

branches: 1.1.2;
Basic support for the Intel i80321 I/O Processor (Xscale core).

Note: This is a snapshot of work-in-progress; there are still some
bugs to be shaken out.

Rework microcode for IXP425 npe(4).

Instead of using objcopy(1), which cannot handle EABI version
embedded in e_flags of ELF header, add a dedicated asm file.

If proprietary microcode binary is present, it is incbin'ed
from that asm file.

Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.

branches: 1.11.136; 1.11.138;
Support the IXP425 watchdog timer.

Add a port of Sam Leffler's IXP425 micro-engine support (from FreeBSD).

This is very much a work in progress. At the present time, only Ethernet
is supported.

branches: 1.9.14; 1.9.16;
Allow the kernel config file to override the default timer frequency
using "options IXP425_CLOCK_FREQ".

branches: 1.8.4; 1.8.6;
merge ktrace-lwp.

branches: 1.7.12;
COM_PXA2X0 is now defflag'd in sys/conf/files

Add support for picking up the size of SDRAM by reading the memory
controller's config register.

- Remove ixpsip_bs_tag (ixp425_sip_io.c). It just duplicated some of
the functionality of ixp425_bs_tag.
- Add missing stream_{read,write}_1 ops to ixp425_bs_tag.
- Re-work the delay() implementation to use the free-running Time-
Stamp counter. This removes the need to bootstrap TMR0 early on.

Make it easier to support different types of IXP425 board:

- Move board-specific PCI/GPIO initialisation to its rightful place.

- Handle clearing down latched GPIO interrupts in a board-independent way.

- Use MI com(4) driver for on-chip UARTs.

- Misc. tidying up.

Tested on IXDP425.

pci bus support

branches: 1.2.2;
add console unit number to configuration parameter.
move structure of uart information

support IXP425 Intel Network Processor
running on BigEndian

Merge isaki-audio2 branch, the overhaul of audio subsystem.
- Interrupt-oriented system rather than thread-oriented.
- Improve stability, quality and performance.
- Split playback and record cleanly. Improve halfduplex support.
- Many bugs are fixed including deadlocks, resource leaks, abuses, etc.
- Simplify audio filter mechanism. The encoding/channels/frequency
conversions are completely handled in the upper layer. So the hard-
ware driver only converts its hardware encoding (if necessary).
- audio_hw_if changes:
- Obsoletes query_encoding and add query_format instead.
- Obsoletes set_params and add set_format instead.
- Remove drain, setfd, mappage.
- The call sequences are changed.
- ioctl AUDIO_GETFD/SETFD, AUDIO_GETCHAN/SETCHAN are obsoleted.
- ioctl AUDIO_{QUERY,GET,SET}FORMAT are introduced.
- cleanup config attributes: au*conv and mulaw.
- All hardware drivers should follow it (I've done as much as possible).

Some file paths are changed:
- dev/audio.c -> dev/audio/audio.c (rewritten)
- dev/audiovar.h -> dev/audio/audiovar.h
- dev/audio_dai.h -> dev/audio/audio_dai.h
- dev/audio_if.h -> dev/audio/audio_if.h
- dev/audiobell.c -> dev/audio/audiobell.c
- dev/audiobellvar.h -> dev/audio/audiobellvar.h
- dev/mulaw.[ch] -> dev/audio/mulaw.[ch] + dev/audio/alaw.c

branches: 1.20.2; 1.20.4;
fix device attributes

branches: 1.19.4;
Add gpio support for Xscale

From Stephan Meisenger in PR/52163

branches: 1.18.2; 1.18.16;
Provide generic a[24]x bus_space methods (aNx is normal access, offset
multipled by N).

Use the generic method and delete the other versions.

Discussed with matt@

branches: 1.17.4; 1.17.10;
PXA2X0_LCD_WRITETHROUGH is defflag'd.

branches: 1.16.4; 1.16.6;
Added SD/MMC support from OpenBSD.
tested on i386, amd64 at current-users ML by pgoyette@.
tested on zaurus by myself.

branches: 1.15.18; 1.15.26; 1.15.32;
Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

branches: 1.14.4; 1.14.18; 1.14.20; 1.14.22; 1.14.24; 1.14.30;
Add PXA2x0 RTC driver.

branches: 1.13.2;
Updates to allow Zaurus screen to rotate 90 degrees to a usable state with the keyboard. Patch from peter@ copied from OpenBSD. Feedback and OK from matt@

Update from the latest Zaurus source from NONAKA Kimihiro.

Includes drivers for I2C, I2S, PCMCIA controller, USB device controller,
OHCI USB controller (from OpenBSD) and some improvements to the LCD
controller driver.

Zaurus Port from OpenBSD by Nonaka Kimihiro
OK gimpy

Add definition the HWUART (and NSSP).

branches: 1.9.20; 1.9.22;
merge ktrace-lwp.

branches: 1.8.2;
The first step to support Intel PXA270.

kernel config option CPU_XSCALE_PXA2X0 is now obsoleted by
CPU_XSCALE_PXA250 and CPU_XSCALE_PXA270. If both of them are defined,
CPU is determined run-time.

Add support for the DMA and AC97 controllers on PXA2x0, and enable them
on the Lubbock evaluation board.

Many thanks to Hiroyuki Bessho for testing this driver with the new
aurateconv interface, as I no longer have access to the hardware.

Contributed by Wasabi Systems, Inc.

branches: 1.6.4;
COM_PXA2X0 is now defflag'd in sys/conf/files

branches: 1.5.2;
Gah, fix previous. s/defopt/defflag/

- Rearrange the PXA2x0 support code to better support attaching
child drivers such as interrupt and gpio controllers.
- Add a function to probe SDRAM size at boot time.
- Add a function to configure the Clock Manager's CKEN settings.
- Add an INTC driver.
- Add a GPIO driver.
- Add attach glue for the PXA2x0's "almost" 16550-compatible uarts.
- Tweak the LCD driver to use the GPIO driver's services for setting
up GPIO pin function.

Use the generic irq_dispatch.S

comment out a file that is not in the tree yet.

branches: 1.1.2;
Config information for Intel PXA2xx application processors.

Remove irqframe and replace with identical trapframe.

branches: 1.9.114;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

Follow up the type change of i80200_extirq_dispatch which now takes
an irqframe* and not a clockframe* as argument.

branches: 1.6.16;
__KERNEL_RCSID()

branches: 1.5.8;
Interrupt steering register is cp13.8, not cp13.2 (D'oh!).

branches: 1.4.2; 1.4.4;
Restructure a few things in order to support other XScale core
I/O processors:
* The i80200 and the i80321 have the same CPU ID, so split the
CPU_XSCALE option into CPU_XSCALE_80200 and CPU_XSCALE_80321
options, and don't let them both be defined at the same time.
XXX May want to revisit this in the future.
* Split some registers common between the i80200 and i80321 into
<arm/xscale/xscalereg.h>.
* Rename a few existing functions.

branches: 1.3.2; 1.3.4;
Make the software copy of INTCTL volatile.

Add an IRQ vector to be shared by all i80200 applications. This
consults the interrupt source bits in the i80200 ICU and calls
a board-specific external IRQ dispatcher if an external IRQ is
pending.

Add generic code to manipulate the i80200 ICU.

Adjust egister usage so that r4 and r5 are preserved as cur{cpu,lwp}
respectively as required by the change to make ASTs operate per-LWP
rather than per-CPU. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS expects this.

XXX untested

branches: 1.18.12;
Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.

branches: 1.17.28; 1.17.30;
Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>

branches: 1.16.34; 1.16.44; 1.16.50;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.15.6; 1.15.8; 1.15.10;
Truly kill current_intr_depth once and for all.

branches: 1.14.8; 1.14.16; 1.14.20; 1.14.22; 1.14.28; 1.14.34;
Rewrite the ARM mutex implementation to be of the simple-mutex variety.
Because pre-v6 ARM lacks support for an atomic compare-and-swap, we
implement _lock_cas() as a restartable atomic squence that is checked
in the IRQ handler right before AST processing. (This is safe because,
for all practical purposes, there are no SMP pre-v6 ARM systems.)

This can serve as a model for other non-MP platforms that lack the
necessary atomic operations for mutexes (SuperH, for example).

Upshots of this change:
- kmutex_t is now down to 8 bytes on ARM; about as good as we can get.
- ARM2 systems don't have to trap and emulate SWP or SWPB for mutexes.

The acorn26 port is not updated by this commit to do the LOCK_CAS_CHECK.
That is left as an exercise for the port maintainer.

Reviewed and tested by Matt Thomas.

branches: 1.13.26;
merge ktrace-lwp.

branches: 1.12.2;
remove vestigal {,e}intr{names,cnt} symbols now that vmstat doesn't need them.

Enable/Restore alignment fault state on interrupt handler entry/exit.

branches: 1.10.2;
Garbage-collect prev_intr_depth; nothing uses it.

Restore .Lpmc_intr_return -- ben only removed one of two references to it.

Pull down rev 1.7.2.1 [must be careful which branch I commit to!]:
Reinstate .Lextirq_return: it was used in two places, and I only removed one
of them.

branches: 1.7.2;
Continue the " - . - 8" purge. Specifically:

add rd, pc, #foo - . - 8 -> adr rd, foo
ldr rd, [pc, #foo - . - 8] -> ldr rd, foo

Also, when saving the return address for a function pointer call, use
"mov lr, pc" just before the call unless the return address is somewhere
other than just after the call site.

Finally, a few obvious little micro-optimisations like using LDR directly
rather than ADR followed by LDR, and loading directly into PC rather than
bouncing via R0.

Use correct-for-ELF local labels.

Use cpsr_c rather then cpsr_all where appropriate.

Implement pmc(9) -- An interface to hardware performance monitoring
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.

Clean up some comments.

* Interrupt status is in cp13.4, not cp13.1 (D'oh!)
* Fix an inverted test.

branches: 1.1.2; 1.1.4; 1.1.12; 1.1.14;
Add an IRQ vector to be shared by all i80200 applications. This
consults the interrupt source bits in the i80200 ICU and calls
a board-specific external IRQ dispatcher if an external IRQ is
pending.

Correct a comment.

branches: 1.3.2; 1.3.4;
Restructure a few things in order to support other XScale core
I/O processors:
* The i80200 and the i80321 have the same CPU ID, so split the
CPU_XSCALE option into CPU_XSCALE_80200 and CPU_XSCALE_80321
options, and don't let them both be defined at the same time.
XXX May want to revisit this in the future.
* Split some registers common between the i80200 and i80321 into
<arm/xscale/xscalereg.h>.
* Rename a few existing functions.

Make this usable directly by assembly code.

branches: 1.1.2; 1.1.4;
Add register definitions for the i80200 Interrupt Controller Unit,
Bus Controller Unit, and Performance Monitoring Unit.

Remove irqframe and replace with identical trapframe.

Fix more -fno-common fallout.
Move more variables to common locations.

branches: 1.4.150;
i80200_extirq_dispatch takes a struct irqframe * now.

branches: 1.3.2;
Restructure a few things in order to support other XScale core
I/O processors:
* The i80200 and the i80321 have the same CPU ID, so split the
CPU_XSCALE option into CPU_XSCALE_80200 and CPU_XSCALE_80321
options, and don't let them both be defined at the same time.
XXX May want to revisit this in the future.
* Split some registers common between the i80200 and i80321 into
<arm/xscale/xscalereg.h>.
* Rename a few existing functions.

branches: 1.2.2; 1.2.4;
Add an IRQ vector to be shared by all i80200 applications. This
consults the interrupt source bits in the i80200 ICU and calls
a board-specific external IRQ dispatcher if an external IRQ is
pending.

Add generic code to manipulate the i80200 ICU.

Merge thorpej-cfargs2.

branches: 1.25.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.24.14;
- Almost all ppbreg.h's definitions are also in pcireg.h. Remove duplicated
definitions from ppbreg.h and move some definitions from ppbreg.h to
pcireg.h.
- Change fast back-to-back "capable" to "enable" in pci_subr.c.
- Print Primary Discard Timer, Secondary Discard Timer, Discard Timer Status
and Discard Timer SERR# Enable bit in pci_subr.c.
- PCI_BRIDGE_PREFETCHBASE32_REG and PCI_BRIDGE_PREFETCHLIMIT32_REG are
"upper" 32bit registers, rename to *UP32_REG to avoid confusion.
- Use macro.

branches: 1.23.38;
struct device * -> device_t for IXP4xx (and nslu2).
Tested with my NSLU2.

Add bounce buffer support for ARM bus_dma(9). Add macros to help initialize
bus_dma_tag structures.

branches: 1.21.2; 1.21.12;
#include <sys/bus.h> instead of <machine/bus.h>.

PCI_FLAGS_IO_ENABLED and PCI_FLAGS_MEM_ENABLED changed their functional
role in NetBSD (drivers are no longer supposed to write these to
pa_flags) without changing name. Correct that.

Rename PCI_FLAGS_IO_ENABLED to PCI_FLAGS_IO_OKAY and
PCI_FLAGS_MEM_ENABLED to PCI_FLAGS_MEM_OKAY, thus making their names
consistent with the other PCI flags and poisoning 3rd-party driver
sources that use the flags in the old bad way.

This patch produces no binary changes in this set of PCI kernels when
they are compiled w/o 'options DIAGNOSTIC' and w/ -V MKREPRO=yes:

algor P4032 P5064 P6032
alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE
evbarm-el GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321
evbarm-el IXDP425 IXM1200 KUROBOX_PRO
evbarm-el LUBBOCK MARVELL_NAS NAPPI NSLU2 SHEEVAPLUG SMDK2800 TEAMASA_NPWR
evbarm-el TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
evbppc OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
iyonix GENERIC
landisk GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sbmips-el GENERIC
sgimips GENERIC32_IP2x GENERIC32_IP3x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

branches: 1.19.96; 1.19.102;
Fix some typos.

branches: 1.18.2; 1.18.4; 1.18.6;
merge ktrace-lwp.

branches: 1.17.12;
Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

Add support for the i80312 and i80321 I2C controllers.

__KERNEL_RCSID()

branches: 1.14.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Use aprint_normal() for cfprint routines.

remove trailing \n in panic(). approved perry.

Use separate function pointers for dmamap_sync pre- vs post- operations.
Change the bus_dmamap_sync() macro to test the ops argument against pre-
and post- constants. The compiler will optimize out dead code because
of the constants. Since post- operations are not needed on ARM (except
for ISA bounce buffers), this eliminate a large number of function calls
which are noops, each of which cost at least 6 cycles just in the call
and return overhead (not to mention whatever other useless work the
compiler decides to do in the callee).

Move the DMA tag initialization functions into i80312.c.

* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.

branches: 1.8.8;
Actually set the i80312_softc global.

branches: 1.7.2;
Initialize pba_intrswiz and pba_intrtag before configuring PCI bus.

Clarify a comment to state that it is intentional that we attach
only the Secondary PCI bus (it's the only bus which can have a
device space hidden from any PCI host on the Primary bus).

Also, use the bus number from the PPB businfo register seecondary bus
field rather than hard-coding "1".

Add routines for accessing the general purpose I/O facility of
the i80312 Companion I/O chip.

Disable MRL, MRM, and MWI for now.

branches: 1.3.2; 1.3.4;
Add a comment explaining that we expect the memory controller
registers to already be subregion'd off, and actually init
the PCI DMA tag.

Disable the ATU interrupt sources (i.e. interrupts that occur when
we get Master or Target aborts).

Snapshot of work-in-progress for Intel i80312 Companion I/O chip;
just basic Inbound and Outbound window setup is done, PCI configuration
space access (not quite working yet), and I/O and Memory space routines
so far.

#include <sys/bus.h> instead of <machine/bus.h>.

merge ktrace-lwp.

__KERNEL_RCSID()

branches: 1.1.2; 1.1.4; 1.1.22;
Add routines for accessing the general purpose I/O facility of
the i80312 Companion I/O chip.

Cleanup i2c bus acquire / release, centralizing all of the logic into
iic_acquire_bus() / iic_release_bus(). "acquire" and "release" hooks
no longer need to be provided by back-end controller drivers (only if
they need special handling, e.g. powering on the i2c controller).
This results in the removal of a bunch of rendundant code from each
back-end controller driver.

Assert that we are not in hard interrupt context in iic_acquire_bus(),
iic_exec(), and iic_release_bus().

branches: 1.6.48;
split iopi2c(4) device/softc

branches: 1.5.2; 1.5.6;
#include <sys/bus.h> instead of <machine/bus.h>.

lockmgr -> mutex

branches: 1.3.24; 1.3.36; 1.3.38; 1.3.40; 1.3.42; 1.3.48; 1.3.52;
Use the SI capitalization for "Hz", "kHz", and "MHz" in comments and strings.
Add a space between numbers and Hz unit.

branches: 1.2.4; 1.2.6; 1.2.8; 1.2.10;
merge ktrace-lwp.

branches: 1.1.4; 1.1.18;
Add support for the i80312 and i80321 I2C controllers.

Sprinkle #include "opt_arm_debug.h" where VERBOSE_INIT_ARM is used

branches: 1.5.52; 1.5.54;
#include <sys/bus.h> instead of <machine/bus.h>.

merge ktrace-lwp.

__KERNEL_RCSID()

branches: 1.2.2; 1.2.20;
Change some #if 0 to #ifdef VERBOSE_INIT_ARM.

branches: 1.1.2; 1.1.4;
Routines for handling the i80312 memory controller for XScale.
Currently includes a routine to determine memory size from the
SDRAM configuration registers.

Remove unnecessary sys/malloc.h include

Overhaul the interface to pci_configure_bus():
- Don't expose how PCI bus configuration resource management is implemented.
Provide a new resource provider API:

==> pciconf_resource_init() -- Initialize a PCI configuration resources
container.
==> pciconf_resource_add() -- Add a PCI configuration resource to the
container (I/O, MEM, or prefetchable MEM). Multiple resources of
each type may be added.
==> pciconf_resource_fini() -- Tear down the PCI configurtation resources
container once the bus has been configured.

This is much easier to use than the previous method of providing an
extent map for each kind of resource, and works better for e.g. ACPI
platforms that provide potentially multiple PCI resources in tables
provided by firmware.

- Re-implement PCI configuration resource management using vmem arenas,
rather than extent maps.

replace EX_NOWAIT with EX_WAITOK in device attach methods.
remove checks for failures that can no longer occur.

- Almost all ppbreg.h's definitions are also in pcireg.h. Remove duplicated
definitions from ppbreg.h and move some definitions from ppbreg.h to
pcireg.h.
- Change fast back-to-back "capable" to "enable" in pci_subr.c.
- Print Primary Discard Timer, Secondary Discard Timer, Discard Timer Status
and Discard Timer SERR# Enable bit in pci_subr.c.
- PCI_BRIDGE_PREFETCHBASE32_REG and PCI_BRIDGE_PREFETCHLIMIT32_REG are
"upper" 32bit registers, rename to *UP32_REG to avoid confusion.
- Use macro.

branches: 1.16.18;
PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific

branches: 1.15.6;
Remove an unused variable

<arm/locore.h> fallout (fixes some include ordering errors)

branches: 1.13.2;
struct device * -> device_t for IXP4xx (and nslu2).
Tested with my NSLU2.

branches: 1.12.2;
Fix more pci_conf_interrupt/pci_conf_hook problems

converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

branches: 1.10.2; 1.10.6;
#include <sys/bus.h> instead of <machine/bus.h>.

merge ktrace-lwp.

__KERNEL_RCSID()

branches: 1.7.2;
Sprinkle a few aprint_normal()s in place of printf().

branches: 1.6.2;
Clarify a comment.

Use the new arm_dcache_align variable to set the PCI device BHLC
register.

Add a "cacheline_size" argument to pci_configure_bus(). It is used
to set the cacheline size in the BHLC register. This should be the
size of the largest D-cache line on a system.

branches: 1.3.2; 1.3.4;
Add support for configuring the PCI bus (starting with the Secondary
bus only, for now).

XXX Some cleanup wrt. pci_conf_interrupt() needs to happen.

Clear the Master Abort after reading config space for a non-existent
PCI device. Disable debugging messages, as PCI config space works now.

Snapshot of work-in-progress for Intel i80312 Companion I/O chip;
just basic Inbound and Outbound window setup is done, PCI configuration
space access (not quite working yet), and I/O and Memory space routines
so far.

Move the DMA tag initialization functions into i80312.c.

Overhaul how DMA ranges work in the ARM bus_dma implementation.

A new "arm32_dma_range" structure now describes a DMA window, with
a system address base, bus address base, and length. In addition to
providing info about which memory regions are legal for DMA, the new
structure provides address translation support, as well.

As before, if a tag does not list any ranges, then all addresses are
considered valid, and no DMA address translation is performed.

This allows us to remove a large chunk of code which was duplicated and
tweaked slightly (to do the address translation) from the stock ARM
bus_dma in the XScale IOP and ARM Integrator ports.

Test compiled on all ARM platforms, test booted on Intel IQ80321 and Shark.

Change the way that DMA map syncs are done. Instead of remembering
the virtual address for each DMA segment, just cache a pointer to the
original buffer/buftype used to load the DMA map, and use that. This
lets us shrink the bus_dma_segment_t down from 12 bytes to 8, and the
cache flushing is also more efficient.

Tested on an i80321 -- changes to others are mechanical.

branches: 1.3.2; 1.3.4;
Fix error reporting in the bus_dmamap_load_mbuf() routines.

Overhaul bus_dmamap_sync for the ARM:
* Track which process (XXX really, vmspace) owns the mapping. When
we sync the map, if the mapping doesn't belong to the kernel or to
the current process (XXX really, vmspace), then no cache fobbing
is necessary, since the cache is Wb-Inv'd on context switch (XXX need
to revisit this when we support FCSE).
* Be smarter about which cache operation we do when sync'ing the map:
- PREREAD -- Invalidate D$ (XXX right now, we actually do Wb-Inv)
- PREWRITE -- Write-back D$ (note, we do NOT invalidate here)
- PREREAD|PREWRITE -- Wb-Inv D$

More work is needed here. In particular, a version for CPUs
with write-through caches should be provided, to eliminate
the write-back steps (which are noops on such CPUs, but skipping
two branches would be nice).

branches: 1.1.2; 1.1.4; 1.1.6;
Add support for PCI DMA on the i80312. We currently just do
DMA via the Secondary Inbound window, for now. Will probably
need to revisit this at some point.

Require that the board-specific i80312 front-end slice off a
subregion for the memory controller before calling i80312_attach(),
and fix a bug in the IQ80310 front-end that caused the Secondary
Inbound window to be configured incorrectly.

use designated initializer to make adaptability and flexibility for changing struct bus_space.
no functional change.

branches: 1.11.52;
#include <sys/bus.h> instead of <machine/bus.h>.

Typo in comment.

branches: 1.9.80; 1.9.100;
bus_dmamem_map: honour BUS_DMA_NOWAIT. noted by Manuel Bouyer.
bus_space_map: always do NOWAIT allocation as it used to be before yamt-km.

we have too many copies!

branches: 1.8.2; 1.8.8;
merge yamt-km branch.
- don't use managed mappings/backing objects for wired memory allocations.
save some resources like pv_entry. also fix (most of) PR/27030.
- simplify kernel memory management API.
- simplify pmap bootstrap of some ports.
- some related cleanups.

branches: 1.7.8; 1.7.10;
Make sure to pass mod/ref seeds with PMAP_WIRED.

__KERNEL_RCSID()

branches: 1.5.8;
remove trailing \n in panic(). approved perry.

Use generic_bs_sr_4 for bus_space_set_region_4.

branches: 1.3.2; 1.3.4;
Use the bus_space_generic bus space ops.

branches: 1.2.2;
Oops, make sure to add in the physical base of the PCI memory
window when mapping PCI mem space. (Whee, I can take out my
local hack, now).

branches: 1.1.2; 1.1.4;
Snapshot of work-in-progress for Intel i80312 Companion I/O chip;
just basic Inbound and Outbound window setup is done, PCI configuration
space access (not quite working yet), and I/O and Memory space routines
so far.

Use the bus_space_generic bus space ops.

branches: 1.1.2; 1.1.4; 1.1.6;
Snapshot of work-in-progress for Intel i80312 Companion I/O chip;
just basic Inbound and Outbound window setup is done, PCI configuration
space access (not quite working yet), and I/O and Memory space routines
so far.

Typos.

Remove clause 3 and 4 from TNF licenses

branches: 1.10.2; 1.10.124; 1.10.126; 1.10.128;
Clean up the i80312 PMU definitions.

Update copyright.

branches: 1.8.2;
Disable the ATU interrupt sources (i.e. interrupts that occur when
we get Master or Target aborts).

Snapshot of work-in-progress for Intel i80312 Companion I/O chip;
just basic Inbound and Outbound window setup is done, PCI configuration
space access (not quite working yet), and I/O and Memory space routines
so far.

Adjust the way the PMMRs are defined -- offsets from a base, not
absolutes. Also, add PPB and more ATU registers.

Add PCI window addresses.

Add a comment describing what this file is.

Add missing RCS ID, add missing name.

branches: 1.2.4;
Fix some register definitions.

Add i80312 register definitions (just registers for now).

struct device * -> device_t for IXP4xx (and nslu2).
Tested with my NSLU2.

branches: 1.10.2; 1.10.12;
#include <sys/bus.h> instead of <machine/bus.h>.

merge ktrace-lwp.

Add support for the i80312 and i80321 I2C controllers.

branches: 1.7.8;
Move the DMA tag initialization functions into i80312.c.

Overhaul how DMA ranges work in the ARM bus_dma implementation.

A new "arm32_dma_range" structure now describes a DMA window, with
a system address base, bus address base, and length. In addition to
providing info about which memory regions are legal for DMA, the new
structure provides address translation support, as well.

As before, if a tag does not list any ranges, then all addresses are
considered valid, and no DMA address translation is performed.

This allows us to remove a large chunk of code which was duplicated and
tweaked slightly (to do the address translation) from the stock ARM
bus_dma in the XScale IOP and ARM Integrator ports.

Test compiled on all ARM platforms, test booted on Intel IQ80321 and Shark.

branches: 1.5.2; 1.5.10;
Add routines for accessing the general purpose I/O facility of
the i80312 Companion I/O chip.

branches: 1.4.2; 1.4.4;
Add support for PCI DMA on the i80312. We currently just do
DMA via the Secondary Inbound window, for now. Will probably
need to revisit this at some point.

Require that the board-specific i80312 front-end slice off a
subregion for the memory controller before calling i80312_attach(),
and fix a bug in the IQ80310 front-end that caused the Secondary
Inbound window to be configured incorrectly.

Snapshot of work-in-progress for Intel i80312 Companion I/O chip;
just basic Inbound and Outbound window setup is done, PCI configuration
space access (not quite working yet), and I/O and Memory space routines
so far.

RCS ID.

Prototypes for i80312 routines.

Merge thorpej-cfargs2.

branches: 1.25.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.24.52;
Add bounce buffer support for ARM bus_dma(9). Add macros to help initialize
bus_dma_tag structures.

branches: 1.23.6;
Change old-stlye-defintions to C89 prototypes.
Switch to CFATTACH_DECL_NEW/device_t/cfdata_t
Defer attaching interrupt evcnts.

Approved by releng.

branches: 1.22.2; 1.22.6;
#include <sys/bus.h> instead of <machine/bus.h>.

PCI_FLAGS_IO_ENABLED and PCI_FLAGS_MEM_ENABLED changed their functional
role in NetBSD (drivers are no longer supposed to write these to
pa_flags) without changing name. Correct that.

Rename PCI_FLAGS_IO_ENABLED to PCI_FLAGS_IO_OKAY and
PCI_FLAGS_MEM_ENABLED to PCI_FLAGS_MEM_OKAY, thus making their names
consistent with the other PCI flags and poisoning 3rd-party driver
sources that use the flags in the old bad way.

This patch produces no binary changes in this set of PCI kernels when
they are compiled w/o 'options DIAGNOSTIC' and w/ -V MKREPRO=yes:

algor P4032 P5064 P6032
alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE
evbarm-el GUMSTIX HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321
evbarm-el IXDP425 IXM1200 KUROBOX_PRO
evbarm-el LUBBOCK MARVELL_NAS NAPPI NSLU2 SHEEVAPLUG SMDK2800 TEAMASA_NPWR
evbarm-el TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
evbppc OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
iyonix GENERIC
landisk GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sbmips-el GENERIC
sgimips GENERIC32_IP2x GENERIC32_IP3x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

branches: 1.20.42; 1.20.48;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.19.10; 1.19.12;
Implement ATU Direct Window in order to increase available PCI address
space.

branches: 1.18.20; 1.18.24; 1.18.26; 1.18.32;
Fix some typos.

branches: 1.17.2; 1.17.4; 1.17.6;
merge ktrace-lwp.

branches: 1.16.12;
Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

Add support for the i80312 and i80321 I2C controllers.

__KERNEL_RCSID()

branches: 1.13.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Define the iopmu (even though it's not being used yet).
Export i80321_local_dma_init().
Make !sc->sc_is_host configuration a little more friendly.
Go back to using IABAR2 instead of IABAR3 for inbound SDRAM access.

Use iwin[3] instead of iwin[2] for RAM access and leave iwin[2] unused.

Program the BARs after the limit regs. When the BARs are written, the
value actually stored in the BAR is masked by the limit register.

* Use a device node for each DMA channel.
* Use aprint_normal() for cfprint routines.

remove trailing \n in panic(). approved perry.

Use separate function pointers for dmamap_sync pre- vs post- operations.
Change the bus_dmamap_sync() macro to test the ops argument against pre-
and post- constants. The compiler will optimize out dead code because
of the constants. Since post- operations are not needed on ARM (except
for ISA bounce buffers), this eliminate a large number of function calls
which are noops, each of which cost at least 6 cycles just in the call
and return overhead (not to mention whatever other useless work the
compiler decides to do in the callee).

Move the DMA tag initialization functions into i80321.c.

Overhaul how DMA ranges work in the ARM bus_dma implementation.

A new "arm32_dma_range" structure now describes a DMA window, with
a system address base, bus address base, and length. In addition to
providing info about which memory regions are legal for DMA, the new
structure provides address translation support, as well.

As before, if a tag does not list any ranges, then all addresses are
considered valid, and no DMA address translation is performed.

This allows us to remove a large chunk of code which was duplicated and
tweaked slightly (to do the address translation) from the stock ARM
bus_dma in the XScale IOP and ARM Integrator ports.

Test compiled on all ARM platforms, test booted on Intel IQ80321 and Shark.

Add support for attaching IOP built-in sub-devices (aau, dma, ssp,
watchdog, etc.)

Add support for DMA to/from the on-chip devices of the i80321 (no
PCI window translation).

XXX This would be better done by overhauling the shared ARM bus_dma code.

branches: 1.2.2; 1.2.4;
* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.

branches: 1.1.2; 1.1.4;
Basic support for the Intel i80321 I/O Processor (Xscale core).

Note: This is a snapshot of work-in-progress; there are still some
bugs to be shaken out.

Change old-stlye-defintions to C89 prototypes.
Switch to CFATTACH_DECL_NEW/device_t/cfdata_t
Defer attaching interrupt evcnts.

Approved by releng.

branches: 1.14.14; 1.14.18;
Don't try to use iopaau_desc_4/8_cache before they're initialized.

branches: 1.13.8; 1.13.10;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.12.6; 1.12.8; 1.12.10;
Fix includes.

branches: 1.11.6;
For the last time, compile!

Make it compile.

branches: 1.9.18; 1.9.60; 1.9.76; 1.9.78; 1.9.80; 1.9.82; 1.9.86; 1.9.88;
Use aprint*().

Use CFATTACH_DECL().

Declare all cfattach structures const.

Rather than referencing the cfdriver directly in the cfdata entries,
instead use a string naming the driver. The cfdriver is then looked
up in a list which is built at run-time.

branches: 1.5.2; 1.5.4; 1.5.6;
Add support for "xor5", "xor6", "xor7", and "xor8".

Restructure the iopaau_function slightly to provide greater
flexibility when using different descriptor formats.

Add support for xor2, xor3, and xor4. Fix inverted direction
indications in some bus_dma operations.

Grr, RCS ID tag typo.

Add support for the Intel i80321 I/O Processor's Application Accelerator
Unit. The AAU provides block fill, block copy, XOR, and XOR-parity-check
operations. We currently provide dmover(9) functions for "zero", "fill8",
and "copy".

Much of this code can be shared with the i80312 Companion I/O AAU, and
will be when support for the older chip is implemented.

#include <sys/bus.h> instead of <machine/bus.h>.

merge ktrace-lwp.

branches: 1.1.4;
Add support for the i80312 and i80321 I2C controllers.

Cleanup i2c bus acquire / release, centralizing all of the logic into
iic_acquire_bus() / iic_release_bus(). "acquire" and "release" hooks
no longer need to be provided by back-end controller drivers (only if
they need special handling, e.g. powering on the i2c controller).
This results in the removal of a bunch of rendundant code from each
back-end controller driver.

Assert that we are not in hard interrupt context in iic_acquire_bus(),
iic_exec(), and iic_release_bus().

branches: 1.5.48;
split iopi2c(4) device/softc

branches: 1.4.2; 1.4.6;
#include <sys/bus.h> instead of <machine/bus.h>.

lockmgr -> mutex

branches: 1.2.34; 1.2.46; 1.2.48; 1.2.50; 1.2.52; 1.2.58; 1.2.62;
merge ktrace-lwp.

branches: 1.1.4; 1.1.18;
Add support for the i80312 and i80321 I2C controllers.

Simplify i80321_intr_calculate_masks().

G/C unused members of struct intrq.

No functional changes intended.

malloc(9) -> kmem(9)

branches: 1.25.8;
in many device attach paths, allocate memory with M_WAITOK instead of M_NOWAIT
and remove code to handle failures that can no longer happen.

branches: 1.24.40;
Remove irqframe and replace with identical trapframe.

Change old-stlye-defintions to C89 prototypes.
Switch to CFATTACH_DECL_NEW/device_t/cfdata_t
Defer attaching interrupt evcnts.

Approved by releng.

branches: 1.22.2; 1.22.6;
#include <sys/bus.h> instead of <machine/bus.h>.

Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits. Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

Apply fixes for PR port-arm/43339:
Set proper IPL_SOFTfoo values even in !FAST_SOFTINTS case.
Some assertions in MI code expect they have unique values,
per comments from rmind@.

Also cleanup various "interrupt hierarchy" code since IPL_NONE and
IPL_SOFTfoo should not be set by any hardware interrupt establish functions.

Ok'ed by mrg@, tested on shark and hpcarm.

branches: 1.19.4; 1.19.6;
Ifdef out and comment a KASSERT() that's a bit too aggressive. There
are never any interrupts masked at IPL_VM before any interrupts have
been registered.

branches: 1.18.8; 1.18.10;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.17.6; 1.17.8; 1.17.10;
Cleanup softint lossage.

And you, be ye fruitful, and multiply; bring forth abundantly in the earth,
and multiply therein. (Genesis 9:6-8)

branches: 1.15.2; 1.15.4; 1.15.6;
Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

branches: 1.14.8; 1.14.24; 1.14.26; 1.14.28; 1.14.30; 1.14.36;
s/heirarchy/hierarchy/, from Zafer.

If I80321_HPI_ENABLED is defined, add support for handling interrupts from
devices hooked up to the HPI pin.

HPIs cannot be masked at the interrupt controller; they can only be masked
by disabling IRQs in the XScale core. To deal with this, we tweak the
interrupt frame so that IRQs are disabled when the interrupt dispatcher
returns due to a masked HPI interrupt. IRQs will be re-enabled by a
subsequent splx(9).

Fortunately the only instance where HPI is used is for the console UART
on a couple of boards, so this hack does not adversely affect performance.

Contributed by Wasabi Systems.

branches: 1.12.8; 1.12.10;
remove 'inline' from the xxx_do_pending() function that is called from
external sources, and conflicts with it's prototype.

branches: 1.11.4; 1.11.6; 1.11.8; 1.11.12;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.9.16;
As per the recent ixp425 fix (which is based on this code):

In the interrupt dispatch loop, make sure to handle any pending interrupts
which came in while we were dealing with the first interrupt(s), and which
are enabled at the current spl.

This fixes a problem where the intr_enabled/hw mask is not updated to
allow pending interrupts through until the next splx(). In some case,
interrupts could be delayed until the next clock tick.

__KERNEL_RCSID()

branches: 1.7.2;
Rename IPL_IMP -> IPL_VM.

Clean up some bad interaction between the spl inlining stuff and
strict-prototypes.

Add a new option EVBARM_BOARDTYPE to differentiate between different
evbarm ports. Inline _splraise/_spllower/splx for i80321 and iq80310
for more performance.

Don't need to frob CPSR in _splraise().

Use more descriptive interrupt names.

branches: 1.2.2; 1.2.4; 1.2.6; 1.2.8;
Fix soft interrupts.

Basic support for the Intel i80321 I/O Processor (Xscale core).

Note: This is a snapshot of work-in-progress; there are still some
bugs to be shaken out.

Do *NOT* lower IPL in i80321_splraise().

Fix various strange crashes for DIAGNOSTIC kernel on evbarm/HDL_G,
including one worked around by if_wm.c rev 1.706:

http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/dev/pci/if_wm.c#rev1.706

Remove port-acorn26

OK core@

_setsoftintr is long dead. reap any leftovers from arm.

branches: 1.10.34; 1.10.44; 1.10.50;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.9.30; 1.9.54; 1.9.56; 1.9.58;
If I80321_HPI_ENABLED is defined, add support for handling interrupts from
devices hooked up to the HPI pin.

HPIs cannot be masked at the interrupt controller; they can only be masked
by disabling IRQs in the XScale core. To deal with this, we tweak the
interrupt frame so that IRQs are disabled when the interrupt dispatcher
returns due to a masked HPI interrupt. IRQs will be re-enabled by a
subsequent splx(9).

Fortunately the only instance where HPI is used is for the console UART
on a couple of boards, so this hack does not adversely affect performance.

Contributed by Wasabi Systems.

branches: 1.8.8; 1.8.10;
Tab Police.

branches: 1.7.4; 1.7.6; 1.7.8; 1.7.10; 1.7.12;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.5.16;
Use __insn_barrier() to prevent the compiler reordering splx/splraise
relative to the code they're supposed to protect.

Fix GCC 3.3.1 nits.

branches: 1.3.2;
Use the generic irq_dispatch.S

Clean up some bad interaction between the spl inlining stuff and
strict-prototypes.

branches: 1.1.2; 1.1.4; 1.1.6;
Add a new option EVBARM_BOARDTYPE to differentiate between different
evbarm ports. Inline _splraise/_spllower/splx for i80321 and iq80310
for more performance.

Use the generic irq_dispatch.S

Garbage-collect prev_intr_depth; nothing uses it.

Continue the " - . - 8" purge. Specifically:

add rd, pc, #foo - . - 8 -> adr rd, foo
ldr rd, [pc, #foo - . - 8] -> ldr rd, foo

Also, when saving the return address for a function pointer call, use
"mov lr, pc" just before the call unless the return address is somewhere
other than just after the call site.

Finally, a few obvious little micro-optimisations like using LDR directly
rather than ADR followed by LDR, and loading directly into PC rather than
bouncing via R0.

Use correct-for-ELF local labels.

Use cpsr_c rather then cpsr_all where appropriate.

Clean up some comments.

branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8;
Basic support for the Intel i80321 I/O Processor (Xscale core).

Note: This is a snapshot of work-in-progress; there are still some
bugs to be shaken out.

branches: 1.4.4;
Move the DMA tag initialization functions into i80321.c.

branches: 1.3.2;
Overhaul how DMA ranges work in the ARM bus_dma implementation.

A new "arm32_dma_range" structure now describes a DMA window, with
a system address base, bus address base, and length. In addition to
providing info about which memory regions are legal for DMA, the new
structure provides address translation support, as well.

As before, if a tag does not list any ranges, then all addresses are
considered valid, and no DMA address translation is performed.

This allows us to remove a large chunk of code which was duplicated and
tweaked slightly (to do the address translation) from the stock ARM
bus_dma in the XScale IOP and ARM Integrator ports.

Test compiled on all ARM platforms, test booted on Intel IQ80321 and Shark.

Change the way that DMA map syncs are done. Instead of remembering
the virtual address for each DMA segment, just cache a pointer to the
original buffer/buftype used to load the DMA map, and use that. This
lets us shrink the bus_dma_segment_t down from 12 bytes to 8, and the
cache flushing is also more efficient.

Tested on an i80321 -- changes to others are mechanical.

Add support for DMA to/from the on-chip devices of the i80321 (no
PCI window translation).

XXX This would be better done by overhauling the shared ARM bus_dma code.

#include <sys/bus.h> instead of <machine/bus.h>.

merge ktrace-lwp.

__KERNEL_RCSID()

branches: 1.1.2; 1.1.8; 1.1.16;
Basic support for the Intel i80321 I/O Processor (Xscale core).

Note: This is a snapshot of work-in-progress; there are still some
bugs to be shaken out.

Remove unnecessary sys/malloc.h include

Overhaul the interface to pci_configure_bus():
- Don't expose how PCI bus configuration resource management is implemented.
Provide a new resource provider API:

==> pciconf_resource_init() -- Initialize a PCI configuration resources
container.
==> pciconf_resource_add() -- Add a PCI configuration resource to the
container (I/O, MEM, or prefetchable MEM). Multiple resources of
each type may be added.
==> pciconf_resource_fini() -- Tear down the PCI configurtation resources
container once the bus has been configured.

This is much easier to use than the previous method of providing an
extent map for each kind of resource, and works better for e.g. ACPI
platforms that provide potentially multiple PCI resources in tables
provided by firmware.

- Re-implement PCI configuration resource management using vmem arenas,
rather than extent maps.

replace EX_NOWAIT with EX_WAITOK in device attach methods.
remove checks for failures that can no longer occur.

PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific

branches: 1.15.6;
<arm/locore.h> fallout (fixes some include ordering errors)

branches: 1.14.2;
struct device * -> device_t for IXP4xx (and nslu2).
Tested with my NSLU2.

branches: 1.13.2;
Fix more pci_conf_interrupt/pci_conf_hook problems

Change old-stlye-defintions to C89 prototypes.
Switch to CFATTACH_DECL_NEW/device_t/cfdata_t
Defer attaching interrupt evcnts.

Approved by releng.

converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

branches: 1.10.2; 1.10.6;
#include <sys/bus.h> instead of <machine/bus.h>.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.8.10; 1.8.12;
Implement ATU Direct Window in order to increase available PCI address
space.

branches: 1.7.26; 1.7.30; 1.7.32; 1.7.38;
Add an offset to the I/O port translations. This allows IQ80321
and others to avoid providing PCI I/O space at address 0.
Iyonix, however, needs to provide PCI I/O space at 0.
The others require I/O space to be offset in part due to a bug
work-around in wm(4) which requires that I/O space access be used
to reset the controllers. If I/O space is mapped at zero, the card
claims, but ignores, the transactions, and the controller doesn't
get reset properly and can't then be used.

merge ktrace-lwp.

branches: 1.5.10;
Start I/O range at base+0x1000 to avoid 0.

branches: 1.4.6;
__KERNEL_RCSID()

branches: 1.3.2;
PCI-X requires that that devices updated their PCIXSR on every
config write with the device number specified in AD[15:11]. If
we don't set this field when issuing a Type 0 cycle, each device
could end of thinking it is at device 0, which can cause a number
of problems. Doing this unconditionally should be OK when only
PCI devices are present.

Use aprint*().

branches: 1.1.2; 1.1.8;
Basic support for the Intel i80321 I/O Processor (Xscale core).

Note: This is a snapshot of work-in-progress; there are still some
bugs to be shaken out.

Move the DMA tag initialization functions into i80321.c.

Overhaul how DMA ranges work in the ARM bus_dma implementation.

A new "arm32_dma_range" structure now describes a DMA window, with
a system address base, bus address base, and length. In addition to
providing info about which memory regions are legal for DMA, the new
structure provides address translation support, as well.

As before, if a tag does not list any ranges, then all addresses are
considered valid, and no DMA address translation is performed.

This allows us to remove a large chunk of code which was duplicated and
tweaked slightly (to do the address translation) from the stock ARM
bus_dma in the XScale IOP and ARM Integrator ports.

Test compiled on all ARM platforms, test booted on Intel IQ80321 and Shark.

Change the way that DMA map syncs are done. Instead of remembering
the virtual address for each DMA segment, just cache a pointer to the
original buffer/buftype used to load the DMA map, and use that. This
lets us shrink the bus_dma_segment_t down from 12 bytes to 8, and the
cache flushing is also more efficient.

Tested on an i80321 -- changes to others are mechanical.

branches: 1.3.2; 1.3.4; 1.3.6;
Fix error reporting in the bus_dmamap_load_mbuf() routines.

branches: 1.2.2;
iwin_base_lo is a BAR value; make sure to mask off the non-address
bits when using it.

Basic support for the Intel i80321 I/O Processor (Xscale core).

Note: This is a snapshot of work-in-progress; there are still some
bugs to be shaken out.

further de-cargocult the new mmap() methods

EINVAL (22) is a valid return value for ARM mmap routines; we need to
return -1 for invalid mmap attempts.

- support *_mmap()
- support BUS_SPACE_MAP_PREFETCHABLE for memory spaces
- fill in *_stream methods if needed
With this Xorg with wsfb works on iyonix. The nv driver still crashes ( and
needs options INSECURE ), something seems to be wrong with accessing IO space.
But, progress.

branches: 1.15.2;
use designated initializer to make adaptability and flexibility for changing struct bus_space.
no functional change.

branches: 1.14.28;
Skip a tautologic check if we know it is one.

branches: 1.13.2; 1.13.12; 1.13.16;
#include <sys/bus.h> instead of <machine/bus.h>.

Typo in comment.

branches: 1.11.20; 1.11.40;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.10.10; 1.10.12;
Implement ATU Direct Window in order to increase available PCI address
space.

branches: 1.9.26; 1.9.30; 1.9.32; 1.9.38;
bus_dmamem_map: honour BUS_DMA_NOWAIT. noted by Manuel Bouyer.
bus_space_map: always do NOWAIT allocation as it used to be before yamt-km.

we have too many copies!

branches: 1.8.2; 1.8.8;
merge yamt-km branch.
- don't use managed mappings/backing objects for wired memory allocations.
save some resources like pv_entry. also fix (most of) PR/27030.
- simplify kernel memory management API.
- simplify pmap bootstrap of some ports.
- some related cleanups.

branches: 1.7.4; 1.7.6;
Supply rr_1 and wr_1.

Make sure to pass mod/ref seeds with PMAP_WIRED.

__KERNEL_RCSID()

branches: 1.4.8;
remove trailing \n in panic(). approved perry.

Use generic_bs_sr_4 for bus_space_set_region_4.

branches: 1.2.2; 1.2.4; 1.2.6;
Use the bus_space_generic bus space ops.

branches: 1.1.2;
Basic support for the Intel i80321 I/O Processor (Xscale core).

Note: This is a snapshot of work-in-progress; there are still some
bugs to be shaken out.

Use the bus_space_generic bus space ops.

branches: 1.1.2;
Basic support for the Intel i80321 I/O Processor (Xscale core).

Note: This is a snapshot of work-in-progress; there are still some
bugs to be shaken out.

Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.

branches: 1.21.28; 1.21.30;
Mark tmr0_read and tmr1_read as unused.

branches: 1.20.2; 1.20.12; 1.20.16;
#include <sys/bus.h> instead of <machine/bus.h>.

Merge kernel changes in matt-armv6 to HEAD.

branches: 1.18.6; 1.18.8; 1.18.10;
Convert evbarm to timecounter. Only one of the systems was tested, the
rest of the patch is compile-time tested only.

branches: 1.17.6;
Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

branches: 1.16.6; 1.16.20; 1.16.22; 1.16.24; 1.16.26; 1.16.32;
Add generic TOD support. From Bucky Katz.

branches: 1.15.4;
i80321 timecounter support.

Patch from Garrett D'Amore, tested by me.

Do not supply our own versions of inittodr, etc. if a port declares
__HAVE_GENERIC_TODR.

branches: 1.13.8; 1.13.20;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.11.2;
Rename an (unused) argument to avoid shadowing.

Fix the various todr_gettime() and todr_settime() fallouts from
-Wcast-qual differently, by instead changing the signatore of those
"functions" to take a "volatile struct timeval*" instead of a
"struct timeval*". Many places, these functions are called with
&time, and time is declared as volatile in <sys/kernel.h>. This
way we can get rid of all the ugly casts which now also triggered
warnings, and caused more code to be added to work around the
problem.

Reviewed by thorpej.

Watch out for those unexpected tains.

Permit the counter frequency to be overridden by a board configuration

branches: 1.7.8; 1.7.10;
Fix think'o in last. Pointed out by Izumi Tsutsui.

Flesh out inittodr() and resettodr().

__KERNEL_RCSID()

branches: 1.4.2;
Use aprint*().

Move XScale common prototypes to xscalevar.h. Add xscale_pmc_dispatch()
prototype. Include xscalevar.h has necessary to being prototypes into
scope.

Implement pmc(9) -- An interface to hardware performance monitoring
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.

branches: 1.1.2; 1.1.4; 1.1.8;
Basic support for the Intel i80321 I/O Processor (Xscale core).

Note: This is a snapshot of work-in-progress; there are still some
bugs to be shaken out.

Change old-stlye-defintions to C89 prototypes.
Switch to CFATTACH_DECL_NEW/device_t/cfdata_t
Defer attaching interrupt evcnts.

Approved by releng.

branches: 1.9.2; 1.9.6;
#include <sys/bus.h> instead of <machine/bus.h>.

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.6.16;
__KERNEL_RCSID()

branches: 1.5.2;
Use aprint*().

branches: 1.4.4;
Use CFATTACH_DECL().

Declare all cfattach structures const.

Rather than referencing the cfdriver directly in the cfdata entries,
instead use a string naming the driver. The cfdriver is then looked
up in a list which is built at run-time.

branches: 1.1.2; 1.1.4; 1.1.6;
Add support for the i80321 watchdog timer.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.