Remove unnecessary <sys/malloc.h>.

Remove bounce buffer support since there is now generic bounce buffer support

branches: 1.17.8; 1.17.18;
Fix DEBUG kernel build.

branches: 1.16.64; 1.16.66;
Use uint8_t * instead of void */char * for ptr arithmetic.

Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.14.26;
merge ktrace-lwp.

branches: 1.13.16;
Add bouncing support

__KERNEL_RCSID()

branches: 1.11.6;
Use separate function pointers for dmamap_sync pre- vs post- operations.
Change the bus_dmamap_sync() macro to test the ops argument against pre-
and post- constants. The compiler will optimize out dead code because
of the constants. Since post- operations are not needed on ARM (except
for ISA bounce buffers), this eliminate a large number of function calls
which are noops, each of which cost at least 6 cycles just in the call
and return overhead (not to mention whatever other useless work the
compiler decides to do in the callee).

Overhaul how DMA ranges work in the ARM bus_dma implementation.

A new "arm32_dma_range" structure now describes a DMA window, with
a system address base, bus address base, and length. In addition to
providing info about which memory regions are legal for DMA, the new
structure provides address translation support, as well.

As before, if a tag does not list any ranges, then all addresses are
considered valid, and no DMA address translation is performed.

This allows us to remove a large chunk of code which was duplicated and
tweaked slightly (to do the address translation) from the stock ARM
bus_dma in the XScale IOP and ARM Integrator ports.

Test compiled on all ARM platforms, test booted on Intel IQ80321 and Shark.

Change the way that DMA map syncs are done. Instead of remembering
the virtual address for each DMA segment, just cache a pointer to the
original buffer/buftype used to load the DMA map, and use that. This
lets us shrink the bus_dma_segment_t down from 12 bytes to 8, and the
cache flushing is also more efficient.

Tested on an i80321 -- changes to others are mechanical.

move initialization of the "struct pglist" returned by uvm_pglistalloc()
from the calling code into uvm_pglistalloc() itself for consistency
and easier error handling

branches: 1.7.2; 1.7.4;
* Rewrite the 32-bit ARM pte.h based on the ARM architecture manual.
Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h. While
doing this, two bugs (as a result of typos) were fixed in

arm/arm32/bus_dma.c
evbarm/integrator/int_bus_dma.c

* arm_byte_to_page() -> arm_btop()
* arm_page_to_byte() -> arm_ptob()

Overhaul bus_dmamap_sync for the ARM:
* Track which process (XXX really, vmspace) owns the mapping. When
we sync the map, if the mapping doesn't belong to the kernel or to
the current process (XXX really, vmspace), then no cache fobbing
is necessary, since the cache is Wb-Inv'd on context switch (XXX need
to revisit this when we support FCSE).
* Be smarter about which cache operation we do when sync'ing the map:
- PREREAD -- Invalidate D$ (XXX right now, we actually do Wb-Inv)
- PREWRITE -- Write-back D$ (note, we do NOT invalidate here)
- PREREAD|PREWRITE -- Wb-Inv D$

More work is needed here. In particular, a version for CPUs
with write-through caches should be provided, to eliminate
the write-back steps (which are noops on such CPUs, but skipping
two branches would be nice).

Overhaul of the ARM cache code. This is mostly a simplification
pass. Rather than providing a whole slew of cache operations that
aren't ever used, distill them down to some useful primitives:

icache_sync_all Synchronize I-cache
icache_sync_range Synchronize I-cache range

dcache_wbinv_all Write-back and Invalidate D-cache
dcache_wbinv_range Write-back and Invalidate D-cache range
dcache_inv_range Invalidate D-cache range
dcache_wb_range Write-back D-cache range

idcache_wbinv_all Write-back and Invalidate D-cache,
Invalidate I-cache
idcache_wbinv_range Write-back and Invalidate D-cache,
Invalidate I-cache range

Note: This does not yet include an overhaul of the actual asm files
that implement the primitives. Instead, we've provided a safe default
for each CPU type, and the individual CPU types can now be optimized
one at a time.

branches: 1.3.2;
Don't include <machine/psl.h> directly.

Use <arm/cpufunc.h>, not <machine/cpufunc.h>.

branches: 1.1.2;
Basic support for the Integrator/AP board.

#include <sys/bus.h> instead of <machine/bus.h>.

Overhaul how DMA ranges work in the ARM bus_dma implementation.

A new "arm32_dma_range" structure now describes a DMA window, with
a system address base, bus address base, and length. In addition to
providing info about which memory regions are legal for DMA, the new
structure provides address translation support, as well.

As before, if a tag does not list any ranges, then all addresses are
considered valid, and no DMA address translation is performed.

This allows us to remove a large chunk of code which was duplicated and
tweaked slightly (to do the address translation) from the stock ARM
bus_dma in the XScale IOP and ARM Integrator ports.

Test compiled on all ARM platforms, test booted on Intel IQ80321 and Shark.

branches: 1.1.2; 1.1.4; 1.1.12;
Basic support for the Integrator/AP board.

branches: 1.1.2; 1.1.4;
Basic support for the Integrator/AP board.

Fix typo in error message.

Provide a shared pmap_devmap implementation and convert all pmap_devmap
arrays to use DEVMAP_ENTRY{,_END}

G/C unused flag

PMAP_DEBUG has been deleted on arm

Trailing whitespace

branches: 1.77.8;
Consistently use vaddr_t as initarm and friends return type.

Makes no difference to binaries except for aarch64 where it's required

Centralise defparam CONSADDR, CONSPEED, CONMODE and CONADDR into
opt_console.h and adjust.

Sprinkle #include "opt_arm_debug.h" where VERBOSE_INIT_ARM is used

branches: 1.74.28; 1.74.30;
<arm/locore.h> fallout (fixes some include ordering errors)

branches: 1.73.2;
Add support for the ARM Integrator/CP from Sergio L�pez.

The code hasn't been tested on real hardware, but INTEGRATOR_CP config
is useful for QEMU which supports it.

Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.

branches: 1.71.2;
Move the standard definitions of the {UND,IRQ,FIQ,ABT}_STACK_SIZE to
<arm32/machdep.h>
Move the extern for cpu_reset_address to the same file.
Add cpu_reset_address_paddr.
Kill cpu_reset_v4_MMU_disable.
if cpu_reset_address is NULL, then the MMU will be disabled.

Fix more -fno-common fallout.
Move more variables to common locations.

Add support for the PL011 to plcom. Pull across a bunch of fixes from
com(4) while I'm here and do some other tidyup.

Tested on a RaspberryPi.

PL010 not tested.

branches: 1.68.2; 1.68.8;
#include <sys/bus.h> instead of <machine/bus.h>.

dependant -> dependent

Use cpu_* prefix to call cpu_* functions (setttb() -> cpu_setttb()); no
functional changes.

Garbage collect an unused global, vm_offset_t pagetables_start.

- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

Kill proc0paddr. Use lwp0.l_addr instead.

Remove all declarations of physmem from sys/arch. Add an include of
<sys/systm.h> to the one file that did not already contain it.
This now means that physmem can be changed by updating systm.h and uvm_page.c
(excluding fixing printfs)

As discussed on tech-kern: mutex_init is too heavyweight for early bootstrap
phases, so move the initialization of the ksyms mutex back into main via
a function called ksyms_init. Rename the existing (but quite different)
ksyms_init* variations into ksyms_addsyms_elf() and ksyms_addsyms_explicit()
and adapt machdep code accordingly.

Remove LKMs and switch to the module framework, pass 1.

Proposed on tech-kern@.

It is not appropriate to call pmf_system_shutdown(9) from
doshutdownhooks(9): shutdown hooks registered by shutdownhook_establish(9)
expect to be called with interrupts disabled, but shutdown hooks
registered with pmf_device_register1(9) expect to be called with
interrupts enabled. So I have made two changes:

1 Do not call pmf_system_shutdown() from doshutdownhooks(). Instead,
change every call to doshutdownhooks() to a call to doshutdownhooks()
followed by a call to pmf_system_shutdown(). No functional change
is intended by this change.

2 Make i386 re-enable interrupts briefly while it calls
pmf_system_shutdown(). I leave it to others either to fix the
other ports, or to factor out some MI shutdown code, as joerg@
suggests, and fix that. Note that a functional change *is* intended
by this change.

I hope that this patch will stop us from flip-flopping between
calling doshutdownhooks() and pmf_system_shutdown() sometimes with
and sometimes without interrupts enabled.

branches: 1.58.6; 1.58.8;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.57.6; 1.57.8; 1.57.10;
Remove arm support for IPKDB.

It hasn't worked since arm was broken out from arm32 in Jan 2001, and
no-one has noticed or cared to fix it.

branches: 1.56.34; 1.56.38; 1.56.44; 1.56.52;
in initarm(), initialise kernel_l1pt.pv_va as well as kernel_l1pt.pv_pa.

branches: 1.55.4; 1.55.6; 1.55.8; 1.55.12;
bare asm -> __asm

merge ktrace-lwp.

branches: 1.53.10;
Fix comments regarding configration bounaries

Fix comments slighly

Don't use vector_page before it's been initialized.

Uppercase CPU, plural is CPUs.

Remove include of ifpga/irqhandler.h.

Switch to using generic soft interrupts.

General cleanups of the bootstrap code

When an Integrator board has less than 256M of SDRAM fitted, the
memory that is "obscured" by the SSRAM is visible at a wrapped address.
So we can use the full amount of SDRAM in almost all cases.

Remove a verbose-boot message that kills the bootstrap (since the
console port mapping has just been moved).

The third argument to pmap_map_chunk is the pa not the va.

__KERNEL_RCSID()

branches: 1.42.2;
Replace the ad-hoc "section mapping table" for static device mappings
with a more generic "devmap" structure that can also handle mappings
made with large and small pages. Add new pmap routines to enter these
mappings during bootstrap (and "remember" the devmap), and routines to
look up the static mappings once the kernel is running.

Also pass a type argument to comcnattach() and com_kgdb_attach().
comspeed() (and thus cominit()) may need this information.

Move KERNEL_VM_SIZE into the C files where its used.

Move KERNEL_VM_BASE inside where it is used (it won't be there for long).

Decrease the verbosity level unless VERBOSE_INIT_ARM is defiend.

Remove declaration of unused local variable: kernel_ptpt.

Don't expose KERNEL_TEXT_BASE outside of board-specific code. This gives
individual board start-up code more flexibility about where the kernel
starts in the kernel address space.

Reduce differences between ARM32_NEW_VM_LAYOUT and not; always pass
the start and end of the kernel managed virtual address space to
pmap_bootstrap() in the new pmap.

Remove old pmap support for platforms which have fully switched over.

Switch Integrator, IXM1200, and SMDK2800 to ARM32_PMAP_NEW. These
are the last of the ARM platforms to be converted.

Call ksyms_init() instead of ddb_init() in case of
NKSYMS || defined(DDB) || defined(LKM)

Use PAGE_SIZE rather than NBPG.

There are two #defines of CONSPEED in here; didn't make sense to me.

Merge the nathanw_sa branch.

remove trailing \n in panic(). approved perry.

Enable caching on kernel and user page tables. This saves having
to do uncached memory access during VM operations (which can be
quite expensive on some CPUs).

We currently write-back PTEs as soon as they're modified; there is
some room for optimization (to write them back in larger chunks).
For PTEs in the APTE space (i.e. PTEs for pmaps that describe another
process's address space), PTEs must also be evicted from the cache
complete (PTEs in PTE space will be evicted durint a context switch).

Do cached memory access to L1 tables, making sure to write-back the
cache after any L1 table modifications.

Move the calls to uvm_page_physload() out of pmap_bootstrap() and
into platform-specific initialization code, giving platform-specific
code control over which free list a given chunk of memory gets put
onto.

Changes are essentially mechanical. Test compiled for all ARM
platforms, test booted on Intel IQ80321 and Shark.

Discussed some time ago on port-arm.

Move the uvm_setpagesize() call to platform-dependent code in preparation
for other changes to pmap_bootstrap().

Changes to allow for the fact that the kernel is now mapped at
0xc0200000. Tidy up to remove dead comments and code.
Allow more than one L1 entry for the kernel space and use the 'spare'
memory below the kernel code for the initial page tables in the same
way that the iq80310 does.

branches: 1.22.2; 1.22.4;
Remove footbridge-specific stuff that will never apply on the Integrator.

* Rewrite the 32-bit ARM pte.h based on the ARM architecture manual.
Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h. While
doing this, two bugs (as a result of typos) were fixed in

arm/arm32/bus_dma.c
evbarm/integrator/int_bus_dma.c

Clean up handling of the vector page on 32-bit ARM systems:
* Don't refer to VA 0, instead refer to a new variable: vector_page
* Delete the old zero_page_*() functions, replacing them with a new
one: vector_page_setprot().
* When manipulating vector page mappings in user pmaps, only do so if
the vector page is below KERNEL_BASE (if it's above KERNEL_BASE, the
vector page is mapped by the kernel pmap).
* Add a new function, arm32_vector_init(), which takes the virtual
address of the vector page (which MUST be valid when the function
is called) and a bitmask of vectors the kernel is going to take
over, and performs all vector page initialization, including setting
the V bit in the CPU Control register ("relocate vectors to high
address"), if necessary.

* Fix use of pmap_curmaxkvaddr.
* Use the PTP hint in the pmap.

* Rename PROCESS_PAGE_TBLS_BASE -> PTE_BASE
* Rename ALT_PAGE_TBLS_BASE -> APTE_BASE
* Garbage-collect PAGE_TABLE_SPACE_START

Implement pmap_growkernel for arm32 based ports.
Note that this has been compiled on some systems, cats, IQ80310, IPAQ, netwinder and shark (note that shark's build is currently broken due to other reasons), but only actually run on cats.
Shark doesn't make use of the functionality as I believe there has to be a correlation between OFW and the kernel tables so that calls into OFW work.

Fix the "va" argument to pmap_map_entry() when mapping kernel_ptpt.

Change pmap_map_entry() to work like pmap_map_chunk(): take a pointer
to the L1 table and a virtual address, and no pointer to the L2 table.
The L2 table will be looked up by pmap_map_entry(), which will panic
if the there is no L2 table for the requested VA.

NOTE: IT IS EXTREMELY IMPORTANT THAT THE CORRECT VIRTUAL ADDRESS
BE PROVIDED TO pmap_map_entry()! Notably, the code that mapped
the kernel L2 tables into the kernel PT mapping L2 table were not
passing actual virtual addresses, but rather offsets into the range
mapped by the L2 table. I have fixed up all of these call sites,
and tested the resulting kernel on both an IQ80310 and a Shark.
Other portmasters should examine their pmap_map_entry() calls if
their new kernels fail.

Keep track of which kernel PTs are available during bootstrap,
and let pmap_map_chunk() lookup the correct one to use for the
current VA. Eliminate the "l2table" argument to pmap_map_chunk().

Add a second L2 table for mapping kernel text/data/bss on the
IQ80310 (fixes booting kernels with ramdisks).

Always pass the L1 table to pmap_map_chunk(). This allows pmap_map_chunk()
to perform some error checking.

map_chunk() -> pmap_map_chunk(), and move it to pmap.c

map_pagetable() -> pmap_link_l2pt(), and move it to pmap.c

Collapse map_entry{,ro,nc}() into a single pmap_map_entry() that
takes a prot and a "cacheable" indicator.

Rename map_section() to pmap_map_section(), move it to pmap.c, and give it
an extra argument (prot - specifies protection of the mapping).

Pull in <evbarm/ifpga/irqhandler.h> for now.

Overhaul of the ARM cache code. This is mostly a simplification
pass. Rather than providing a whole slew of cache operations that
aren't ever used, distill them down to some useful primitives:

icache_sync_all Synchronize I-cache
icache_sync_range Synchronize I-cache range

dcache_wbinv_all Write-back and Invalidate D-cache
dcache_wbinv_range Write-back and Invalidate D-cache range
dcache_inv_range Invalidate D-cache range
dcache_wb_range Write-back D-cache range

idcache_wbinv_all Write-back and Invalidate D-cache,
Invalidate I-cache
idcache_wbinv_range Write-back and Invalidate D-cache,
Invalidate I-cache range

Note: This does not yet include an overhaul of the actual asm files
that implement the primitives. Instead, we've provided a safe default
for each CPU type, and the individual CPU types can now be optimized
one at a time.

branches: 1.6.2;
Use <arm/undefined.h> instead of <machine/undefined.h>.

No need to pull in <machine/pte.h> directly.

branches: 1.4.2;
Add some rudimentary support for ELF symbols in DDB on the ARM ports.
On platforms which load the kernel sans symbols directly from firmware
(possibly in e.g. S-Record format), call ddb_init() with empty arguments,
so that it will search any compiled in SYMTAB_SPACE. On all other platforms,
if __ELF__, also call ddb_init() with empty arguments until ELF bootloaders
which pass symbol information are ready.

Remove unneeded declarations of the db_machine_init() function. The
ARM ports are the only ones that actually have one, and it is about
to change.

Remove unnecessary prototypes for zero_page_read{only,write}().

Basic support for the Integrator/AP board.

Convert to unified syntax

branches: 1.11.4; 1.11.14; 1.11.18;
Add RCSID when needed.
Don't include pmap.h or pte.h, include "assym.h" instead.
Use assym.h provided values.

branches: 1.10.100; 1.10.106; 1.10.108;
merge ktrace-lwp.

Enable use of the CM1136J-s core module on the Integrator.

Fix the v6 boot check: A '6' in the architecture field really means
Architecture v5TEJ.

Add a couple of sanity checks in case someone tries to boot the kernel
on a CM board that we can't support. In essence that means any board
without an MMU. For now also fault v6 based CPUs since the kernel
doesn't know how to handle these yet.

Uppercase CPU, plural is CPUs.

branches: 1.5.6;
Map the low 4M of memory at 0xc0000000.

branches: 1.4.2;
* Rewrite the 32-bit ARM pte.h based on the ARM architecture manual.
Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h. While
doing this, two bugs (as a result of typos) were fixed in

arm/arm32/bus_dma.c
evbarm/integrator/int_bus_dma.c

* Add support for running the IQ80310 kernel where KERNEL_BASE !=
physical memory start. Garbage-collect some cruft while here.
* Move the kernel up to 0xc0000000, giving a 1G/3G kernel/user split.
* Adjust the Integrator startup code accordingly.

branches: 1.2.2;
- Move more contents of various <machine/vmparam.h> files into
<arm/arm32/vmparam.h> (mostly the stuff that's tied to the pmap
implementation).
- Since the MMU definitions in pte.h are specific to ARM processors
that support 32-bit mode, move pte.h to <arm/arm32/pte.h>.
- Make the Netwinder startup file build again (use PT_B|PT_C, rather
than PT_CACHEABLE, since the latter expands to a variable these days).

branches: 1.1.2;
Basic support for the Integrator/AP board.

<sys/extent.h> not needed here.

Fix pci_conf_interrupt issues

Fix pci_conf_interrupt lossage.

branches: 1.4.34;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.3.50; 1.3.74; 1.3.76; 1.3.78;
merge ktrace-lwp.

__KERNEL_RCSID()

branches: 1.1.2; 1.1.4; 1.1.20;
Basic support for the Integrator/AP board.