Clean up initialization of com_regs structure, in preparation for
some additional changers.

branches: 1.14.52; 1.14.54;
#include <sys/bus.h> instead of <machine/bus.h>.

Remove clause 3 and 4 from TNF licenses

branches: 1.12.2; 1.12.4;
Split device_t and softc for all com(4) devices (well, everything that
uses a com_softc backend). Use proper types and ansify where appropriate.

branches: 1.11.34; 1.11.54; 1.11.58;
Add an option COM_REGMAP to allow com(4) to use an array of register indices.
This allows us to convert aucom to just another com attachment, and cleanup
some code in the com_arbus.c.

Additionally, we use a common com_cleanup routine rather than having a
zillion copies of it in the attachment points.

This has been tested on a number architectures, and it has been shown to get
close to comparable performance when COM_REGMAP is defined, and comparable
when it is not defined.

Approved by core@. Fixes PR port-evbmips/32362.

branches: 1.10.4; 1.10.8; 1.10.16;
merge ktrace-lwp.

branches: 1.9.16;
__KERNEL_RCSID()

branches: 1.8.6;
Use indirect configuration for on-board devices (i.e. those things
attached to "obio") on the IQ80310 and IQ80321. It makes more sense
to do it this way for this type of system (the goal being to encapsulate
as much information about the board as possible into one file).

Use CFATTACH_DECL().

Declare all cfattach structures const.

Rather than referencing the cfdriver directly in the cfdata entries,
instead use a string naming the driver. The cfdriver is then looked
up in a list which is built at run-time.

branches: 1.4.6;
* Add a new hwflag, COM_HW_NO_TXPRELOAD, which tells comstart() to
not pre-load the chip's Tx buffer, but instead waits for the Tx Ready
interrupt to transmit the first chunk of data.
* On the IOP310, set COM_HW_NO_TXPRELOAD, rather than COM_HW_TXFIFO_DISABLE.

This solves the "UART hangs" problem on the Npwr in a nicer way (i.e. we
get to use the FIFO, whee). The COM_HW_NO_TXPRELOAD happens to match the
Linux 16550 driver's Tx algorithm, and the "UART hang" was never observed
on the Npwr running Linux.

Eventually, we might want to eliminate the COM_HW_NO_TXPRELOAD, and simply
always use its algorithm. But it should be tested on more 16x50 variants
before we do that.

Kudos to Valeriy Ushakov <uwe@netbsd.org> for pointing out this solution
(which also happens to fix the stray UART interrupt issue on the Krups
Javastation), and to Allen Briggs <briggs@netbsd.org> for experimenting
with various methods of fixing this.

Disable TXFIFO on npwr. There is some sort of serial interrupt lossage that
seems to be greatly alleviated by this change.

branches: 1.2.2;
Rework and fleshing out of Intel IQ80310 XScale eval board support.
More work to do -- this is a snapshot of work-in-progress.

branches: 1.1.4;
com (16550) attachment for iq80310

New interrupt framework for NetBSD/evbarm, and accompanying new
interrupt code for the IQ80310 board support package.

XXX The Integrator board support package still uses the old-style
arm32 interrupt code, so some compatibility hacks have been added
for it. When the Integrator uses new-style interrupts, those hacks
can go away.

branches: 1.2.2; 1.2.4;
* Share a common vector page between arm26 and arm32.
* Use a common set of exception handlers for all arm32 platforms.
* New FIQ framework based on discussions with Ben Harris, shared
between arm26 and arm32.

Move interrupt-related stuff out of the generic 32-bit ARM genassym.cf
and into platform-specific genassym.cf files.

struct device * -> device_t change.
Not tested though.

defer evcnt attachment correctly.

branches: 1.14.2; 1.14.8; 1.14.12;
#include <sys/bus.h> instead of <machine/bus.h>.

merge ktrace-lwp.

s/the the/the/ (only in sources that aren't regularly imported from
elsewhere).

__KERNEL_RCSID()

branches: 1.10.6;
Fix script-o.

Use CFATTACH_DECL().

Declare all cfattach structures const.

remove trailing \n in panic(). approved perry.

Rather than referencing the cfdriver directly in the cfdata entries,
instead use a string naming the driver. The cfdriver is then looked
up in a list which is built at run-time.

No point in setting the ATU Subsys vendor/dev ID on boards that
can't plug into a PCI host.

Add support for the Team ASA Npwr IOP310-based server appliance.

branches: 1.3.2; 1.3.4; 1.3.6;
Add support for PCI DMA on the i80312. We currently just do
DMA via the Secondary Inbound window, for now. Will probably
need to revisit this at some point.

Require that the board-specific i80312 front-end slice off a
subregion for the memory controller before calling i80312_attach(),
and fix a bug in the IQ80310 front-end that caused the Secondary
Inbound window to be configured incorrectly.

PCI interrupt mapping support for the IQ80310.

IQ80310-specific setup for the i80312 Companion I/O chip driver.

#include <sys/bus.h> instead of <machine/bus.h>.

merge ktrace-lwp.

__KERNEL_RCSID()

branches: 1.7.2;
Move the 7-segment display definitions into the C file.

* Add the ability to display .'s on the 7seg display.
* Display . . when halted.

Some prototype cleanup.

branches: 1.4.2;
Make the snake slither in a slightly more interesting pattern that
also happens to have 8 positions (and thus has a slightly more efficient
implementation).

Implement a "snake" for the 7-segment display.

branches: 1.2.2; 1.2.4;
We were already cheating w/ CPLD register access, so cheat all the
way and use pointer derefs rather than bus_space to access them.

Rework and fleshing out of Intel IQ80310 XScale eval board support.
More work to do -- this is a snapshot of work-in-progress.

malloc(9) -> kmem(9)

branches: 1.35.8;
in many device attach paths, allocate memory with M_WAITOK instead of M_NOWAIT
and remove code to handle failures that can no longer happen.

branches: 1.34.30;
kill sprintf.

Unused variable police

branches: 1.32.2;
defer evcnt attachment correctly.

branches: 1.31.2;
move evcnt_attach_dynamic() calls later to avoid assertions.

Remove irqframe and replace with identical trapframe.

branches: 1.29.2; 1.29.8;
#include <sys/bus.h> instead of <machine/bus.h>.

Correct __HAVE_FAST_SOFTINTRS typos, use only __HAVE_FAST_SOFTINTS.

branches: 1.27.2; 1.27.4;
Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits. Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

branches: 1.26.22;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.25.6; 1.25.8; 1.25.10;
Cleanup softint lossage.

branches: 1.24.24; 1.24.28; 1.24.34; 1.24.42;
s/heirarchy/hierarchy/, from Zafer.

branches: 1.23.20; 1.23.22;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

Follow up the type change of i80200_extirq_dispatch which now takes
an irqframe* and not a clockframe* as argument.

branches: 1.20.16;
__KERNEL_RCSID()

branches: 1.19.2;
Rename IPL_IMP -> IPL_VM.

Clean up some bad interaction between the spl inlining stuff and
strict-prototypes.

Add a new option EVBARM_BOARDTYPE to differentiate between different
evbarm ports. Inline _splraise/_spllower/splx for i80321 and iq80310
for more performance.

Don't need to frob CPSR in _splraise().

Implement pmc(9) -- An interface to hardware performance monitoring
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.

#if 0 the stray interrupt messages -- we tend to get them "a lot"
during normal activity on some IOP310-based designs.

Report stray interrupts.

branches: 1.12.2; 1.12.4;
Fix typo in last (luckily, search/replace makes the same typo everywhere).

iq80310_do_pending -> iq80310_do_soft, to accurately describe what's
actually going on there.

Processing pending interrupts before reenabling external interrupts in splx().

branches: 1.9.4;
* The Npwr only has 5 interrupt sources, all in XINT3, so don't bother
reading XINT0 (which isn't even implemented by the CPLD on Npwr).
* Adjust the mask of valid IRQ bits for the Npwr.

New interrupt framework for NetBSD/evbarm, and accompanying new
interrupt code for the IQ80310 board support package.

XXX The Integrator board support package still uses the old-style
arm32 interrupt code, so some compatibility hacks have been added
for it. When the Integrator uses new-style interrupts, those hacks
can go away.

Some prototype cleanup.

branches: 1.6.2;
- Don't enable FIQs; nothing uses them (yet).
- Steer i80200 PMU and BCU interrupts to IRQ# (for lack of a better
place, at the moment).
- Disable all interrupts other than external-IRQ# in the i80200 ICU;
we don't deal with any of the others, yet.

Use <arm/cpufunc.h>, not <machine/cpufunc.h>.

branches: 1.4.2; 1.4.4;
When we read the interrupt status bits, mask it with the shadow copy
of the "currently enabled interrupts" -- the CPLD appears to light
up the status bit even if it doesn't cause the CPU IRQ line to be
asserted.

We were already cheating w/ CPLD register access, so cheat all the
way and use pointer derefs rather than bus_space to access them.

* Pass the IRQ number to stray_irqhandler() and display it in
the panic message.
* Mask off undefined bits from the XINT3 and XINT0 registers in the CPLD.

Rework and fleshing out of Intel IQ80310 XScale eval board support.
More work to do -- this is a snapshot of work-in-progress.

Unused variable police

branches: 1.8.12; 1.8.22; 1.8.26;
Also include <arm/cpu.h> here for the required definitions of
curcpl() and set_curcpl(), so that kern_ssp.c builds here as well.

branches: 1.7.8; 1.7.10; 1.7.14;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.6.6; 1.6.8; 1.6.10;
Cleanup softint lossage.

branches: 1.5.46; 1.5.50; 1.5.56; 1.5.64;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.3.16;
Copy code from iq80321 / ixp425:
Use __insn_barrier() to prevent the compiler reordering splx/splraise
relative to the code they're supposed to protect.

branches: 1.2.6;
Clean up some bad interaction between the spl inlining stuff and
strict-prototypes.

branches: 1.1.2; 1.1.4; 1.1.6;
Add a new option EVBARM_BOARDTYPE to differentiate between different
evbarm ports. Inline _splraise/_spllower/splx for i80321 and iq80310
for more performance.

New interrupt framework for NetBSD/evbarm, and accompanying new
interrupt code for the IQ80310 board support package.

XXX The Integrator board support package still uses the old-style
arm32 interrupt code, so some compatibility hacks have been added
for it. When the Integrator uses new-style interrupts, those hacks
can go away.

branches: 1.3.2;
When processing ASTs:
- Loop until astpending is clear upon return from ast().
- Clear astpending *before* re-enabling interrupts.

branches: 1.2.2; 1.2.4;
* Pass the IRQ number to stray_irqhandler() and display it in
the panic message.
* Mask off undefined bits from the XINT3 and XINT0 registers in the CPLD.

Rework and fleshing out of Intel IQ80310 XScale eval board support.
More work to do -- this is a snapshot of work-in-progress.

Fix format specifier for physmem from %d to 0x%"PRIxPSIZE" in multiple places.

Should fix VERBOSE_INIT_ARM for various evbarm kernel configs.
Also add 0x prefix in few previously fixed places to improve readability.

Fix non-DIAGNOSTIC builds

Provide a shared pmap_devmap implementation and convert all pmap_devmap
arrays to use DEVMAP_ENTRY{,_END}

branches: 1.94.4;
fix multiplei repetitive typos in comments, messages and documentation. mainly because copy paste code big amount of files are affected.

PMAP_DEBUG has been deleted on arm

Trailing whitespace

branches: 1.91.8;
Consistently use vaddr_t as initarm and friends return type.

Makes no difference to binaries except for aarch64 where it's required

- Almost all ppbreg.h's definitions are also in pcireg.h. Remove duplicated
definitions from ppbreg.h and move some definitions from ppbreg.h to
pcireg.h.
- Change fast back-to-back "capable" to "enable" in pci_subr.c.
- Print Primary Discard Timer, Secondary Discard Timer, Discard Timer Status
and Discard Timer SERR# Enable bit in pci_subr.c.
- PCI_BRIDGE_PREFETCHBASE32_REG and PCI_BRIDGE_PREFETCHLIMIT32_REG are
"upper" 32bit registers, rename to *UP32_REG to avoid confusion.
- Use macro.

Fix a commit

Centralise defparam CONSADDR, CONSPEED, CONMODE and CONADDR into
opt_console.h and adjust.

Sprinkle #include "opt_arm_debug.h" where VERBOSE_INIT_ARM is used

branches: 1.86.14; 1.86.16;
switch all ports to use uvm_init.c:uvm_md_init()

uvm_setpagesize() is now subsumed within this funciton.

branches: 1.85.2; 1.85.4;
Replace more vm_offset_t, vm_size_t with vaddr_t, vsize_t
Use paddr_t for msgbufphys

<arm/locore.h> fallout (fixes some include ordering errors)

branches: 1.83.2;
Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.

branches: 1.82.2;
Move the standard definitions of the {UND,IRQ,FIQ,ABT}_STACK_SIZE to
<arm32/machdep.h>
Move the extern for cpu_reset_address to the same file.
Add cpu_reset_address_paddr.
Kill cpu_reset_v4_MMU_disable.
if cpu_reset_address is NULL, then the MMU will be disabled.

Fix more -fno-common fallout.
Move more variables to common locations.

branches: 1.80.2;
#include <sys/bus.h> instead of <machine/bus.h>.

dependant -> dependent

Use cpu_* prefix to call cpu_* functions (setttb() -> cpu_setttb()); no
functional changes.

Garbage collect an unused global, vm_offset_t pagetables_start.

- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

Kill proc0paddr. Use lwp0.l_addr instead.

Remove all declarations of physmem from sys/arch. Add an include of
<sys/systm.h> to the one file that did not already contain it.
This now means that physmem can be changed by updating systm.h and uvm_page.c
(excluding fixing printfs)

As discussed on tech-kern: mutex_init is too heavyweight for early bootstrap
phases, so move the initialization of the ksyms mutex back into main via
a function called ksyms_init. Rename the existing (but quite different)
ksyms_init* variations into ksyms_addsyms_elf() and ksyms_addsyms_explicit()
and adapt machdep code accordingly.

Remove LKMs and switch to the module framework, pass 1.

Proposed on tech-kern@.

It is not appropriate to call pmf_system_shutdown(9) from
doshutdownhooks(9): shutdown hooks registered by shutdownhook_establish(9)
expect to be called with interrupts disabled, but shutdown hooks
registered with pmf_device_register1(9) expect to be called with
interrupts enabled. So I have made two changes:

1 Do not call pmf_system_shutdown() from doshutdownhooks(). Instead,
change every call to doshutdownhooks() to a call to doshutdownhooks()
followed by a call to pmf_system_shutdown(). No functional change
is intended by this change.

2 Make i386 re-enable interrupts briefly while it calls
pmf_system_shutdown(). I leave it to others either to fix the
other ports, or to factor out some MI shutdown code, as joerg@
suggests, and fix that. Note that a functional change *is* intended
by this change.

I hope that this patch will stop us from flip-flopping between
calling doshutdownhooks() and pmf_system_shutdown() sometimes with
and sometimes without interrupts enabled.

branches: 1.70.6; 1.70.8;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.69.6; 1.69.8; 1.69.10;
Remove arm support for IPKDB.

It hasn't worked since arm was broken out from arm32 in Jan 2001, and
no-one has noticed or cared to fix it.

branches: 1.68.24; 1.68.28; 1.68.34; 1.68.42;
s/independant/independent/, from Zafer.

branches: 1.67.8; 1.67.10;
in initarm(), initialise kernel_l1pt.pv_va as well as kernel_l1pt.pv_pa.

branches: 1.66.4; 1.66.6; 1.66.8; 1.66.12;
merge ktrace-lwp.

branches: 1.65.10;
Fix comments regarding configration bounaries

Fix comments slighly

Uppercase CPU, plural is CPUs.

Bump initial kernel PTs to 4.

__KERNEL_RCSID()

branches: 1.60.2;
Use the new pmap_devmap facility in the on-board device mapping code.

Replace the ad-hoc "section mapping table" for static device mappings
with a more generic "devmap" structure that can also handle mappings
made with large and small pages. Add new pmap routines to enter these
mappings during bootstrap (and "remember" the devmap), and routines to
look up the static mappings once the kernel is running.

Also pass a type argument to comcnattach() and com_kgdb_attach().
comspeed() (and thus cominit()) may need this information.

Move KERNEL_VM_SIZE into the C files where its used.

Move KERNEL_VM_BASE inside where it is used (it won't be there for long).

Decrease the verbosity level unless VERBOSE_INIT_ARM is defiend.

Don't expose KERNEL_TEXT_BASE outside of board-specific code. This gives
individual board start-up code more flexibility about where the kernel
starts in the kernel address space.

Reduce differences between ARM32_NEW_VM_LAYOUT and not; always pass
the start and end of the kernel managed virtual address space to
pmap_bootstrap() in the new pmap.

Remove old pmap support for platforms which have fully switched over.

Eliminate PTE_BASE and the PT-PT completely in the ARM32_PMAP_NEW case.
Also in the ARM32_PMAP_NEW case, reclaim the USPACE-bytes of wasted space
at the top of the user address that hasn't been needed for a very very
long time.

Call ksyms_init() instead of ddb_init() in case of
NKSYMS || defined(DDB) || defined(LKM)

Use high vectors on IQ80321 and IQ80310.

Adapt to ARM32_PMAP_NEW.

Use PAGE_SIZE rather than NBPG.

Merge the nathanw_sa branch.

remove trailing \n in panic(). approved perry.

Enable caching on kernel and user page tables. This saves having
to do uncached memory access during VM operations (which can be
quite expensive on some CPUs).

We currently write-back PTEs as soon as they're modified; there is
some room for optimization (to write them back in larger chunks).
For PTEs in the APTE space (i.e. PTEs for pmaps that describe another
process's address space), PTEs must also be evicted from the cache
complete (PTEs in PTE space will be evicted durint a context switch).

Do cached memory access to L1 tables, making sure to write-back the
cache after any L1 table modifications.

Move the calls to uvm_page_physload() out of pmap_bootstrap() and
into platform-specific initialization code, giving platform-specific
code control over which free list a given chunk of memory gets put
onto.

Changes are essentially mechanical. Test compiled for all ARM
platforms, test booted on Intel IQ80321 and Shark.

Discussed some time ago on port-arm.

Move the uvm_setpagesize() call to platform-dependent code in preparation
for other changes to pmap_bootstrap().

branches: 1.40.2; 1.40.4;
* Add the ability to display .'s on the 7seg display.
* Display . . when halted.

Remove exception for CONSPEED on NPWR -- current redboot uses 115200, too.

* Move the code that cleans the XScale mini-data cache into its
own function.
* Add a new function which sets up the mini-data cache clean area
properly.

* Rewrite the 32-bit ARM pte.h based on the ARM architecture manual.
Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h. While
doing this, two bugs (as a result of typos) were fixed in

arm/arm32/bus_dma.c
evbarm/integrator/int_bus_dma.c

Clean up handling of the vector page on 32-bit ARM systems:
* Don't refer to VA 0, instead refer to a new variable: vector_page
* Delete the old zero_page_*() functions, replacing them with a new
one: vector_page_setprot().
* When manipulating vector page mappings in user pmaps, only do so if
the vector page is below KERNEL_BASE (if it's above KERNEL_BASE, the
vector page is mapped by the kernel pmap).
* Add a new function, arm32_vector_init(), which takes the virtual
address of the vector page (which MUST be valid when the function
is called) and a bitmask of vectors the kernel is going to take
over, and performs all vector page initialization, including setting
the V bit in the CPU Control register ("relocate vectors to high
address"), if necessary.

* Fix use of pmap_curmaxkvaddr.
* Use the PTP hint in the pmap.

* Rename PROCESS_PAGE_TBLS_BASE -> PTE_BASE
* Rename ALT_PAGE_TBLS_BASE -> APTE_BASE
* Garbage-collect PAGE_TABLE_SPACE_START

* Add support for running the IQ80310 kernel where KERNEL_BASE !=
physical memory start. Garbage-collect some cruft while here.
* Move the kernel up to 0xc0000000, giving a 1G/3G kernel/user split.
* Adjust the Integrator startup code accordingly.

Implement pmap_growkernel for arm32 based ports.
Note that this has been compiled on some systems, cats, IQ80310, IPAQ, netwinder and shark (note that shark's build is currently broken due to other reasons), but only actually run on cats.
Shark doesn't make use of the functionality as I believe there has to be a correlation between OFW and the kernel tables so that calls into OFW work.

Add some nops after we enable the MMU, for good measure (enough for
the nops to be the prefetch'd insns when the MMU switch occurs).

Make sure the MMU is enabled after we switch to the new kernel
page tables (gzboot disables the MMU before it does its work).

Fix the "va" argument to pmap_map_entry() when mapping kernel_ptpt.
This happened to work in the IOP310 because the kernel runs VA==PA.

Change pmap_map_entry() to work like pmap_map_chunk(): take a pointer
to the L1 table and a virtual address, and no pointer to the L2 table.
The L2 table will be looked up by pmap_map_entry(), which will panic
if the there is no L2 table for the requested VA.

NOTE: IT IS EXTREMELY IMPORTANT THAT THE CORRECT VIRTUAL ADDRESS
BE PROVIDED TO pmap_map_entry()! Notably, the code that mapped
the kernel L2 tables into the kernel PT mapping L2 table were not
passing actual virtual addresses, but rather offsets into the range
mapped by the L2 table. I have fixed up all of these call sites,
and tested the resulting kernel on both an IQ80310 and a Shark.
Other portmasters should examine their pmap_map_entry() calls if
their new kernels fail.

Keep track of which kernel PTs are available during bootstrap,
and let pmap_map_chunk() lookup the correct one to use for the
current VA. Eliminate the "l2table" argument to pmap_map_chunk().

Add a second L2 table for mapping kernel text/data/bss on the
IQ80310 (fixes booting kernels with ramdisks).

Always pass the L1 table to pmap_map_chunk(). This allows pmap_map_chunk()
to perform some error checking.

map_chunk() -> pmap_map_chunk(), and move it to pmap.c

Fix typo in comment.

map_pagetable() -> pmap_link_l2pt(), and move it to pmap.c

Collapse map_entry{,ro,nc}() into a single pmap_map_entry() that
takes a prot and a "cacheable" indicator.

Rename map_section() to pmap_map_section(), move it to pmap.c, and give it
an extra argument (prot - specifies protection of the mapping).

branches: 1.20.2;
Default the console to the correct speed on the Npwr (so that
it doesn't have to be set in the kernel config file).

Don't hard-code the console address in error messages.

irq_init() -> iq80310_intr_init()

Overhaul of the ARM cache code. This is mostly a simplification
pass. Rather than providing a whole slew of cache operations that
aren't ever used, distill them down to some useful primitives:

icache_sync_all Synchronize I-cache
icache_sync_range Synchronize I-cache range

dcache_wbinv_all Write-back and Invalidate D-cache
dcache_wbinv_range Write-back and Invalidate D-cache range
dcache_inv_range Invalidate D-cache range
dcache_wb_range Write-back D-cache range

idcache_wbinv_all Write-back and Invalidate D-cache,
Invalidate I-cache
idcache_wbinv_range Write-back and Invalidate D-cache,
Invalidate I-cache range

Note: This does not yet include an overhaul of the actual asm files
that implement the primitives. Instead, we've provided a safe default
for each CPU type, and the individual CPU types can now be optimized
one at a time.

Some prototype cleanup.

Allow the console unit to be overridden with the CONUNIT configuration
option.

When mapping the kernel text/data/bss:
* Round the text size up the next page, don't truncate it.
* Pass the kernel L1 table to map_chunk() so that it can try
to use section mappings.

If we're attaching UART2, then use UART2 in failure-case panic()s.

Update copyright notice.

Don't need to include <machine/irqhandler.h>

Use <arm/undefined.h> instead of <machine/undefined.h>.

No need to pull in <machine/pte.h> directly.

branches: 1.8.2;
Allocate the appropriate space for the XScale global cache clean code.

Add some rudimentary support for ELF symbols in DDB on the ARM ports.
On platforms which load the kernel sans symbols directly from firmware
(possibly in e.g. S-Record format), call ddb_init() with empty arguments,
so that it will search any compiled in SYMTAB_SPACE. On all other platforms,
if __ELF__, also call ddb_init() with empty arguments until ELF bootloaders
which pass symbol information are ready.

Remove unneeded declarations of the db_machine_init() function. The
ARM ports are the only ones that actually have one, and it is about
to change.

Remove unnecessary prototypes for zero_page_read{only,write}().

Correct a comment.

* Define fixed virtual addresses for the Primary and Secondary
PCI I/O spaces, as well as the i80312 PMMRs. Map these regions
in early bootstrap along with the on-board device address space.
* Adjust call to i80312_sdram_bounds() for the new way the PMMRs
are defined in i80312reg.h
* Word around some serious braindamage in RedBoot -- RedBoot uses
the on-board Ethernet to TFTP the kernel image. However, it does
not stop the Ethernet before transferring control to the loaded
program. This means that if it happens to receive another packet
(broadcast/multicast/unicast), it will happily scribble over the
memory of the new running program. Work around this problem by
performing a secondary-bus-reset on the i80312's PPB. XXX This
could be problematic if we ever encounter an application where
the i80312's PPB is actually used as a passthrough PPB.

Rework and fleshing out of Intel IQ80310 XScale eval board support.
More work to do -- this is a snapshot of work-in-progress.

branches: 1.1.4;
more evbarm files (very incomplete).

- Almost all ppbreg.h's definitions are also in pcireg.h. Remove duplicated
definitions from ppbreg.h and move some definitions from ppbreg.h to
pcireg.h.
- Change fast back-to-back "capable" to "enable" in pci_subr.c.
- Print Primary Discard Timer, Secondary Discard Timer, Discard Timer Status
and Discard Timer SERR# Enable bit in pci_subr.c.
- PCI_BRIDGE_PREFETCHBASE32_REG and PCI_BRIDGE_PREFETCHLIMIT32_REG are
"upper" 32bit registers, rename to *UP32_REG to avoid confusion.
- Use macro.

Add intr_establish_xname support to arm and expose it to intrctl

Fix printf format strings - pci_intr_handle_t is uint64_t now on arm

branches: 1.13.28; 1.13.30;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

kill sprintf.

branches: 1.11.2; 1.11.12; 1.11.16;
#include <sys/bus.h> instead of <machine/bus.h>.

Neither pci_dma64_available(), pci_probe_device(), pci_mapreg_map(9),
pci_find_rom(), pci_intr_map(9), pci_enumerate_bus(), nor the match
predicate passed to pciide_compat_intr_establish() should ever modify
their pci_attach_args argument, so make their pci_attach_args arguments
const and deal with the fallout throughout the kernel.

For the most part, these changes add a 'const' where there was no
'const' before, however, some drivers and MD code used to modify
pci_attach_args. Now those drivers either copy their pci_attach_args
and modify the copy, or refrain from modifying pci_attach_args:

Xen: according to Manuel Bouyer, writing to pci_attach_args in
pci_intr_map() was a leftover from Xen 2. Probably a bug. I
stopped writing it. I have not tested this change.

siside(4): sis_hostbr_match() needlessly wrote to pci_attach_args.
Probably a bug. I use a temporary variable. I have not tested this
change.

slide(4): sl82c105_chip_map() overwrote the caller's pci_attach_args.
Probably a bug. Use a local pci_attach_args. I have not tested
this change.

viaide(4): via_sata_chip_map() and via_sata_chip_map_new() overwrote the
caller's pci_attach_args. Probably a bug. Make a local copy of the
caller's pci_attach_args and modify the copy. I have not tested
this change.

While I'm here, make pci_mapreg_submap() static.

With these changes in place, I have tested the compilation of these
kernels:

alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-eb NSLU2
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE GUMSTIX
HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321 IXDP425 IXM1200
KUROBOX_PRO LUBBOCK MARVELL_NAS NAPPI SHEEVAPLUG SMDK2800 TEAMASA_NPWR
TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sgimips GENERIC32_IP2x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

As of Sun Apr 3 15:26:26 CDT 2011, I could not compile these kernels
with or without my patches in place:

### evbmips-el GDIUM

nbmake: nbmake: don't know how to make /home/dyoung/pristine-nbsd/src/sys/arch/mips/mips/softintr.c. Stop

### evbarm-el MPCSA_GENERIC
src/sys/arch/evbarm/conf/MPCSA_GENERIC:318: ds1672rtc*: unknown device `ds1672rtc'

### ia64 GENERIC

/tmp/genassym.28085/assym.c: In function 'f111':
/tmp/genassym.28085/assym.c:67: error: invalid application of 'sizeof' to incomplete type 'struct pcb'
/tmp/genassym.28085/assym.c:76: error: dereferencing pointer to incomplete type

### sgimips GENERIC32_IP3x

crmfb.o: In function `crmfb_attach':
crmfb.c:(.text+0x2304): undefined reference to `ddc_read_edid'
crmfb.c:(.text+0x2304): relocation truncated to fit: R_MIPS_26 against `ddc_read_edid'
crmfb.c:(.text+0x234c): undefined reference to `edid_parse'
crmfb.c:(.text+0x234c): relocation truncated to fit: R_MIPS_26 against `edid_parse'
crmfb.c:(.text+0x2354): undefined reference to `edid_print'
crmfb.c:(.text+0x2354): relocation truncated to fit: R_MIPS_26 against `edid_print'

branches: 1.9.100; 1.9.106;
merge ktrace-lwp.

__KERNEL_RCSID()

branches: 1.7.16;
Wire the internal devices to the right interrupts on NPWR.

Let this compile with the IOP310_TEAMASA_NPWR option.

Add support for the Team ASA Npwr IOP310-based server appliance.

New interrupt framework for NetBSD/evbarm, and accompanying new
interrupt code for the IQ80310 board support package.

XXX The Integrator board support package still uses the old-style
arm32 interrupt code, so some compatibility hacks have been added
for it. When the Integrator uses new-style interrupts, those hacks
can go away.

s/CPLD/iq80310/g

branches: 1.2.2; 1.2.4; 1.2.6;
Fix typos in determing the ATU and PPB bus numbers.

PCI interrupt mapping support for the IQ80310.

Add RCSID when needed.
Don't include pmap.h or pte.h, include "assym.h" instead.
Use assym.h provided values.

branches: 1.4.134; 1.4.140; 1.4.142;
Continue the " - . - 8" purge. Specifically:

add rd, pc, #foo - . - 8 -> adr rd, foo
ldr rd, [pc, #foo - . - 8] -> ldr rd, foo

Also, when saving the return address for a function pointer call, use
"mov lr, pc" just before the call unless the return address is somewhere
other than just after the call site.

Finally, a few obvious little micro-optimisations like using LDR directly
rather than ADR followed by LDR, and loading directly into PC rather than
bouncing via R0.

Issue a CPWAIT sequence after enabling the MMU to make sure
it's really enabled.

* Rewrite the 32-bit ARM pte.h based on the ARM architecture manual.
Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h. While
doing this, two bugs (as a result of typos) were fixed in

arm/arm32/bus_dma.c
evbarm/integrator/int_bus_dma.c

branches: 1.1.4; 1.1.8;
* Add support for running the IQ80310 kernel where KERNEL_BASE !=
physical memory start. Garbage-collect some cruft while here.
* Move the kernel up to 0xc0000000, giving a 1G/3G kernel/user split.
* Adjust the Integrator startup code accordingly.

fix typos in comments, mainly s/harware/hardware/.

branches: 1.23.26;
For struct timecounter, use C99 initializers.
Compile tested. No functional changes intended.

#include <sys/bus.h> instead of <machine/bus.h>.

Convert evbarm to timecounter. Only one of the systems was tested, the
rest of the patch is compile-time tested only.

branches: 1.20.18; 1.20.22; 1.20.28; 1.20.34;
Convert evbarm to __HAVE_GENERIC_TODR.

branches: 1.19.24; 1.19.26;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.17.2;
Rename an (unused) argument to appease -Wshadow.

Fix the various todr_gettime() and todr_settime() fallouts from
-Wcast-qual differently, by instead changing the signatore of those
"functions" to take a "volatile struct timeval*" instead of a
"struct timeval*". Many places, these functions are called with
&time, and time is declared as volatile in <sys/kernel.h>. This
way we can get rid of all the ugly casts which now also triggered
warnings, and caused more code to be added to work around the
problem.

Reviewed by thorpej.

Watch out for those unexpected tains.

branches: 1.14.8; 1.14.10;
Fix think'o in last. Pointed out by Izumi Tsutsui.

Flesh out inittodr() and resettodr().

__KERNEL_RCSID()

branches: 1.11.10;
* Delcare COUNTER_MASK properly.
* Restructure timer_read() so that the compiler generates better code.

Gah, correct editor mistake in last.

* Eliminate some redundant masking.
* Don't run the snake if the board doesn't have a 7-segment display.

inittodr(): Actually initialize time from the file system time.

The Npwr has a 19-bit timer. Make sure values programmed into
the counter fit.

branches: 1.6.2;
Implement a "snake" for the 7-segment display.

Fix brain'o in handling of schedhz and profhz. Also, make sure to
compute tickfix after computing tick (not that tickfix should ever
be non-zero, but there for completeness).

Use <arm/cpufunc.h>, not <machine/cpufunc.h>.

branches: 1.3.2; 1.3.4;
Fix delay().

We were already cheating w/ CPLD register access, so cheat all the
way and use pointer derefs rather than bus_space to access them.

Rework and fleshing out of Intel IQ80310 XScale eval board support.
More work to do -- this is a snapshot of work-in-progress.

branches: 1.2.2;
Rework and fleshing out of Intel IQ80310 XScale eval board support.
More work to do -- this is a snapshot of work-in-progress.

branches: 1.1.4;
more evbarm files (very incomplete).

Fix regisers typo

branches: 1.6.122; 1.6.142; 1.6.146;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

branches: 1.5.18;
Move the 7-segment display definitions into the C file.

branches: 1.4.2;
Remove U from the display seg constants.

branches: 1.3.2; 1.3.4;
* Define fixed virtual addresses for the Primary and Secondary
PCI I/O spaces, as well as the i80312 PMMRs. Map these regions
in early bootstrap along with the on-board device address space.
* Adjust call to i80312_sdram_bounds() for the new way the PMMRs
are defined in i80312reg.h
* Word around some serious braindamage in RedBoot -- RedBoot uses
the on-board Ethernet to TFTP the kernel image. However, it does
not stop the Ethernet before transferring control to the loaded
program. This means that if it happens to receive another packet
(broadcast/multicast/unicast), it will happily scribble over the
memory of the new running program. Work around this problem by
performing a secondary-bus-reset on the i80312's PPB. XXX This
could be problematic if we ever encounter an application where
the i80312's PPB is actually used as a passthrough PPB.

We were already cheating w/ CPLD register access, so cheat all the
way and use pointer derefs rather than bus_space to access them.

Rework and fleshing out of Intel IQ80310 XScale eval board support.
More work to do -- this is a snapshot of work-in-progress.

defer evcnt attachment correctly.

branches: 1.7.146; 1.7.152; 1.7.156;
Fix a typo.

Add macros to convert an "IRQ" number to its respective XINT3/XINT0 bit.

Add support for the Team ASA Npwr IOP310-based server appliance.

New interrupt framework for NetBSD/evbarm, and accompanying new
interrupt code for the IQ80310 board support package.

XXX The Integrator board support package still uses the old-style
arm32 interrupt code, so some compatibility hacks have been added
for it. When the Integrator uses new-style interrupts, those hacks
can go away.

branches: 1.3.2;
Implement a "snake" for the 7-segment display.

branches: 1.2.2; 1.2.4;
PCI interrupt mapping support for the IQ80310.

Rework and fleshing out of Intel IQ80310 XScale eval board support.
More work to do -- this is a snapshot of work-in-progress.

Merge thorpej-cfargs2.

branches: 1.21.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.20.68;
#include <sys/bus.h> instead of <machine/bus.h>.

Some more device_t, cfdata_t, CFATTACH_DECL_NEW cleanup.

branches: 1.18.100; 1.18.110;
merge ktrace-lwp.

s/locdesc_t/int/g

branches: 1.16.2;
adaptions to config_search() change, and minor autoconf fixes, mostly from Havard Eidnes

__KERNEL_RCSID()

branches: 1.14.2;
Give every obio implementation a size and width locator.

Add an optional "width" locator to the obio bus, specifying the
bus width of the device.

Use aprint_normal() for cfprint routines.

Use indirect configuration for on-board devices (i.e. those things
attached to "obio") on the IQ80310 and IQ80321. It makes more sense
to do it this way for this type of system (the goal being to encapsulate
as much information about the board as possible into one file).

Use CFATTACH_DECL().

Declare all cfattach structures const.

Introduce a new routine, config_match(), which invokes the
cfattach->ca_match function in behalf of the caller. Use it
rather than invoking cfattach->ca_match directly.

Rather than referencing the cfdriver directly in the cfdata entries,
instead use a string naming the driver. The cfdriver is then looked
up in a list which is built at run-time.

The Npwr doesn't have the board_rev/cpld_rev/backplane_det registers,
do don't bother reading them.

finish conversion from TEAMASA_NPWR to IOP310_TEAMASA_NPWR

Add support for the Team ASA Npwr IOP310-based server appliance.

branches: 1.3.2;
Reorder the device table to make the UART at J9 attach before the
UART at J10 (this is the same ordering the RedBoot uses, and also
is intuitive).

branches: 1.2.2; 1.2.4;
We were already cheating w/ CPLD register access, so cheat all the
way and use pointer derefs rather than bus_space to access them.

Rework and fleshing out of Intel IQ80310 XScale eval board support.
More work to do -- this is a snapshot of work-in-progress.

Trailing whitespace.

use designated initializer to make adaptability and flexibility for changing struct bus_space.
no functional change.

branches: 1.15.28;
Don't manipulate the pte to get uncached memory, use PMAP_NOCACHE instead.
Convert footbring to kenter_pa/kremove

branches: 1.14.2; 1.14.12; 1.14.16;
#include <sys/bus.h> instead of <machine/bus.h>.

Add a flags argument to pmap_kenter_pa(9).
Patch showed on tech-kern@ http://mail-index.netbsd.org/tech-kern/2009/11/04/msg006434.html
No objections.

branches: 1.12.78;
bus_dmamem_map: honour BUS_DMA_NOWAIT. noted by Manuel Bouyer.
bus_space_map: always do NOWAIT allocation as it used to be before yamt-km.

we have too many copies!

branches: 1.11.2; 1.11.8;
merge yamt-km branch.
- don't use managed mappings/backing objects for wired memory allocations.
save some resources like pv_entry. also fix (most of) PR/27030.
- simplify kernel memory management API.
- simplify pmap bootstrap of some ports.
- some related cleanups.

branches: 1.10.8; 1.10.10;
__KERNEL_RCSID()

branches: 1.9.2;
Use the new pmap_devmap facility in the on-board device mapping code.

remove trailing \n in panic(). approved perry.

* Add PTE_SYNC() and PTE_SYNC_RANGE() macros. These don't actually do
anything yet.
* Use PTE_SYNC() and PTE_SYNC_RANGE() in some obvious places, i.e.
where vtopte() is used.

branches: 1.6.2;
Use the bus_space_generic bus space ops.

* Split pte_cache_mode into pte_l1_s_cache_mode, pte_l2_l_cache_mode,
and pte_l2_s_cache_mode. The cache-meaningful bits are different
for these descriptor types on some processor models.
* Add pte_*_cache_mask, corresponding to each above, which has a mask
of the cache-meangful bits, and define those for generic and XScale
MMU classes. Note, the L2_S_CACHE_MASK_xscale definition requires
use of the Extended Small Page L2 descriptor (the "X" bit overlaps
with AP bits otherwise).

Use pte_cache_mode instead of PT_CACHEABLE;

Use vtopte() instead of pmap_pte().

Use obio_bs_rr_1.
In obio_bs_map(): Create a mapping for regions that are not in the
standard on-board I/O space.

branches: 1.1.2; 1.1.4; 1.1.6;
Rework and fleshing out of Intel IQ80310 XScale eval board support.
More work to do -- this is a snapshot of work-in-progress.

Use the bus_space_generic bus space ops.

Implement obio_bs_rr_1.

branches: 1.1.2; 1.1.4; 1.1.6;
Rework and fleshing out of Intel IQ80310 XScale eval board support.
More work to do -- this is a snapshot of work-in-progress.

Give every obio implementation a size and width locator.

Add an optional "width" locator to the obio bus, specifying the
bus width of the device.

Use indirect configuration for on-board devices (i.e. those things
attached to "obio") on the IQ80310 and IQ80321. It makes more sense
to do it this way for this type of system (the goal being to encapsulate
as much information about the board as possible into one file).

branches: 1.1.2; 1.1.4; 1.1.6;
Rework and fleshing out of Intel IQ80310 XScale eval board support.
More work to do -- this is a snapshot of work-in-progress.