Use device_setprop_data() to set the "mac-address" property.

branches: 1.3.8;
Trailing whitespace

add mechanism to pass a MAC address to dme

branches: 1.1.2;
initial support for CI20 / Ingenic JZ4780
not much there yet, it loads, attaches a serial port and you can drop into
ddb

For struct timecounter, use C99 initializers.
Compile tested. No functional changes intended.

branches: 1.10.8;
Provide and use some CP0 accessor functions instead of M[TF]C0 macros
for readability.

While here convert some other M[TF]C0 uses to already exising accessor
functions, e.g. mipsNN_cp0_ebase_read

Trailing whitespace

Adjust evbmips_iointr to pass a clockframe pointer and use it for
pwmclock @ voyager.

Suggested by matt@

Hi macallan!

first shot at SMP support, very much broken and experimental
So far the 2nd core wakes up, makes its way to the idle loop, and things lock
up when we start the timer interrupt.

don't mess with the cycle counter event counter, out timer interrupt comes
from elsewhere and is counted there

Move struct clockframe cf as extern declaration into ingenic_clockintr(),
to avoid a duplicate common.

use #ifdef USE_OST to switch between OS Timer and timer 5
always enable interrupts, not just with INGENIC_CLOCK_DEBUG

use defflag-ed debug options

add timecounter, timer interrupt and plenty of debugging goop
very much work in progress

branches: 1.1.2;
initial support for CI20 / Ingenic JZ4780
not much there yet, it loads, attaches a serial port and you can drop into
ddb

mips: Carefully use device_set_private for cpuN.

But don't do it in cpu_attach_common because the callers aren't set
up right -- instead leave a comment about what's wrong, to be dealt
with later.

branches: 1.4.8;
Provide and use some CP0 accessor functions instead of M[TF]C0 macros
for readability.

While here convert some other M[TF]C0 uses to already exising accessor
functions, e.g. mipsNN_cp0_ebase_read

Trailing whitespace

#include "opt_multiprocessor.h"

branches: 1.1.2;
first shot at SMP support, very much broken and experimental
So far the 2nd core wakes up, makes its way to the idle loop, and things lock
up when we start the timer interrupt.

mips: Add missing barriers in cpu_switchto.

Details in comments.

PR kern/57240

XXX pullup-8
XXX pullup-9
XXX pullup-10

branches: 1.1.2; 1.1.12; 1.1.18; 1.1.26; 1.1.52;
first shot at SMP support, very much broken and experimental
So far the 2nd core wakes up, makes its way to the idle loop, and things lock
up when we start the timer interrupt.

branches: 1.13.8;
Provide and use some CP0 accessor functions instead of M[TF]C0 macros
for readability.

While here convert some other M[TF]C0 uses to already exising accessor
functions, e.g. mipsNN_cp0_ebase_read

Trailing whitespace

Adjust evbmips_iointr to pass a clockframe pointer and use it for
pwmclock @ voyager.

Suggested by matt@

Hi macallan!

first shot at SMP support, very much broken and experimental
So far the 2nd core wakes up, makes its way to the idle loop, and things lock
up when we start the timer interrupt.

branches: 1.9.2;
add IPI support
compile-tested only since we don't actually spin up the 2nd core yet

PIC -> INTC to match documentation
no functional change

add an event counter for clock interrupts

count all interrupts, not just the ones we have handlers for

disable interrupts while processing them, reenable when we're done

make interrupt names part of the handler struct so event counters will show
up correctly
also reshuffle debug code a bit

use separate debugging flag for interrupts

preliminary support for the interrupt controller
didn't get much testing yet

timer interrupt and IPIs

Move the at-shutdown call to resettodr() from cpu_reboot() to kern_reboot().

It's a small step, but it's a step.

Add some compile time asserts for endianness on boards/systems that
only support a single endianness.

s/reseting/resetting/

branches: 1.14.8;
Provide and use some CP0 accessor functions instead of M[TF]C0 macros
for readability.

While here convert some other M[TF]C0 uses to already exising accessor
functions, e.g. mipsNN_cp0_ebase_read

Trailing whitespace

switch all ports to use uvm_init.c:uvm_md_init()

uvm_setpagesize() is now subsumed within this funciton.

#include "opt_multiprocessor.h"

branches: 1.10.2;
first shot at SMP support, very much broken and experimental
So far the 2nd core wakes up, makes its way to the idle loop, and things lock
up when we start the timer interrupt.

- get rid of private bus space in ingenic_com.c
- move com to apbus
- attach the other UARTs

Use cpu_startup_common()

use kcpuset_isset()

add IPI support
compile-tested only since we don't actually spin up the 2nd core yet

enable the full 1GB of RAM
TODO: actually probe for it

only use the first 256MB for now until I figure out how to properly access
the rest

use defflag-ed debug options

apbus attachment goop, move interrupt stuff to intr.c

branches: 1.1.2;
initial support for CI20 / Ingenic JZ4780
not much there yet, it loads, attaches a serial port and you can drop into
ddb

Merge thorpej-cfargs2.

branches: 1.8.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.7.8; 1.7.26;
Provide and use some CP0 accessor functions instead of M[TF]C0 macros
for readability.

While here convert some other M[TF]C0 uses to already exising accessor
functions, e.g. mipsNN_cp0_ebase_read

Trailing whitespace

first shot at SMP support, very much broken and experimental
So far the 2nd core wakes up, makes its way to the idle loop, and things lock
up when we start the timer interrupt.

add IPI support
compile-tested only since we don't actually spin up the 2nd core yet

use defflag-ed debug options

apbus attachment goop, move interrupt stuff to intr.c

branches: 1.1.2;
initial support for CI20 / Ingenic JZ4780
not much there yet, it loads, attaches a serial port and you can drop into
ddb