| History log of /src/sys/arch/evbmips/ingenic |
| Revision | Date | Author | Comments |
| 1.4 | 03-Oct-2025 |
thorpej | Use device_setprop_data() to set the "mac-address" property.
|
| 1.3 | 19-May-2017 |
skrll | branches: 1.3.8;
Trailing whitespace
|
| 1.2 | 08-Oct-2015 |
macallan | add mechanism to pass a MAC address to dme
|
| 1.1 | 22-Nov-2014 |
macallan | branches: 1.1.2;
initial support for CI20 / Ingenic JZ4780
not much there yet, it loads, attaches a serial port and you can drop into
ddb
|
| 1.1.2.2 | 28-Aug-2017 |
skrll | Sync with HEAD
|
| 1.1.2.1 | 27-Dec-2015 |
skrll | Sync with HEAD (as of 26th Dec)
|
| 1.3.8.2 | 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.3.8.1 | 19-May-2017 |
jdolecek | file autoconf.c was added on branch tls-maxphys on 2017-12-03 11:36:09 +0000
|
| 1.11 | 29-May-2020 |
rin | For struct timecounter, use C99 initializers.
Compile tested. No functional changes intended.
|
| 1.10 | 21-May-2017 |
skrll | branches: 1.10.8;
Provide and use some CP0 accessor functions instead of M[TF]C0 macros
for readability.
While here convert some other M[TF]C0 uses to already exising accessor
functions, e.g. mipsNN_cp0_ebase_read
|
| 1.9 | 19-May-2017 |
skrll | Trailing whitespace
|
| 1.8 | 26-Aug-2016 |
skrll | Adjust evbmips_iointr to pass a clockframe pointer and use it for
pwmclock @ voyager.
Suggested by matt@
Hi macallan!
|
| 1.7 | 29-Jan-2016 |
macallan | first shot at SMP support, very much broken and experimental
So far the 2nd core wakes up, makes its way to the idle loop, and things lock
up when we start the timer interrupt.
|
| 1.6 | 30-Jun-2015 |
macallan | don't mess with the cycle counter event counter, out timer interrupt comes
from elsewhere and is counted there
|
| 1.5 | 31-Dec-2014 |
martin | Move struct clockframe cf as extern declaration into ingenic_clockintr(),
to avoid a duplicate common.
|
| 1.4 | 26-Dec-2014 |
macallan | use #ifdef USE_OST to switch between OS Timer and timer 5
always enable interrupts, not just with INGENIC_CLOCK_DEBUG
|
| 1.3 | 23-Dec-2014 |
macallan | use defflag-ed debug options
|
| 1.2 | 06-Dec-2014 |
macallan | add timecounter, timer interrupt and plenty of debugging goop
very much work in progress
|
| 1.1 | 22-Nov-2014 |
macallan | branches: 1.1.2;
initial support for CI20 / Ingenic JZ4780
not much there yet, it loads, attaches a serial port and you can drop into
ddb
|
| 1.1.2.5 | 28-Aug-2017 |
skrll | Sync with HEAD
|
| 1.1.2.4 | 05-Oct-2016 |
skrll | Sync with HEAD
|
| 1.1.2.3 | 19-Mar-2016 |
skrll | Sync with HEAD
|
| 1.1.2.2 | 22-Sep-2015 |
skrll | Sync with HEAD
|
| 1.1.2.1 | 06-Apr-2015 |
skrll | Sync with HEAD
|
| 1.10.8.2 | 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.10.8.1 | 21-May-2017 |
jdolecek | file clock.c was added on branch tls-maxphys on 2017-12-03 11:36:09 +0000
|
| 1.5 | 03-Mar-2022 |
riastradh | mips: Carefully use device_set_private for cpuN.
But don't do it in cpu_attach_common because the callers aren't set
up right -- instead leave a comment about what's wrong, to be dealt
with later.
|
| 1.4 | 21-May-2017 |
skrll | branches: 1.4.8;
Provide and use some CP0 accessor functions instead of M[TF]C0 macros
for readability.
While here convert some other M[TF]C0 uses to already exising accessor
functions, e.g. mipsNN_cp0_ebase_read
|
| 1.3 | 19-May-2017 |
skrll | Trailing whitespace
|
| 1.2 | 26-Aug-2016 |
skrll | #include "opt_multiprocessor.h"
|
| 1.1 | 29-Jan-2016 |
macallan | branches: 1.1.2;
first shot at SMP support, very much broken and experimental
So far the 2nd core wakes up, makes its way to the idle loop, and things lock
up when we start the timer interrupt.
|
| 1.1.2.4 | 28-Aug-2017 |
skrll | Sync with HEAD
|
| 1.1.2.3 | 05-Oct-2016 |
skrll | Sync with HEAD
|
| 1.1.2.2 | 19-Mar-2016 |
skrll | Sync with HEAD
|
| 1.1.2.1 | 29-Jan-2016 |
skrll | file cpu.c was added on branch nick-nhusb on 2016-03-19 11:29:59 +0000
|
| 1.4.8.2 | 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.4.8.1 | 21-May-2017 |
jdolecek | file cpu.c was added on branch tls-maxphys on 2017-12-03 11:36:09 +0000
|
| 1.2 | 23-Feb-2023 |
riastradh | mips: Add missing barriers in cpu_switchto.
Details in comments.
PR kern/57240
XXX pullup-8
XXX pullup-9
XXX pullup-10
|
| 1.1 | 29-Jan-2016 |
macallan | branches: 1.1.2; 1.1.12; 1.1.18; 1.1.26; 1.1.52;
first shot at SMP support, very much broken and experimental
So far the 2nd core wakes up, makes its way to the idle loop, and things lock
up when we start the timer interrupt.
|
| 1.1.52.1 | 31-Jul-2023 |
martin | Pull up following revision(s) (requested by riastradh in ticket #264):
sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
sys/arch/aarch64/aarch64/locore.S: revision 1.91
sys/arch/mips/include/asm.h: revision 1.74
sys/arch/hppa/include/cpu.h: revision 1.13
sys/arch/arm/arm/armv6_start.S: revision 1.38
sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
sys/arch/mips/mips/locore.S: revision 1.229
sys/arch/aarch64/aarch64/cpuswitch.S: revision 1.40
sys/arch/alpha/include/asm.h: revision 1.45
sys/arch/sparc64/sparc64/locore.s: revision 1.432
sys/arch/vax/vax/subr.S: revision 1.42
sys/arch/mips/mips/locore_mips3.S: revision 1.116
sys/arch/riscv/riscv/cpu_switch.S: revision 1.3
sys/arch/ia64/ia64/machdep.c: revision 1.44
sys/arch/arm/arm32/cpuswitch.S: revision 1.106
sys/arch/sparc/sparc/locore.s: revision 1.284
aarch64: Add missing barriers in cpu_switchto.
Details in comments.
Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.
PR kern/57240
alpha: Add missing barriers in cpu_switchto.
Details in comments.
arm32: Add missing barriers in cpu_switchto.
Details in comments.
hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?
ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)
mips: Add missing barriers in cpu_switchto.
Details in comments.
powerpc: Add missing barriers in cpu_switchto.
Details in comments.
riscv: Add missing barriers in cpu_switchto.
Details in comments.
sparc: Add missing barriers in cpu_switchto.
sparc64: Add missing barriers in cpu_switchto.
Details in comments.
vax: Note where cpu_switchto needs barriers.
Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.
|
| 1.1.26.1 | 31-Jul-2023 |
martin | Pull up following revision(s) (requested by riastradh in ticket #1676):
sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
sys/arch/aarch64/aarch64/locore.S: revision 1.91
sys/arch/mips/include/asm.h: revision 1.74
sys/arch/hppa/include/cpu.h: revision 1.13
sys/arch/arm/arm/armv6_start.S: revision 1.38
sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
sys/arch/mips/mips/locore.S: revision 1.229
sys/arch/aarch64/aarch64/cpuswitch.S: revision 1.40
sys/arch/alpha/include/asm.h: revision 1.45
sys/arch/sparc64/sparc64/locore.s: revision 1.432
sys/arch/vax/vax/subr.S: revision 1.42
sys/arch/mips/mips/locore_mips3.S: revision 1.116
sys/arch/ia64/ia64/machdep.c: revision 1.44
sys/arch/arm/arm32/cpuswitch.S: revision 1.106
sys/arch/sparc/sparc/locore.s: revision 1.284
(all via patch)
aarch64: Add missing barriers in cpu_switchto.
Details in comments.
Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.
PR kern/57240
alpha: Add missing barriers in cpu_switchto.
Details in comments.
arm32: Add missing barriers in cpu_switchto.
Details in comments.
hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?
ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)
mips: Add missing barriers in cpu_switchto.
Details in comments.
powerpc: Add missing barriers in cpu_switchto.
Details in comments.
sparc: Add missing barriers in cpu_switchto.
sparc64: Add missing barriers in cpu_switchto.
Details in comments.
vax: Note where cpu_switchto needs barriers.
Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.
|
| 1.1.18.2 | 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.1.18.1 | 29-Jan-2016 |
jdolecek | file cpu_startup.S was added on branch tls-maxphys on 2017-12-03 11:36:09 +0000
|
| 1.1.12.1 | 31-Jul-2023 |
martin | Pull up following revision(s) (requested by riastradh in ticket #1859):
sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
sys/arch/aarch64/aarch64/locore.S: revision 1.91
sys/arch/mips/include/asm.h: revision 1.74
sys/arch/hppa/include/cpu.h: revision 1.13
sys/arch/arm/arm/armv6_start.S: revision 1.38
(applied also to sys/arch/arm/cortex/a9_mpsubr.S,
sys/arch/arm/cortex/a9_mpsubr.S,
sys/arch/arm/cortex/cortex_init.S)
sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
sys/arch/mips/mips/locore.S: revision 1.229
sys/arch/alpha/include/asm.h: revision 1.45
(applied to sys/arch/alpha/alpha/multiproc.s)
sys/arch/sparc64/sparc64/locore.s: revision 1.432
sys/arch/vax/vax/subr.S: revision 1.42
sys/arch/mips/mips/locore_mips3.S: revision 1.116
sys/arch/ia64/ia64/machdep.c: revision 1.44
sys/arch/arm/arm32/cpuswitch.S: revision 1.106
sys/arch/sparc/sparc/locore.s: revision 1.284
(all via patch)
aarch64: Add missing barriers in cpu_switchto.
Details in comments.
Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.
PR kern/57240
alpha: Add missing barriers in cpu_switchto.
Details in comments.
arm32: Add missing barriers in cpu_switchto.
Details in comments.
hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?
ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)
mips: Add missing barriers in cpu_switchto.
Details in comments.
powerpc: Add missing barriers in cpu_switchto.
Details in comments.
sparc: Add missing barriers in cpu_switchto.
sparc64: Add missing barriers in cpu_switchto.
Details in comments.
vax: Note where cpu_switchto needs barriers.
Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.
|
| 1.1.2.2 | 19-Mar-2016 |
skrll | Sync with HEAD
|
| 1.1.2.1 | 29-Jan-2016 |
skrll | file cpu_startup.S was added on branch nick-nhusb on 2016-03-19 11:29:59 +0000
|
| 1.13 | 21-May-2017 |
skrll | branches: 1.13.8;
Provide and use some CP0 accessor functions instead of M[TF]C0 macros
for readability.
While here convert some other M[TF]C0 uses to already exising accessor
functions, e.g. mipsNN_cp0_ebase_read
|
| 1.12 | 27-Aug-2016 |
skrll | Trailing whitespace
|
| 1.11 | 26-Aug-2016 |
skrll | Adjust evbmips_iointr to pass a clockframe pointer and use it for
pwmclock @ voyager.
Suggested by matt@
Hi macallan!
|
| 1.10 | 29-Jan-2016 |
macallan | first shot at SMP support, very much broken and experimental
So far the 2nd core wakes up, makes its way to the idle loop, and things lock
up when we start the timer interrupt.
|
| 1.9 | 04-Apr-2015 |
macallan | branches: 1.9.2;
add IPI support
compile-tested only since we don't actually spin up the 2nd core yet
|
| 1.8 | 28-Mar-2015 |
macallan | PIC -> INTC to match documentation
no functional change
|
| 1.7 | 11-Mar-2015 |
macallan | add an event counter for clock interrupts
|
| 1.6 | 07-Mar-2015 |
macallan | count all interrupts, not just the ones we have handlers for
|
| 1.5 | 05-Mar-2015 |
macallan | disable interrupts while processing them, reenable when we're done
|
| 1.4 | 26-Dec-2014 |
macallan | make interrupt names part of the handler struct so event counters will show
up correctly
also reshuffle debug code a bit
|
| 1.3 | 23-Dec-2014 |
macallan | use separate debugging flag for interrupts
|
| 1.2 | 23-Dec-2014 |
macallan | preliminary support for the interrupt controller
didn't get much testing yet
|
| 1.1 | 06-Dec-2014 |
macallan | timer interrupt and IPIs
|
| 1.9.2.5 | 28-Aug-2017 |
skrll | Sync with HEAD
|
| 1.9.2.4 | 05-Oct-2016 |
skrll | Sync with HEAD
|
| 1.9.2.3 | 19-Mar-2016 |
skrll | Sync with HEAD
|
| 1.9.2.2 | 06-Apr-2015 |
skrll | Sync with HEAD
|
| 1.9.2.1 | 04-Apr-2015 |
skrll | file intr.c was added on branch nick-nhusb on 2015-04-06 15:17:56 +0000
|
| 1.13.8.2 | 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.13.8.1 | 21-May-2017 |
jdolecek | file intr.c was added on branch tls-maxphys on 2017-12-03 11:36:09 +0000
|
| 1.17 | 05-Mar-2024 |
thorpej | Move the at-shutdown call to resettodr() from cpu_reboot() to kern_reboot().
It's a small step, but it's a step.
|
| 1.16 | 17-Aug-2020 |
simonb | Add some compile time asserts for endianness on boards/systems that
only support a single endianness.
|
| 1.15 | 22-Jul-2020 |
msaitoh | s/reseting/resetting/
|
| 1.14 | 21-May-2017 |
skrll | branches: 1.14.8;
Provide and use some CP0 accessor functions instead of M[TF]C0 macros
for readability.
While here convert some other M[TF]C0 uses to already exising accessor
functions, e.g. mipsNN_cp0_ebase_read
|
| 1.13 | 19-May-2017 |
skrll | Trailing whitespace
|
| 1.12 | 22-Dec-2016 |
cherry | switch all ports to use uvm_init.c:uvm_md_init()
uvm_setpagesize() is now subsumed within this funciton.
|
| 1.11 | 26-Aug-2016 |
skrll | #include "opt_multiprocessor.h"
|
| 1.10 | 29-Jan-2016 |
macallan | branches: 1.10.2;
first shot at SMP support, very much broken and experimental
So far the 2nd core wakes up, makes its way to the idle loop, and things lock
up when we start the timer interrupt.
|
| 1.9 | 11-Jul-2015 |
macallan | - get rid of private bus space in ingenic_com.c
- move com to apbus
- attach the other UARTs
|
| 1.8 | 30-Jun-2015 |
matt | Use cpu_startup_common()
|
| 1.7 | 11-Jun-2015 |
macallan | use kcpuset_isset()
|
| 1.6 | 04-Apr-2015 |
macallan | add IPI support
compile-tested only since we don't actually spin up the 2nd core yet
|
| 1.5 | 10-Mar-2015 |
macallan | enable the full 1GB of RAM
TODO: actually probe for it
|
| 1.4 | 07-Mar-2015 |
macallan | only use the first 256MB for now until I figure out how to properly access
the rest
|
| 1.3 | 23-Dec-2014 |
macallan | use defflag-ed debug options
|
| 1.2 | 06-Dec-2014 |
macallan | apbus attachment goop, move interrupt stuff to intr.c
|
| 1.1 | 22-Nov-2014 |
macallan | branches: 1.1.2;
initial support for CI20 / Ingenic JZ4780
not much there yet, it loads, attaches a serial port and you can drop into
ddb
|
| 1.1.2.6 | 28-Aug-2017 |
skrll | Sync with HEAD
|
| 1.1.2.5 | 05-Feb-2017 |
skrll | Sync with HEAD
|
| 1.1.2.4 | 05-Oct-2016 |
skrll | Sync with HEAD
|
| 1.1.2.3 | 19-Mar-2016 |
skrll | Sync with HEAD
|
| 1.1.2.2 | 22-Sep-2015 |
skrll | Sync with HEAD
|
| 1.1.2.1 | 06-Apr-2015 |
skrll | Sync with HEAD
|
| 1.10.2.1 | 07-Jan-2017 |
pgoyette | Sync with HEAD. (Note that most of these changes are simply $NetBSD$
tag issues.)
|
| 1.14.8.2 | 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.14.8.1 | 21-May-2017 |
jdolecek | file machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:09 +0000
|
| 1.9 | 07-Aug-2021 |
thorpej | Merge thorpej-cfargs2.
|
| 1.8 | 24-Apr-2021 |
thorpej | branches: 1.8.8;
Merge thorpej-cfargs branch:
Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.
Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)
Remove unnecessary or redundant interface attributes where they're not
needed.
There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)
...and a sentinel value CFARG_EOL.
Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.
Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).
|
| 1.7 | 21-May-2017 |
skrll | branches: 1.7.8; 1.7.26;
Provide and use some CP0 accessor functions instead of M[TF]C0 macros
for readability.
While here convert some other M[TF]C0 uses to already exising accessor
functions, e.g. mipsNN_cp0_ebase_read
|
| 1.6 | 19-May-2017 |
skrll | Trailing whitespace
|
| 1.5 | 29-Jan-2016 |
macallan | first shot at SMP support, very much broken and experimental
So far the 2nd core wakes up, makes its way to the idle loop, and things lock
up when we start the timer interrupt.
|
| 1.4 | 04-Apr-2015 |
macallan | add IPI support
compile-tested only since we don't actually spin up the 2nd core yet
|
| 1.3 | 23-Dec-2014 |
macallan | use defflag-ed debug options
|
| 1.2 | 06-Dec-2014 |
macallan | apbus attachment goop, move interrupt stuff to intr.c
|
| 1.1 | 22-Nov-2014 |
macallan | branches: 1.1.2;
initial support for CI20 / Ingenic JZ4780
not much there yet, it loads, attaches a serial port and you can drop into
ddb
|
| 1.1.2.3 | 28-Aug-2017 |
skrll | Sync with HEAD
|
| 1.1.2.2 | 19-Mar-2016 |
skrll | Sync with HEAD
|
| 1.1.2.1 | 06-Apr-2015 |
skrll | Sync with HEAD
|
| 1.7.26.1 | 23-Mar-2021 |
thorpej | Convert config_found_ia() call sites where the device only carries
a single interface attribute to bare config_found() calls.
|
| 1.7.8.2 | 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.7.8.1 | 21-May-2017 |
jdolecek | file mainbus.c was added on branch tls-maxphys on 2017-12-03 11:36:09 +0000
|
| 1.8.8.1 | 04-Aug-2021 |
thorpej | Adapt to CFARGS().
|
