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History log of /src/sys/arch/mips/include
RevisionDateAuthorComments
 1.38 30-Nov-2024  christos Create a new header lwp_private.h to contain _lwp_getprivate_fast,
_lwp_gettcb_fast, _lwp_settcb and remove them from mcontext.h, so that:
1. we don't need special hacks to hide them
2. we can include <lwp.h> where needed to get the necessary prototypes
without redefining them locally.
 1.37 04-Nov-2024  christos Undo previous lwp.h change.
 1.36 03-Nov-2024  christos Split __lwp_getprivate_fast and __lwp_*tcb from mcontext.h into a separate
lwp.h file.
 1.35 29-Mar-2021  simonb branches: 1.35.22;
Install <mips/frame.h>, now needed for dtrace.
 1.34 12-Jul-2018  maxv branches: 1.34.12; 1.34.14;
Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.
 1.33 21-Dec-2015  christos branches: 1.33.16; 1.33.18;
Add mips fenv.h (From FreeBSD)
 1.32 23-Jul-2014  alnsn branches: 1.32.4;
Rename sljitarch.h to sljit_machdep.h.
 1.31 25-Nov-2012  alnsn branches: 1.31.10;
Add sljitarch.h to all mips machines.
 1.30 17-Jul-2011  joerg branches: 1.30.2; 1.30.12;
Retire varargs.h support. Move machine/stdarg.h logic into MI
sys/stdarg.h and expect compiler to provide proper builtins, defaulting
to the GCC interface. lint still has a special fallback.
Reduce abuse of _BSD_VA_LIST_ by defining __va_list by default and
derive va_list as required by standards.
 1.29 17-Aug-2009  matt Don't install aout_machpep.h and bsd-aout.h
 1.28 09-Feb-2007  ad branches: 1.28.48;
Merge newlock2 to head.
 1.27 26-Jul-2006  drochner branches: 1.27.4;
don't install <machine/db_machdep.h>, this is kernel only
 1.26 11-Dec-2005  christos branches: 1.26.4; 1.26.8;
merge ktrace-lwp.
 1.25 08-May-2004  kleink branches: 1.25.12;
Factor out W{CHAR,INT}_{MAX,MIN} into their own header file.
 1.24 17-Jan-2003  thorpej branches: 1.24.2;
Merge the nathanw_sa branch.
 1.23 26-Nov-2002  lukem Remove KDIR=, since SYS_INCLUDE=symlinks and KDIR are not supported any more.
 1.22 07-Aug-2002  briggs Implement pmc(9) -- An interface to hardware performance monitoring
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.
 1.21 28-Nov-2001  manu branches: 1.21.8;
Back out the copy of theses files to userland
 1.20 28-Nov-2001  manu We need to copy new SVR4 header files to /usr/include/sys...
 1.19 15-Apr-2001  kleink branches: 1.19.2; 1.19.8;
Add definitions of C99 integer format conversion macros.
XXX Fastest minimum-width integer types haven't been decided upon yet.
 1.18 15-Apr-2001  kleink Add definitions of C99 specified-width integer type limits.
XXX Fastest minimum-width integer types haven't been decided upon yet.
 1.17 14-Apr-2001  kleink Add definitions of C99 integer constant macros.
Tidy Makefiles up a little.
 1.16 14-Apr-2001  kleink Add definitions of C99 minimum-width and greatest-width integer types.
XXX Fastest minimum-width integer types haven't been decided upon yet.
 1.15 26-Jun-2000  kleink branches: 1.15.2;
Add <machine/int_types.h>, which provides namespace-pure definitions
of exact-width integer types.
 1.14 29-Apr-2000  thorpej Require that each each MACHINE/MACHINE_ARCH supply a lock.h. This file
contains the values __SIMPLELOCK_LOCKED and __SIMPLELOCK_UNLOCKED, which
replace the old SIMPLELOCK_LOCKED and SIMPLELOCK_UNLOCKED. These files
are also required to supply inline functions __cpu_simple_lock(),
__cpu_simple_lock_try(), and __cpu_simple_unlock() if locking is to be
supported on that platform (i.e. if MULTIPROCESSOR is defined in the
_KERNEL case). Change these functions to take an int * (&alp->lock_data)
rather than the struct simplelock * itself.

These changes make it possible for userland to use the locking primitives
by including <machine/lock.h>.
 1.13 17-Mar-2000  tron Install "machineendian_machdep.h".
 1.12 23-Dec-1999  kleink C99: Define a NAN macro in <math.h> which evaulates to a constant expression of
a single-precision quiet NaN; only to be defined on platforms that do support
this value.
 1.11 09-Nov-1999  kleink Per discussion on tech-toolchain, remove MIPS-specific <machine/elf.h> header;
all the information is available from <sys/exec_elf.h>.
 1.10 30-Aug-1999  mrg branches: 1.10.2; 1.10.4; 1.10.8;
install ieee.h
 1.9 30-Mar-1999  simonb Don't install intr.h - there's only a kernel function prototype in
this file.
 1.8 24-Mar-1999  nisimura - Restore 'regdef.h' lost since last January.
 1.7 15-Mar-1999  nisimura - Eliminate 'conf.h' from MIPS common code.
 1.6 13-Mar-1999  drochner g/c regdef.h (went into asm.h)
 1.5 18-Jan-1999  castor Forgot to also ship out regnum.h
 1.4 18-Jan-1999  castor Remove vestiges of cpuarch.h. Revert to using cpuregs.h instead.
 1.3 15-Jan-1999  bouyer Move the bswap functions from libutil to libc (this bups the
minor of libc and the major of libutil). For little-endian architectures
merge the bnswap() assembly versions with nto* and hton* using symbols
aliasing. Use symbol renaming for the bswap function in this case to avoid
namespace pollution.
Declare bswap* in machine/bswap.h, not machine/endian.h. For little-endian
machines, common code for inline macros go in machine/byte_swap.h
Sync libkern with libc.
Adjust #include in kernel sources for machine/bswap.h.
 1.2 14-Jan-1999  castor * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.1 12-Jun-1998  cgd Rework the way kernel include files are installed. In the new method,
as with user-land programs, include files are installed by each directory
in the tree that has includes to install. (This allows more flexibility
as to what gets installed, makes 'partial installs' easier, and gives us
more options as to which machines' includes get installed at any given
time.) The old SYS_INCLUDES={symlinks,copies} behaviours are _both_
still supported, though at least one bug in the 'symlinks' case is
fixed by this change. Include files can't be build before installation,
so directories that have includes as targets (e.g. dev/pci) have to move
those targets into a different Makefile.
 1.10.8.1 27-Dec-1999  wrstuden Pull up to last week's -current.
 1.10.4.1 15-Nov-1999  fvdl Sync with -current
 1.10.2.2 21-Apr-2001  bouyer Sync with HEAD
 1.10.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.15.2.1 21-Jun-2001  nathanw Catch up to -current.
 1.19.8.5 11-Dec-2002  thorpej Sync with HEAD.
 1.19.8.4 13-Aug-2002  nathanw Catch up to -current.
 1.19.8.3 08-Jan-2002  nathanw Catch up to -current.
 1.19.8.2 17-Nov-2001  wdk mcontext support for MIPS based ports.
 1.19.8.1 15-Apr-2001  wdk file Makefile was added on branch nathanw_sa on 2001-11-17 23:12:03 +0000
 1.19.2.2 06-Sep-2002  jdolecek sync kqueue branch with HEAD
 1.19.2.1 10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.21.8.1 31-Aug-2002  gehenna catch up with -current.
 1.24.2.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.24.2.2 18-Sep-2004  skrll Sync with HEAD.
 1.24.2.1 03-Aug-2004  skrll Sync with HEAD
 1.25.12.2 26-Feb-2007  yamt sync with head.
 1.25.12.1 30-Dec-2006  yamt sync with head.
 1.26.8.1 11-Aug-2006  yamt sync with head
 1.26.4.1 09-Sep-2006  rpaulo sync with head
 1.27.4.1 01-Feb-2007  ad Header file cleanup.
 1.28.48.1 19-Aug-2009  yamt sync with head.
 1.30.12.3 03-Dec-2017  jdolecek update from HEAD
 1.30.12.2 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.30.12.1 25-Feb-2013  tls resync with head
 1.30.2.1 16-Jan-2013  yamt sync with (a bit old) head
 1.31.10.1 10-Aug-2014  tls Rebase.
 1.32.4.1 27-Dec-2015  skrll Sync with HEAD (as of 26th Dec)
 1.33.18.1 10-Jun-2019  christos Sync with HEAD
 1.33.16.1 28-Jul-2018  pgoyette Sync with HEAD
 1.34.14.1 03-Apr-2021  thorpej Sync with HEAD.
 1.34.12.1 03-Apr-2021  thorpej Sync with HEAD.
 1.35.22.1 02-Aug-2025  perseant Sync with HEAD
 1.11 23-Mar-2021  simonb Remove addition of -msym32 to CFLAGS. Hinders rather than helps build
MIPS modules.
 1.10 09-Jun-2016  martin branches: 1.10.30; 1.10.32;
Sync register number for curlwp with the kernel
 1.9 21-Jan-2011  joerg branches: 1.9.14; 1.9.32;
Switch remaining platforms to modern CPP for assembler.
 1.8 29-Nov-2009  pooka branches: 1.8.4; 1.8.6; 1.8.8;
Don't build rump kernel with -mno-abicalls, because it's effectively
"no pic".
(should be used only for shared lib rump kernel, but this is just
bandaid for now)
 1.7 21-Dec-2008  ad Update flags to match reality.
 1.6 02-Jun-2006  mrg branches: 1.6.60; 1.6.64; 1.6.72;
remove GCC2 support.
 1.5 07-Apr-2006  mrg branches: 1.5.2;
retire HAVE_GCC3/HAVE_GCC4 and introduce HAVE_GCC that is set to 2, 3 or 4.
 1.4 11-Dec-2005  christos branches: 1.4.4; 1.4.6; 1.4.8; 1.4.10; 1.4.12;
merge ktrace-lwp.
 1.3 27-Aug-2003  mrg branches: 1.3.16;
introduce an additional switch to enable building GCC3 instead of GCC2:
HAVE_GCC3. if this is set, we also set USE_TOOLS_TOOLCHAIN=no. change
the definition of the former to be restricted to whether tools/toolchain
is used or not.
 1.2 26-Jul-2003  mrg don't need -mno-half-pic with gcc3
 1.1 05-Oct-2001  simonb branches: 1.1.2; 1.1.6; 1.1.8; 1.1.24;
This Makefile.inc is used for building LKMS - add the standard MIPS
kernel compile flags as well as "-mlong-calls" so that calls from the
LKM in KSEG2 work to the kernel in KSEG0.

MIPS LKMs now build and can be loaded with the right Magick command line
args to modload(8). Changes to modload coming...

Thanks to Chris Demetriou for pointing out the -mlong-calls gcc option
that had been staring me in the face all along.
 1.1.24.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.1.24.2 18-Sep-2004  skrll Sync with HEAD.
 1.1.24.1 03-Aug-2004  skrll Sync with HEAD
 1.1.8.2 10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.1.8.1 05-Oct-2001  thorpej file Makefile.inc was added on branch kqueue on 2002-01-10 19:45:59 +0000
 1.1.6.2 05-Oct-2001  simonb This Makefile.inc is used for building LKMS - add the standard MIPS
kernel compile flags as well as "-mlong-calls" so that calls from the
LKM in KSEG2 work to the kernel in KSEG0.

MIPS LKMs now build and can be loaded with the right Magick command line
args to modload(8). Changes to modload coming...

Thanks to Chris Demetriou for pointing out the -mlong-calls gcc option
that had been staring me in the face all along.
 1.1.6.1 05-Oct-2001  simonb file Makefile.inc was added on branch nathanw_sa on 2001-10-05 15:36:47 +0000
 1.1.2.2 11-Oct-2001  fvdl Catch up with -current. Fix some bogons in the sparc64 kbd/ms
attach code. cd18xx conversion provided by mrg.
 1.1.2.1 05-Oct-2001  fvdl file Makefile.inc was added on branch thorpej-devvp on 2001-10-11 00:01:47 +0000
 1.3.16.1 21-Jun-2006  yamt sync with head.
 1.4.12.1 24-May-2006  tron Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.
 1.4.10.1 19-Apr-2006  elad sync with head - hopefully this will work
 1.4.8.2 26-Jun-2006  yamt sync with head.
 1.4.8.1 11-Apr-2006  yamt sync with head
 1.4.6.2 03-Jun-2006  kardel Sync with head.
 1.4.6.1 22-Apr-2006  simonb Sync with head.
 1.4.4.1 09-Sep-2006  rpaulo sync with head
 1.5.2.1 19-Jun-2006  chap Sync with head.
 1.6.72.1 19-Jan-2009  skrll Sync with HEAD.
 1.6.64.2 11-Mar-2010  yamt sync with head
 1.6.64.1 04-May-2009  yamt sync with head.
 1.6.60.1 17-Jan-2009  mjf Sync with HEAD.
 1.8.8.1 08-Feb-2011  bouyer Sync with HEAD
 1.8.6.1 06-Jun-2011  jruoho Sync with HEAD.
 1.8.4.1 05-Mar-2011  rmind sync with head
 1.9.32.1 09-Jul-2016  skrll Sync with HEAD
 1.9.14.1 03-Dec-2017  jdolecek update from HEAD
 1.10.32.1 03-Apr-2021  thorpej Sync with HEAD.
 1.10.30.1 03-Apr-2021  thorpej Sync with HEAD.
 1.30 07-May-2019  kamil Switch all users (except ia64) of custom machine/ansi.h to common_ansi.h

Deduplicate the code among ports and poll definitions of types
directly from a compiler.

This fixes miscompilation of certain programs that instruct compilers
to generate code for different types. This bug has been detected with
-fshort-wchar in EFI firmware.

Proposed and discussed on a mailing list (twice).

Itanium uses custom !ELF fallback switch, temporarily leave it as it is.
 1.29 17-Jun-2015  matt branches: 1.29.18;
Make _BSD_CLOCK_T_ unsigned int so it's the same for IPL32 and LP64
environments. We don't really have a powerpc64 native userland
and the mips64 native userland is IPL32 so this shouldn't affect anything.
 1.28 17-Jul-2011  joerg branches: 1.28.12; 1.28.28; 1.28.30;
Retire varargs.h support. Move machine/stdarg.h logic into MI
sys/stdarg.h and expect compiler to provide proper builtins, defaulting
to the GCC interface. lint still has a special fallback.
Reduce abuse of _BSD_VA_LIST_ by defining __va_list by default and
derive va_list as required by standards.
 1.27 27-Mar-2010  tnozaki 1. {wctype,wctrans,mbstate}_t: switch MD to MI like other
libc implementation (such as *BSD and glibc2).

2. don't typedef void * wc{type,trans}_t, suggested by soda@-san.
it may pass through compiler type check, it's harmful.
so i introduce dummy struct __tag_wc{type,trans}_t(iconv_t already does).

no ABI change was made.
 1.26 14-Dec-2009  matt branches: 1.26.2; 1.26.4;
Fix merge botch (we use 64bit times now).
 1.25 14-Dec-2009  matt Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.24 11-Jan-2009  christos merge christos-time_t
 1.23 17-Oct-2007  garbled branches: 1.23.16; 1.23.18; 1.23.22; 1.23.30; 1.23.38;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.22 03-Sep-2007  drochner clean up some definitions around rune_t which are not needed anymore
 1.21 04-Oct-2006  tnozaki branches: 1.21.8; 1.21.16; 1.21.22; 1.21.26; 1.21.28;
fix gcc -Werror -Wmissing-braces problem
mbstate_t(this is opaque object)'s initializer should be ``{ 0 }'',
so changed 1st field of union from character array to integer.
 1.20 11-Dec-2005  christos branches: 1.20.20; 1.20.22;
merge ktrace-lwp.
 1.19 25-Oct-2003  mycroft branches: 1.19.16;
Update for GCC3 (basically, use the __builtin_va_* implementation).
 1.18 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.17 30-May-2003  simonb branches: 1.17.2;
#define<tab>
 1.16 02-Mar-2003  tshiozak add some ISO C 1995 I18N functions and types:
btowc, wctrans, towctrans, wcscoll, wcsxfrm, wctype_t and wctrans_t.
 1.15 03-Nov-2002  thorpej Add _LP64 types.
 1.14 03-Jan-2001  takemura branches: 1.14.8;
replace 'long long' with int64_t to compile stand alone program with
compiler other than GCC.
 1.13 26-Dec-2000  itojun make mbstate_t bigger (32 -> 128 bytes).
XXX if you have libc after citrus locale import, please recompile libc,
and your applications that use mbstate_t (rather rare). really sorry
for the mess.
 1.12 21-Dec-2000  itojun populate _BSD_MBSTATE_T_. add warning regarding to rune_t.
 1.11 27-Jun-2000  kleink G/c _BSD_INTPTR_T_ and _BSD_UINTPTR_T_.
 1.10 24-Apr-1999  simonb branches: 1.10.2; 1.10.10;
Nuke register and remove trailling white space.
 1.9 27-Apr-1998  kleink branches: 1.9.12;
Provide definitions for intptr_t and uintptr_t, signed resp. unsigned integral
types large enough to hold any pointer.
 1.8 23-Nov-1997  kleink Add _BSD_SUSECONDS_T_ and _BSD_USECONDS_T_; do some space vs. tab formatting
cleanup
 1.7 15-Nov-1996  jtc Define _BSD_CLOCKID_T_ and _BSD_TIMER_T_
 1.6 16-Mar-1996  jtc Add _BSD_WINT_T_ definition so we can handle wint_t type added in NA1.
 1.5 26-Oct-1994  cgd new RCS ID format.
 1.4 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.3 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.2 15-Oct-1993  deraadt update from rick, tarfile of Oct 11 10:46
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.9.12.1 21-Jun-1999  thorpej Sync w/ -current.
 1.10.10.1 28-May-2000  minoura Citrus Project XPG4DL, an implementation of I18N (locale) framework,
is imported.
 1.10.2.2 05-Jan-2001  bouyer Sync with HEAD
 1.10.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.14.8.1 11-Nov-2002  nathanw Catch up to -current
 1.17.2.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.17.2.2 18-Sep-2004  skrll Sync with HEAD.
 1.17.2.1 03-Aug-2004  skrll Sync with HEAD
 1.19.16.2 27-Oct-2007  yamt sync with head.
 1.19.16.1 30-Dec-2006  yamt sync with head.
 1.20.22.1 22-Oct-2006  yamt sync with head
 1.20.20.1 18-Nov-2006  ad Sync with head.
 1.21.28.1 06-Nov-2007  matt sync with HEAD
 1.21.26.1 02-Oct-2007  joerg Sync with HEAD.
 1.21.22.1 10-Sep-2007  skrll Sync with HEAD.
 1.21.16.1 03-Oct-2007  garbled Sync with HEAD
 1.21.8.1 09-Oct-2007  ad Sync with head.
 1.23.38.1 11-Dec-2009  matt Unless we are in O32, use long int for size_t/ptrdiff_t/intptr_t. This
allows N32 and N64 use both use the same type.
 1.23.30.1 19-Jan-2009  skrll Sync with HEAD.
 1.23.22.3 11-Aug-2010  yamt sync with head.
 1.23.22.2 11-Mar-2010  yamt sync with head
 1.23.22.1 04-May-2009  yamt sync with head.
 1.23.18.3 04-Jan-2009  christos handle LP64
 1.23.18.2 30-Mar-2008  christos time_t is now __int64_t
 1.23.18.1 29-Mar-2008  christos Welcome to the time_t=long long dev_t=uint64_t branch.
 1.23.16.1 17-Jan-2009  mjf Sync with HEAD.
 1.26.4.1 30-May-2010  rmind sync with head
 1.26.2.1 30-Apr-2010  uebayasi Sync with HEAD.
 1.28.30.1 22-Sep-2015  skrll Sync with HEAD
 1.28.28.1 16-Jul-2015  riz Pull up following revision(s) (requested by martin in ticket #846):
sys/arch/mips/include/ansi.h: revision 1.29
sys/arch/sh3/include/ansi.h: revision 1.16
sys/arch/sparc64/include/ansi.h: revision 1.18
sys/arch/m68k/include/ansi.h: revision 1.24
sys/arch/powerpc/include/ansi.h: revision 1.30
sys/arch/hppa/include/ansi.h: revision 1.14
sys/arch/i386/include/ansi.h: revision 1.27
sys/arch/alpha/include/ansi.h: revision 1.25
sys/arch/usermode/include/ansi.h: revision 1.5
sys/arch/sparc/include/ansi.h: revision 1.24
Make _BSD_CLOCK_T_ unsigned int so it's the same for IPL32 and LP64
environments. We don't really have a powerpc64 native userland
and the mips64 native userland is IPL32 so this shouldn't affect anything.
Make clock_t unsigned
Make clock_t unsigned int everywhere.
Ok: matt@, mrg@
 1.28.12.1 03-Dec-2017  jdolecek update from HEAD
 1.29.18.1 10-Jun-2019  christos Sync with HEAD
 1.9 12-Aug-2009  matt Nuke a.out support for MIPS.
 1.8 11-Dec-2005  christos branches: 1.8.78; 1.8.92;
merge ktrace-lwp.
 1.7 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.6 10-Dec-2002  thorpej branches: 1.6.6;
Rename __LDPGSZ to AOUT_LDPGSZ, to accurately reflect what it is.
 1.5 26-Oct-1994  cgd branches: 1.5.48;
new RCS ID format.
 1.4 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.3 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.2 14-Jan-1994  deraadt some pmax updating (Terry Friedrichsen is helping on this now).
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.5.48.1 11-Dec-2002  thorpej Sync with HEAD.
 1.6.6.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.6.6.2 18-Sep-2004  skrll Sync with HEAD.
 1.6.6.1 03-Aug-2004  skrll Sync with HEAD
 1.8.92.1 24-Oct-2010  jym Sync with HEAD
 1.8.78.1 19-Aug-2009  yamt sync with head.
 1.77 06-Jan-2025  martin PR 58960: fix misunderstanding in semantic and provide both the original
id string as well as _NETBSD_REVISIONID.
Do not rely on string concatenation in the inline assembler, use .ascii
and .asciz for individual string parts instead.
 1.76 04-Jan-2025  martin PR 58960: mips/asm.h: Respect NETBSD_REVISIONID.
 1.75 14-Sep-2023  rin branches: 1.75.6;
mips: Add initial support to gprof(1) for n64 userland

Use gp relative call for _mcount().

Stop using macro name MCOUNT as well for clarity. It has nothing to
do with one provided by <machine/profile.h>.

Now, gprof(1) works just fine for C programs. On the other hand, some
C++ profiling tests of ATF fail as partially observed for n32.

More C++ profile tests become broken for GCC12 in comparison to GCC10.
Something needs to be adjusted for us, or GCC, or both.
 1.74 23-Feb-2023  riastradh mips: Add missing barriers in cpu_switchto.

Details in comments.

PR kern/57240

XXX pullup-8
XXX pullup-9
XXX pullup-10
 1.73 20-Feb-2023  riastradh mips/asm.h: Make membar macros conditional on MULTIPROCESSOR.

For !MULTIPROCESSOR, define them to be empty or nop as appropriate.
 1.72 13-Feb-2023  riastradh mips/asm.h: Cite source for Cavium sync plunger business.
 1.71 21-Apr-2022  riastradh branches: 1.71.4;
mips/cavium: Take advantage of Octeon's guaranteed r/rw ordering.
 1.70 09-Apr-2022  riastradh mips/rmi: Hack to get XLSATX64.MP kernel building again.

Using <mips/asm.h> in a .c file is kinda grody but CALLFRAME_SIZ
doesn't seem to be defined anywhere else. Not sure how this was ever
supposed to work...
 1.69 27-Feb-2022  riastradh mips: Redefine LLSCSYNC as empty on non-Octeon MP.

This change deletes memory barriers on non-Octeon MP. However, all
the appropriate acquire and release barriers are already used in
mutex stubs, and no barriers are needed in atomic_* unless we set
__HAVE_ATOMIC_AS_MEMBAR which we don't on MIPS. So this should be
safe.

Unclear whether we need this even on Octeon -- don't have a clear
reference on why it's here.
 1.68 27-Feb-2022  riastradh mips: Redefine BDSYNC as sync on Octeon, not syncw.

BDSYNC is used for membar_sync, which is supposed to be a full
sequential consistency barrier, which is not provided by syncw, so
this is necessary for correctness.

BDSYNC is not used for anything else, so this can't hurt performance,
except where it was necessary for correctness anyway or where the
semantic choice of membar_sync was too strong anyway.
 1.67 27-Feb-2022  riastradh mips: Omit needless SYNC in mutex_exit.

This change deletes a memory barrier. However, it should be safe:
The semantic requirement for this is already provided by the SYNC_REL
above, before the ll. And as currently defined, SYNC_REL is at least
as strong as SYNC, so this change can't hurt correctness on its own
(barring CPU errata, which would apply to other users of SYNC_REL and
can be addressed in the definition of SYNC_REL).

Later, perhaps we can relax SYNC_REL to syncw on Octeon if we prove
that it is correct (e.g., if Octeon follows the SPARCv9 partial store
order semantics).

Nix now-unused SYNC macro in asm.h.
 1.66 27-Feb-2022  riastradh mips: Membar audit.

This change should be safe because it doesn't remove or weaken any
memory barriers, but does add, clarify, or strengthen barriers.

Goals:

- Make sure mutex_enter/exit and mutex_spin_enter/exit have
acquire/release semantics.

- New macros make maintenance easier and purpose clearer:

. SYNC_ACQ is for load-before-load/store barrier, and BDSYNC_ACQ
for a branch delay slot -- currently defined as plain sync for MP
and nothing, or nop, for UP; thus it is no weaker than SYNC and
BDSYNC as currently defined, which is syncw on Octeon, plain sync
on non-Octeon MP, and nothing/nop on UP.

It is not clear to me whether load-then-syncw or ll/sc-then-syncw
or even bare load provides load-acquire semantics on Octeon -- if
no, this will fix bugs; if yes (like it is on SPARC PSO), we can
relax SYNC_ACQ to be syncw or nothing later.

. SYNC_REL is for load/store-before-store barrier -- currently
defined as plain sync for MP and nothing for UP.

It is not clear to me whether syncw-then-store is enough for
store-release on Octeon -- if no, we can leave this as is; if
yes, we can relax SYNC_REL to be syncw on Octeon.

. SYNC_PLUNGER is there to flush clogged Cavium store buffers, and
BDSYNC_PLUNGER for a branch delay slot -- syncw on Octeon,
nothing or nop on non-Octeon.

=> This is not necessary (or, as far as I'm aware, sufficient)
for acquire semantics -- it serves only to flush store buffers
where stores might otherwise linger for hundreds of thousands
of cycles, which would, e.g., cause spin locks to be held for
unreasonably long durations.

Newerish revisions of the MIPS ISA also have finer-grained sync
variants that could be plopped in here.

Mechanism:

Insert these barriers in the right places, replacing only those where
the definition is currently equivalent, so this change is safe.

- Replace #ifdef _MIPS_ARCH_OCTEONP / syncw / #endif at the end of
atomic_cas_* by SYNC_PLUNGER, which is `sync 4' (a.k.a. syncw) if
__OCTEON__ and empty otherwise.

=> From what I can tell, __OCTEON__ is defined in at least as many
contexts as _MIPS_ARCH_OCTEONP -- i.e., there are some Octeons
with no _MIPS_ARCH_OCTEONP, but I don't know if any of them are
relevant to us or ever saw the light of day outside Cavium; we
seem to buid with `-march=octeonp' so this is unlikely to make a
difference. If it turns out that we do care, well, now there's
a central place to make the distinction for sync instructions.

- Replace post-ll/sc SYNC by SYNC_ACQ in _atomic_cas_*, which are
internal kernel versions used in sys/arch/mips/include/lock.h where
it assumes they have load-acquire semantics. Should move this to
lock.h later, since we _don't_ define __HAVE_ATOMIC_AS_MEMBAR on
MIPS and so the extra barrier might be costly.

- Insert SYNC_REL before ll/sc, and replace post-ll/sc SYNC by
SYNC_ACQ, in _ucas_*, which is used without any barriers in futex
code and doesn't mention barriers in the man page so I have to
assume it is required to be a release/acquire barrier.

- Change BDSYNC to BDSYNC_ACQ in mutex_enter and mutex_spin_enter.
This is necessary to provide load-acquire semantics -- unclear if
it was provided already by syncw on Octeon, but it seems more
likely that either (a) no sync or syncw is needed at all, or (b)
syncw is not enough and sync is needed, since syncw is only a
store-before-store ordering barrier.

- Insert SYNC_REL before ll/sc in mutex_exit and mutex_spin_exit.
This is currently redundant with the SYNC already there, but
SYNC_REL more clearly identifies the necessary semantics in case we
want to define it differently on different systems, and having a
sync in the middle of an ll/sc is a bit weird and possibly not a
good idea, so I intend to (carefully) remove the redundant SYNC in
a later change.

- Change BDSYNC to BDSYNC_PLUNGER at the end of mutex_exit. This has
no semantic change right now -- it's syncw on Octeon, sync on
non-Octeon MP, nop on UP -- but we can relax it later to nop on
non-Cavium MP.

- Leave LLSCSYNC in for now -- it is apparently there for a Cavium
erratum, but I'm not sure what the erratum is, exactly, and I have
no reference for it. I suspect these can be safely removed, but we
might have to double up some other syncw instructions -- Linux uses
it only in store-release sequences, not at the head of every ll/sc.
 1.65 18-Feb-2021  simonb Add an abicalls version of asm mcount prologue. XXX not tested because
profiled programs fail to link, but fixes build. Thanks dholland@ for
help analysing this.

While here, rename _KERN_MCOUNT to _MIPS_ASM_MCOUNT - it's not kernel
specific.
 1.64 16-Feb-2021  simonb Working kernel profiling for n32/n64:
- Different MCOUNT and _KERN_MCOUNT macros for n32/n64.
- Don't profile mipsXX_lwp_trampoline().
- Allow a few new instructions in the stub fixups.
 1.63 04-Feb-2021  skrll Use t9 instead of $25 in the SETUP_GP64 macro to hopefully make things
a bit clearer. Same libc binary after.
 1.62 26-Sep-2020  simonb branches: 1.62.2;
Add EXPORT_OBJECT - export definition of symbol of symbol type Object,
visible to ksyms(4) address search.
 1.61 12-Aug-2020  skrll Provide assmebler versions of BITS(3) macros. These are only good for
32 bit masks
 1.60 10-Aug-2020  skrll More SYNC centralisation
 1.59 09-Aug-2020  skrll Use compiler defines to determine which LLSCSYNC, et al
to provide.

This should fix mips builds.
 1.58 06-Aug-2020  skrll Centralise SYNC/BDSYNC in asm.h and introduce a new LLCSCSYNC and use it
before any ll/sc sequences.

Define LLSCSYNC as syncw; syncw for cnMIPS - issue two as early cnMIPS
has errat{um,a} that means the first can fail.
 1.57 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.56 17-Apr-2020  joerg Mark the .ident section as mergable string section to avoid redundant
entries.
 1.55 04-Sep-2018  mrg branches: 1.55.4; 1.55.10;
mark STATIC_NESTED_NOPROFILE() functions as functions.
 1.54 25-Feb-2017  joerg branches: 1.54.6; 1.54.12; 1.54.14;
Switch from __ABICALLS__ to __mips_abicalls like upstream GCC does in
the generic MIPS target logic.
 1.53 11-Nov-2016  maya branches: 1.53.2;
switch mfc0_hazard to be superscalar nop, some mips3 are superscalar
and need this to do the right thing
 1.52 09-Nov-2016  maya Move MFC0_HAZARD definition to asm.h instead of defining it twice
 1.51 13-Aug-2016  skrll Move the NOP_L macro into asm.h
 1.50 13-Aug-2016  skrll Trailing whitespace
 1.49 11-Jul-2016  matt branches: 1.49.2;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.48 17-Sep-2014  joerg branches: 1.48.2;
Normal spelling is .asciz, so use that on MIPS too.
 1.47 30-May-2014  joerg Drop undocumented and redundant 0 argument to .ent.
 1.46 10-Nov-2011  joerg branches: 1.46.10; 1.46.24;
Don't redefine _C_LABEL.
 1.45 01-Jul-2011  matt branches: 1.45.2;
xxx_SUB macros should use a variant of subu, not add
 1.44 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.43 20-Dec-2010  joerg branches: 1.43.2; 1.43.4;
Consistently use .gnu.warning with .pushsectio and .popsection on all
architectures instead of obsolete STABS frames for linker warnings.
 1.42 07-Jul-2010  chs implement ucas_* for mips.
 1.41 14-Dec-2009  matt branches: 1.41.2; 1.41.4;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.40 17-Oct-2007  garbled branches: 1.40.20; 1.40.38;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.39 17-May-2007  yamt branches: 1.39.2; 1.39.10;
merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.
 1.38 09-Feb-2007  ad branches: 1.38.2; 1.38.6; 1.38.8; 1.38.14;
Merge newlock2 to head.
 1.37 20-Jan-2006  christos branches: 1.37.18;
Add a STRONG_ALIAS macro
 1.36 11-Dec-2005  christos branches: 1.36.2;
merge ktrace-lwp.
 1.35 07-Aug-2003  agc branches: 1.35.16;
Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.34 27-Jun-2003  simonb branches: 1.34.2;
Add STATIC_LEAF and STATIC_XLEAF macros, ala the alpha port.
 1.33 05-Jun-2002  simonb Remove an ELF-related comment that isn't needed any more.
 1.32 13-May-2002  simonb branches: 1.32.2;
Oops, remove an #endif leftover from the previous change.
 1.31 13-May-2002  simonb All MIPS ports have been ELF for a long time (most since they were
created); remove non-ELF assembly support.
 1.30 05-Mar-2002  simonb Include <machine/cdefs.h> to select 32/64bit APIs.
 1.29 14-Dec-2000  jeffs branches: 1.29.4; 1.29.8;
For MIPS software masking option, when returning to user mode apply
the mask to all interrupts to catch changes in the mask state faster.
Does not affect platforms w/o this option enabled.
 1.28 30-Aug-2000  jeffs Correct _KERN_MCOUNT restoration of $t9.
From Ethan Solomita (ethan@geocast.com).
 1.27 09-Aug-2000  jeffs Fix a bug in how .S routines call _mcount to allocate stack before
use. By Ethan Solomita (ethan@geocast.com).
 1.26 27-Jul-2000  cgd add nops after jals in PANIC and PRINTF. (these macros are often used in
code which has noreorder set, and they're not used with nops afterwards,
as is appropriate in that case, so put the nops in the macros.)
 1.25 25-Jul-2000  jeffs Add option to apply additional mask to the SR at run-time for MIPS3 platforms.
By default this is off, and only slightly changes the code to load SR when
a temp register is available. This can be used by the platform code to
handle slow to clear interrupts (our case) or to mask off any interrupt
any interrupt at run-time. This can be very useful for embedded platforms
that have less than desirable interrupt properties.
 1.24 23-Jun-2000  kleink Add a WEAK_ALIAS() macro.
 1.23 12-Jun-2000  castor branches: 1.23.2;
Profiling fixes from Ethan Solomita <ethan@geocast.com>.

Merge Kernel MCOUNT and user MCOUNT.

The earlier code which was inserted to call _mcount in profiling
assembler routines is busted badly. This gets it working with PIC
code and should work with any arbitrary assembler routine.
 1.22 24-Apr-1999  simonb branches: 1.22.2; 1.22.10;
Nuke register and remove trailling white space.
 1.21 01-Apr-1999  soda branches: 1.21.4;
do not include <machine/regdef.h>, but include <mips/regdef.h>,
requested by Matthias Drochner and Toru Nishimura.
 1.20 30-Mar-1999  soda - add _C_LABEL() to IMPORT(), to make this consistent with EXPORT().
- fix some oversight of previous my changes on defined(USE_AENT) or
!defined(__NO_LEADING_UNDERSCORES__) case.
 1.19 30-Mar-1999  soda - regdef.h is back, so use it.
- ALIAS() is not needed, use XLEAF() or XNESTED() instead
- use AENT() instead of .aent
- _END_LABEL() is not needed (and was wrong)
- define ALEAF(), NLEAF(), NON_LEAF(), NNON_LEAF() by
XLEAF(), LEAF_NONPROFILE(), NESTED(), NESTED_NONPROFILE()
 1.18 24-Feb-1999  drochner sync to [nisimura-pmax-wscons] version
(only change: include register definitions from regdef.h)
 1.17 16-Feb-1999  jonathan Add VECTOR() and VECTOR_END() macros for declaring exception-vector
code. Fold in <xxx>End names used to copy exception code to vector
locations. Use in mips3 locore code.
 1.16 31-Jan-1999  castor Remove genpubassym.cf stuff. The macro _MIPS_BSD_API allows selection of a
64-bit clean compilation model.
 1.15 14-Jan-1999  castor * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.14 02-Dec-1998  thorpej Implement WARN_REFERENCES().
 1.13 20-Jul-1997  jonathan branches: 1.13.10;
Don't emit ".set reorder ; .set noreorder" around mcount profiling
stubs if _LOCORE or _KERNEL are defined,. _LOCORE means we're
compiling locore. Locore assumes ".set noreorder" for the whole file.
 1.12 23-Jun-1997  jonathan Align to 8-byte boundary after ASMSTR(), for mips3.
 1.11 30-Nov-1996  jtc PROF -> GPROF
 1.10 13-Oct-1996  christos backout previous kprintf change
 1.9 11-Oct-1996  christos printf -> kprintf
 1.8 25-Mar-1996  jonathan Rename from pmax/include/machAsmDefs.h to mips/include/asm.h.
Update the include-idempotency preprocessor token to match.

References to machAsmDefs in vendor (sprite, 4.4bsd) headers left unchanged,
for historical accuracy.
 1.7 18-Jan-1995  mellon Support for alternate compilers and file formats
 1.6 15-Dec-1994  mycroft Make a new macro _C_LABEL(), which prepends an underscore to the argument unless
NO_UNDERSCORES is defined. Use it in the *LEAF() and END() macros.
 1.5 14-Nov-1994  dean Prepended underscores
 1.4 26-Oct-1994  cgd new RCS ID format.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.13.10.3 06-Dec-1998  drochner pull up 1.14 - WARN_REFERENCES()
 1.13.10.2 30-Oct-1998  nisimura - Make pm.c monochrome-aware and compilable with UVM.
- Make trap.c compilable with UVM.
- Place #ifdef _KERNEL guard in cpu.h
- Make asm.h more MIPS standard-alike while retaining current definitions.
 1.13.10.1 15-Oct-1998  nisimura - cpuregs.h was modifed a bit, then renamed with cpuarch.h.
- mips_cpu.h has gone.
- CPU's register mnemonics in regdef.h is now a part of asm.h.
 1.21.4.1 21-Jun-1999  thorpej Sync w/ -current.
 1.22.10.1 22-Jun-2000  minoura Sync w/ netbsd-1-5-base.
 1.22.2.2 05-Jan-2001  bouyer Sync with HEAD
 1.22.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.23.2.2 07-Jun-2001  he Pull up revision 1.25 (requested by hubertf, reviewed by thorpej):
Implement power saving for RM5200 and RM7000 CPUs, as used in
e.g. Cobalt RaQ2.
 1.23.2.1 25-Jul-2000  kleink Pull up rev. 1.24 (approved by thorpej):
For ELF, add a WEAK_ALIAS() macro.
 1.29.8.2 20-Jun-2002  nathanw Catch up to -current.
 1.29.8.1 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.29.4.2 23-Jun-2002  jdolecek catch up with -current on kqueue branch
 1.29.4.1 16-Mar-2002  jdolecek Catch up with -current.
 1.32.2.1 14-Jul-2002  gehenna catch up with -current.
 1.34.2.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.34.2.2 18-Sep-2004  skrll Sync with HEAD.
 1.34.2.1 03-Aug-2004  skrll Sync with HEAD
 1.35.16.3 03-Sep-2007  yamt sync with head.
 1.35.16.2 26-Feb-2007  yamt sync with head.
 1.35.16.1 21-Jun-2006  yamt sync with head.
 1.36.2.1 01-Feb-2006  yamt sync with head.
 1.37.18.1 27-Jan-2007  ad Make mips systems work.
 1.38.14.1 22-May-2007  matt Update to HEAD.
 1.38.8.1 11-Jul-2007  mjf Sync with head.
 1.38.6.1 27-May-2007  ad Sync with head.
 1.38.2.1 18-Apr-2007  ad - Further adaptations to MIPS for the yamt-idlelwp branch.
- Make curlwp a register variable on MIPS.
 1.39.10.1 06-Nov-2007  matt sync with HEAD
 1.39.2.1 18-Jul-2007  matt Add PTR_L/PTR_S/ADDR_L/REGADD utility macros to make code portable between
o32/n32/n64.
 1.40.38.14 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.40.38.13 24-Dec-2010  matt MIPS_LOCK_RAS_SIZE needs to be 256 since each RAS need 64 bytes and we can
have 4 of them.
 1.40.38.12 15-Feb-2010  matt Fix a comment.
 1.40.38.11 16-Jan-2010  matt Rework the exception code. All the exceptions (except for mips3_5900) are
now padded to 128 bytes each and placed in the right order so they can be
copied with one memcpy. This also allows us to branch to unused space space
since the relative locations will remain the same.

When leaving the exception vectors, k1 will now always contain the address
of CURLWP for that CPU. The rest of the exception code no longer needs (and
is not allowed to) to access CPUVAR(CURLWP).

kill outofworld and just let trap panic, if it can. Allow for sb1_subr.S
or rmixl_subr.S in the future. Fix TLB read/write code.
 1.40.38.10 15-Jan-2010  matt Get rid of most of the studly caps.
First to MULTIPROCESSOR support for pmap: move some pmap globals to cpu_info.
Define per-cpu ASID number spaces.
Remove some mips1/!mips1 difference in db_interface.c
Add mips32/64 knowledge to stacktrace.
 1.40.38.9 07-Sep-2009  matt Simplify PTR_ case (32 bit or 64 bit)
 1.40.38.8 05-Sep-2009  matt Add REG_LL/REG_SC/REG_ADDU
 1.40.38.7 03-Sep-2009  matt Don't use .set noorder/.set reorder.
instead use .set push; .set noreorder; .set pop
This will preserve noorder
 1.40.38.6 21-Aug-2009  matt For now use old callframe defs for O32 to reduce spurious code gen
differences make real differences easier to spot.
 1.40.38.5 20-Aug-2009  matt Add XXX_WORD for INT and LONG.
Use PTR_LA in the PANIC macro.
 1.40.38.4 19-Aug-2009  matt Add XXX_SCALESHIFT for all types, not just PTR
REG_PROLOGUE/REG_EPILOGUE cleanup.
 1.40.38.3 18-Aug-2009  matt Fix .cpsetup use $25 instead of $t9.
kill FPST/FPLD and use FP_S/FP_L which match INT_S/PTR_S/REG_S ...
 1.40.38.2 18-Aug-2009  uebayasi Provide FP_L / FP_S as aliases of FPLD / FPST. Fix build.
 1.40.38.1 16-Aug-2009  matt Completely rework to support multiple ABIs. Includes macros/ops to make
writing ABI independent assembly much easier. Add macros to handle PIC
for N32/N64 as well as O32/O64.
 1.40.20.2 11-Aug-2010  yamt sync with head.
 1.40.20.1 11-Mar-2010  yamt sync with head
 1.41.4.1 05-Mar-2011  rmind sync with head
 1.41.2.1 17-Aug-2010  uebayasi Sync with HEAD.
 1.43.4.1 05-Mar-2011  bouyer Sync with HEAD
 1.43.2.1 06-Jun-2011  jruoho Sync with HEAD.
 1.45.2.1 10-Nov-2011  yamt sync with head
 1.46.24.1 10-Aug-2014  tls Rebase.
 1.46.10.2 03-Dec-2017  jdolecek update from HEAD
 1.46.10.1 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.48.2.3 28-Aug-2017  skrll Sync with HEAD
 1.48.2.2 05-Dec-2016  skrll Sync with HEAD
 1.48.2.1 05-Oct-2016  skrll Sync with HEAD
 1.49.2.2 20-Mar-2017  pgoyette Sync with HEAD
 1.49.2.1 07-Jan-2017  pgoyette Sync with HEAD. (Note that most of these changes are simply $NetBSD$
tag issues.)
 1.53.2.1 21-Apr-2017  bouyer Sync with HEAD
 1.54.14.2 21-Apr-2020  martin Sync with HEAD
 1.54.14.1 10-Jun-2019  christos Sync with HEAD
 1.54.12.1 06-Sep-2018  pgoyette Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)
 1.54.6.2 01-Aug-2023  martin Apply patch, requested by riastradh in ticket #1859:

sys/arch/mips/include/asm.h (apply patch)

Additional build fix for mips1 (and mips2?)
(patch taken from [pullup-9 #1676])
 1.54.6.1 31-Jul-2023  martin Pull up following revision(s) (requested by riastradh in ticket #1859):

sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
sys/arch/aarch64/aarch64/locore.S: revision 1.91
sys/arch/mips/include/asm.h: revision 1.74
sys/arch/hppa/include/cpu.h: revision 1.13
sys/arch/arm/arm/armv6_start.S: revision 1.38
(applied also to sys/arch/arm/cortex/a9_mpsubr.S,
sys/arch/arm/cortex/a9_mpsubr.S,
sys/arch/arm/cortex/cortex_init.S)
sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
sys/arch/mips/mips/locore.S: revision 1.229
sys/arch/alpha/include/asm.h: revision 1.45
(applied to sys/arch/alpha/alpha/multiproc.s)
sys/arch/sparc64/sparc64/locore.s: revision 1.432
sys/arch/vax/vax/subr.S: revision 1.42
sys/arch/mips/mips/locore_mips3.S: revision 1.116
sys/arch/ia64/ia64/machdep.c: revision 1.44
sys/arch/arm/arm32/cpuswitch.S: revision 1.106
sys/arch/sparc/sparc/locore.s: revision 1.284
(all via patch)

aarch64: Add missing barriers in cpu_switchto.
Details in comments.

Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.

PR kern/57240

alpha: Add missing barriers in cpu_switchto.
Details in comments.

arm32: Add missing barriers in cpu_switchto.
Details in comments.

hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?

ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)

mips: Add missing barriers in cpu_switchto.
Details in comments.

powerpc: Add missing barriers in cpu_switchto.
Details in comments.

sparc: Add missing barriers in cpu_switchto.

sparc64: Add missing barriers in cpu_switchto.
Details in comments.

vax: Note where cpu_switchto needs barriers.

Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.
 1.55.10.1 20-Apr-2020  bouyer Sync with HEAD
 1.55.4.2 01-Aug-2023  martin Apply patch, requested by riastradh in ticket #1676:

sys/arch/mips/include/asm.h (apply patch)

Additional build fix for mips1 (and mips2?)
 1.55.4.1 31-Jul-2023  martin Pull up following revision(s) (requested by riastradh in ticket #1676):

sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
sys/arch/aarch64/aarch64/locore.S: revision 1.91
sys/arch/mips/include/asm.h: revision 1.74
sys/arch/hppa/include/cpu.h: revision 1.13
sys/arch/arm/arm/armv6_start.S: revision 1.38
sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
sys/arch/mips/mips/locore.S: revision 1.229
sys/arch/aarch64/aarch64/cpuswitch.S: revision 1.40
sys/arch/alpha/include/asm.h: revision 1.45
sys/arch/sparc64/sparc64/locore.s: revision 1.432
sys/arch/vax/vax/subr.S: revision 1.42
sys/arch/mips/mips/locore_mips3.S: revision 1.116
sys/arch/ia64/ia64/machdep.c: revision 1.44
sys/arch/arm/arm32/cpuswitch.S: revision 1.106
sys/arch/sparc/sparc/locore.s: revision 1.284
(all via patch)

aarch64: Add missing barriers in cpu_switchto.
Details in comments.

Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.

PR kern/57240

alpha: Add missing barriers in cpu_switchto.
Details in comments.

arm32: Add missing barriers in cpu_switchto.
Details in comments.

hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?

ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)

mips: Add missing barriers in cpu_switchto.
Details in comments.

powerpc: Add missing barriers in cpu_switchto.
Details in comments.

sparc: Add missing barriers in cpu_switchto.

sparc64: Add missing barriers in cpu_switchto.
Details in comments.

vax: Note where cpu_switchto needs barriers.

Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.
 1.62.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.71.4.1 31-Jul-2023  martin Pull up following revision(s) (requested by riastradh in ticket #264):

sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
sys/arch/aarch64/aarch64/locore.S: revision 1.91
sys/arch/mips/include/asm.h: revision 1.74
sys/arch/hppa/include/cpu.h: revision 1.13
sys/arch/arm/arm/armv6_start.S: revision 1.38
sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
sys/arch/mips/mips/locore.S: revision 1.229
sys/arch/aarch64/aarch64/cpuswitch.S: revision 1.40
sys/arch/alpha/include/asm.h: revision 1.45
sys/arch/sparc64/sparc64/locore.s: revision 1.432
sys/arch/vax/vax/subr.S: revision 1.42
sys/arch/mips/mips/locore_mips3.S: revision 1.116
sys/arch/riscv/riscv/cpu_switch.S: revision 1.3
sys/arch/ia64/ia64/machdep.c: revision 1.44
sys/arch/arm/arm32/cpuswitch.S: revision 1.106
sys/arch/sparc/sparc/locore.s: revision 1.284

aarch64: Add missing barriers in cpu_switchto.
Details in comments.

Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.

PR kern/57240

alpha: Add missing barriers in cpu_switchto.
Details in comments.

arm32: Add missing barriers in cpu_switchto.
Details in comments.

hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?

ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)

mips: Add missing barriers in cpu_switchto.
Details in comments.

powerpc: Add missing barriers in cpu_switchto.
Details in comments.

riscv: Add missing barriers in cpu_switchto.
Details in comments.

sparc: Add missing barriers in cpu_switchto.

sparc64: Add missing barriers in cpu_switchto.
Details in comments.

vax: Note where cpu_switchto needs barriers.

Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.
 1.75.6.1 02-Aug-2025  perseant Sync with HEAD
 1.6 12-Aug-2009  matt Nuke a.out support for MIPS.
 1.5 30-Nov-2002  simonb branches: 1.5.112; 1.5.126;
Standardise on #ifdef _MIPS_<header>_H_ for multiple inclusion tests.
 1.4 24-Apr-1999  simonb branches: 1.4.20;
Nuke register and remove trailling white space.
 1.3 05-Jan-1998  perry branches: 1.3.12;
RCSID Police.
 1.2 28-Mar-1995  jtc KERNEL -> _KERNEL
 1.1 18-Jan-1995  mellon 4.4BSD binary format
 1.3.12.1 21-Jun-1999  thorpej Sync w/ -current.
 1.4.20.1 11-Dec-2002  thorpej Sync with HEAD.
 1.5.126.1 24-Oct-2010  jym Sync with HEAD
 1.5.112.1 19-Aug-2009  yamt sync with head.
 1.5 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.4 23-May-2013  christos add generic copyrights so FreeBSD can use them.
 1.3 30-Nov-2002  simonb branches: 1.3.146; 1.3.156;
Standardise on #ifdef _MIPS_<header>_H_ for multiple inclusion tests.
 1.2 21-Aug-1999  simonb branches: 1.2.20;
Include <sys/bswap.h> for function prototypes. i386, pc532 and vax
still include <machine/byte_swap.h> and define macros for some of
the bswap*() functions.
 1.1 15-Jan-1999  bouyer Move the bswap functions from libutil to libc (this bups the
minor of libc and the major of libutil). For little-endian architectures
merge the bnswap() assembly versions with nto* and hton* using symbols
aliasing. Use symbol renaming for the bswap function in this case to avoid
namespace pollution.
Declare bswap* in machine/bswap.h, not machine/endian.h. For little-endian
machines, common code for inline macros go in machine/byte_swap.h
Sync libkern with libc.
Adjust #include in kernel sources for machine/bswap.h.
 1.2.20.1 11-Dec-2002  thorpej Sync with HEAD.
 1.3.156.1 23-Jun-2013  tls resync from head
 1.3.146.1 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.11 28-May-2014  skrll Remove unused file.
 1.10 20-Feb-2011  matt branches: 1.10.14; 1.10.28;
Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.9 28-Apr-2008  martin branches: 1.9.18; 1.9.22; 1.9.28; 1.9.30;
Remove clause 3 and 4 from TNF licenses
 1.8 04-Mar-2007  christos branches: 1.8.40; 1.8.42; 1.8.44;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.
 1.7 21-Feb-2007  mrg add a pair of new bus_dma(9) functions:
int _bus_dmatag_subregion(bus_dma_tag_t tag,
bus_addr_t min_addr,
bus_addr_t max_addr,
bus_dma_tag_t *newtag,
int flags)
void _bus_dmatag_destroy(bus_dma_tag_t tag)

that allow a (normally broken/limited) device to restrict the bus address
range it can talk to. this is used by bce(4) to limit DMA addresses to
1GB range, the maximum the chip can address.

all this is from Yorick Hardy <yhardy@uj.ac.za> with input from several
people on tech-kern.

XXX: bus_dma(9) needs an update still.
 1.6 01-Mar-2006  yamt branches: 1.6.20;
merge yamt-uio_vmspace branch.

- use vmspace rather than proc or lwp where appropriate.
the latter is more natural to specify an address space.
(and less likely to be abused for random purposes.)
- fix a swdmover race.
 1.5 11-Dec-2005  christos branches: 1.5.2; 1.5.4; 1.5.6;
merge ktrace-lwp.
 1.4 09-Mar-2005  matt branches: 1.4.4;
Add a dm_maxsegsz public member to bus_dmamap_t. This allows a user of the API
to select the maximum segment size for each bus_dmamap_load (up to the maxsegsz
supplied to bus_dmamap_create). dm_maxsegsz is reset to the value supplied to
bus_dmamap_create when the dmamap is unloaded.
 1.3 28-Jan-2003  kent branches: 1.3.2; 1.3.10; 1.3.12;
Introduce BUS_DMA_NOCACHE, and bus_dmamem_map() of i386 supports it.
 1.2 18-Mar-2002  simonb branches: 1.2.4; 1.2.10;
Oops, balance #ifdef/#endif _KERNEL.
 1.1 18-Mar-2002  simonb Add generic MIPS bus_space and bus_dma headers; these are a straight
split of the algor <machine/bus.h>.
 1.2.10.2 23-Jun-2002  jdolecek catch up with -current on kqueue branch
 1.2.10.1 18-Mar-2002  jdolecek file bus_dma.h was added on branch kqueue on 2002-06-23 17:38:01 +0000
 1.2.4.2 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.2.4.1 18-Mar-2002  nathanw file bus_dma.h was added on branch nathanw_sa on 2002-04-01 07:40:57 +0000
 1.3.12.1 19-Mar-2005  yamt sync with head. xen and whitespace. xen part is not finished.
 1.3.10.1 29-Apr-2005  kent sync with -current
 1.3.2.1 01-Apr-2005  skrll Sync with HEAD.
 1.4.4.3 03-Sep-2007  yamt sync with head.
 1.4.4.2 26-Feb-2007  yamt sync with head.
 1.4.4.1 21-Jun-2006  yamt sync with head.
 1.5.6.1 22-Apr-2006  simonb Sync with head.
 1.5.4.1 09-Sep-2006  rpaulo sync with head
 1.5.2.1 18-Feb-2006  yamt _dm_proc -> _dm_vmspace.
 1.6.20.2 12-Mar-2007  rmind Sync with HEAD.
 1.6.20.1 27-Feb-2007  yamt - sync with head.
- move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.
 1.8.44.1 16-May-2008  yamt sync with head.
 1.8.42.1 18-May-2008  yamt sync with head.
 1.8.40.1 02-Jun-2008  mjf Sync with HEAD.
 1.9.30.1 05-Mar-2011  bouyer Sync with HEAD
 1.9.28.1 06-Jun-2011  jruoho Sync with HEAD.
 1.9.22.1 05-Mar-2011  rmind sync with head
 1.9.18.2 12-Jan-2010  matt Rework bounce buffers so that it can also deal with non-coherent buffers.
 1.9.18.1 10-Jan-2010  matt Add generic support for DMA bounce buffers and real version of
bus_dmatag_subregion. MALTA uses it for ISADMA. Make RMIXL use
for creating 32bit and 29bit subregions.
 1.10.28.1 10-Aug-2014  tls Rebase.
 1.10.14.1 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.6 22-Jan-2022  skrll Ensure bus_dmatag_subregion is called with an inclusive max_addr
everywhere.
 1.5 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.4 07-Feb-2019  mrg add missing BUS_DMA_PREFETCHABLE
 1.3 30-Jul-2016  matt branches: 1.3.16;
Use register_t for _ds_vaddr
 1.2 11-Jun-2015  matt branches: 1.2.2;
Add struct pmap_limits and pm_{min,max}addr from uvm/pmap/map.h and use it to
store avail_start, avail_end, virtual_start, and virtual_end.
Remove iospace and let emips just bump pmap_limits.virtual_start to get the
VA space it needs.
pmap_segtab.c is almost identical to uvm/pmap/pmap_segtab.c now. It won't
be long until we switch to the uvm/pmap one.
 1.1 01-Jul-2011  dyoung branches: 1.1.12; 1.1.30;
Add new files involved in the bus.h->bus_defs.h/bus_funcs.h split.
 1.1.30.2 05-Oct-2016  skrll Sync with HEAD
 1.1.30.1 22-Sep-2015  skrll Sync with HEAD
 1.1.12.1 03-Dec-2017  jdolecek update from HEAD
 1.2.2.1 06-Aug-2016  pgoyette Sync with HEAD
 1.3.16.1 10-Jun-2019  christos Sync with HEAD
 1.1 01-Jul-2011  dyoung Add new files involved in the bus.h->bus_defs.h/bus_funcs.h split.
 1.6 17-Jul-2011  dyoung Switch MIPS and MIPS-ish architectures to new-style <sys/bus.h>. This
involves moving some inline bus_space(9) implementation into .c files.
 1.5 14-Dec-2009  matt Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.4 28-Apr-2008  martin branches: 1.4.18;
Remove clause 3 and 4 from TNF licenses
 1.3 04-Feb-2006  gdamore branches: 1.3.68; 1.3.70; 1.3.72;
Provide streaming bus_space methods that don't swap if bus is otherwise
swapped from host byte order.
Closes PR port-mips/31910
Reviewed by <izumi>, <matt>, and <simonb>
 1.2 18-Mar-2002  simonb branches: 1.2.4; 1.2.10; 1.2.32; 1.2.44; 1.2.46; 1.2.48;
Oops, balance #ifdef/#endif _KERNEL.
 1.1 18-Mar-2002  simonb Add generic MIPS bus_space and bus_dma headers; these are a straight
split of the algor <machine/bus.h>.
 1.2.48.1 22-Apr-2006  simonb Sync with head.
 1.2.46.1 09-Sep-2006  rpaulo sync with head
 1.2.44.1 18-Feb-2006  yamt sync with head.
 1.2.32.1 21-Jun-2006  yamt sync with head.
 1.2.10.2 23-Jun-2002  jdolecek catch up with -current on kqueue branch
 1.2.10.1 18-Mar-2002  jdolecek file bus_space.h was added on branch kqueue on 2002-06-23 17:38:01 +0000
 1.2.4.2 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.2.4.1 18-Mar-2002  nathanw file bus_space.h was added on branch nathanw_sa on 2002-04-01 07:40:57 +0000
 1.3.72.2 11-Mar-2010  yamt sync with head
 1.3.72.1 16-May-2008  yamt sync with head.
 1.3.70.1 18-May-2008  yamt sync with head.
 1.3.68.1 02-Jun-2008  mjf Sync with HEAD.
 1.4.18.3 19-Jan-2012  matt When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses. There are exceptions.
bus_space_handles are now register_t instead of intptr_t. This allows them
to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address. This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs. If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.
 1.4.18.2 17-Nov-2009  matt Add/use PRIxBUS{ADDR,SIZE} and PRIxBSH
 1.4.18.1 15-Nov-2009  cliff - need to be able to handle >32 bit bus addrs in N32 kernel
- bus_addr_t is now paddr_t
- bus_size_t is now psize_t
- bus_space_handle_t is now intptr_t
- this will impact other MIPS ports, TBD
 1.5 28-Mar-2023  nakayama Add missing PRIuBUSSIZE to mips.
 1.4 26-Jul-2020  simonb branches: 1.4.20;
#define<tab>
Nuke trailing whitespace.
 1.3 15-Sep-2016  jdolecek remove last isolated islands using BUS_SPACE_BARRIER_SYNC and
BUS_SPACE_BARRIER_X_BEFORE_X - these were only ever defined for mips and ia64,
and never actually implemented even there
 1.2 11-Jul-2016  matt branches: 1.2.2;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.1 01-Jul-2011  dyoung branches: 1.1.12; 1.1.30;
Add new files involved in the bus.h->bus_defs.h/bus_funcs.h split.
 1.1.30.1 05-Oct-2016  skrll Sync with HEAD
 1.1.12.1 03-Dec-2017  jdolecek update from HEAD
 1.2.2.1 04-Nov-2016  pgoyette Sync with HEAD
 1.4.20.1 03-Apr-2023  martin Additionally pull up following revision(s) for ticket #128
to unbreak the build:

sys/arch/mips/include/types.h: revision 1.78
sys/arch/mips/include/bus_space_defs.h: revision 1.5

Add missing PRIuBUSSIZE to mips.
 1.2 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.1 01-Jul-2011  dyoung Add new files involved in the bus.h->bus_defs.h/bus_funcs.h split.
 1.17 03-May-2025  riastradh mips: Include opt_cputype.h before any of the flags it defines.

PR port-evbmips/59385: PGSHIFT is inconsistently defined on MIPS
 1.16 27-Jul-2020  skrll branches: 1.16.26;
s/MODULE/_MODULE/

spotted by chuq@
 1.15 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.14 18-Aug-2016  skrll Need to compile in cache alias support when MIPS3 or MIPS4
 1.13 11-Jul-2016  matt Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.12 07-Jun-2015  matt Multiple inclusion protection
 1.11 15-Mar-2011  matt branches: 1.11.14; 1.11.32;
Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.
 1.10 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.9 11-Dec-2005  christos branches: 1.9.96; 1.9.100; 1.9.106; 1.9.108;
merge ktrace-lwp.
 1.8 26-Mar-2005  tsutsui Add a workaround to handle virtual alias which may cause data corruption
on R5000/Rm52xx machines:
- Add a new global variable mips_cache_virtual_alias in mips/cache.c,
which indicates that VIPT cache on the CPU could cause virtual alias
and software support is required to handle it. (i.e. no VCED/VCEI)
- Add several cache flush/invalidate ops around KSEG0 access which
might cause virtual alias if mips_cache_virtual_alias is true.
(note checking mips_sdcache_line_size isn't valid for R5000/Rm52xx
because only R4000/R4400 with L2 cache have VCED/VCEI)
- Remove a global variable mips_sdcache_forceinv, which is now superseded
by new mips_cache_virtual_alias.

While here, also change some R4000/R4400 cache ops:
- Don't override mips_cache_alias_mask and mips_cache_prefer_mask with
values based on MIPS3_MAX_PCACHE_SIZE for R4000/R4400 with L2 cache
because it's still worth to reduce VCED/VCEI.
- Flush dcache in pmap_zero_page(9) unconditionally on all MIPS_HAS_R4K_MMU
CPUs and remove cache flush code from cpu_lwp_fork() in vm_machdep.c.

Thanks to Markus W Kilbinger for testing patches on port-cobalt/port-mips.


XXX This fix is just a workaround because it doesn't handle all possible
XXX virtual aliases. As discussed on port-mips, maybe the real fix
XXX for virtual alias is to change MI UVM to adapt it to VIPT cache.
XXX (all VA mappings against the same PA must have the same VAC index etc.)
 1.7 01-Mar-2005  sekiya branches: 1.7.2;
Add a hint variable (mips_sdcache_forceinv, explicitly initialized to zero)
that tells pmap_zero_page() and pmap_copy_page() to unconditionally invalidate
pages for r5k-class CPUs with secondary cache.

This behavior must be explicitly enabled by setting mips_sdcache_forceinv to 1.

This is the last bit of a patch that has been kicked around since 2000 between
rafal@, tsutsui@, and myself.
 1.6 17-Feb-2003  simonb branches: 1.6.2; 1.6.10; 1.6.12;
No need to protect headers with #ifdef _KERNEL if they're never installed
in /usr/include.
 1.5 17-Dec-2002  simonb Add support for caches where the data cache is fully coherent, and
either requires flushing either only when the I cache ops are used
or not at all. Currently only used by MIPS32/MIPS64 cache code.
 1.4 09-Nov-2002  thorpej Make cache size/mask variables unsigned.
 1.3 19-Nov-2001  thorpej branches: 1.3.2;
Add mips_dcache_align and mips_dcache_align_mask variables that
contain information suitable for allowing other parts of the kernel
to determine if a memory region is aligned to the largest data cache
line size present in the system.

Add a mips_dcache_compute_align() function which must be called whenever
one of the data cache line size variables is changed, in order to
compute mips_dcache_align and mips_dcache_align_mask.
 1.2 14-Nov-2001  thorpej branches: 1.2.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.
 1.1 24-Oct-2001  thorpej branches: 1.1.2;
file cache.h was initially added on branch thorpej-mips-cache.
 1.1.2.1 24-Oct-2001  thorpej New MIPS cache primitives and code to configure which ones are used.
 1.2.2.4 19-Dec-2002  thorpej Sync with HEAD.
 1.2.2.3 11-Nov-2002  nathanw Catch up to -current
 1.2.2.2 01-Feb-2002  gmcgarry Pull-up cache ops from -current
 1.2.2.1 14-Nov-2001  gmcgarry file cache.h was added on branch nathanw_sa on 2002-02-01 04:57:44 +0000
 1.3.2.2 10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.3.2.1 19-Nov-2001  thorpej file cache.h was added on branch kqueue on 2002-01-10 19:45:59 +0000
 1.6.12.2 26-Mar-2005  yamt sync with head.
 1.6.12.1 19-Mar-2005  yamt sync with head. xen and whitespace. xen part is not finished.
 1.6.10.1 29-Apr-2005  kent sync with -current
 1.6.2.2 01-Apr-2005  skrll Sync with HEAD.
 1.6.2.1 04-Mar-2005  skrll Sync with HEAD.

Hi Perry!
 1.7.2.1 21-Nov-2005  tron Pull up following revision(s) (requested by tsutsui in ticket #961):
sys/arch/mips/mips/cache.c: revision 1.27
sys/arch/mips/include/cache.h: revision 1.8
sys/arch/mips/mips/pmap.c: revision 1.158
sys/arch/mips/mips/vm_machdep.c: revision 1.106
sys/arch/mips/mips/mem.c: revision 1.30
sys/arch/mips/include/pmap.h: revision 1.47
Add a workaround to handle virtual alias which may cause data corruption
on R5000/Rm52xx machines:
- Add a new global variable mips_cache_virtual_alias in mips/cache.c,
which indicates that VIPT cache on the CPU could cause virtual alias
and software support is required to handle it. (i.e. no VCED/VCEI)
- Add several cache flush/invalidate ops around KSEG0 access which
might cause virtual alias if mips_cache_virtual_alias is true.
(note checking mips_sdcache_line_size isn't valid for R5000/Rm52xx
because only R4000/R4400 with L2 cache have VCED/VCEI)
- Remove a global variable mips_sdcache_forceinv, which is now superseded
by new mips_cache_virtual_alias.
While here, also change some R4000/R4400 cache ops:
- Don't override mips_cache_alias_mask and mips_cache_prefer_mask with
values based on MIPS3_MAX_PCACHE_SIZE for R4000/R4400 with L2 cache
because it's still worth to reduce VCED/VCEI.
- Flush dcache in pmap_zero_page(9) unconditionally on all MIPS_HAS_R4K_MMU
CPUs and remove cache flush code from cpu_lwp_fork() in vm_machdep.c.
Thanks to Markus W Kilbinger for testing patches on port-cobalt/port-mips.
XXX This fix is just a workaround because it doesn't handle all possible
XXX virtual aliases. As discussed on port-mips, maybe the real fix
XXX for virtual alias is to change MI UVM to adapt it to VIPT cache.
XXX (all VA mappings against the same PA must have the same VAC index etc.)
 1.9.108.1 05-Mar-2011  bouyer Sync with HEAD
 1.9.106.1 06-Jun-2011  jruoho Sync with HEAD.
 1.9.100.2 21-Apr-2011  rmind sync with head
 1.9.100.1 05-Mar-2011  rmind sync with head
 1.9.96.8 19-Jan-2012  matt When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses. There are exceptions.
bus_space_handles are now register_t instead of intptr_t. This allows them
to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address. This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs. If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.
 1.9.96.7 12-Jan-2012  matt Add an optimization for UP system with non-virtually tagged caches (which are
most of them these days).

If a page needs to be have an icache_sync performed and the page has a direct
map alias (XKPHYS or KSEG0), then don't do an index op; instead do a range op
on the XKPHYS or KSEG0 address. This results in unneeded fewer cache line
invalidations.
 1.9.96.6 27-Dec-2011  matt Make these play nice with modules.
 1.9.96.5 23-Dec-2011  matt Add multiple inclusion protection.
Add separate variable for dealing with icache virtual aliases
 1.9.96.4 26-May-2011  matt Add MIPS64_RMIXL (XLR/XLS) and MIPS64R2_RMIXL (XLP). This allows the kernel
to treat this special which is needed for MP support. When accessing the TLB,
always lock the TLB before hand. If in the miss handlers, the TLB is already
locked let trap deal with the exeception.
 1.9.96.3 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.9.96.2 26-Jan-2010  matt Revamp pmap. Add exec page caching logic from powerpc oea pmap. Shrink struct
vm_page by placing the first pv_entry in it. Remove pv_flags since nothing
really needed it. Add pmap counters. Rework virtual cache alias logic.
Allow pmap_copy_page and pmap_zero_page to deal with non-KSEG0 mappable pages.
 1.9.96.1 20-Jan-2010  matt Revamp things a bit. Move of the globals mips uses into either cpu_info,
mips_options, or mips_cache_info. Make MALT64 be able to boot MULTIPROCESSOR.
(some pmap MP work).
 1.11.32.2 05-Oct-2016  skrll Sync with HEAD
 1.11.32.1 22-Sep-2015  skrll Sync with HEAD
 1.11.14.1 03-Dec-2017  jdolecek update from HEAD
 1.16.26.1 02-Aug-2025  perseant Sync with HEAD
 1.4 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.3 11-Jul-2016  matt Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.2 11-Aug-2009  matt branches: 1.2.2; 1.2.24; 1.2.42;
Flush by increasing way, then increasing addr. flush L1 before L2 (even
though according to the specification it should be needed). Reset
mips_sdcache_size to 0 so we will configure it.
 1.1 07-Aug-2009  matt Add loongson2 specific cache ops
 1.2.42.1 05-Oct-2016  skrll Sync with HEAD
 1.2.24.1 03-Dec-2017  jdolecek update from HEAD
 1.2.2.2 19-Aug-2009  yamt sync with head.
 1.2.2.1 11-Aug-2009  yamt file cache_ls2.h was added on branch yamt-nfs-mp on 2009-08-19 18:46:29 +0000
 1.6 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.5 11-Jul-2016  matt Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.4 17-Feb-2003  simonb branches: 1.4.126; 1.4.152; 1.4.172;
No need to protect headers with #ifdef _KERNEL if they're never installed
in /usr/include.
 1.3 24-Nov-2002  simonb New generic way-aware MIPS32/64 range-index cache functions with proper
handling for phyiscally-indexed caches where the way size is greater than
the page size.
These work fine with pass 1 SB1 cores, so g/c those workarounds.

Much thanks to Chris Demetriou for many suggestions and helping me get
my head around all this.
 1.2 03-Apr-2002  simonb Include 2way cache ops for mips{32,64} CPUs.
 1.1 05-Mar-2002  simonb branches: 1.1.4; 1.1.8;
Prototypes for MIPS32/64 cache ops.
 1.1.8.4 11-Dec-2002  thorpej Sync with HEAD.
 1.1.8.3 17-Apr-2002  nathanw Catch up to -current.
 1.1.8.2 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.1.8.1 05-Mar-2002  nathanw file cache_mipsNN.h was added on branch nathanw_sa on 2002-04-01 07:40:57 +0000
 1.1.4.3 23-Jun-2002  jdolecek catch up with -current on kqueue branch
 1.1.4.2 16-Mar-2002  jdolecek Catch up with -current.
 1.1.4.1 05-Mar-2002  jdolecek file cache_mipsNN.h was added on branch kqueue on 2002-03-16 15:58:33 +0000
 1.4.172.1 05-Oct-2016  skrll Sync with HEAD
 1.4.152.1 03-Dec-2017  jdolecek update from HEAD
 1.4.126.2 19-Jan-2012  matt When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses. There are exceptions.
bus_space_handles are now register_t instead of intptr_t. This allows them
to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address. This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs. If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.
 1.4.126.1 27-Dec-2011  matt Make these play nice with modules.
 1.5 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.4 14-Jun-2020  simonb Define Octeon Cavium cache layouts for various cnMIPS cores.
 1.3 11-Apr-2019  simonb Fix tyop.
 1.2 11-Jul-2016  matt branches: 1.2.16; 1.2.20;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.1 29-Apr-2015  hikaru branches: 1.1.2;
Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.
 1.1.2.3 05-Oct-2016  skrll Sync with HEAD
 1.1.2.2 06-Jun-2015  skrll Sync with HEAD
 1.1.2.1 29-Apr-2015  skrll file cache_octeon.h was added on branch nick-nhusb on 2015-06-06 14:40:01 +0000
 1.2.20.1 10-Jun-2019  christos Sync with HEAD
 1.2.16.2 03-Dec-2017  jdolecek update from HEAD
 1.2.16.1 11-Jul-2016  jdolecek file cache_octeon.h was added on branch tls-maxphys on 2017-12-03 11:36:27 +0000
 1.4 11-Jul-2016  matt Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.3 11-Dec-2005  christos branches: 1.3.96; 1.3.122; 1.3.142;
merge ktrace-lwp.
 1.2 01-Nov-2003  shin branches: 1.2.4;
cache_r10k.c rev. 1.1 is broken. Because,

1) R10k uses VA0 to select cache ways, but in rev. 1.1, VA14
is used instead.
2) R10k does not support HitWriteBack and should map HitWriteBack
to HitWriteBackInvalidate, but in rev. 1.1, HitWriteBack is not
handled properly.

So, cache_r10k.c rev. 1.1 was replaced by new implementation.
 1.1 05-Oct-2003  tsutsui Add R10000 cache ops, written by KIYOHARA Takashi and posted on port-sgimips.
Enabled by options ENABLE_MIPS4_CACHE_R10K for now.
 1.2.4.4 21-Sep-2004  skrll Fix the sync with head I botched.
 1.2.4.3 18-Sep-2004  skrll Sync with HEAD.
 1.2.4.2 03-Aug-2004  skrll Sync with HEAD
 1.2.4.1 01-Nov-2003  skrll file cache_r10k.h was added on branch ktrace-lwp on 2004-08-03 10:37:39 +0000
 1.3.142.1 05-Oct-2016  skrll Sync with HEAD
 1.3.122.1 03-Dec-2017  jdolecek update from HEAD
 1.3.96.1 19-Jan-2012  matt When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses. There are exceptions.
bus_space_handles are now register_t instead of intptr_t. This allows them
to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address. This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs. If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.
 1.4 11-Jul-2016  matt Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.3 17-Feb-2003  simonb branches: 1.3.126; 1.3.152; 1.3.172;
No need to protect headers with #ifdef _KERNEL if they're never installed
in /usr/include.
 1.2 14-Nov-2001  thorpej branches: 1.2.2; 1.2.4;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.
 1.1 24-Oct-2001  thorpej branches: 1.1.2;
file cache_r3k.h was initially added on branch thorpej-mips-cache.
 1.1.2.1 24-Oct-2001  thorpej New style cache operations for R2000/R3000-style caches.
 1.2.4.2 10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.2.4.1 14-Nov-2001  thorpej file cache_r3k.h was added on branch kqueue on 2002-01-10 19:45:59 +0000
 1.2.2.2 14-Nov-2001  thorpej Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.
 1.2.2.1 14-Nov-2001  thorpej file cache_r3k.h was added on branch nathanw_sa on 2001-11-14 18:26:22 +0000
 1.3.172.1 05-Oct-2016  skrll Sync with HEAD
 1.3.152.1 03-Dec-2017  jdolecek update from HEAD
 1.3.126.1 19-Jan-2012  matt When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses. There are exceptions.
bus_space_handles are now register_t instead of intptr_t. This allows them
to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address. This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs. If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.
 1.17 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.16 12-Jul-2016  skrll Appease gcc and asm
 1.15 12-Jul-2016  skrll Fix RCSId
 1.14 11-Jul-2016  matt Use sdcache routines.
Remove old cache support.
Switch to new cache routines.
 1.13 11-Jul-2016  skrll Trailing whitespace
 1.12 11-Jul-2016  matt Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.11 24-Dec-2005  perry branches: 1.11.96; 1.11.122; 1.11.142;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.
 1.10 08-Mar-2003  rafal branches: 1.10.18;
Add support for R5k secondary caches, from code Chris Sekiya sent me a long
time ago, with small tweaks by me. Since the R5k doesn't do VCE, the pmap
still needs to be whacked for R5kSC CPUs to work correctly, but this is a
start.
 1.9 17-Feb-2003  simonb No need to protect headers with #ifdef _KERNEL if they're never installed
in /usr/include.
 1.8 17-Nov-2002  simonb Add cache_r4k_op_8lines_{16,32} macros to perform cache ops on 8
consecutive lines.
 1.7 05-Mar-2002  simonb Add 4way 16/32-byte-line cache op primitives.
 1.6 19-Jan-2002  shin add VR4131 cache-op bug workaround code.
we can't use Hit_WriteBack_Invalidate.
 1.5 23-Dec-2001  takemura branches: 1.5.2;
Added Vr4131 support.
 1.4 23-Nov-2001  tsutsui Add 32B/l L1 D/I-cache ops for newer ARC machines.
 1.3 18-Nov-2001  thorpej Add 128b/l L2 cache ops.
 1.2 14-Nov-2001  thorpej branches: 1.2.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.
 1.1 24-Oct-2001  thorpej branches: 1.1.2;
file cache_r4k.h was initially added on branch thorpej-mips-cache.
 1.1.2.3 13-Nov-2001  thorpej Fix 3 bad offsets in the cache_r4k_op_32lines_32() loop.
 1.1.2.2 12-Nov-2001  shin improve R4000/4400 secondary cache support.
add support for secondary cache line sizes 16, 64, 128.
 1.1.2.1 24-Oct-2001  thorpej New style cache operations for R4000/R4400-style caches.
 1.2.2.5 11-Dec-2002  thorpej Sync with HEAD.
 1.2.2.4 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.2.2.3 28-Feb-2002  nathanw Catch up to -current.
 1.2.2.2 01-Feb-2002  gmcgarry Pull-up cache ops from -current
 1.2.2.1 14-Nov-2001  gmcgarry file cache_r4k.h was added on branch nathanw_sa on 2002-02-01 04:57:44 +0000
 1.5.2.4 16-Mar-2002  jdolecek Catch up with -current.
 1.5.2.3 11-Feb-2002  jdolecek Sync w/ -current.
 1.5.2.2 10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.5.2.1 23-Dec-2001  thorpej file cache_r4k.h was added on branch kqueue on 2002-01-10 19:45:59 +0000
 1.10.18.1 21-Jun-2006  yamt sync with head.
 1.11.142.1 05-Oct-2016  skrll Sync with HEAD
 1.11.122.1 03-Dec-2017  jdolecek update from HEAD
 1.11.96.3 19-Jan-2012  matt When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses. There are exceptions.
bus_space_handles are now register_t instead of intptr_t. This allows them
to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address. This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs. If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.
 1.11.96.2 27-Dec-2011  matt Make these play nice with modules.
 1.11.96.1 24-Dec-2011  matt Change macros with embedded asm into static inline functions.
Pass in line_size to asm and gas expand to the proper offsets.
 1.10 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.9 11-Jul-2016  matt Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.8 02-Jul-2014  martin branches: 1.8.4; 1.8.6;
Restore file for playstation2 accidently overlooked in the big revitilazation
 1.7 20-Feb-2011  matt branches: 1.7.12;
Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.6 28-Apr-2008  martin branches: 1.6.18; 1.6.22; 1.6.28; 1.6.30;
Remove clause 3 and 4 from TNF licenses
 1.5 24-Dec-2005  perry branches: 1.5.74; 1.5.76; 1.5.78;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.
 1.4 17-Feb-2003  simonb branches: 1.4.18;
No need to protect headers with #ifdef _KERNEL if they're never installed
in /usr/include.
 1.3 23-Nov-2001  uch branches: 1.3.2;
add #ifndef _LOCORE.
 1.2 14-Nov-2001  thorpej branches: 1.2.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.
 1.1 10-Nov-2001  uch branches: 1.1.2;
file cache_r5900.h was initially added on branch thorpej-mips-cache.
 1.1.2.1 10-Nov-2001  uch new cache code for R5900 and playstation2
 1.2.2.2 01-Feb-2002  gmcgarry Pull-up cache ops from -current
 1.2.2.1 14-Nov-2001  gmcgarry file cache_r5900.h was added on branch nathanw_sa on 2002-02-01 04:57:44 +0000
 1.3.2.2 10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.3.2.1 23-Nov-2001  thorpej file cache_r5900.h was added on branch kqueue on 2002-01-10 19:46:00 +0000
 1.4.18.1 21-Jun-2006  yamt sync with head.
 1.5.78.1 16-May-2008  yamt sync with head.
 1.5.76.1 18-May-2008  yamt sync with head.
 1.5.74.1 02-Jun-2008  mjf Sync with HEAD.
 1.6.30.1 05-Mar-2011  bouyer Sync with HEAD
 1.6.28.1 06-Jun-2011  jruoho Sync with HEAD.
 1.6.22.1 05-Mar-2011  rmind sync with head
 1.6.18.1 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.7.12.1 10-Aug-2014  tls Rebase.
 1.8.6.1 05-Oct-2016  skrll Sync with HEAD
 1.8.4.3 03-Dec-2017  jdolecek update from HEAD
 1.8.4.2 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.8.4.1 02-Jul-2014  tls file cache_r5900.h was added on branch tls-maxphys on 2014-08-20 00:03:12 +0000
 1.6 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.5 14-Jun-2020  tsutsui Use proper "page" alignments for R5k Page Invalidate(S) op. PR/55139

According to NEC "User's Manual VR5000, VR1000 64-BIT MICROPROCESSOR
INSTRUCTION" (U12754EJ1V0UMJ1), R5000 Page Invalidate (S) op does
"a page invalidate by doing a burst of 128 line invalidates to
the secondary cache at the page specified by the effective address
generated by the CACHE instruction, which must be page aligned."

This description looks a bit confusing, but "page" used here
implies fixed 32 byte cacheline * 128 lines == 4096 bytes,
not our variable "PAGE_SIZE" used in VM paging ops. Note
the current default PAGE_SIZE for MIPS3 has been changed to 8192.

While here, also define and use proper macro for the "page" and CACHEOP
arg for the R5k Page_Invalidate_S op, as the manual also describes
the cache op field 10111 as "Page Invalidate" for the secondary cache.

No visible regression on Cobalt Qube 2700 (Rm5230) through
whole installation using netbsd-9 based Cobalt RestoreCD/USB.
 1.4 11-Jul-2016  matt branches: 1.4.22;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.3 11-Dec-2005  christos branches: 1.3.96; 1.3.122; 1.3.142;
merge ktrace-lwp.
 1.2 13-Dec-2004  sekiya Add prototype for r5k_sdcache_wbinv_range_index()
 1.1 08-Mar-2003  rafal branches: 1.1.2;
Add support for R5k secondary caches, from code Chris Sekiya sent me a long
time ago, with small tweaks by me. Since the R5k doesn't do VCE, the pmap
still needs to be whacked for R5kSC CPUs to work correctly, but this is a
start.
 1.1.2.1 18-Dec-2004  skrll Sync with HEAD.
 1.3.142.1 05-Oct-2016  skrll Sync with HEAD
 1.3.122.1 03-Dec-2017  jdolecek update from HEAD
 1.3.96.1 19-Jan-2012  matt When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses. There are exceptions.
bus_space_handles are now register_t instead of intptr_t. This allows them
to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address. This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs. If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.
 1.4.22.1 20-Jun-2020  martin Pull up following revision(s) (requested by tsutsui in ticket #965):

sys/arch/mips/include/cache_r5k.h: revision 1.5
sys/arch/mips/mips/cache_r5k_subr.S: revision 1.4
sys/arch/mips/mips/cache_r5k.c: revision 1.21

Use proper "page" alignments for R5k Page Invalidate(S) op. PR/55139

According to NEC "User's Manual VR5000, VR1000 64-BIT MICROPROCESSOR
INSTRUCTION" (U12754EJ1V0UMJ1), R5000 Page Invalidate (S) op does
"a page invalidate by doing a burst of 128 line invalidates to
the secondary cache at the page specified by the effective address
generated by the CACHE instruction, which must be page aligned."

This description looks a bit confusing, but "page" used here
implies fixed 32 byte cacheline * 128 lines == 4096 bytes,
not our variable "PAGE_SIZE" used in VM paging ops. Note
the current default PAGE_SIZE for MIPS3 has been changed to 8192.

While here, also define and use proper macro for the "page" and CACHEOP
arg for the R5k Page_Invalidate_S op, as the manual also describes
the cache op field 10111 as "Page Invalidate" for the secondary cache.

No visible regression on Cobalt Qube 2700 (Rm5230) through
whole installation using netbsd-9 based Cobalt RestoreCD/USB.
 1.7 11-Jul-2016  matt Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.6 28-Apr-2008  martin branches: 1.6.18; 1.6.44; 1.6.64;
Remove clause 3 and 4 from TNF licenses
 1.5 24-Dec-2005  perry branches: 1.5.74; 1.5.76; 1.5.78;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.
 1.4 17-Feb-2003  simonb branches: 1.4.18;
No need to protect headers with #ifdef _KERNEL if they're never installed
in /usr/include.
 1.3 05-Mar-2002  simonb Clean up #ifdef checks a little.
 1.2 14-Nov-2001  thorpej branches: 1.2.2; 1.2.4;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.
 1.1 24-Oct-2001  thorpej branches: 1.1.2;
file cache_tx39.h was initially added on branch thorpej-mips-cache.
 1.1.2.2 30-Oct-2001  uch add #ifndef _LOCORE
 1.1.2.1 24-Oct-2001  thorpej New style cache operations for TX39-style caches. XXX This is not
yet complete.
 1.2.4.3 16-Mar-2002  jdolecek Catch up with -current.
 1.2.4.2 10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.2.4.1 14-Nov-2001  thorpej file cache_tx39.h was added on branch kqueue on 2002-01-10 19:46:00 +0000
 1.2.2.2 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.2.2.1 14-Nov-2001  nathanw file cache_tx39.h was added on branch nathanw_sa on 2002-04-01 07:40:57 +0000
 1.4.18.1 21-Jun-2006  yamt sync with head.
 1.5.78.1 16-May-2008  yamt sync with head.
 1.5.76.1 18-May-2008  yamt sync with head.
 1.5.74.1 02-Jun-2008  mjf Sync with HEAD.
 1.6.64.1 05-Oct-2016  skrll Sync with HEAD
 1.6.44.1 03-Dec-2017  jdolecek update from HEAD
 1.6.18.1 19-Jan-2012  matt When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses. There are exceptions.
bus_space_handles are now register_t instead of intptr_t. This allows them
to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address. This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs. If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.
 1.11 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.10 29-Mar-2012  christos - elide parameter tags
- make argument size_t as appropriate
- add begin/end decls
 1.9 14-Mar-2009  dsl branches: 1.9.12; 1.9.16;
Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.
 1.8 28-Apr-2008  martin branches: 1.8.8; 1.8.14;
Remove clause 3 and 4 from TNF licenses
 1.7 11-Dec-2005  christos branches: 1.7.74; 1.7.76; 1.7.78;
merge ktrace-lwp.
 1.6 06-Nov-2004  christos Don't use "int" to represent lengths; this is what size_t is for. This
does not change the ABI since we don't have 64 bit mips yet.
 1.5 05-Mar-2002  simonb branches: 1.5.14;
ANSIfy.
 1.4 07-Jan-2001  simonb branches: 1.4.4; 1.4.8;
Move prototypes for mips_user_cachectl() and mips_user_cacheflush()
to <mips/cachectl.h>.
 1.3 18-Oct-1997  jonathan branches: 1.3.18;
Prototype ANSI-safe gcc trampoline entrypoint.
 1.2 09-Jun-1997  jonathan Add sys_sysarch() calls for the standard mips userspace cache-control calls.
 1.1 08-Jun-1997  jonathan Declarations for standard MIPS-ABI cacheflush() and cachectl() calls,
as used by g++ trampoline code.
 1.3.18.1 18-Jan-2001  bouyer Sync with head (for UBC+NFS fixes, mostly).
 1.4.8.1 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.4.4.1 16-Mar-2002  jdolecek Catch up with -current.
 1.5.14.1 14-Nov-2004  skrll Sync with HEAD.
 1.7.78.2 04-May-2009  yamt sync with head.
 1.7.78.1 16-May-2008  yamt sync with head.
 1.7.76.1 18-May-2008  yamt sync with head.
 1.7.74.1 02-Jun-2008  mjf Sync with HEAD.
 1.8.14.1 13-May-2009  jym Sync with HEAD.

Commit is split, to avoid a "too many arguments" protocol error.
 1.8.8.1 28-Apr-2009  skrll Sync with HEAD.
 1.9.16.1 05-Apr-2012  mrg sync to latest -current.
 1.9.12.1 17-Apr-2012  yamt sync with head
 1.17 24-Mar-2021  simonb s/depreciated/deprecated/g
 1.16 26-Jul-2020  simonb branches: 1.16.2; 1.16.4;
#define<tab>
Nuke trailing whitespace.
 1.15 18-Mar-2014  christos Make all __ALIGNBYTES macros return the same type (size_t)
 1.14 20-Jan-2012  joerg branches: 1.14.6; 1.14.10;
Change CMSG_SPACE and CMSG_LEN to provide Integer Constant Expressions
again. This was changed in sys/socket.h r1.51 to work around fallout
from the IPv6 aux data migration. It broke the historic ABI on some
platforms. This commit restores compatibility for netbsd32 code on such
platforms and provides a template for future changes to the CMSG_*
alignment. Revert PCC/Clang workarounds in postfix and tmux.
 1.13 14-Dec-2009  matt branches: 1.13.12; 1.13.16;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.12 27-Aug-2006  matt branches: 1.12.60; 1.12.78;
Define _MIPS_BSD_API correctly according to GCC builting __mips_n64,
__mips_n32, and __mips_o64.
 1.11 24-Apr-1999  simonb branches: 1.11.52; 1.11.66; 1.11.70;
Nuke register and remove trailling white space.
 1.10 20-Mar-1999  thorpej branches: 1.10.4;
Garbage-collect.
 1.9 31-Jan-1999  castor Remove genpubassym.cf stuff. The macro _MIPS_BSD_API allows selection of a
64-bit clean compilation model.
 1.8 14-Jan-1999  castor * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.7 04-Nov-1997  thorpej Bug fixes and cleanup from Chris Demetriou <cgd@pa.dec.com>:
- fix _C_LABEL so that it actually works.
- make __RENAME use _C_LABEL.
- fix __RENAME so that it expects an unquoted argument.
- fix __indr_reference and __warn_references so that they
supply their own final semicolon.
- define __warn_references to nothing if not GNU C (required
by the way it's used).

The __warn_references semicolon change has to be made
so that __warn_references can be defined into nothing.
(A ; all by itself isn't a great idea.) The __indr_reference
change was made for consistency.
 1.6 22-Oct-1997  thorpej Implement __RENAME() in <machine/cdefs.h>
 1.5 15-May-1997  jonathan branches: 1.5.8;
Add hooks for definiing kernel RCSId and copyright symbols,
via asm(".section"), for compatibility with Alpha tc and ioasic drivers.

Assumes ELF and binutils-2.8 toolchain.
 1.4 15-Dec-1995  jonathan Change mips __warn_references() macro to use the ELF warning features
in binutils 2.6 and (patched) gcc 2.7.2. Only works with gcc in ANSI C
mode, for now.
 1.3 03-May-1995  mellon Use Alpha cdefs.h
 1.2 23-Mar-1995  jtc Changed name of __weak_reference() to __indr_reference(). They really
are indirect references, and I want to add a real __weak_reference()
macro to <machine/cdefs.h> soon.
 1.1 19-Jan-1995  jtc This file, which will be included by <sys/cdefs.h>, will contain macros
such as __warn_references() and __weak_reference() which are actually
machine dependant. This will make it easier for ports that are being
bootstraped with ELF and ECOFF based toolchains.

This change also introduces a new macro, _C_LABEL(x). _C_LABEL expands
its argument, an identifier, to a character string of the identifier
name as it is represented in an object file.

For most ports, _C_LABEL(x) will expand to "_x", for ELF based ports
_C_LABEL(x) will expand to "x".
 1.5.8.2 04-Nov-1997  thorpej Pull up from trunk: bug fixes and cleaups.
 1.5.8.1 22-Oct-1997  thorpej Pull up from trunk: Implement __RENAME() in <machine/cdefs.h>
 1.10.4.1 21-Jun-1999  thorpej Sync w/ -current.
 1.11.70.1 03-Sep-2006  yamt sync with head.
 1.11.66.1 09-Sep-2006  rpaulo sync with head
 1.11.52.1 30-Dec-2006  yamt sync with head.
 1.12.78.3 23-Aug-2009  matt Use #if defined(__mips_xxx) not #if __mips_xxx
 1.12.78.2 21-Aug-2009  matt Add support for testing instruction sets and cleanup ABI a little.
 1.12.78.1 16-Aug-2009  matt Kill use of _MIPS_BSD_ABI - switch to __mips_<abi>
Use device_t where appropriate.
Remove magic numbers.
 1.12.60.1 11-Mar-2010  yamt sync with head
 1.13.16.1 18-Feb-2012  mrg merge to -current.
 1.13.12.2 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.13.12.1 17-Apr-2012  yamt sync with head
 1.14.10.1 18-May-2014  rmind sync with head
 1.14.6.1 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.16.4.1 03-Apr-2021  thorpej Sync with HEAD.
 1.16.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.2 15-Mar-1999  nisimura - Nuke old leftover; round four. This file has little usefuls, and
target MIPS ports are expected to have 'machine/conf.h' if necessary.
 1.1 24-May-1997  jonathan lint: Create mips/include/conf.h with prototypes for {mem device.
Add 'struct proc *p' 4th arg to mmopen(), mmclose().
Delete unused variable.
 1.135 23-Jul-2023  skrll USE __BIT() for CPUF_* flags. NFCI.
 1.134 31-Jan-2023  andvar fix few typos in comments.
 1.133 14-Aug-2021  ryo Improved the performance of kernel profiling on MULTIPROCESSOR, and possible to get profiling data for each CPU.

In the current implementation, locks are acquired at the entrance of the mcount
internal function, so the higher the number of cores, the more lock conflict
occurs, making profiling performance in a MULTIPROCESSOR environment unusable
and slow. Profiling buffers has been changed to be reserved for each CPU,
improving profiling performance in MP by several to several dozen times.

- Eliminated cpu_simple_lock in mcount internal function, using per-CPU buffers.
- Add ci_gmon member to struct cpu_info of each MP arch.
- Add kern.profiling.percpu node in sysctl tree.
- Add new -c <cpuid> option to kgmon(8) to specify the cpuid, like openbsd.
For compatibility, if the -c option is not specified, the entire system can be
operated as before, and the -p option will get the total profiling data for
all CPUs.
 1.132 29-Mar-2021  simonb Include #include <mips/frame.h> to get lwp_trapframe() definition.
Needed for dtrace.
 1.131 17-Aug-2020  mrg branches: 1.131.2; 1.131.4;
port crash(8) to mips. (most of the kernel side.)

- expose parts of _KERNEL to _KMEMUSER as well
- hide more things for _KERNEL
- avoid DB_MACHINE_COMMANDS in crash(8)
- XXX add mips_label_t for !_KERNEL and use it in the pcb to
avoid conflicting with the ddb/crash one
- enable dumppcb

some changes to make stack trace fail instead of SEGV and
the userland changes to crash itself not part of this change.
 1.130 09-Aug-2020  skrll Don't kcpuset_clone every pmap_tlb_shootdown_bystanders. Instead allocate
a kcpuset_t per cpu_info and use that.
 1.129 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.128 01-Dec-2019  ad Fix false sharing problems with cpu_info. Identified with tprof(8).
This was a very nice win in my tests on a 48 CPU box.

- Reorganise cpu_data slightly according to usage.
- Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc).
- On x86, put some items in their own cache lines according to usage, like
the IPI bitmask and ci_want_resched.
 1.127 21-Nov-2019  ad mi_userret(): take care of calling preempt(), set spc_curpriority directly,
and remove MD code that does the same.
 1.126 16-Sep-2018  skrll interrupt has two 'r's

fix another typo while I'm here (flsah)
 1.125 22-Aug-2018  msaitoh - Cleanup for dynamic sysctl:
- Remove unused *_NAMES macros for sysctl.
- Remove unused *_MAXID for sysctls.
- Move CTL_MACHDEP sysctl definitions for m68k into m68k/include/cpu.h and
use them on all m68k machines.
 1.124 07-Mar-2018  maya branches: 1.124.2;
Adjust ci on the second iteration.

Now a MULTIPROCESSOR+LOCKDEBUG ERLITE reaches userland again
 1.123 22-Jan-2018  maya branches: 1.123.2;
Don't attempt to dereference cpu_infos if ncpus == 0.
Instead use the already initialized cpu_info_store.

(Also, now we assume all ncpus have cpu_infos initialized. seems to work.)

fixes PR port-mips/52940: ERLITE multiprocessor hangs early
 1.122 16-Dec-2017  mrg CPU_INFO_FOREACH() must always iterate at least the boot cpu.
document this in sys/cpu.h and fix the arm and mips versions
to check ncpu is non zero before using it as an iterator max.

this should fix the new assert in init_main.c.
 1.121 31-Oct-2016  skrll branches: 1.121.8;
Pre-allocate some kcpuset_ts so that we don't try and allocate in the
wrong context.
 1.120 16-Jul-2016  macallan move sysctl-related #defines out of #ifdef _KERNEL so userland can see them
now pixman builds again on loongson
 1.119 11-Jul-2016  skrll branches: 1.119.2;
Remove commented #include
 1.118 11-Jul-2016  matt Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.117 11-Jun-2015  matt Define (but not use) separate kernel and user pagetables.
Move to the new names.
 1.116 10-Jun-2015  matt Transition from __cpuset_t to kcpuset_t *. This brings the local pmap one
step closer to uvm/pmap, its eventual replacement. Tested on ERLITE MP kernel.
 1.115 07-Jun-2015  matt assembly no longer include <machine/cpu.h>. Instead MIPS_CURLWP is gotten
from regdef.h and everything else from assym.h. <mips/mips_param.h> no
longer include <machine/cpu.h>
 1.114 06-Jun-2015  matt Reuse the ci_next to hold the nmi exception stack.
 1.113 02-Jun-2015  matt Fix CPU_INFO_FOREACH which had the MULTIPROCESSOR/!MULTIPROCESSOR definitions
reversed.
 1.112 01-Jun-2015  matt Rework cavium support in preparation for MULTIPROCESSOR support
 1.111 28-May-2015  matt Use the lwp_getcpu() inline for curcpu().
 1.110 02-May-2015  matt Don't define MIPS1/MIPS32/MIPS32R2 if ABI is N32 or N64.
 1.109 10-Nov-2013  christos branches: 1.109.6;
fix unused
 1.108 10-Nov-2013  christos use __unused instead of __USE and void cast to mark iterator variable unused
where needed (from phone)
 1.107 28-Feb-2013  macallan branches: 1.107.6;
add sysctl machdep.loongson-mmi to indicate wether Loongson Multimedia
Instructions are supported
mostly for pixman
 1.106 22-Sep-2011  macallan branches: 1.106.2; 1.106.12;
support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory and
DMA buffers with cacheing disabled but things like write combining, relaxed
ordering etc. allowed when the CPU supports it
so far enabled only on Loongson, should work on R1xk and probably newer CPUs
 1.105 16-Aug-2011  matt Add support for the MIPS DSP ASE (as a second PCU).
 1.104 31-Jul-2011  matt Add CPU_MIPS_LOONGSON2 flag (rather defining a CPU_ARCH_MIPS3_LOONGSON2).
This is much less intrusive and disruptive.
 1.103 06-Jul-2011  matt Add

uint32_t kfetch_32(volatile uint32_t *, uint32_t);

which fetches a 32-bit value from a provided addess or returns
an user supplied value on error.
 1.102 02-May-2011  rmind Extend PCU:
- Add pcu_ops_t::pcu_state_release() operation for PCU_RELEASE case.
- Add pcu_switchpoint() to perform release operation on context switch.
- Sprinkle const, misc. Also, sync MIPS with changes.

Per discussions with matt@.
 1.101 14-Apr-2011  cliff - MIPS CPU (COP0) watchpoint support moved from db_machdep.h to cpu.h
- CPU watchpoints are per-cpu; add ci_cpuwatch_count, ci_watchpoint_tab[]
to struct cpuinfo
 1.100 06-Apr-2011  matt Fix LKM/MODULAR case.
 1.99 15-Mar-2011  matt Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.
 1.98 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.97 26-Jan-2011  pooka Add support for the Extensible MIPS ("eMIPS") platform. The
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the
Giano system simulator.

eMIPS is a platform developed at Microsoft Research for researching
reconfigurable computing. eMIPS allows dynamic loading and scheduling
of application-specific circuits for the purpose of accelerating
computations based on the current workload.

NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research
by Alessandro Forin and Neil Pittman. Microsoft Corporation has
donated full copyright to The NetBSD Foundation.

Platform support for eMIPS is the first part of Microsoft's
contribution. The second part includes the hardware accelerator
framework and will be proposed on tech-kern soon.
 1.96 22-Dec-2010  nisimura branches: 1.96.2; 1.96.4;
PROC_PC() should have been changed to LWP_PC().
 1.95 23-Jan-2010  mrg branches: 1.95.4;
rename pridtab{}::cpu_name to cpu_displayname.

should fix a build error reported by he@.
 1.94 14-Dec-2009  matt Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.93 27-Nov-2009  rmind - Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.
 1.92 21-Nov-2009  rmind Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.
 1.91 21-Oct-2009  rmind Remove uarea swap-out functionality:

- Addresses the issue described in PR/38828.
- Some simplification in threading and sleepq subsystems.
- Eliminates pmap_collect() and, as a side note, allows pmap optimisations.
- Eliminates XS_CTL_DATA_ONSTACK in scsipi code.
- Avoids few scans on LWP list and thus potentially long holds of proc_lock.
- Cuts ~1.5k lines of code. Reduces amd64 kernel size by ~4k.
- Removes __SWAP_BROKEN cases.

Tested on x86, mips, acorn32 (thanks <mpumford>) and partly tested on
acorn26 (thanks to <bjh21>).

Discussed on <tech-kern>, reviewed by <ad>.
 1.90 26-May-2008  tsutsui branches: 1.90.16;
Remove all initialization of obsolete ci_divisor_recip in
mips struct cpu_info and related macroes.
The member was prepared for a hack in MD microtime(9) implementation
but it has been superseded by MI timecounter(9).
 1.89 27-Feb-2008  xtraeme branches: 1.89.2; 1.89.4; 1.89.6;
Remove CTL_MACHDEP_NAMES, it's not used anywhere.

Ok by martin@.
 1.88 09-Jan-2008  wiz branches: 1.88.2; 1.88.6;
Fix typo in macro name and comments.
 1.87 04-Dec-2007  he branches: 1.87.4;
Define the various MIPS* CPU macros also for _STANDALONE in addition
to for _LKM, so that we don't #error out in that case.

This fixes the build for sgimips boot programs, which wants to use
libkern, which now includes the atomic stuff, which for the mips ports
ends up including this file.

"simonb said OK"
 1.86 03-Dec-2007  ad branches: 1.86.2;
Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.
 1.85 19-Oct-2007  ad branches: 1.85.2;
Merge from vmlocking: add CPU_INFO_ITERATOR.
 1.84 17-Oct-2007  garbled Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.83 04-Aug-2007  ad branches: 1.83.2; 1.83.6;
Add ci_cpuid where it's missing.
 1.82 17-May-2007  yamt branches: 1.82.2; 1.82.4; 1.82.8;
merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.
 1.81 21-Feb-2007  simonb branches: 1.81.4; 1.81.6; 1.81.12;
Fix a tyop.
 1.80 16-Feb-2007  oster branches: 1.80.2;
Fix typo from newlock2 merge, allowing MIPS64 to build again.
 1.79 16-Feb-2007  ad Remove spllowersoftclock() and CLKF_BASEPRI(), and always dispatch callouts
via a soft interrupt. In the near future, softclock will be run from process
context.
 1.78 09-Feb-2007  ad Merge newlock2 to head.
 1.77 23-Mar-2006  tsutsui branches: 1.77.8;
include/cpu.h: make sure MIPS3_PLUS properly defined even if _LOCORE is defined
mips/fp.S: include <mips/cpu.h> for #ifdef MIPS3_PLUS

Closes PR port-mips/27298.
 1.76 24-Dec-2005  perry branches: 1.76.4; 1.76.6; 1.76.8; 1.76.10; 1.76.12;
bare asm -> __asm
 1.75 11-Dec-2005  christos merge ktrace-lwp.
 1.74 05-Nov-2005  tsutsui Make MIPS3_PG_SHIFT a variable and initialize it accordingly
in mips_vector_init() if options MIPS3_4100 is specified
so that kernels which have options MIPS3_4100 also work
on other MIPS3 CPUs.

XXX: now should we rename options MIPS3_4100 to options ENABLE_MIPS_R4100,
XXX: or just make MIPS3_PG_SHIFT always a variable?
 1.73 22-Sep-2004  yamt branches: 1.73.10; 1.73.12; 1.73.18;
move some per-cpu data definitions to MI place so that they can be modified
without touching all ports. discussed on tech-kern@.
 1.72 04-Jan-2004  jdolecek Rearrange process exit path to avoid need to free resources from different
process context ('reaper').

From within the exiting process context:
* deactivate pmap and free vmspace while we can still block
* introduce MD cpu_lwp_free() - this cleans all MD-specific context (such
as FPU state), and is the last potentially blocking operation;
all of cpu_wait(), and most of cpu_exit(), is now folded into cpu_lwp_free()
* process is now immediatelly marked as zombie and made available for pickup
by parent; the remaining last lwp continues the exit as fully detached
* MI (rather than MD) code bumps uvmexp.swtch, cpu_exit() is now same
for both 'process' and 'lwp' exit

uvm_lwp_exit() is modified to never block; the u-area memory is now
always just linked to the list of available u-areas. Introduce (blocking)
uvm_uarea_drain(), which is called to release the excessive u-area memory;
this is called by parent within wait4(), or by pagedaemon on memory shortage.
uvm_uarea_free() is now private function within uvm_glue.c.

MD process/lwp exit code now always calls lwp_exit2() immediatelly after
switching away from the exiting lwp.

g/c now unneeded routines and variables, including the reaper kernel thread
 1.71 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.70 17-Jan-2003  thorpej branches: 1.70.2;
Merge the nathanw_sa branch.
 1.69 17-Dec-2002  simonb Add support for caches where the data cache is fully coherent, and
either requires flushing either only when the I cache ops are used
or not at all. Currently only used by MIPS32/MIPS64 cache code.
 1.68 24-Nov-2002  simonb Move the curpcb and segbase extern decls to cpu.h to better group together
what will need to change for SMP.
Hide 'struct cpu_info' and some macros in #ifdef _KERNEL/#endif.
 1.67 05-Aug-2002  shin ++CPU_MAXID for CPU_LLSC.
 1.66 04-Aug-2002  gmcgarry Add sysctl variable to represent native CPU support for LL/SC instructions.
 1.65 23-Jun-2002  manu Typo
 1.64 04-Jun-2002  simonb 3 ports are now using the reciprocal count divisor code now, move it
to <mips/cpu.h>, and add MIPS_SET_CI_RECIPRICAL and MIPS_COUNT_TO_MHZ
macros to use it.
 1.63 01-Jun-2002  simonb Add two new cpu capability flags: CPU_MIPS_USE_WAIT for CPUs that use a
"wait" instruction based cpu_idle(), and CPU_MIPS_NO_WAIT for specific
CPUs that don't use this (applicable to mips32/64 mainly).
 1.62 05-Apr-2002  simonb branches: 1.62.2;
Add a "CPU_MIPS_DOUBLE_COUNT" flag for CPUs where the cp0 count register
ticks over at half the CPU clock speed, and set this flag for the known
CPUs with this behaviour. Better names for this flag gratefully accepted!

Also adjust comment about known R4000/R4400 revisions.
 1.61 03-Apr-2002  simonb Add prototype for badaddr64().
 1.60 19-Mar-2002  simonb Define all CPU types if _LKM is defined; fixes problems building LKM's
as noted by FUKAUMI Naoki on port-mips.
 1.59 06-Mar-2002  simonb Add a field for the reciprocal of the divisor delay for use by microtime.
 1.58 05-Mar-2002  simonb Add support for MIPS32 and MIPS64 architectures:
- Clean up (somewhat) mips1 vs mips3+ configuration.
XXX: this is still quite messy.
- Add cpu frequency info to struct cpu_info.
- ANSIfy.
 1.57 14-Nov-2001  thorpej branches: 1.57.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.
 1.56 16-Oct-2001  uch branches: 1.56.2;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.
 1.55 04-Sep-2001  simonb Oops, <sys/sched.h> isn't asm safe, move inside an "#ifndef LOCORE" block.
 1.54 04-Sep-2001  simonb May as well include <mips/cpuregs.h> in <mips/cpu.h> once rather than
in every MIPS port's <machine/cpu.h>.
 1.53 04-Sep-2001  simonb Centralise struct cpu_info declaration and related info to <mips/cpu.h>.
 1.52 14-Jun-2001  thorpej branches: 1.52.2;
Don't need to prototype child_return() here, it's in <sys/proc.h>.
 1.51 11-Jun-2001  wiz Fix various misspellings of compatible/compatibility.
 1.50 14-Jan-2001  thorpej branches: 1.50.2;
Make the astpending flag per-process.
 1.49 14-Jan-2001  thorpej - Make ast() loop around astpending; it's possible for a new
AST to be posted when delivering signals, or after a process
is preempted.
- Move all signal posting to ast(). userret() is now a one-liner.
 1.48 11-Jan-2001  thorpej Mmm, dependency problems. Add a cast to make PROC_PC() actually
work.
 1.47 11-Jan-2001  thorpej Modeled after mycroft's changes to the Alpha port, add PROC_PC() to
get profiling out of userret(), and move the preemption check to ast().
 1.46 05-Oct-2000  cgd always have to declare cpu_arch and the related constants (since setting
it isn't conditionalized). (d'oh!)
 1.45 05-Oct-2000  cgd tweak cpu_arch. Eliminate all direct checks of it (making them
use the macro CPUISMIPS3 -- which is badly misnamed), and set it
from #defines named CPU_ARCH_N (where N is 1..5, 32, 64).
 1.44 25-Aug-2000  thorpej Make need_resched() take a "struct cpu_info *" argument. This
causes gives a primitive form of processor affinity. Its use in
roundrobin() still needs some work.
 1.43 13-Jul-2000  jeffs Add comment that overriding the sysctl defines in machine/cpu.h
breaks userland binary compatiabiltiy between mips ports. Move
check down so common values are always defined here.
 1.42 11-Jul-2000  jeffs Only define machdep sysctls if CPU_MAXID is not defined by machine/cpu.h.
This lets mips ports have additional machdep sysctl. Define CPUISMIPS3
for MIPS1+MIPS2 as cpu_arch >= 3 to support mips4. Add cpu_intr()
prototype so this is defined in one place.
 1.41 30-May-2000  nisimura branches: 1.41.2;
savefpregs() and loadfpregs() are defined in mips_machdep.c
 1.40 26-May-2000  thorpej branches: 1.40.2;
First sweep at scheduler state cleanup. Collect MI scheduler
state into global and per-CPU scheduler state:

- Global state: sched_qs (run queues), sched_whichqs (bitmap
of non-empty run queues), sched_slpque (sleep queues).
NOTE: These may collectively move into a struct schedstate
at some point in the future.

- Per-CPU state, struct schedstate_percpu: spc_runtime
(time process on this CPU started running), spc_flags
(replaces struct proc's p_schedflags), and
spc_curpriority (usrpri of processes on this CPU).

- Every platform must now supply a struct cpu_info and
a curcpu() macro. Simplify existing cpu_info declarations
where appropriate.

- All references to per-CPU scheduler state now made through
curcpu(). NOTE: this will likely be adjusted in the future
after further changes to struct proc are made.

Tested on i386 and Alpha. Changes are mostly mechanical, but apologies
in advance if it doesn't compile on a particular platform.
 1.39 15-Apr-2000  soda remove following symbols which became unnecessary in recent cpu_intr() change:
mips_hardware_intr
MIPS3_INTERNAL_TIMER_INTERRUPT
mips3_intr_cycle_count
mips3_timer_delta
 1.38 11-Apr-2000  nisimura Introduce cpu_intr() whose body is now provided by target ports in
their own ways. Ugly fixup #define in machine/intr.h have gone.
mips_hardware_intr global variable patch work has gone.
 1.37 28-Mar-2000  simonb Move fpcurproc declaration to <mips/cpu.h>.
 1.36 24-Mar-2000  soren Revert previous.
 1.35 24-Mar-2000  soren Move sysctl definitions from arch/mips to arch/foo.
 1.34 07-Mar-2000  soren Garbage collect MIPS_SR_INT_ENAB/MIPS_SR_INT_ENA_CUR definitions.
 1.33 09-Jan-2000  simonb Use the badaddr() prototype in mips/include/cpu.h by including
<machine/cpu.h> in mips/include/mips_param.h. Remove duplicate
badaddr() prototypes from some pmax header files.
 1.32 10-Aug-1999  thorpej branches: 1.32.2;
Define cpu_number() as discussed on tech-smp.
 1.31 20-May-1999  lukem * convert to using MI allocsys(). most ports were using an MD allocsys(),
although a couple still used the old pre-4.4-lite (?) mechanism.
* use format_bytes() to format the various printf()s that print out memory sizes
 1.30 18-May-1999  nisimura - Move MachSetPID(1) call to pmap_bootstrap() adajacent to kernel pmap
initialization code.
- Abandon mips_init_proc0() and do the 4 lines straightly in MD mach_init().
- Restore a block of code accidentally lost in prevous commit.
- Change the term 'tlbpid' to a MIPS3 nomenclature 'asid'.
- Hide PTE size exposures by symbolic names in locore.S
 1.29 23-Mar-1999  simonb branches: 1.29.4;
Add CPU_BOOTED_KERNEL to CTL_MACHDEP definition.
 1.28 14-Jan-1999  castor * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.27 11-Nov-1998  thorpej Changes to support fork_kthread():
- cpu_set_kpc() now takes void *arg third argument, passed to the
entry point.
- cpu_fork() allows parent to be non-curproc iff parent is proc0.
When forking non-curproc, assume its state has already been saved.
- Adjust various pieces of machine-dependent code to account of all of this.
 1.26 28-Oct-1998  jonathan Add `struct proc;' to keep egcs warnings happy in userland.
XXX why are kernel prototypes visible here at all?
 1.25 11-Sep-1998  jonathan branches: 1.25.2;
Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.

* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.
 1.24 25-Feb-1998  thorpej Prototype allocsys(), mips_init_msgbuf(), and mips_init_proc0().
 1.23 19-Feb-1998  thorpej Prototype dumpsys() and savectx().
 1.22 22-Jun-1997  jonathan * Change Sprite MACH_xxx prefix to MIPS_xxx.

* Use standard mips terminology (xxx_KSEG0, xxx_KSEG1) instead of the
(more meaningful) Sprite names (xxx_CACHED, xxx_UNCACHED).
 1.21 21-Jun-1997  jonathan More mips1/mips3 changes to cpuregs.h and psl.h:
* cpuregs.h:
Delete unused VMMACH_ names (e.g., duplicates of PTE bits in pte.h).
Change remaining VMMACH_xxx names to MIPS1_xxx or MIPS3_xx.
Fold remaining compile-time definitions into a single #ifdef MIPS3.

* Use MIPS1_ names in locore_r2000.S, mips3_ names in locore_r4000.S

* Garbage-collect MachHitFlushDCache()

* psl.h:
use MIPS1_, MIPS3_ symbolic names for Cause register bits.
change _R3K to MIPS1_, _R4K to MIPS3. Conditionalize for mips1 only,
mips3 only, or when both are defined, use runtime CPUISMIPS3 test.
 1.20 16-Jun-1997  jonathan Changes for configuring both MIPS1 and MIPS3, from a merge of
similar design and code by Jason Thorpe and Jonathan Stone.

NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.

mips/include/cpu.h:
Add CPUISMIPS3 for run-time tests of what CPU architecture level
we're running on.

mips/include/locore.h:
Add declarations of locore cache-size variables for ref/def toolchain.

mips/include/mips1_pte.h:
mips1 TLB bit definitions.

mips/include/mips3_pte.h:
mips3 TLB bit definitions.

mips/include/pte.h:
define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
that expand to CPU constants if only one CPU arch is configured,
or to inline functions if both MIPS1 and MIPS3 are configured.

mips/mips/locore_r2000.S:
Use MIPS1_PG_xxx constants inside mips1-specific code.

mips/mips/locore_r4000.S:
Use MIPS3_PG_xxx constants inside mips3-specific code.

mips/mips/locore.S:
Use MIPS1_PG_xxx constants inside mips3-specific code.
Use MIPS1_PG_xxx constants inside mips1-specific code.
(Needs more work!)

mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
Use MIPS3_PG_xxx constants inside mips3-specific functions,
and MIPS1_PG_XXX inside mips1-specific code.
Otherwise, use mips_pg_XXX_bit() macros where they apply,
and use "if (CPUISMIPS3) { ... } else {... }" where they don't.

mips/mips/mips_machdep.c:
Import Michael Hitch's fixes from the pmax locore-init code
into mips_vector_init().

pmax/pmax/machdep.c:
Use generic mips_vector_init() locore vector-init function.
 1.19 16-Jun-1997  jonathan Garbage-collect redundant declarations:
mips/include/locore.h:
Add prototypes for HitFlushDCache() functions. Moe cpu_prid definition here.
mips/include/cpu.h:
remove cpu_prid definition.
pmax/pmax/machdep.c:
remove local protoypes of HitFlushDCache() functions.
mips/mips/vm_machdep.c, mips/mips/vm_machdep.c::
remove local protoypes of HitFlushDCache() functions.
 1.18 16-Jun-1997  jonathan Yet more merging:
* Move declaration of locore communcation variables (CPU family,
cache sizes, etc) to mips/include/locore.h. Delete from
pmax/include/cpu.h and older versions from pica/include/cpu.h.

* Move definitions of CLKF_BASEPRI, CLKF_USERMODE to mips/include/cpu.
* Delete duplicate definitions in pica/include/cpu.h, pmax/include/cpu.h.
 1.17 16-Jun-1997  jonathan Garbage-collect #include <machine/machConst.h>.
 1.16 15-Jun-1997  mhitch From Toru Nishimura: _FORKBRAINDAMAGE is gone, user process entered through
proc_trampoline().
 1.15 23-Mar-1996  jonathan fix case typo: CLKF_BASEPRI_R4k to _R4K
 1.14 23-Mar-1996  jonathan Factor out r3000 versus r4000 differences (CLKF_USERMODE() and CLKF_BASEPRI()),
provide r3k and r4k versions of each, and move to sys/arch/mips/include.

Note in comments where each mips-based port should provide
definitions in its own cpu.h after including this file.
 1.13 19-Mar-1996  jonathan Add additional mips CPU and FPU ids from Pica port:
IDT r3081 family, r4600, MIPS-IV architecture, others.
 1.12 28-Jun-1995  cgd remove unused cpu_exec() definitions. moved "broken swap" markers, for
ports that still need it, to types.h.
 1.11 05-May-1995  cgd define BROKEN_SWAP and/or cpu_swapout as appropriate.
 1.10 22-Apr-1995  christos - added sunos_machdep.c for sun3, atari, amiga and mac68k.
- changed machdep.c and trap.c to use struct emul.
- remove ep_setup references.
- added struct emul to all emulations.
 1.9 28-Mar-1995  jtc KERNEL -> _KERNEL
 1.8 26-Oct-1994  cgd new RCS ID format.
 1.7 02-Jun-1994  glass fix a few integration bugs, add vmfault debugging, more ultrix stuff
 1.6 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.5 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.4 15-Jan-1994  deraadt intrframe -> clockframe
 1.3 14-Jan-1994  deraadt some pmax updating (Terry Friedrichsen is helping on this now).
 1.2 15-Oct-1993  deraadt update from rick, tarfile of Oct 11 10:46
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.25.2.4 16-Nov-1998  nisimura - Step forward to MIPS64 support. Incorporate partially Caster Fu's
patches. Still some work is missing to satisfy his QED 5230 port.

- More symbolic definitions in genassym.cf which improve possible 64bit-ness
of locore_mips{1,3}.S.

- Fix mips3 L1 cache line size detection logic in cpuarch.h as pointed by
Caster.

- Fix a bug in proc_trampoline() code in locore_mips3.S as pointed by Caster.

- Replace vm_offset_t with vaddr_t/paddr_t entirely. Note that
NetBSD/newsmips has purged vm_offset_t too.

- Synchronize various files according to recent changes made in main trunk.
 1.25.2.3 14-Nov-1998  drochner fix egcs warnings
kdbpeek() prototype cleanup, ala PR port-mips/5252
 1.25.2.2 30-Oct-1998  nisimura - Make pm.c monochrome-aware and compilable with UVM.
- Make trap.c compilable with UVM.
- Place #ifdef _KERNEL guard in cpu.h
- Make asm.h more MIPS standard-alike while retaining current definitions.
 1.25.2.1 15-Oct-1998  nisimura - cpuregs.h was modifed a bit, then renamed with cpuarch.h.
- mips_cpu.h has gone.
- CPU's register mnemonics in regdef.h is now a part of asm.h.
 1.29.4.1 21-Jun-1999  thorpej Sync w/ -current.
 1.32.2.2 18-Jan-2001  bouyer Sync with head (for UBC+NFS fixes, mostly).
 1.32.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.40.2.1 22-Jun-2000  minoura Sync w/ netbsd-1-5-base.
 1.41.2.1 19-Jul-2000  jeffs Pull up cpu_intr() prototype + platform dependent machdeps.
(approved by thorepj).
 1.50.2.1 21-Jun-2001  nathanw Catch up to -current.
 1.52.2.5 06-Sep-2002  jdolecek sync kqueue branch with HEAD
 1.52.2.4 23-Jun-2002  jdolecek catch up with -current on kqueue branch
 1.52.2.3 16-Mar-2002  jdolecek Catch up with -current.
 1.52.2.2 10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.52.2.1 13-Sep-2001  thorpej Update the kqueue branch to HEAD.
 1.56.2.1 11-Nov-2001  shin delete obsolete variables.

mips_L2CacheSize
mips_L2CacheIsSnooping
mips_L2CacheMixed
 1.57.2.13 19-Dec-2002  thorpej Sync with HEAD.
 1.57.2.12 11-Dec-2002  thorpej Sync with HEAD.
 1.57.2.11 13-Aug-2002  nathanw Catch up to -current.
 1.57.2.10 01-Aug-2002  nathanw Catch up to -current.
 1.57.2.9 02-Jul-2002  nathanw Whitespace.
 1.57.2.8 24-Jun-2002  nathanw Curproc->curlwp renaming.

Change uses of "curproc->l_proc" back to "curproc", which is more like the
original use. Bare uses of "curproc" are now "curlwp".

"curproc" is now #defined in proc.h as ((curlwp) ? (curlwp)->l_proc) : NULL)
so that it is always safe to reference curproc (*de*referencing curproc
is another story, but that's always been true).
 1.57.2.7 20-Jun-2002  nathanw Catch up to -current.
 1.57.2.6 17-Apr-2002  nathanw Catch up to -current.
 1.57.2.5 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.57.2.4 08-Jan-2002  nathanw Catch up to -current.
 1.57.2.3 08-Dec-2001  thorpej Add a cpu_proc_fork(), called from uvm_proc_fork(), which takes care
of machine-dependent handling a fork() time (this is different from
forking the actual context in an LWP world). #define it away on
platforms which do not need it.

Problem noted by Gregory McGarry.
 1.57.2.2 17-Nov-2001  wdk Inital support for Scheduler Activation on MIPS architectures.

Compiles for sgimips. Needs more work in locore.S in order to reach
single user and beyond.
 1.57.2.1 14-Nov-2001  wdk file cpu.h was added on branch nathanw_sa on 2001-11-17 23:43:41 +0000
 1.62.2.3 31-Aug-2002  gehenna catch up with -current.
 1.62.2.2 16-Jul-2002  gehenna catch up with -current.
 1.62.2.1 14-Jul-2002  gehenna catch up with -current.
 1.70.2.5 10-Nov-2005  skrll Sync with HEAD. Here we go again...
 1.70.2.4 24-Sep-2004  skrll Sync with HEAD.
 1.70.2.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.70.2.2 18-Sep-2004  skrll Sync with HEAD.
 1.70.2.1 03-Aug-2004  skrll Sync with HEAD
 1.73.18.1 19-Apr-2006  tron Pull up following revision(s) (requested by tsutsui in ticket #1259):
sys/arch/mips/mips/fp.S: revision 1.30
sys/arch/mips/include/cpu.h: revision 1.77
include/cpu.h: make sure MIPS3_PLUS properly defined even if _LOCORE is defined
mips/fp.S: include <mips/cpu.h> for #ifdef MIPS3_PLUS
Closes PR port-mips/27298.
 1.73.12.7 17-Mar-2008  yamt sync with head.
 1.73.12.6 21-Jan-2008  yamt sync with head
 1.73.12.5 07-Dec-2007  yamt sync with head
 1.73.12.4 27-Oct-2007  yamt sync with head.
 1.73.12.3 03-Sep-2007  yamt sync with head.
 1.73.12.2 26-Feb-2007  yamt sync with head.
 1.73.12.1 21-Jun-2006  yamt sync with head.
 1.73.10.1 19-Apr-2006  tron Pull up following revision(s) (requested by tsutsui in ticket #1259):
sys/arch/mips/mips/fp.S: revision 1.30
sys/arch/mips/include/cpu.h: revision 1.77
include/cpu.h: make sure MIPS3_PLUS properly defined even if _LOCORE is defined
mips/fp.S: include <mips/cpu.h> for #ifdef MIPS3_PLUS
Closes PR port-mips/27298.
 1.76.12.1 28-Mar-2006  tron Merge 2006-03-28 NetBSD-current into the "peter-altq" branch.
 1.76.10.1 19-Apr-2006  elad sync with head - hopefully this will work
 1.76.8.1 01-Apr-2006  yamt sync with head.
 1.76.6.1 22-Apr-2006  simonb Sync with head.
 1.76.4.1 09-Sep-2006  rpaulo sync with head
 1.77.8.2 11-Jan-2007  ad Checkpoint work in progress.
 1.77.8.1 29-Dec-2006  ad Checkpoint work in progress.
 1.80.2.3 18-Apr-2007  ad - Further adaptations to MIPS for the yamt-idlelwp branch.
- Make curlwp a register variable on MIPS.
 1.80.2.2 21-Mar-2007  ad Initial changes for MIPS. Not yet working under gxemul.
 1.80.2.1 27-Feb-2007  yamt - sync with head.
- move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.
 1.81.12.2 03-Oct-2007  garbled Sync with HEAD
 1.81.12.1 22-May-2007  matt Update to HEAD.
 1.81.6.1 11-Jul-2007  mjf Sync with head.
 1.81.4.3 03-Dec-2007  ad Sync with HEAD.
 1.81.4.2 15-Jul-2007  ad Get pmax working.
 1.81.4.1 27-May-2007  ad Sync with head.
 1.82.8.3 09-Dec-2007  jmcneill Sync with HEAD.
 1.82.8.2 26-Oct-2007  joerg Sync with HEAD.

Follow the merge of pmap.c on i386 and amd64 and move
pmap_init_tmp_pgtbl into arch/x86/x86/pmap.c. Modify the ACPI wakeup
code to restore CR4 before jumping back into kernel space as the large
page option might cover that.
 1.82.8.1 04-Aug-2007  jmcneill Sync with HEAD.
 1.82.4.1 15-Aug-2007  skrll Sync with HEAD.
 1.82.2.2 07-Aug-2007  matt Sync with HEAD.
 1.82.2.1 18-Jul-2007  matt Make sure to copy p_md in cpu_proc_fork. Generate an error if MULTIPROCESSOR
is defined.
 1.83.6.1 25-Oct-2007  bouyer Sync with HEAD.
 1.83.2.3 23-Mar-2008  matt sync with HEAD
 1.83.2.2 09-Jan-2008  matt sync with HEAD
 1.83.2.1 06-Nov-2007  matt sync with HEAD
 1.85.2.2 18-Feb-2008  mjf Sync with HEAD.
 1.85.2.1 08-Dec-2007  mjf Sync with HEAD.
 1.86.2.1 08-Dec-2007  ad Sync with head.
 1.87.4.1 10-Jan-2008  bouyer Sync with HEAD
 1.88.6.2 02-Jun-2008  mjf Sync with HEAD.
 1.88.6.1 03-Apr-2008  mjf Sync with HEAD.
 1.88.2.1 24-Mar-2008  keiichi sync with head.
 1.89.6.1 23-Jun-2008  wrstuden Sync w/ -current. 34 merge conflicts to follow.
 1.89.4.2 11-Mar-2010  yamt sync with head
 1.89.4.1 04-May-2009  yamt sync with head.
 1.89.2.1 04-Jun-2008  yamt sync with head
 1.90.16.46 04-Aug-2012  matt Make MIPS use a multi-level page table for the kernel address space.
(just like the user address does). XXX fix mips1
 1.90.16.45 09-Jul-2012  matt Use a spinlock to protect the segtab queues. Use union pmap_segmap and
pmap_segmap_t to track -HEAD. Use KERNEL_PID for the same reason.
 1.90.16.44 27-Feb-2012  matt Count all traps types.
 1.90.16.43 13-Feb-2012  matt Add mm_md_direct_mapped_virt (inverse of mm_md_direct_mapped_phys). Add a
third argument, vsize_t *, which, if not NULL, returns the amount of virtual
space left in that direct mapped segment.
Get rid most of the individual direct_mapped assert and use the above
routines instead.
Improve kernel core dump code.
 1.90.16.42 13-Feb-2012  matt Fix emulation to not panic when it encounters something it doesn't like.
(so running crashme won't crash the system).
Centralize the trapsignal processing so we can print out the trap info if
so desired.
Add a machdep.printfataltraps sysctl knob.
 1.90.16.41 28-Jan-2012  matt Add mm_md_direct_mapped_phys from current.
 1.90.16.40 19-Jan-2012  matt When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses. There are exceptions.
bus_space_handles are now register_t instead of intptr_t. This allows them
to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address. This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs. If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.
 1.90.16.39 23-Dec-2011  matt Make CPUISMIPS3 deal with MIPS32R2 and MIPS64R2
Add mips_num_tlb_asids.
Allow a caller to cpu_identify to supply a cpuname (or NULL).
 1.90.16.38 03-Dec-2011  matt Rework things a bit for the XLR/XLS/XLP TLB. Before dealing with the TLB when
MP on the XL?, disable interrupts and take out a lock to prevent concurrent
updates to the TLB. In the TLB miss and invalid exception handlers, if the
lock is already owned by another CPU, simply return from the exception and
let it continue or restart as appropriate. This prevents concurrent TLB
exceptions in multiple threads from possibly updating the TLB multiple times
for a single address.
 1.90.16.37 26-May-2011  matt Add MIPS64_RMIXL (XLR/XLS) and MIPS64R2_RMIXL (XLP). This allows the kernel
to treat this special which is needed for MP support. When accessing the TLB,
always lock the TLB before hand. If in the miss handlers, the TLB is already
locked let trap deal with the exeception.
 1.90.16.36 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.90.16.35 08-Feb-2011  cliff - fix cpu_number() define for non- MULTIPROCESSOR case
 1.90.16.34 08-Feb-2011  cliff - re-define cpu_number() to now mean ci_index instead of ci_cpuid
- re-define CPU_IS_PRIMARY() to use CPUF_PRIMARY instead of ci_cpuid
 1.90.16.33 05-Feb-2011  cliff - include cpuset.h, we're using CPUSET_* macros now for cpus_running, cpus_paused, etc.
those data are now type mips_cpuset_t.
- move opt_* includes up above sys/* includes
- add declarations for IPI broadcast, multicast functions
- add declarations for cpu halt, pause, resume, etc functions useful for ddb
 1.90.16.32 01-Sep-2010  matt Fill cpu_data cpu_{node,core,smt}_id for RMI.
 1.90.16.31 18-Aug-2010  matt *** empty log message ***
 1.90.16.30 16-Aug-2010  matt Support user VAs > 4GB (but less than 1TB for now) using a 3 level page table.
Add debug code to help find redundant faults (PMAP_FAULTINFO).
 1.90.16.29 09-Jun-2010  matt Add support for setting/clearing PK_32 on _LP64 kernels. Make cpu_proc_fork
a real function and add it to vm_machdep.c and let it copy PK_32 on fork.
Properly clear/set PK_32 depending on ABI in setregs. Lack of PX_32 use
tracked down by Cliff Neighbors. [Ya! ps now works!]
 1.90.16.28 21-Mar-2010  cliff - add ci_next_cp0_clk_intr, ci_count_compare_evcnt, ci_count_compare_missed_evcnt
to struct cpu_info, for per-CPU count/compare clock programming
- add ci_request_ipis to struct cpu_info to allow passing IPI tags
on systems where hardware does not provide such feature; use atomic ops for this.
- declaration of mips_vector_init was moved from here to mips/include/locore.h
 1.90.16.27 11-Mar-2010  matt Add MP-aware icache support.
 1.90.16.26 11-Mar-2010  matt Add ci_softc member to cpu_info.
 1.90.16.25 01-Mar-2010  matt Add secondary processor spinup support (cpu_trampoline is in locore_mips3.S).
Nuke lse_boot_secondary_processors (not needed).
Move cpu_info_store to cpu_subr.C
 1.90.16.24 28-Feb-2010  matt Split FPU support into separate file and keep internals private to that file.
Make it MPSAFE. Change interface to be very similar to what's used on other
architectures.
Add l_md.md_fpcpu to mdlwp (needed for MPSAFE)
Move pridtab from <mips/cpu.h> to <mips/locore.h>
Add initial common IPI dispatcher.
Split cpu_* routines from mips_machdep.c into cpu_subr.c
Add cpu_startup_common which has the code replicated in half-dozen
plus machdep.c files.
 1.90.16.23 27-Feb-2010  matt Add mipsXX_tlb_enter which modifies/sets a specific TLB entry with a new
mapping (useful for wired TLB entries).
Add mips_fixup_exceptions which will walk through the exception vectors
and allows the fixup of any cpu_info references to be changed to a more
MP-friendly incarnation.
Define a common fixup method to use a wired TLB entry at -PAGE_SIZE allowing
direct loads using a negative based from the zero register.
Change varible pmap_tlb_info t pmap_tlb0_info.
 1.90.16.22 25-Feb-2010  matt Remove ci_curpm since it isn't used.
 1.90.16.21 23-Feb-2010  matt Make sure <mips/locore.h> is not included by MI code.
Add send_ipi and cpu_offline_md hooks to locoresw.
Add MP support to pmap (pvlist locking, tlb locking).
Add TLB shootdown support (see comment at the top of mips/pmap_tlb.c).
Add mipsXX_tlb_invalidate_globals routine
 1.90.16.20 16-Feb-2010  matt Add __HAVE_PREEMPTION support for NetBSD/mips. Kill IPL_PREEMPT since it
isn't needed.
 1.90.16.19 15-Feb-2010  matt Completely redo how interrupts and SPL are handled in NetBSD/mips.
[XXX locore_mips1.S still needs to adapted.]

Nested interrupts now work. Except for MIPS_SOFT_MASK and MIPS_SR_INT_IE,
how interrupts work is completely abstracted. spl is handled through the
mips_splsw table. Direct manipulation of the status register is no longer
done (except for MIPS_SR_INT_IE). A new <mips/intr.h> contains the common
IPL/IST/spl* definitions for all ports.

Interrupt delivery is completely different. Clock interrupts may interrupt
device interrupts. ci_idepth is now handled by the caller of cpu_intr as
are softints (both can be optimized/simplified in the case of interrupts of
usermode code). cpu_intr has new arguments and now get called at IPL_HIGH
with MIPS_SR_INT_IE set and its logic is:

void
cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
int ipl;
uint32_t pending;
while (ppl < (ipl = splintr(&pending))) {
splx(ipl); /* enable interrupts */
<handle pending interrupts>
(void)splhigh(); /* disable interrupts */
}
}

mipsX_subr.S has been reworked. All user handlers (user_intr, systemcall,
user_gen_exception) now use common return to usermode code in lwp_trampoline.
ast() has changed to void ast(void) since the previous pc argument was never
used.

The playstation IPL_ICU_MASK support has been nuked.
MIPS_DYNAMIC_STATUS_MASK may soon be nuked soon.

A bunch of debugging code was left conditionalized by PARANOIA. If this
code detects a bug, it will enter an infinite loop. It is expected that
the kernel will be debugged in a simulator or with a hardware debugger so
that the state at that point can be analyzed.
 1.90.16.18 05-Feb-2010  matt Add __HAVE_FAST_SOFTINTS support.
Add routine to remap an uarea via a direct-mapped address. This avoids
TLB machinations when swtching to/from the softint thread. This can only
be done for lwp which won't exit.
 1.90.16.17 01-Feb-2010  matt Merge frame into trapframe. While this costs a bit more stack space on
kernel exceptions, the resulting simplifications are worth it. This is
a step to fast softints and kernel preemption.

trapframe now includes a struct reg instead of a separate array of registers.
 1.90.16.16 30-Jan-2010  matt Change MIPS_CURLWP from s7 to t8. In a MALTA64 kernel, s6 is used 9155 times
which means the compiler could really use s7 is was free to do so. The least
used temporary was t8 (288 times). Once the kernel was switched to use t8 for
MIPS_CURLWP, s7 was used 7524 times.

Additionally a MALTA32 kernel shrunk by 6205 instructions (24820 bytes) or
about 1% of its text size.

[For some reason, pre-change t1 was never used and post change t2 was never
used. Not sure why.]
 1.90.16.15 26-Jan-2010  matt Revamp pmap. Add exec page caching logic from powerpc oea pmap. Shrink struct
vm_page by placing the first pv_entry in it. Remove pv_flags since nothing
really needed it. Add pmap counters. Rework virtual cache alias logic.
Allow pmap_copy_page and pmap_zero_page to deal with non-KSEG0 mappable pages.
 1.90.16.14 20-Jan-2010  matt Adjust things to the new world order.
 1.90.16.13 20-Jan-2010  matt Revamp things a bit. Move of the globals mips uses into either cpu_info,
mips_options, or mips_cache_info. Make MALT64 be able to boot MULTIPROCESSOR.
(some pmap MP work).
 1.90.16.12 15-Jan-2010  matt Get rid of most of the studly caps.
First to MULTIPROCESSOR support for pmap: move some pmap globals to cpu_info.
Define per-cpu ASID number spaces.
Remove some mips1/!mips1 difference in db_interface.c
Add mips32/64 knowledge to stacktrace.
 1.90.16.11 14-Jan-2010  matt More fixes for the CFATTAL_DECL_NEW changes and rmixl cpucore/cpu changes.
 1.90.16.10 13-Jan-2010  cliff - cpu_identify() now gets device_t arg
- add CIDFL's for RMI L2, cores, threads attributes
 1.90.16.9 30-Dec-2009  matt Please segtab lookups into separate file.
Add mips_add_physload
Add mips_init_lwp0_uarea
cleanup lwp0/cpu_info_store initialization.
 1.90.16.8 23-Nov-2009  cliff fix types in struct clockframe and args to cpu_intr
to be corect for 32 or 64 bit kernel
 1.90.16.7 15-Nov-2009  matt Fix typo.
 1.90.16.6 14-Nov-2009  matt switch from fu*/su* to ufetch_*/ustore_*.
 1.90.16.5 13-Nov-2009  cliff - struct pridtab definition is moved here from mips_machdep.c
- 'mycpu' is now global (was static); uh, a name change might be nice?
- new bit for cpu_flags 'CPU_MIPS_HAVE_MxCR' denotes
mfcr, mtcr instructions are available on this CPU
- new field 'cpu_cp0flags' in pridtab tracks whether (some) CP0 regs exist
- define bits in cpu_cp0flags, including a "USE" bit that,
if clear means cpu_cp0flags can be ignored. common CP0 regs do not
need to be represented here, only newer optional ones are.
- new field 'cpu_cidflags' in pridtab allows defining company-specific flags
- some RMI company specific flags are defined to track chip family
 1.90.16.4 15-Sep-2009  matt Define MIPS_HAS_LLADDR everywhere it should be.
 1.90.16.3 15-Sep-2009  matt Add a CPU_MIPS_NO_LLADDR flag / MIPS_HAS_LLADDR macro. And use to determine
whether to printf lladdr COP0 register
 1.90.16.2 08-Sep-2009  matt Add and optimize MIPS_PHYS_TO_XKPHYS_{UN,}CACHED(pa).
Treat like mips3_pg_cached: add mips3_xkphys_cached which contains the
starting address of the cached XKPHYS region. It also respects SPECIAL_CCA.
 1.90.16.1 21-Aug-2009  matt Make cpu_proc_fork copy the abi from process to process.
 1.95.4.3 31-May-2011  rmind sync with head
 1.95.4.2 21-Apr-2011  rmind sync with head
 1.95.4.1 05-Mar-2011  rmind sync with head
 1.96.4.2 05-Mar-2011  bouyer Sync with HEAD
 1.96.4.1 08-Feb-2011  bouyer Sync with HEAD
 1.96.2.1 06-Jun-2011  jruoho Sync with HEAD.
 1.106.12.3 03-Dec-2017  jdolecek update from HEAD
 1.106.12.2 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.106.12.1 23-Jun-2013  tls resync from head
 1.106.2.1 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.107.6.1 18-May-2014  rmind sync with head
 1.109.6.4 05-Dec-2016  skrll Sync with HEAD
 1.109.6.3 05-Oct-2016  skrll Sync with HEAD
 1.109.6.2 22-Sep-2015  skrll Sync with HEAD
 1.109.6.1 06-Jun-2015  skrll Sync with HEAD
 1.119.2.2 04-Nov-2016  pgoyette Sync with HEAD
 1.119.2.1 26-Jul-2016  pgoyette Sync with HEAD
 1.121.8.1 26-Feb-2018  snj Pull up following revision(s) (requested by skrll in ticket #566):
sys/arch/arm/include/cpu.h: 1.94
sys/arch/mips/include/cpu.h: 1.122
sys/arch/powerpc/include/cpu.h: 1.103
sys/sys/cpu.h: 1.42
CPU_INFO_FOREACH() must always iterate at least the boot cpu.
document this in sys/cpu.h and fix the arm and mips versions
to check ncpu is non zero before using it as an iterator max.
this should fix the new assert in init_main.c.
--
apply the same change for powerpc as mrg did for arm and mips:
CPU_INFO_FOREACH() must always iterate at least the boot cpu.
document this in sys/cpu.h and fix the arm and mips versions
to check ncpu is non zero before using it as an iterator max.
this should fix the new assert in init_main.c.
 1.123.2.3 30-Sep-2018  pgoyette Ssync with HEAD
 1.123.2.2 06-Sep-2018  pgoyette Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)
 1.123.2.1 15-Mar-2018  pgoyette Synch with HEAD
 1.124.2.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.124.2.1 10-Jun-2019  christos Sync with HEAD
 1.131.4.1 03-Apr-2021  thorpej Sync with HEAD.
 1.131.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.6 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.5 11-Jul-2016  matt Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.4 20-Feb-2011  matt branches: 1.4.14; 1.4.32;
Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.3 16-Feb-2006  perry branches: 1.3.90; 1.3.94; 1.3.100; 1.3.102;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.
 1.2 24-Dec-2005  perry branches: 1.2.2; 1.2.4; 1.2.6;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.
 1.1 05-Feb-2003  nakayama Replace machine/rnd.h with more appropriate name to share it
with cycle counter based microtime in kern/kern_microtime.c.
 1.2.6.1 22-Apr-2006  simonb Sync with head.
 1.2.4.1 09-Sep-2006  rpaulo sync with head
 1.2.2.1 18-Feb-2006  yamt sync with head.
 1.3.102.1 05-Mar-2011  bouyer Sync with HEAD
 1.3.100.1 06-Jun-2011  jruoho Sync with HEAD.
 1.3.94.1 05-Mar-2011  rmind sync with head
 1.3.90.2 22-Feb-2010  matt Don't include <mips/locore.h>. Rely on the weak alias in locore_mips3.S
 1.3.90.1 20-Jan-2010  matt Revamp things a bit. Move of the globals mips uses into either cpu_info,
mips_options, or mips_cache_info. Make MALT64 be able to boot MULTIPROCESSOR.
(some pmap MP work).
 1.4.32.1 05-Oct-2016  skrll Sync with HEAD
 1.4.14.1 03-Dec-2017  jdolecek update from HEAD
 1.3 16-Jan-1999  nisimura - Update 'cpuregs.h' and decline 'cpuarch.h'.
 1.2 14-Jan-1999  castor * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.1 15-Oct-1998  nisimura branches: 1.1.2;
file cpuarch.h was initially added on branch nisimura-pmax-wscons.
 1.1.2.3 19-Nov-1998  nisimura - Forgot to commit most important changes.
 1.1.2.2 30-Oct-1998  nisimura - Make pm.c monochrome-aware and compilable with UVM.
- Make trap.c compilable with UVM.
- Place #ifdef _KERNEL guard in cpu.h
- Make asm.h more MIPS standard-alike while retaining current definitions.
 1.1.2.1 15-Oct-1998  nisimura - cpuregs.h was modifed a bit, then renamed with cpuarch.h.
- mips_cpu.h has gone.
- CPU's register mnemonics in regdef.h is now a part of asm.h.
 1.116 16-Nov-2021  simonb Use the architecture documented name ULR for the RDHWR user local
register.
 1.115 16-Nov-2021  simonb Add some comments for the RDHWR register numbers.
 1.114 16-Nov-2021  simonb Only need one #define for MIPS_HWR_CPUNUM.
 1.113 01-Nov-2021  andvar fix typos, mainly in words minimum and maximum, but also few others.
 1.112 09-Aug-2021  andvar s/definitons/definitions/
 1.111 29-May-2021  simonb Update the FPU register names and bit definitions to something somewhat
modern (MIPS32/MIPS64) and convert to __BIT/__BITS.
 1.110 17-Mar-2021  simonb branches: 1.110.4; 1.110.6;
Handle gas/gcc generating a break/trap 6 for integer overflow and
break/trap 7 for integer divide by zero and setting the SIGFPE
si_code of FPE_INTOVF or FPE_INTDIV respectively. The break/trap
6/7 seems to have existed since the early days of MIPS but not
well documented anywhere.

Fixes ATF lib/libc/gen/t_siginfo::sigfpe_int .
 1.109 22-Aug-2020  simonb branches: 1.109.2;
Remove bogus duplicate MIPS_COP_0_CONTEXT definition, it's not a MIPS32/64
specific reg and we already define MIPS_COP_0_TLB_CONTEXT elsewhere.
 1.108 02-Aug-2020  simonb Add a few more perfcnt CP0 registers.
 1.107 31-Jul-2020  simonb Add two cnMIPS III COP0 register names.
 1.106 29-Jul-2020  simonb Add definitions for the CP0 WatchLo/WatchHi registers.
 1.105 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.104 26-Jul-2020  simonb Add CP0 Config Registers 6 and 7.
 1.103 26-Jul-2020  simonb Remove mostly duplicate MIPS spec CP0 regs from octeon_corereg.h, move
the Cavium specific CP0 regs to <mips/cpuregs.h> as done for other core
specific regs.
 1.102 20-Jul-2020  simonb Expose the width of the MIPS_EBASE_CPUNUM bitfield for asm code.
 1.101 20-Jul-2020  simonb Add an extra bitfield in MIPS_COP_0_EBASE.
 1.100 13-Jul-2020  simonb Remove a magic number.
 1.99 24-May-2020  simonb Add mipsNN_cp0_rdhwr_cpunum() which returns the current CPU number
read from the CPUNum hardware register on MIPS{32,64}R2.
 1.98 23-May-2020  simonb Add CX73xx and CXF75xx Cavium Octeon PRIDs.
 1.97 07-May-2020  simonb Add PRID definition for newer SiByte SB1 cores (rev 0x11).
Add a constant for SiByte/BCRM cacheable coherent TLB cache attribute.
 1.96 07-May-2017  skrll Trailing whitespace
 1.95 11-Jul-2016  matt branches: 1.95.8;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.94 11-Jun-2015  matt Add a few MIPS32 R3 bits
 1.93 10-Jun-2015  matt Add MIPS 1074K
 1.92 07-Jun-2015  matt Define COP0 register that use select value in <mips/cpuregs.h>
Use those new definitions
 1.91 01-Jun-2015  matt Rework cavium support in preparation for MULTIPROCESSOR support
 1.90 29-Apr-2015  hikaru Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.
 1.89 22-Nov-2014  macallan branches: 1.89.2;
deal with Ingenic XBurst CPUs
 1.88 29-Oct-2011  jakllsch branches: 1.88.12;
Add Broadcom BCM3302 CPU to the table.
 1.87 22-Sep-2011  macallan support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory and
DMA buffers with cacheing disabled but things like write combining, relaxed
ordering etc. allowed when the CPU supports it
so far enabled only on Loongson, should work on R1xk and probably newer CPUs
 1.86 27-Aug-2011  bouyer loongson2f support:
- Add some loongson2 definitions to cpuregs.h, from OpenBSD
- Make sure that the at register is useable before every jump register
instruction (exept when register is k0 or k1) because -mfix-loongson2f-btb
needs the at register for its workaround
- add code to mips_fixup.c to handle the instructions added by
-mfix-loongson2f-btb
- Add a ls2-specific tlb miss handler: it doesn't have separate handler
for the xtlbmiss exeption.
- Fixes for some #ifdef MIPS3_LOONGSON2 assembly code (using the wrong
register)
 1.85 02-Aug-2011  matt Add Loongson2 DIAG register definitions (partial)
 1.84 31-Jul-2011  matt Add define for loongson2 DIAG register
 1.83 06-Apr-2011  matt Fix some comments.
 1.82 15-Mar-2011  matt Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.
 1.81 03-Mar-2011  matt Change MIPS_CP0FL_CONFIG*
Add MIPS_CP0FL_HWRENA and USERLOCAL
 1.80 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.79 26-Jan-2011  pooka Add support for the Extensible MIPS ("eMIPS") platform. The
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the
Giano system simulator.

eMIPS is a platform developed at Microsoft Research for researching
reconfigurable computing. eMIPS allows dynamic loading and scheduling
of application-specific circuits for the purpose of accelerating
computations based on the current workload.

NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research
by Alessandro Forin and Neil Pittman. Microsoft Corporation has
donated full copyright to The NetBSD Foundation.

Platform support for eMIPS is the first part of Microsoft's
contribution. The second part includes the hardware accelerator
framework and will be proposed on tech-kern soon.
 1.78 27-Feb-2010  snj branches: 1.78.2; 1.78.4; 1.78.6;
Spell "exception" properly.
 1.77 14-Dec-2009  matt branches: 1.77.2;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.76 06-Aug-2009  matt LOONGSON2 is a MIPS III
 1.75 01-Aug-2009  matt Add Loongson2 chip ids
 1.74 19-Feb-2008  simonb branches: 1.74.10; 1.74.28;
Add PrID's for MIPS's 24K, 24KE, 34K and 74K cores.

From Alexander Voropay in mail to port-mips@.
 1.73 17-Oct-2007  garbled Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.72 16-Oct-2007  simonb Recognise the R2000A cpu as found in some pmaxen.

From Dennis Grevenstein on port-pmax@.
 1.71 26-Aug-2006  matt branches: 1.71.6; 1.71.12; 1.71.20; 1.71.22; 1.71.30; 1.71.32; 1.71.34;
Don't cast pointers using unsigned and/or int. Use intptr_t or uintptr_t
as appropriate.
 1.70 15-May-2006  simonb Fix typo in MIPS3_SR_EIE.
From Anders Gavare.
 1.69 20-Dec-2005  tron branches: 1.69.4; 1.69.6; 1.69.8; 1.69.12;
Add basic support for Alchemy Au1550 processor (CPU and devices).
Patch contributed by Garrett D'Amore in PR port-evbmips/32030.
 1.68 11-Dec-2005  christos merge ktrace-lwp.
 1.67 05-Nov-2005  tsutsui Remove unused and incorrect MIPS_KSEG2_TO_PHYS() and MIPS_PHYS_TO_KSEG2()
macro.
 1.66 04-Nov-2005  tsutsui Check MIPS3_CONFIG_CS and adjust csizebase at runtime on MIPS_R4100 CPUs,
and remove "XXXCDC: THIS MIPS3_4100 SPECIAL CASE SHOULD GO AWAY" part
from cpuregs.h. Tested on gxemul.

BTW, cache.c doesn't have MIPS_RC32364 config which was added
in mips_machdep.c rev 1.101?
 1.65 29-Oct-2003  simonb branches: 1.65.14; 1.65.16;
Add some more MTI CPU ids.
 1.64 28-Sep-2003  tsutsui - Add MIPS_KSEG2_TO_PHYS() and MIPS_PHYS_TO_KSEG2() macro.
- Add definitions of the MIPS4 config register.

From Christopher SEKIYA.
 1.63 28-Sep-2003  tsutsui Add another R4000 CPU revision ID. From Christopher SEKIYA.
 1.62 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.61 10-Jun-2003  simonb branches: 1.61.2;
Change MIPS3_SR_FR_32 to MIPS3_SR_FR. Both the old R4000 manual and the
current MIPS64 manuals don't use the "32" in the bit name.
 1.60 09-Jun-2003  simonb Remove definitions and usage of MIPS_COP_0_STATUS_REG and
MIPS_COP_0_CAUSE_REG - use MIPS_COP_0_STATUS and MIPS_COP_0_CAUSE
instead.
 1.59 10-Jan-2003  rafal Add the MIPS3_CONFIG_SE (name taken from Rm52xx manual) bit, which is the
external cache enable bit -- this allows software to enable or disable the
(external) L2 cache on the R5k and Rm527x and the (external) L3 cache on
the Rm7k. If the (external) cache is disabled, treat it as if there were
no cache for the purposes of the cache setup code.

Also, update sgimips code to use the new name.
 1.58 15-Nov-2002  simonb Define COP0_HAZARD_FPUENABLE as four nops.
Include <mips/sb1regs.h> if MIPS64_SB1 is defined.
 1.57 03-Nov-2002  nisimura Add two PRiD values.
- 0x55 for NEC Vr5500. ISA might be MIPS64.
- 0x38 for Toshiba TX79. This has thirty-two 128bit GPRs while
maintaining 32bit only virtual address space. Any of pointer related
registers have 32bit.
 1.56 28-Aug-2002  simonb Add the Toshiba TX4927 CPU.
 1.55 26-Jul-2002  simonb Add support for detecting Alchemy Semiconductor CPUs. Alchemy use the
processor ID field to donote the CPU core revision and the company
options field do donate the SOC chip type, so we need to add an extra
field to the "pridtab" structure to identify these CPUs.
 1.54 06-Jul-2002  gmcgarry Overhaul the emulation facility. We do this by:

- accumulating all emulation code (including floating-point) in one place
- steal MachFPInterrupt() back from SOFTFLOAT for use only with interrupts
and traps from *real* FPUs
- introducing MachEmulateInst() as a common dispatch point for all
emulated instructions
- cleaning up emulation dispatch in trap()

Also, while we're here, implement MIPS2 LL/SC/SYNC emulation for MIPS1.

Tested on r3k with and without SOFTFLOAT enabled.
 1.53 27-Jun-2002  simonb Add the 20Kc processor ID.
 1.52 05-Jun-2002  simonb For the CP0 status register bit definitions- add the MX, PX and NMI bits
and rename TLB_SHUTDOWN and SOFT_RESET to TS and SR (the abbreviations
in the MIPS documentation).

XXX: this file really needs to be cleaned up one day...
 1.51 01-Jun-2002  simonb Standardise on the name "MIPS_SR_BEV" instead of a couple of different
#defines for the same status bit.
 1.50 13-Mar-2002  simonb branches: 1.50.4;
Add R4400 reg 0x60 to the MIPS CPU table.
From PR port-mips/15894 from Thilo Manske.
 1.49 05-Mar-2002  simonb Add support for MIPS32 and MIPS64 architectures:
- Add XKPHYS macros (from Broadcom Corp).
- Add some r5900 register bit definitions.
- Add extra exception vector addresses for mips32/mips64 and r5900.
- Make the mips cp0 register definitions available from both asm and C.
- Add some Alchemy and Sandcraft CPU ids.
- Add r3000, tx39xx and r4x00 CPU revision ids.
- Remove defines for the number of TLBs on some CPUs.
 1.48 28-Dec-2001  shin R4000/R4400 always detects virtual alias as if
primary cache size is 32KB. Actual primary cache size
is ignored wrt VCED/VCEI.
 1.47 16-Oct-2001  uch branches: 1.47.4;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.
 1.46 17-Aug-2001  simonb Describe the widths of various coprocessor 0 registers (for mips1,
mips3, mips32 and mips64).
 1.45 15-Aug-2001  simonb _Never_ make a cosmetic change to a comment without test-compiling...
 1.44 15-Aug-2001  simonb Add some MIPS, Alchemy and SiByte CPU PRIDs (from oss.sgi.com).
 1.43 31-May-2001  nisimura branches: 1.43.2;
PRiD 0x18 is shared by RC32334, 332 and 355. These SoCs are
distinguished by SYSID register in the system controller. Note
that PRiD 0x20 is for a standalone RC32364 processor which has the
same 32300 core inside. Rather better to name them MIPS32 ISA.
 1.42 30-May-2001  soren Pasto.
 1.41 30-May-2001  nisimura Add PRiD 0x18 for IDT RC32332/RC32334 processors.
 1.40 15-May-2001  simonb Add the processor IDs for the 4Kc and 5Kc CPUs and some MIPS32/64
coprocessor 0 registers.
 1.39 24-Apr-2001  nisimura Add PRiD register imp value 0x2d for Toshiba TX4900 family.
 1.38 27-Nov-2000  soren branches: 1.38.2;
Correct a few cpu/fpu ids.
 1.37 27-Nov-2000  nisimura Use only one TLB entry to wire down process's USPACE since it's
now guranteed to be aligned on 8KB boundary in kernel virutal
address. Retain one more free TLB entry.
 1.36 16-Sep-2000  chuck IDT32364's Config register uses a different base for IC/DC (instruction
and data cache sizes). R4000 uses 2^(12+IC) and 2^(12+DC). IDT32364
uses 2^(9+IC) and 2^(9+DC).

abstract around the problem by making the base a parameter to the
MIPS3_CONFIG_CACHE_SIZE macro. we pass the base down from mips_vector_init
to mips3_vector_init and to mips3_ConfigCache (where it is used).

XXX: someone with an MIPS3_4100 should switch to this and get rid
of the ugly ifdefs in cpuregs.h
 1.35 17-Jul-2000  jeffs if MIPS3_ENABLE_CLOCK_INTR is defined, set MIPS3_[HARD_]INT_MASK
appropriately. This supports ports that use the internal clock.
Add 2 diag register defines that are specific to QED processors.
 1.34 09-Jun-2000  soda branches: 1.34.2;
Decrease MIPS3_TLB_WIRED_ENTRIES from 8 to 2,
and rename it to MIPS3_TLB_WIRED_UPAGES.
The value of wired register becomes variable on arc port,
and arc is the only mips3 port which uses the wired TLB entries 2..7.
 1.33 06-Jun-2000  soren Typo.
 1.32 23-May-2000  soren branches: 1.32.2;
MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.
 1.31 21-May-2000  soren Add R12K PRID.
 1.30 25-Mar-2000  nisimura Add QED RM7000 PrID.
 1.29 24-Mar-2000  soren Remove FPU PRIDs that are identical to the CPU ones.
 1.28 19-Mar-2000  soren Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast.
Many thanks.
 1.27 07-Mar-2000  soren Garbage collect MIPS_SR_INT_ENAB/MIPS_SR_INT_ENA_CUR definitions.
 1.26 27-Dec-1999  castor Add macro for MIPS_PHYS_MASK and document use of bits in system status
registers.
 1.25 22-Dec-1999  jun FIX:
port-mips/9016 [serious/medium]:
MIPS FPU emulator points wrong epc on exception case

Responsible: port-mips-maintainer (NetBSD/mips Portmasters)
State: open
Class: sw-bug
Originator: Shuichiro URATA
Release: current 12/11/1999
Arrival-Date: Fri Dec 17 10:18:00 1999
commit patch
http://www.a-r.org/~ur/softfloat1211.diff.gz
by Shuichiro URATA (ur@a-r.org)
 1.24 29-Nov-1999  uch TX3912/22 support. ENABLE_MIPS_TX3900 enables it.
 1.23 25-Sep-1999  shin branches: 1.23.2; 1.23.8;
Changes for NetBSD/hpcmips.

Support VR4100.
Support 16KB page.
Support CPU without FPU.

Fix virtual alias problem(physio() case).

[new options]

options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */
 1.22 21-May-1999  nisimura - Redefine symbols and parameters to represent CPU design with MIPS
nomenclature, retaining the old heritage.
- Remove API-related definitions for now obsolete utiltity routines.
 1.21 26-Apr-1999  nisimura - MIPS processors do not impose inclusive (nesting) interrupt levels with
their interrupt lines. The notion and implemention of 'spl' are left
for how target ports approach to it.
 1.20 24-Apr-1999  simonb Nuke register and remove trailling white space.
 1.19 23-Jan-1999  nisimura branches: 1.19.4;
- Add NEC Vr5400 processor ID.
 1.18 16-Jan-1999  nisimura - Update 'cpuregs.h' and decline 'cpuarch.h'.
 1.17 04-Dec-1998  nisimura - Fix an error in primary cache line size detection logic; when IC and/or DC
bit is 1, then line size is 32. Otherwise, 16.
 1.16 01-Oct-1998  jonathan branches: 1.16.2;
More patches for ARC from Noriyuki Soda:
* commit isapnpvar.h changes required for ARC to support plain isa.
* fixup mistake over mips/include/cpuregs.h.
* mips/mips_machdep.c:
set L2 cache-size for arc, cleanup use of L2cache present
vs L2 cache-size variables. check for no L2 cache on kernels
configured to require one. misc cleanups.
* mips/mpis/trap.c: more locore stack-traceback label cleanup.
XXX Locore callbacks for mips3, mips4, r4600 cacheflush need more work.
 1.15 11-Sep-1998  jonathan Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.

* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.
 1.14 23-Apr-1998  jonathan define mips3 COUNT and COMPARE cp0 registers (onchip cycle counter)
 1.13 22-Jun-1997  jonathan * Change Sprite MACH_xxx prefix to MIPS_xxx.

* Use standard mips terminology (xxx_KSEG0, xxx_KSEG1) instead of the
(more meaningful) Sprite names (xxx_CACHED, xxx_UNCACHED).
 1.12 22-Jun-1997  jonathan Final changes for configuring MIPS1 and MIPS3 in a single kernel.

* cpuregs.h:
rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx.
Add compile-time MIPS3-only, compile-time MIPS1-only, and
runtime (both) definitions for number of TLB ASIDs (tlb pids)
and shift count to extract a TLB pid.

* locore.h:
Delete unused vector slot for indexed TLB writes.
mips1 and mips3 TLBs are different enough that we have
to break them out at the caller anyway.

* Add compile-time MIPS3-only andcompile-time MIPS1-only
macros to call locore functions directly by name.
Use the existing method table only if

* mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c:
Use MIPS3_ or MIPS1_ specific names for TLB pids in
mips3 and mips1 specific code paths (e.g., creating the kernel stack
for process 0).

Add `options MIPS3' to pmax/conf/GENERIC.
 1.11 21-Jun-1997  jonathan More mips1/mips3 changes to cpuregs.h and psl.h:
* cpuregs.h:
Delete unused VMMACH_ names (e.g., duplicates of PTE bits in pte.h).
Change remaining VMMACH_xxx names to MIPS1_xxx or MIPS3_xx.
Fold remaining compile-time definitions into a single #ifdef MIPS3.

* Use MIPS1_ names in locore_r2000.S, mips3_ names in locore_r4000.S

* Garbage-collect MachHitFlushDCache()

* psl.h:
use MIPS1_, MIPS3_ symbolic names for Cause register bits.
change _R3K to MIPS1_, _R4K to MIPS3. Conditionalize for mips1 only,
mips3 only, or when both are defined, use runtime CPUISMIPS3 test.
 1.10 16-Jun-1997  jonathan Fix idempotent inclusion test macro: _MACHCONST -> _MIPS_CPUREGS_H_
to avoid collision with obsolete Sprite-derived NetBSD/pica header file.
 1.9 16-Jun-1997  jonathan Garbage-collect MIPS_3K_xxx, MIPS_4K_xxx outidde mips/include/cpuregs.h:
MIPS_3K_xxx -> MIPS1_xxx
MIPS_4K_xxx -> MIPS3_xxx
 1.8 15-Jun-1997  mhitch More merged MIPS1/MIPS3 support: still only allows single-architecture
support.
 1.7 19-May-1997  jonathan Fix typo.
 1.6 18-May-1997  jonathan Add defines for increasing SPL levels, assuming devices are wired up
in to CPU interrupt pins in order of increasing priority.
 1.5 28-Mar-1996  jonathan Resolve all differences between the Pica and pmax versions of machConst.h:
* add "MIPS_3k_" for the MIPS-I r[23]000-specific register definitions.
* add "MIPS_4k_" for the MIPS-II/III r4000-specific register definitions.
* add #defines that provide the old values for locore and user
code, so the existing code continues to compile.

Regression-tested against the old headers by grepping for #define's,
editing out the defined symbols, and preprocessing with both the previous
machConst.h headers and this version.

Some unused symbols (CPU and FPU must-be-zero constants) are no longer defined.
Pica interrupt masks are now constant expressions instead of constant
values.

TODO:
* factor out the common #defines into src/sys/arch/mips.
* Get rid of the Sprite coding-style names (MACH_xxx).
* Separate out the r3k/r4k differences from the Pica/pmax differences.
* Figure out how to have a run-time choice of r3k vs. r4k support,
instead of a compile-time choice.
 1.4 26-Oct-1994  cgd new RCS ID format.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.16.2.1 15-Oct-1998  nisimura - cpuregs.h was modifed a bit, then renamed with cpuarch.h.
- mips_cpu.h has gone.
- CPU's register mnemonics in regdef.h is now a part of asm.h.
 1.19.4.1 21-Jun-1999  thorpej Sync w/ -current.
 1.23.8.1 27-Dec-1999  wrstuden Pull up to last week's -current.
 1.23.2.2 08-Dec-2000  bouyer Sync with HEAD.
 1.23.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.32.2.1 22-Jun-2000  minoura Sync w/ netbsd-1-5-base.
 1.34.2.1 19-Jul-2000  jeffs Pull up revision 1.35 (approved by thorpej):
if MIPS3_ENABLE_CLOCK_INTR is defined, set MIPS3_[HARD_]INT_MASK
appropriately. This supports ports that use the internal clock.
Add 2 diag register defines that are specific to QED processors.
 1.38.2.1 21-Jun-2001  nathanw Catch up to -current.
 1.43.2.5 06-Sep-2002  jdolecek sync kqueue branch with HEAD
 1.43.2.4 23-Jun-2002  jdolecek catch up with -current on kqueue branch
 1.43.2.3 16-Mar-2002  jdolecek Catch up with -current.
 1.43.2.2 10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.43.2.1 25-Aug-2001  thorpej Merge Aug 24 -current into the kqueue branch.
 1.47.4.9 15-Jan-2003  thorpej Sync with HEAD.
 1.47.4.8 11-Dec-2002  thorpej Sync with HEAD.
 1.47.4.7 11-Nov-2002  nathanw Catch up to -current
 1.47.4.6 17-Sep-2002  nathanw Catch up to -current.
 1.47.4.5 01-Aug-2002  nathanw Catch up to -current.
 1.47.4.4 20-Jun-2002  nathanw Catch up to -current.
 1.47.4.3 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.47.4.2 08-Jan-2002  nathanw Catch up to -current.
 1.47.4.1 16-Oct-2001  nathanw file cpuregs.h was added on branch nathanw_sa on 2002-01-08 00:26:16 +0000
 1.50.4.3 31-Aug-2002  gehenna catch up with -current.
 1.50.4.2 16-Jul-2002  gehenna catch up with -current.
 1.50.4.1 14-Jul-2002  gehenna catch up with -current.
 1.61.2.4 10-Nov-2005  skrll Sync with HEAD. Here we go again...
 1.61.2.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.61.2.2 18-Sep-2004  skrll Sync with HEAD.
 1.61.2.1 03-Aug-2004  skrll Sync with HEAD
 1.65.16.4 27-Feb-2008  yamt sync with head.
 1.65.16.3 27-Oct-2007  yamt sync with head.
 1.65.16.2 30-Dec-2006  yamt sync with head.
 1.65.16.1 21-Jun-2006  yamt sync with head.
 1.65.14.1 19-Nov-2007  bouyer Pull up following revision(s) (requested by simonb in ticket #1865):
sys/arch/mips/include/cpuregs.h: revision 1.72
sys/arch/mips/mips/mips_machdep.c: revision 1.195
Recognise the R2000A cpu as found in some pmaxen.
From Dennis Grevenstein on port-pmax@.
--
 1.69.12.1 24-May-2006  tron Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.
 1.69.8.2 03-Sep-2006  yamt sync with head.
 1.69.8.1 24-May-2006  yamt sync with head.
 1.69.6.1 01-Jun-2006  kardel Sync with head.
 1.69.4.1 09-Sep-2006  rpaulo sync with head
 1.71.34.1 18-Oct-2007  yamt sync with head.
 1.71.32.2 23-Mar-2008  matt sync with HEAD
 1.71.32.1 06-Nov-2007  matt sync with HEAD
 1.71.30.1 26-Oct-2007  joerg Sync with HEAD.

Follow the merge of pmap.c on i386 and amd64 and move
pmap_init_tmp_pgtbl into arch/x86/x86/pmap.c. Modify the ACPI wakeup
code to restore CR4 before jumping back into kernel space as the large
page option might cover that.
 1.71.22.1 06-Jan-2008  wrstuden Catch up to netbsd-4.0 release.
 1.71.20.1 16-Oct-2007  garbled Sync with HEAD
 1.71.12.1 23-Oct-2007  ad Sync with head.
 1.71.6.1 24-Oct-2007  xtraeme Pull up following revision(s) (requested by simonb in ticket #936):
sys/arch/mips/include/cpuregs.h: revision 1.72
sys/arch/mips/mips/mips_machdep.c: revision 1.195

Recognise the R2000A cpu as found in some pmaxen.
From Dennis Grevenstein on port-pmax@.
 1.74.28.26 15-Dec-2012  matt Add initial support for XLP II (XLP2XX/XLP1XX).
 1.74.28.25 19-Jan-2012  matt When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses. There are exceptions.
bus_space_handles are now register_t instead of intptr_t. This allows them
to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address. This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs. If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.
 1.74.28.24 27-Dec-2011  matt Note that 1004K and 1074K are MT
 1.74.28.23 23-Dec-2011  matt Correct XLP processor ids, add 1074K processor id. Increase ASID space
to 10 bits for MIPS3+ cpus.
 1.74.28.22 04-Nov-2011  matt Add RMI XLP ids
 1.74.28.21 26-May-2011  matt Add MIPS64_RMIXL (XLR/XLS) and MIPS64R2_RMIXL (XLP). This allows the kernel
to treat this special which is needed for MP support. When accessing the TLB,
always lock the TLB before hand. If in the miss handlers, the TLB is already
locked let trap deal with the exeception.
 1.74.28.20 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.74.28.19 29-Dec-2010  matt Add MIPS_TLB_PID mask and use it apporpriately.
 1.74.28.18 27-Apr-2010  cliff seperate RMI CPU revision codes from RMI CPU processor codes
and improve comment
 1.74.28.17 29-Mar-2010  cliff - fix XLR Pid defines; RMI Pid meaning depends on
the Rev value (Stepping B2 or C4)
 1.74.28.16 21-Mar-2010  cliff - define MIPS_SR_COP_2_BIT to control enable/disable of coprocessor 2
 1.74.28.15 27-Feb-2010  matt Add the RMI COP0 OSSCRATCH register
 1.74.28.14 05-Feb-2010  matt Add __HAVE_FAST_SOFTINTS support.
Add routine to remap an uarea via a direct-mapped address. This avoids
TLB machinations when swtching to/from the softint thread. This can only
be done for lwp which won't exit.
 1.74.28.13 20-Jan-2010  matt Revamp things a bit. Move of the globals mips uses into either cpu_info,
mips_options, or mips_cache_info. Make MALT64 be able to boot MULTIPROCESSOR.
(some pmap MP work).
 1.74.28.12 14-Nov-2009  matt Add MIPS_SR_PX
 1.74.28.11 13-Nov-2009  cliff - move #ifndef LOCORE up a few lines to wrap more XSEG, XKSEG stuff
 1.74.28.10 09-Nov-2009  cliff - fix some RMI XLR PRID typos (comments)
 1.74.28.9 13-Sep-2009  cliff include registers file for RMI XL chip family as needed
 1.74.28.8 08-Sep-2009  matt Add and optimize MIPS_PHYS_TO_XKPHYS_{UN,}CACHED(pa).
Treat like mips3_pg_cached: add mips3_xkphys_cached which contains the
starting address of the cached XKPHYS region. It also respects SPECIAL_CCA.
 1.74.28.7 07-Sep-2009  matt Use intptr_t in MIPS_KSEGx_P()
Use uintptr_t in MIPS_XKPHYS*
 1.74.28.6 06-Sep-2009  matt Add some more macros for XUSEG/XSSEK and for testing what segment an address
belongs to.
 1.74.28.5 05-Sep-2009  matt Define MIPS_KSEGn_START as friends as being long.
 1.74.28.4 30-Aug-2009  simonb Update comment for EBASE - this is a MIPS32/MIPS64 only register
 1.74.28.3 30-Aug-2009  matt Add RMI company id.
Add some RMI processor ids.
Add CP0 EBASE defintion.
 1.74.28.2 21-Aug-2009  matt Define manifest kernel addresses as negative so that proper sign extension
happens. This gives proper results for both 32bit and 64bit kernels.
 1.74.28.1 20-Aug-2009  matt Add a MIPS_XKPHYS_P(va) macro.
Define MIPS_XKSEG related macros
 1.74.10.2 11-Mar-2010  yamt sync with head
 1.74.10.1 19-Aug-2009  yamt sync with head.
 1.77.2.1 30-Apr-2010  uebayasi Sync with HEAD.
 1.78.6.2 05-Mar-2011  bouyer Sync with HEAD
 1.78.6.1 08-Feb-2011  bouyer Sync with HEAD
 1.78.4.1 06-Jun-2011  jruoho Sync with HEAD.
 1.78.2.2 21-Apr-2011  rmind sync with head
 1.78.2.1 05-Mar-2011  rmind sync with head
 1.88.12.1 03-Dec-2017  jdolecek update from HEAD
 1.89.2.3 05-Oct-2016  skrll Sync with HEAD
 1.89.2.2 22-Sep-2015  skrll Sync with HEAD
 1.89.2.1 06-Jun-2015  skrll Sync with HEAD
 1.95.8.1 11-May-2017  pgoyette Sync with HEAD
 1.109.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.110.6.1 31-May-2021  cjep sync with head
 1.110.4.1 17-Jun-2021  thorpej Sync w/ HEAD.
 1.4 10-Jun-2015  matt Transition from __cpuset_t to kcpuset_t *. This brings the local pmap one
step closer to uvm/pmap, its eventual replacement. Tested on ERLITE MP kernel.
 1.3 29-Mar-2015  macallan use 32bit __cpuset_t in o32 kernels
ok matt@
 1.2 20-Feb-2011  matt branches: 1.2.2; 1.2.4; 1.2.8; 1.2.20; 1.2.38;
Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.1 05-Feb-2011  cliff branches: 1.1.2;
file cpuset.h was initially added on branch matt-nb5-mips64.
 1.1.2.2 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.1.2.1 05-Feb-2011  cliff add cpuset.h to allow abstracting bit-per-cpu run state variables (cpus_running et. al.)
 1.2.38.2 22-Sep-2015  skrll Sync with HEAD
 1.2.38.1 06-Apr-2015  skrll Sync with HEAD
 1.2.20.1 03-Dec-2017  jdolecek update from HEAD
 1.2.8.2 06-Jun-2011  jruoho Sync with HEAD.
 1.2.8.1 20-Feb-2011  jruoho file cpuset.h was added on branch jruoho-x86intr on 2011-06-06 09:06:03 +0000
 1.2.4.2 05-Mar-2011  rmind sync with head
 1.2.4.1 20-Feb-2011  rmind file cpuset.h was added on branch rmind-uvmplock on 2011-03-05 20:51:03 +0000
 1.2.2.2 05-Mar-2011  bouyer Sync with HEAD
 1.2.2.1 20-Feb-2011  bouyer file cpuset.h was added on branch bouyer-quota2 on 2011-03-05 15:09:48 +0000
 1.38 18-May-2021  skrll Remove argument names from function declaration prototypes.
 1.37 29-Mar-2021  simonb branches: 1.37.2; 1.37.4;
Expose kdbpeek() and kdbrpeek() for dtrace.
 1.36 29-Mar-2021  simonb Move the cpu_reset_address() declaration inside #ifdef _KERNEL, add a
comment.
 1.35 29-Mar-2021  simonb Whitespace nits.
 1.34 10-Feb-2021  simonb branches: 1.34.2;
On MIPS use a helper function to work out the current PC and then
call stacktrace_subr() directly for displaying a stacktrace with
db_stacktrace() and friends.
 1.33 17-Aug-2020  mrg branches: 1.33.2;
port crash(8) to mips. (most of the kernel side.)

- expose parts of _KERNEL to _KMEMUSER as well
- hide more things for _KERNEL
- avoid DB_MACHINE_COMMANDS in crash(8)
- XXX add mips_label_t for !_KERNEL and use it in the pcb to
avoid conflicting with the ddb/crash one
- enable dumppcb

some changes to make stack trace fail instead of SEGV and
the userland changes to crash itself not part of this change.
 1.32 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.31 13-Jul-2020  simonb Copy "mach reset" logic from arm32 recently added by jmcneill@. The
previous MIPS "mach reset" DDB command was hard-coded for Octeon Cavium
CPUs only.
 1.30 06-Nov-2017  christos Cleanup and clarify the ELFSIZE mess:

We now have 2 variables automatically set in elf_machdep.h:

ARCH_ELFSIZE: the size for userland binaries
KERN_ELFSIZE: the size for the kernel binaries

DB_ELFSIZE has been deleted and KERN_ELFSIZE should have always the
same values DB_ELFSIZE used to have.

In sys/exec_elf.h, if ELFSIZE is not set, it is set to KERN_ELFSIZE
for the kernel and ARCH_ELFSIZE for userland. These defaults should
eliminate the need for most manual ELFSIZE setting.
 1.29 06-Jun-2015  matt Make db_expr_t long long when using the N32 ABI.
 1.28 09-Jul-2011  matt branches: 1.28.12; 1.28.30;
Default to DB_ELF_SYMBOLS and DB_ELFSIZE 32
 1.27 26-May-2011  joerg Introduce DDB_EXPR_FMT and replace the logic around DB_EXPR_T_IS_QUAD.
 1.26 14-Apr-2011  cliff - remove include <mips/proc.h>, unused
- db_mach_watch_set_all() is deprecated, removed,
superceded by cpuwatch_set_all()
 1.25 06-Apr-2011  matt minor cleanups. foo -> foo_p. add some whitespace.
 1.24 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.23 14-Jan-2011  rmind branches: 1.23.2; 1.23.4;
Retire struct user, remove sys/user.h inclusions. Note sys/user.h header
as obsolete. Remove USER_TO_UAREA/UAREA_TO_USER macros.

Various #include fixes and review by matt@.
 1.22 28-Feb-2007  thorpej branches: 1.22.62; 1.22.66;
TRUE -> true, FALSE -> false
 1.21 22-Feb-2007  matt Fix more boolean_t -> bool lossage
 1.20 21-Feb-2007  thorpej Replace the Mach-derived boolean_t type with the C99 bool type. A
future commit will replace use of TRUE and FALSE with true and false.
 1.19 01-Sep-2006  matt branches: 1.19.8;
Remove explicit cast which causes assignments to PC_REGS(f) to fail.
 1.18 01-Apr-2006  cherry closes: PR kern/32359

modifies machine/db_machdep.h: BKPT_SET(inst) to BKPT_SET(inst, addr) for all archs ie; passess the
breakpoint address as well.

Patch from cherry@mahiti.org
 1.17 11-Dec-2005  christos branches: 1.17.4; 1.17.6; 1.17.8; 1.17.10; 1.17.12;
merge ktrace-lwp.
 1.16 26-Nov-2003  he branches: 1.16.16;
Hide the register number constants behind an _R_ prefix, and also
rename FPBASE to _FPBASE, so that we avoid polluting the user's
name space when e.g. <sys/ptrace.h> is included. Previously, the
PC symbol in mips/regnum.h would conflict with the declaration of
the external variable by the same name in termcap.h, as discovered
by the ``okheaders'' regression test.
 1.15 29-Apr-2003  scw branches: 1.15.2;
Add a BKPT_ADDR() macro which gives MD code a chance to munge a
breakpoint address before it's used. Currently a no-op on all but sh5.

This is useful on sh5, for example, to mask off the instruction
type encoding in the bottom two address bits, and makes it possible
to do "db> break $rXX" instead of manually munging the address.
 1.14 05-Mar-2002  simonb ANSIfy.
 1.13 15-Feb-2002  simonb Make the ddb_regs declaration an extern in db_machdep.h and declare it on
db_interface.c.
 1.12 09-Nov-2001  thorpej branches: 1.12.2;
Remove unneeded declarations of the db_machine_init() function. The
ARM ports are the only ones that actually have one, and it is about
to change.
 1.11 17-Jul-2000  jeffs branches: 1.11.4; 1.11.6;
Move platform db_trap callback from arch/mips into ddb as suggested by
jhawk. This callback is used by platform code to manage things like
watchdogs that should be disabled while in ddb. Done as a callback
for processors such as mips that support lots of different systems.
 1.10 17-Jul-2000  jeffs Pull in geocast mips ddb improvements and start bringing in kgdb support.
Add ddb support for QED opcodes, fill in enough routines so "next" usually
works, kdbpoke support for any size. Add callback that ports can hook when
entering and leaving ddb. This can be used for things like turning
off watchdogs while in ddb.
 1.9 26-Jun-2000  mrg <vm/vm_param.h> -> <uvm/uvm_param.h>
 1.8 10-Apr-1999  drochner branches: 1.8.2;
while symbol support in DDB is good to have one _can_ live without it
 1.7 23-Mar-1999  simonb branches: 1.7.4;
Move DB_{AOUT,ELF}_SYMBOLS (and DB_ELFSIZE) definition to port-specific
db_machdep.h file.
 1.6 14-Jan-1999  castor * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.5 06-Jan-1999  nisimura - Complete vm_offset_t purge for mips processor.
- bzero() -> memset() and bcopy() -> memcpy().
- Garbage collection in trap.c and db_interface.c.
 1.4 18-Nov-1997  mhitch branches: 1.4.4;
Define PC_ADVANCE() to advance the PC around the break instruction only
if the break instruction is still there. This works around a problem with
the software single step in DDB not recognizing the temporary breakpoint
set to emulate the single step.
 1.3 19-Jul-1997  jonathan branches: 1.3.6;
* Re-apply changes from rev 1.6 of sys/arch/mips/include/reg.h accidentally
undone by rev 1.7:
>redo pmax/include/reg.h
>so that the definitions needed by locore.S are in a separate file,
>pmax/include/regnum.h.

* Add explicit `#include <mips/regnum.h>' where symbolic offsets
into a mips trapframe or struct reg are used..
 1.2 07-Jul-1997  jonathan Typo in RCS id.
 1.1 07-Jul-1997  jonathan DDB for mips.
Add DDB interface to /sys/arch/mips/mips..
Rework heuristic stack traceback to work with DDB.
Add hooks to print exception log from DDB.
Add hooks from pmax console drivers: call Debugger()
after break from serial console, or 'DO' key from LK-xxx.
 1.3.6.1 20-Nov-1997  mellon Pull rev 1.4 up from trunk (mhitch)
 1.4.4.1 19-Nov-1998  nisimura - Forgot to commit many files for vm_offset_t purge last Monday.
 1.7.4.1 21-Jun-1999  thorpej Sync w/ -current.
 1.8.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.11.6.1 12-Nov-2001  thorpej Sync the thorpej-mips-cache branch with -current.
 1.11.4.2 16-Mar-2002  jdolecek Catch up with -current.
 1.11.4.1 10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.12.2.3 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.12.2.2 28-Feb-2002  nathanw Catch up to -current.
 1.12.2.1 09-Nov-2001  nathanw file db_machdep.h was added on branch nathanw_sa on 2002-02-28 04:10:42 +0000
 1.15.2.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.15.2.2 18-Sep-2004  skrll Sync with HEAD.
 1.15.2.1 03-Aug-2004  skrll Sync with HEAD
 1.16.16.4 03-Sep-2007  yamt sync with head.
 1.16.16.3 26-Feb-2007  yamt sync with head.
 1.16.16.2 30-Dec-2006  yamt sync with head.
 1.16.16.1 21-Jun-2006  yamt sync with head.
 1.17.12.1 24-May-2006  tron Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.
 1.17.10.1 19-Apr-2006  elad sync with head - hopefully this will work
 1.17.8.2 03-Sep-2006  yamt sync with head.
 1.17.8.1 11-Apr-2006  yamt sync with head
 1.17.6.1 22-Apr-2006  simonb Sync with head.
 1.17.4.1 09-Sep-2006  rpaulo sync with head
 1.19.8.2 12-Mar-2007  rmind Sync with HEAD.
 1.19.8.1 27-Feb-2007  yamt - sync with head.
- move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.
 1.22.66.3 31-May-2011  rmind sync with head
 1.22.66.2 21-Apr-2011  rmind sync with head
 1.22.66.1 05-Mar-2011  rmind sync with head
 1.22.62.5 16-Feb-2012  matt Change db_expr_t to an register_t so we can see the full register contents
on N32 kernels.
 1.22.62.4 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.22.62.3 08-Feb-2011  cliff - rename ddb_running_on_this_cpu to ddb_running_on_this_cpu_p
according to pedicate unction naming style convention
 1.22.62.2 05-Feb-2011  cliff - declare new md MP ddb functions.
 1.22.62.1 01-Feb-2010  matt Merge frame into trapframe. While this costs a bit more stack space on
kernel exceptions, the resulting simplifications are worth it. This is
a step to fast softints and kernel preemption.

trapframe now includes a struct reg instead of a separate array of registers.
 1.23.4.1 05-Mar-2011  bouyer Sync with HEAD
 1.23.2.1 06-Jun-2011  jruoho Sync with HEAD.
 1.28.30.1 22-Sep-2015  skrll Sync with HEAD
 1.28.12.1 03-Dec-2017  jdolecek update from HEAD
 1.33.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.34.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.37.4.1 31-May-2021  cjep sync with head
 1.37.2.1 17-Jun-2021  thorpej Sync w/ HEAD.
 1.6 26-Sep-1996  cgd rename <machine/ecoff.h> to <machine/ecoff_machdep.h> for clarity and
consistency with the way machdep headers for other things are done.
(the creation of the ecoff_machdep.h files was done on the CVS server, to
keep the RCS logs intact.)
 1.5 09-May-1996  cgd change structure member names to be in line with what various ECOFF
documentation I have calls them, and update for new definitions in
sys/exec_ecoff.h.
 1.4 16-Jun-1995  mellon Put parentheses around macro arguments
 1.3 26-Oct-1994  cgd new RCS ID format.
 1.2 28-May-1994  glass more likely to work now, probably less knf...thats the next project
 1.1 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.24 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.23 23-Feb-2017  christos provide ecoff 32 defines.
 1.22 11-Jul-2016  matt branches: 1.22.2; 1.22.4;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.21 20-Mar-2012  nonaka branches: 1.21.2; 1.21.14; 1.21.16;
fix build failure on mipsel.

>/usr/src/lib/libc/gen/nlist_ecoff.c(112): warning: constant in conditional context [161]
 1.20 10-Dec-2009  matt branches: 1.20.12; 1.20.16;
Change u_long to vaddr_t/vsize_t in exec code where appropriate (mostly
involves setregs and vmcmds). Should result in no code differences.
 1.19 17-Jan-2003  thorpej branches: 1.19.108; 1.19.126;
Merge the nathanw_sa branch.
 1.18 05-Mar-2002  simonb ANSIfy.
 1.17 28-Mar-2000  simonb branches: 1.17.8; 1.17.12;
Don't `extern' function declarations. While we're there, remove trailing
blank lines and white space.
 1.16 24-Apr-1999  simonb branches: 1.16.2;
Nuke register and remove trailling white space.
 1.15 08-Mar-1999  tsubai branches: 1.15.4;
Add big-endian definitions.
 1.14 05-Dec-1998  jonathan #ifdef _KERNEL around cpu_exec_ecoff_setregs() prototype.
 1.13 15-Oct-1997  mhitch branches: 1.13.6;
Fix typo - list/libc/gen/nlist_ecoff.c still wasn't compiling.
 1.12 10-Oct-1997  jonathan Don't check the actual CPU type unless we're in the _KERNEL, or
src/lib/libc/gen/nlist_ecoff.c breaks.
 1.11 08-Oct-1997  jonathan Allow mips3 ECOFF binaries if running on a mips3 CPU.
 1.10 24-Sep-1997  mhitch Fix another missed *setregs() change.
 1.9 20-Jul-1997  jonathan branches: 1.9.2;
Add ecoff ``struct ext_ext'' header fields to ecoff_extsym.h.
Compatible with mips ECOFF nm from GNu binutils or MipsCo toolchain.
 1.8 07-Jul-1997  jonathan Rewrite struct ecoff_symhdr using the same field ordering as GNU
binutils and the MipsCo toolchain, not the Alpha ordering (which has a
block of int32_t symbol counts and a block of long offsets) .
 1.7 25-May-1997  jonathan Add ecoff symbol header definitions for mips1.
 1.6 24-May-1997  jonathan Add prototype for cpu_exec_ecoff_setregs() to mips/inuclde/ecoff_machdep.h.
Use it in compat/ultrix/ultrix_misc.c (setting emul type on mips).
 1.5 09-May-1996  cgd change structure member names to be in line with what various ECOFF
documentation I have calls them, and update for new definitions in
sys/exec_ecoff.h.
 1.4 16-Jun-1995  mellon Put parentheses around macro arguments
 1.3 26-Oct-1994  cgd new RCS ID format.
 1.2 28-May-1994  glass more likely to work now, probably less knf...thats the next project
 1.1 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.9.2.2 14-Oct-1997  thorpej Update marc-pcmcia branch from trunk.
 1.9.2.1 29-Sep-1997  thorpej Update marc-pcmcia branch from trunk.
 1.13.6.1 06-Dec-1998  drochner pull up 1.14 - protect cpu_exec_ecoff_setregs
 1.15.4.1 21-Jun-1999  thorpej Sync w/ -current.
 1.16.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.17.12.2 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.17.12.1 17-Nov-2001  wdk Inital support for Scheduler Activation on MIPS architectures.

Compiles for sgimips. Needs more work in locore.S in order to reach
single user and beyond.
 1.17.8.1 16-Mar-2002  jdolecek Catch up with -current.
 1.19.126.1 26-Aug-2009  matt Fixup (all but mipsco) to deal the new realities in mipsland.
 1.19.108.1 11-Mar-2010  yamt sync with head
 1.20.16.1 05-Apr-2012  mrg sync to latest -current.
 1.20.12.1 17-Apr-2012  yamt sync with head
 1.21.16.2 28-Aug-2017  skrll Sync with HEAD
 1.21.16.1 05-Oct-2016  skrll Sync with HEAD
 1.21.14.1 12-May-2017  snj Pull up following revision(s) (requested by skrll in ticket #1406):
sys/arch/mips/include/ecoff_machdep.h: revision 1.23
sys/sys/exec_ecoff.h: revision 1.21
tools/Makefile.nbincludes: revision 1.5
tools/mips-elf2ecoff/Makefile: revision 1.3
tools/mips-elf2ecoff/machine/ecoff_machdep.h: revision 1.3
tools/mips-elf2ecoff/sys/exec_elf.h: file removal
tools/mips-elf2ecoff/sys/exec_ecoff.h: file removal
usr.bin/elf2ecoff/elf2ecoff.c: revision 1.30-1.33
use the nbcompat copies for those files
--
ignore the abiflags section
--
Add exec_ecoff.h
--
provide ecoff 32 defines.
--
This only works with 32 bit Elf and COFF files, make it specific this way
and use sized types so that it works on 64 bit systems (so it can become
a tool).
--
Provided sized definitions for ecoff 32 bit headers.
--
refresh
--
fix printf format.
--
fix printf format
 1.21.2.1 03-Dec-2017  jdolecek update from HEAD
 1.22.4.1 21-Apr-2017  bouyer Sync with HEAD
 1.22.2.1 20-Mar-2017  pgoyette Sync with HEAD
 1.5 09-Nov-1999  kleink Per discussion on tech-toolchain, remove MIPS-specific <machine/elf.h> header;
all the information is available from <sys/exec_elf.h>.
 1.4 26-Jun-1996  jonathan branches: 1.4.30; 1.4.32; 1.4.36;
Rename unused macro ELF_HDR_SIZE -> MIPS_ELF_HDR_SIZE to avoid clash
with #define of ELF_HDR_SIZE in MI elf code.
 1.3 19-May-1996  jonathan branches: 1.3.4;
Declare mips_elf_makecmds(), not pmax_elf_makecmds().
 1.2 28-Mar-1995  jtc KERNEL -> _KERNEL
 1.1 18-Jan-1995  mellon ELF format (to be combined with elf header in sys/compat later)
 1.3.4.1 26-Jun-1996  jtc Pulled up from trunk by request of Jonathan Stone
 1.4.36.1 27-Dec-1999  wrstuden Pull up to last week's -current.
 1.4.32.1 15-Nov-1999  fvdl Sync with -current
 1.4.30.1 20-Nov-2000  bouyer Remove files that are no longer on the trunck
 1.21 16-Apr-2025  riastradh ld.elf_so: Teach this to handle MIPS PIE rtld debug data.

Adapt t_rtld_r_debug to handle the two MIPS cases too.

XXX t_rtld_r_debug should be tested both as PIE and non-PIE to
exercise both cases.

Context:

The value of a DT_DEBUG .dynamic entry is initialized at load-time,
by ld.elf_so, to a pointer to a data structure set up by ld.elf_so
describing the shared objects loaded by the executable, so debuggers
can find them from, e.g., core dumps. None of this is really
documented anywhere that I can find. Best reference is this post on
the gdb mailing list from a quarter century ago saying there's no
real documentation:

https://web.archive.org/web/20250414021320/https://sourceware.org/pipermail/gdb/2000-April/004509.html

However, on MIPS, the .dynamic section is mapped read-only, so
ld.elf_so can't properly modify it (I imagine technically it could
with some mprotect shenanigans but that's not how it's done on MIPS).
Instead, the linker reserves a location in read/write memory and uses
a DT_MIPS_RLD_MAP entry with a pointer to that location.

However, in position-independent executables, the .dynamic entry
can't have an absolute pointer to that location because it's not
known up front. Instead, the the linker uses a DT_MIPS_RLD_MAP_REL
entry with the relative offset to that location from the Elf_Dyn
entry itself.

I would add a reference for this but it's basically a matter of UTSL
plus some oblique mentions on the web and mailing list discussions:

https://web.archive.org/web/20250414024823/https://cygwin.com/legacy-ml/binutils/2016-04/msg00244.html
https://web.archive.org/web/20250403151803/https://maskray.me/blog/2023-09-04-toolchain-notes-on-mips
https://web.archive.org/web/20211024050833/https://reviews.llvm.org/D12794?id=34533
https://web.archive.org/web/20250407052145/https://wiki.debian.org/MIPSPort
https://web.archive.org/web/20250414024924/https://reviews.freebsd.org/D17867?id=50122

PR port-mips/59296: t_rtld_r_debug test is failing
 1.20 06-Nov-2017  christos branches: 1.20.40;
Handle 64 bit kernels.
 1.19 06-Nov-2017  christos Cleanup and clarify the ELFSIZE mess:

We now have 2 variables automatically set in elf_machdep.h:

ARCH_ELFSIZE: the size for userland binaries
KERN_ELFSIZE: the size for the kernel binaries

DB_ELFSIZE has been deleted and KERN_ELFSIZE should have always the
same values DB_ELFSIZE used to have.

In sys/exec_elf.h, if ELFSIZE is not set, it is set to KERN_ELFSIZE
for the kernel and ARCH_ELFSIZE for userland. These defaults should
eliminate the need for most manual ELFSIZE setting.
 1.18 23-May-2013  christos add generic copyrights so FreeBSD can use them.
 1.17 30-Jan-2013  christos whitespace police
 1.16 30-Jan-2013  matt Add two missing relocs and DT_MIPS_PLTGOT and DT_MIPS_RWPLT
 1.15 15-Mar-2011  matt branches: 1.15.4; 1.15.14;
Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.
 1.14 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.13 14-Dec-2009  mrg branches: 1.13.4; 1.13.6; 1.13.8;
forward declare struct exec_package
 1.12 14-Dec-2009  matt Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.11 30-May-2009  skrll Add TLS relocation definitions.
 1.10 11-Dec-2005  christos branches: 1.10.42; 1.10.78; 1.10.96;
merge ktrace-lwp.
 1.9 31-Oct-2003  drochner don't need ELF_INTER_NON_RELOCATABLE anymore if no COMPAT_16, from simonb
 1.8 09-Dec-2001  thorpej branches: 1.8.16;
Add support for dumping ELF-cormat core files.
 1.7 02-Apr-2000  minoura branches: 1.7.8; 1.7.12;
Move dl* function definitions to libc on ELF.
Based on the patch supplied by Takuya Shiozaki <tshiozak@astec.co.jp>.
See http://mail-index.netbsd.org/tech-userlevel/2000/02/23/0000.html.
 1.6 25-Oct-1999  kleink Update to match new SVR4-style definition names in <sys/exec_elf.h>.
 1.5 24-Apr-1999  simonb branches: 1.5.2; 1.5.4; 1.5.6;
Nuke register and remove trailling white space.
 1.4 25-Mar-1998  mhitch branches: 1.4.12;
Define ELF dynamic types for MIPS (some will be used by ld.elf_so).
 1.3 03-Mar-1997  jonathan branches: 1.3.8;
Add architecture-specific ELf relocs for mips chips.
 1.2 11-Nov-1996  jonathan branches: 1.2.6;
Elf32 fixes for mips shared libraries:

* handle interpreters with nonzero virtual address of entry-point:
subtract p_vaddr from computed entrypoint, as the mips elf exec did.

* Add #ifdef ELF_INTERP_NON_RELOCATABLE/#endif around the code
that tries to choose a `good' address at which to load an interpreter,
if none was set by the emul probe function.
(the address chosen could be improved to avoid fragmenting the
process virtual address space).

* define ELF_INTERP_NON_RELOCATABLE in machine/elf_machdep.h for mips CPUs,
which currently use a GNU-derived ld.so.

ELF_INTERP_NON_RELOCATABLE is not necessary for native NetBSD/alpha ELF
binaries. It may be required for GNU-derived ELF dynamic loaders (Linux/i386?)
 1.1 26-Sep-1996  cgd add and use a machine-dependent header, which currently defines some
macros to use to remove #ifdefs from the machine ID case check.
Eventually, these headers will contain other information, e.g.
machine-dependent relocation information, etc.
 1.2.6.1 12-Mar-1997  is Merge in changes from Trunk
 1.3.8.1 10-May-1998  mycroft Pull up 1.4, per request of mhitch.
 1.4.12.1 21-Jun-1999  thorpej Sync w/ -current.
 1.5.6.1 27-Dec-1999  wrstuden Pull up to last week's -current.
 1.5.4.1 15-Nov-1999  fvdl Sync with -current
 1.5.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.7.12.1 08-Jan-2002  nathanw Catch up to -current.
 1.7.8.1 10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.8.16.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.8.16.2 18-Sep-2004  skrll Sync with HEAD.
 1.8.16.1 03-Aug-2004  skrll Sync with HEAD
 1.10.96.9 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.10.96.8 26-Jan-2010  matt If ELFSIZE == 64, define ELF64_MACHDEP_ID_CASES regardless of _LP64
 1.10.96.7 12-Sep-2009  matt Fix for COMPAT_NETBSD32.
 1.10.96.6 05-Sep-2009  matt Fix EF_ARCH_*. (should be in high nibble)
 1.10.96.5 23-Aug-2009  matt Make sure we only don't run other sized ELFs.
 1.10.96.4 22-Aug-2009  matt Move ELF{32,64}_MACHDEP_ENDIANNESS to <mips/elf_machdep.h>
 1.10.96.3 21-Aug-2009  matt Add prototypes for mips_netbsd_elfXX_probe to verify the current kernel
and cpu support the ABI and architecture specified in the elf header.
Add prototypes for moredump_elfXX_setup which will set the core dump
elf flags to the current abi and what the architecture of the current cpu.
 1.10.96.2 20-Aug-2009  matt On _LP64 default to ELFSIZE=64
Add a ELF64 default case for EM_MIPS
 1.10.96.1 16-Aug-2009  matt Kill use of _MIPS_BSD_ABI - switch to __mips_<abi>
Use device_t where appropriate.
Remove magic numbers.
 1.10.78.2 11-Mar-2010  yamt sync with head
 1.10.78.1 20-Jun-2009  yamt sync with head
 1.10.42.1 18-Jul-2007  matt Add MIPS EF_*. Add ELF64 stuff. Add hooks to check for ABI type.
 1.13.8.1 05-Mar-2011  bouyer Sync with HEAD
 1.13.6.1 06-Jun-2011  jruoho Sync with HEAD.
 1.13.4.2 21-Apr-2011  rmind sync with head
 1.13.4.1 05-Mar-2011  rmind sync with head
 1.15.14.3 03-Dec-2017  jdolecek update from HEAD
 1.15.14.2 23-Jun-2013  tls resync from head
 1.15.14.1 25-Feb-2013  tls resync with head
 1.15.4.1 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.20.40.1 02-Aug-2025  perseant Sync with HEAD
 1.20 23-May-2013  christos add generic copyrights so FreeBSD can use them.
 1.19 17-Mar-2000  mycroft branches: 1.19.168; 1.19.178;
In the `MY THAT'S GROSS' department...
Eliminate the recursive include of machine/endian.h from sys/endian.h.
 1.18 16-Mar-2000  mycroft Foolish consistency. Mainly, always use underscores and sys/endian.h.
 1.17 21-Aug-1999  simonb branches: 1.17.2;
Include <sys/endian.h> after defining whether where are little- or
big-endian. i386, pc532 and vax still include <machine/byte_swap.h>
and define macros for the {n,h}to{h,n}*() functions. mips also
defines some endian-independent assembly-code aliases for unaligned
memory accesses.
 1.16 24-Jan-1999  mycroft Mark [hn]to[nh][ls]() with __const__, so they are subject to CSE.
 1.15 15-Jan-1999  bouyer Move the bswap functions from libutil to libc (this bups the
minor of libc and the major of libutil). For little-endian architectures
merge the bnswap() assembly versions with nto* and hton* using symbols
aliasing. Use symbol renaming for the bswap function in this case to avoid
namespace pollution.
Declare bswap* in machine/bswap.h, not machine/endian.h. For little-endian
machines, common code for inline macros go in machine/byte_swap.h
Sync libkern with libc.
Adjust #include in kernel sources for machine/bswap.h.
 1.14 31-Jul-1998  mycroft (Always) (practice) (safe) (macro expansion).
 1.13 30-Oct-1997  jonathan branches: 1.13.2;
Add missing `(void)' cast to big-endian variant of {NTOH,HTON}{L,S}().
 1.12 20-Oct-1997  jonathan branches: 1.12.2;
Put back duplicate <XXX>_ENDIAN definitions. Defining them as _<XXX>_ENDIAN
loses on non-POSIX source that re-defines <XXX>_ENDIAN itself (e.g., gdb.)
 1.11 20-Oct-1997  jonathan * Use ANSI-clean names for host-specific byte-order definition
(_BYTE_ORDER, _BIG_ENDIAN, _LITTLE_ENDIAN).
Define old names from the ANSI ones if not _POSIX_SOURCE.
* Define _QUAD_HIGHWORD and _QUAD_LOWWORD properly when
_BYTE_ORDER == _BIG_ENDIAN.
 1.10 17-Oct-1997  jonathan Add bi-endian support to mips locore, <mips/endian.h>, and mips_opcode.h.
Derived from a change request (PR port-mips/4277) from
Tsubai Masanari, (tsubai@iri.co.jp).
 1.9 09-Oct-1997  bouyer Add byte-swapping functions (bswap16, bswap32, bswap64) to libkern.
Only assembly version for i386 bswap16 and bswap32 for now (bswap64 uses
bswap32). Contribution of assembly versions of these are welcome.
Add byte-swapping of ext2fs metadata for big-endian systems.
Tested on i386 and sparc.
 1.8 13-Oct-1996  mhitch branches: 1.8.10;
Fix error from in_addr_t changes by christos: htonl() takes in_addr_t
parameter, not in_port_t.
 1.7 13-Oct-1996  christos use in_addr_t and in_port_t
 1.6 05-Jun-1996  jonathan Include <mips/types.h> to bring u_int32_t and u_int16_t in scope for
the argument and return type of {n,h}to{h,n}{l,s}.
 1.5 09-Apr-1996  jonathan branches: 1.5.4;
Fixes for -Wall -Wmissing-prototypes:
Replace impliclty-sized types (u_long, u_short) used in
declarations of byteorder functions witho explicitly sized types
(u_int32_t, u_int16_t).

Avoids problems with using ntohl(foo) as (eg) an argument to printf().
 1.4 26-Oct-1994  cgd new RCS ID format.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.5.4.1 05-Jun-1996  jonathan Pull up u_int16_t and u_int32_t declaration fix from v1.6 of the main branch
 1.8.10.1 14-Oct-1997  thorpej Update marc-pcmcia branch from trunk.
 1.12.2.1 30-Oct-1997  mellon Pull rev 1.13 up from trunk (jonathan)
 1.13.2.1 08-Aug-1998  eeh Revert cdevsw mmap routines to return int.
 1.17.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.19.178.1 23-Jun-2013  tls resync from head
 1.19.168.1 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.3 23-May-2013  christos add generic copyrights so FreeBSD can use them.
 1.2 14-Dec-2009  matt branches: 1.2.12; 1.2.22;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.1 17-Mar-2000  mycroft branches: 1.1.6; 1.1.136; 1.1.154;
In the `MY THAT'S GROSS' department...
Eliminate the recursive include of machine/endian.h from sys/endian.h.
 1.1.154.2 23-Aug-2009  matt Add REG_SHI and REG_SLO
 1.1.154.1 20-Aug-2009  matt Add REG_LLO and REG_LHI macros which expand to the appropriate
lwl/lwr/ldl/ldr instruction
 1.1.136.1 11-Mar-2010  yamt sync with head
 1.1.6.2 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.1.6.1 17-Mar-2000  bouyer file endian_machdep.h was added on branch thorpej_scsipi on 2000-11-20 20:13:31 +0000
 1.2.22.1 23-Jun-2013  tls resync from head
 1.2.12.1 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.6 08-Oct-1996  cgd moved to aout_machdep.h (via repository copy)
 1.5 26-Oct-1994  cgd new RCS ID format.
 1.4 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.3 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.2 14-Jan-1994  deraadt some pmax updating (Terry Friedrichsen is helping on this now).
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.7 30-Oct-2024  riastradh Sprinkle <sys/featuretest.h> where _*_SOURCE macros are consulted.

Otherwise, the feature tests might come out wrong. For example,
header files that check for _NETBSD_SOURCE won't get the default when
no other _*_SOURCE macros are defined; header files that check for
_POSIX_C_SOURCE might miss _XOPEN_SOURCE, which is supposed to imply
a corresponding _POSIX_C_SOURCE.

PR lib/58752: various header files test _*_SOURCE macros but don't
include sys/featuretest.h
 1.6 26-Jul-2020  simonb branches: 1.6.26;
#define<tab>
Nuke trailing whitespace.
 1.5 29-Oct-2019  christos do the pragma dance to avoid -Wshadow
 1.4 22-Mar-2017  chs branches: 1.4.12; 1.4.16;
provide a common softfloat fenv implemenation and use it for softfloat builds.
restore ABI compatibility with previous releases for ieeefp.h on sh3.
add namespace.h protection for all the fenv interfaces.
use MKSOFTFLOAT on sh3 instead of assuming softfloat.
standardize on comparing MKSOFTFLOAT with "no".
remove the arm-specific softfloat fenv code (which also had several bugs).
fix logic errors in the arm hardfloat feraiseexcept() and feupdateenv().
 1.3 27-Feb-2017  chs fix fesetround() to set the FPSR to the desired value rather than
a pointer to a local variable. wrap the asm in inline functions so that
the compiler can do type checking for us.
 1.2 13-Jan-2017  christos branches: 1.2.2;
making this use mips assembly is a good start!
 1.1 21-Dec-2015  christos branches: 1.1.2; 1.1.4;
Add mips fenv.h (From FreeBSD)
 1.1.4.2 26-Apr-2017  pgoyette Sync with HEAD
 1.1.4.1 20-Mar-2017  pgoyette Sync with HEAD
 1.1.2.4 28-Aug-2017  skrll Sync with HEAD
 1.1.2.3 05-Feb-2017  skrll Sync with HEAD
 1.1.2.2 27-Dec-2015  skrll Sync with HEAD (as of 26th Dec)
 1.1.2.1 21-Dec-2015  skrll file fenv.h was added on branch nick-nhusb on 2015-12-27 12:09:38 +0000
 1.2.2.1 21-Apr-2017  bouyer Sync with HEAD
 1.4.16.1 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.4.12.2 03-Dec-2017  jdolecek update from HEAD
 1.4.12.1 22-Mar-2017  jdolecek file fenv.h was added on branch tls-maxphys on 2017-12-03 11:36:27 +0000
 1.6.26.1 02-Aug-2025  perseant Sync with HEAD
 1.20 30-Oct-2024  riastradh Sprinkle <sys/featuretest.h> where _*_SOURCE macros are consulted.

Otherwise, the feature tests might come out wrong. For example,
header files that check for _NETBSD_SOURCE won't get the default when
no other _*_SOURCE macros are defined; header files that check for
_POSIX_C_SOURCE might miss _XOPEN_SOURCE, which is supposed to imply
a corresponding _POSIX_C_SOURCE.

PR lib/58752: various header files test _*_SOURCE macros but don't
include sys/featuretest.h
 1.19 27-Apr-2024  rillig branches: 1.19.2;
mips: fix syntax error in LDBL_MAX (since 2011)
 1.18 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.17 23-May-2013  christos add generic copyrights so FreeBSD can use them.
 1.16 07-Jul-2011  matt branches: 1.16.2; 1.16.12;
Include <sys/cdefs.h> to get __GNUC_PREREQ__
 1.15 07-Jul-2011  matt If GCC 4.1 or newer (or clang), use __LDBL__*__ builtins otherwise if C99
use hex floating point.
 1.14 17-Jan-2011  matt Make the MIPS N32/N64 ABIs properly support 128-bit long doubles. With this
change, we should be fully conformant with the N32 and N64 ABIs.
Add {fpclassify,infinity,isnan,ininf,signbit}l_ieee754.c back to lib/libc/gen.
Note that infinityl_ieee754.c will work with either 64-bit, 80-bit, or
128-bit long doubles.
 1.13 12-May-2003  kleink branches: 1.13.126; 1.13.130; 1.13.136;
Rename <sys/float_ieee.h> to <sys/float_ieee754.h>, following libc's
convention for these.
 1.12 19-Apr-2003  christos PR/3012: Greg A. Woods: Write all float.h files [except the vax of course]
in terms of float_ieee.h
 1.11 28-Mar-2000  simonb Don't `extern' function declarations. While we're there, remove trailing
blank lines and white space.
 1.10 18-Feb-1998  mycroft branches: 1.10.16;
DBL_MIN and DBL_MAX were less precise than they should have been.
Other minor changes to match other float.h files.
 1.9 18-Oct-1997  jonathan branches: 1.9.2;
Prototype __flt_rounds().
 1.8 18-Mar-1996  jonathan NetBSD's ieee FP definitions for the pmax are valid for other mips cpus;
change preprocessor XXX_PMAX_YYY #defines to XXX_MIPS_YYY.
 1.7 20-Jun-1995  jtc Wrap with #ifndef _XXX_FLOAT_H_/#define _XXX_FLOAT_H_/ ... /#endif.
 1.6 20-Jun-1995  jtc #include <sys/cdefs.h>.
Wrap __flt_rounds() declaration with __BEGIN_DECLS/__END_DECLS.
 1.5 11-Apr-1995  jtc Changed FLT_ROUNDS from constant to a call to __flt_rounds(), so that the
current rounding mode is accurately reported.
 1.4 26-Oct-1994  cgd new RCS ID format.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.9.2.1 08-May-1998  mycroft Sync with trunk, per request of mycroft.
 1.10.16.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.13.136.1 06-Jun-2011  jruoho Sync with HEAD.
 1.13.130.1 05-Mar-2011  rmind sync with head
 1.13.126.1 29-Apr-2011  matt Pull in true (128-bit) long double support for MIPS from -current.
 1.16.12.1 23-Jun-2013  tls resync from head
 1.16.2.1 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.19.2.1 02-Aug-2025  perseant Sync with HEAD
 1.13 25-Apr-2025  riastradh mips: Align stack pointer on entry to signal handler.

Based on a patch by rin@. The variant approach I took puts the stack
frame allocation and alignment logic in one place (getframe, used by
sendsig_siginfo for native (n64, on mips), netbsd32_sendsig_siginfo
for compat32 (n32/o32, on mips), and sendsig_sigcontext (compat 1.6))
and reduces the chance of provoking compiler exploitation of
undefined behaviour by doing arithmetic in uintptr_t rather than in
pointers to large aligned structs. This also ensures the resulting
pointer is aligned for the object (struct siginfo_sigframe, struct
siginfo_sigframe32, struct sigcontext), not just for the ABI stack
alignment.

PR kern/59327: user stack pointer is not aligned properly
 1.12 29-Mar-2021  simonb branches: 1.12.22;
Add an lwp_trapframe() interface to return an LWP's user trapframe.
Needed by dtrace.
 1.11 24-Mar-2021  simonb We don't really need a comment at the end of the file saying "this is
the end of the file".
 1.10 26-Jul-2020  simonb branches: 1.10.2; 1.10.4;
#define<tab>
Nuke trailing whitespace.
 1.9 19-Feb-2012  rmind Remove COMPAT_SA / KERN_SA. Welcome to 6.99.3!
Approved by core@.
 1.8 15-Oct-2008  wrstuden branches: 1.8.28; 1.8.32;
Merge wrstuden-revivesa into HEAD.
 1.7 28-Apr-2008  martin branches: 1.7.2; 1.7.6;
Remove clause 3 and 4 from TNF licenses
 1.6 09-Feb-2007  ad branches: 1.6.44; 1.6.46; 1.6.48;
Merge newlock2 to head.
 1.5 11-Dec-2005  christos branches: 1.5.20;
merge ktrace-lwp.
 1.4 24-Jan-2005  drochner branches: 1.4.8;
-remove definition of "struct sigframe" -- haven't found a use of it
(should fix build problems w/o COMPAT_16 reported by Markus W Kilbinger
per PR port-mips/29041 and by Havard Eidnes)
-further shuffle COMPAT_* conditionals to allow COMPAT_ULTRIX
w/o COMPAT_16
 1.3 29-Oct-2003  christos branches: 1.3.8;
first pass siginfo for mips
 1.2 17-Jan-2003  thorpej branches: 1.2.2;
Merge the nathanw_sa branch.
 1.1 28-Nov-2001  wdk branches: 1.1.2;
file frame.h was initially added on branch nathanw_sa.
 1.1.2.3 02-Aug-2002  nathanw Remove unised members from struct sigframe (Parallel change to mainline).
 1.1.2.2 29-Nov-2001  wdk Mips calling convention requires stack space be allocated for the
register passed arguments. Update struct saframe definition to reflect
the calling convention. This ensures the 5th argument to the upcall
handler (which has to be passed on the stack) lands in the correct address.
 1.1.2.1 28-Nov-2001  wdk Add missing mips/frame.h header file.

Move struct siginfo definition from mips_machdep.c

Partially resolves PR#11871
 1.2.2.4 04-Feb-2005  skrll Sync with HEAD.
 1.2.2.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.2.2.2 18-Sep-2004  skrll Sync with HEAD.
 1.2.2.1 03-Aug-2004  skrll Sync with HEAD
 1.3.8.1 29-Apr-2005  kent sync with -current
 1.4.8.1 26-Feb-2007  yamt sync with head.
 1.5.20.1 30-Jan-2007  ad Remove support for SA. Ok core@.
 1.6.48.2 04-May-2009  yamt sync with head.
 1.6.48.1 16-May-2008  yamt sync with head.
 1.6.46.1 18-May-2008  yamt sync with head.
 1.6.44.2 17-Jan-2009  mjf Sync with HEAD.
 1.6.44.1 02-Jun-2008  mjf Sync with HEAD.
 1.7.6.1 19-Oct-2008  haad Sync with HEAD.
 1.7.2.3 22-Jun-2008  wrstuden Re-add cpu_upcall() and page fault code. i386 kernels now compile.
They don't boot, but that seems to be a consequence of current from the
day this branch was started.
 1.7.2.2 14-May-2008  wrstuden Per discussion with ad, remove most of the #include <sys/sa.h> lines
as they were including sa.h just for the type(s) needed for syscallargs.h.

Instead, create a new file, sys/satypes.h, which contains just the
types needed for syscallargs.h. Yes, there's only one now, but that
may change and it's probably more likely to change if it'd be difficult
to handle. :-)

Per discussion with matt at n dot o, add an include of satypes.h to
sigtypes.h. Upcall handlers are kinda signal handlers, and signalling
is the header file that's already included for syscallargs.h that
closest matches SA.

This shaves about 3000 lines off of the diff of the branch relative
to the base. That also represents about 18% of the total before this
checkin.

I think this reduction is very good thing.
 1.7.2.1 10-May-2008  wrstuden Initial checkin of re-adding SA. Everything except kern_sa.c
compiles in GENERIC for i386. This is still a work-in-progress, but
this checkin covers most of the mechanical work (changing signalling
to be able to accomidate SA's process-wide signalling and re-adding
includes of sys/sa.h and savar.h). Subsequent changes will be much
more interesting.

Also, kern_sa.c has received partial cleanup. There's still more
to do, though.
 1.8.32.1 24-Feb-2012  mrg sync to -current.
 1.8.28.1 17-Apr-2012  yamt sync with head
 1.10.4.1 03-Apr-2021  thorpej Sync with HEAD.
 1.10.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.12.22.1 02-Aug-2025  perseant Sync with HEAD
 1.11 31-Jan-2014  matt Consolidate the 128-bit long double defintions to <sys/ieee754.h>
Each arch that uses it now defines __HAVE_LONG_DOUBLE to 128.
<machine/ieee.h> is now just include the machine's math.h followed
by <sys/ieee754.h>
 1.10 31-Jan-2014  matt Convert to uint64_t
 1.9 14-Feb-2013  matt branches: 1.9.2;
Define LDBL_IMPLICIT_NBIT
 1.8 14-Feb-2013  matt Make LDBL_NBIT and mask_nbit_l have no effect.
 1.7 08-Jul-2011  matt branches: 1.7.2; 1.7.12;
Add extu_fraclm and extu_frachm
 1.6 17-Jan-2011  matt Make the MIPS N32/N64 ABIs properly support 128-bit long doubles. With this
change, we should be fully conformant with the N32 and N64 ABIs.
Add {fpclassify,infinity,isnan,ininf,signbit}l_ieee754.c back to lib/libc/gen.
Note that infinityl_ieee754.c will work with either 64-bit, 80-bit, or
128-bit long doubles.
 1.5 11-Dec-2005  christos branches: 1.5.96; 1.5.100; 1.5.106;
merge ktrace-lwp.
 1.4 15-Apr-2005  kleink Push back the descriptions of NaN formats, and descriptions of the
distinction between signalling NaNs and quiet NaNs back into the
machine-dependent headers; treat the implementation of __nanf in the
same spirit.

IEEE 754 leaves the distinction between signalling NaNs and quiet NANs
to the implementation, and unlike our headers used to suggest they're
not identical in the interpretation of the fraction's MSb; in due
course, make those of hppa, mips, sh3, and sh5 reflect reality.
 1.3 26-Oct-2003  kleink branches: 1.3.8; 1.3.14;
Use <sys/ieee754.h> where applicable.
 1.2 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.1 29-Aug-1999  mycroft branches: 1.1.36;
Add ieee.h.
 1.1.36.4 10-Nov-2005  skrll Sync with HEAD. Here we go again...
 1.1.36.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.1.36.2 18-Sep-2004  skrll Sync with HEAD.
 1.1.36.1 03-Aug-2004  skrll Sync with HEAD
 1.3.14.1 19-Apr-2005  tron Pull up revision 1.4 (requested by kleink in ticket #163):
Push back the descriptions of NaN formats, and descriptions of the
distinction between signalling NaNs and quiet NaNs back into the
machine-dependent headers; treat the implementation of __nanf in the
same spirit.
IEEE 754 leaves the distinction between signalling NaNs and quiet NANs
to the implementation, and unlike our headers used to suggest they're
not identical in the interpretation of the fraction's MSb; in due
course, make those of hppa, mips, sh3, and sh5 reflect reality.
 1.3.8.1 29-Apr-2005  kent sync with -current
 1.5.106.1 06-Jun-2011  jruoho Sync with HEAD.
 1.5.100.1 05-Mar-2011  rmind sync with head
 1.5.96.1 29-Apr-2011  matt Pull in true (128-bit) long double support for MIPS from -current.
 1.7.12.2 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.7.12.1 25-Feb-2013  tls resync with head
 1.7.2.1 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.9.2.1 18-May-2014  rmind sync with head
 1.11 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.10 22-Mar-2017  chs provide a common softfloat fenv implemenation and use it for softfloat builds.
restore ABI compatibility with previous releases for ieeefp.h on sh3.
add namespace.h protection for all the fenv interfaces.
use MKSOFTFLOAT on sh3 instead of assuming softfloat.
standardize on comparing MKSOFTFLOAT with "no".
remove the arm-specific softfloat fenv code (which also had several bugs).
fix logic errors in the arm hardfloat feraiseexcept() and feupdateenv().
 1.9 27-Feb-2017  chs the FP_* rounding constants need to be different from the new FE_* constants
to preserve the ABI, so shift them as needed when using them.
 1.8 25-Dec-2015  christos branches: 1.8.2; 1.8.4;
remove dup fenv
 1.7 19-Mar-2012  matt branches: 1.7.2; 1.7.16;
Use unsigned int instead of int fo the fp* typedefs.
 1.6 27-Jan-2011  tsutsui branches: 1.6.4; 1.6.8;
Fix swapped comments.
 1.5 05-Aug-2008  matt branches: 1.5.12; 1.5.16; 1.5.22; 1.5.24;
Update <machine/ieeefp.h> to use the C99 FE_* definitions instead of the
NetBSD defined ones. Redefine the NetBSD ones in terms of the C99 ones.
Step 1 to having <fenv.h>
 1.4 24-Apr-1999  simonb branches: 1.4.138; 1.4.142; 1.4.144; 1.4.148;
Nuke register and remove trailling white space.
 1.3 05-Jan-1998  perry branches: 1.3.12;
RCSID Police.
 1.2 18-Mar-1996  jonathan NetBSD's ieee FP definitions for the pmax are valid for other mips cpus;
change preprocessor XXX_PMAX_YYY #defines to XXX_MIPS_YYY.
 1.1 11-Apr-1995  jtc Mips specific portions of ieeefp.h (fp_rnd, fp_except, constants, etc.).
 1.3.12.1 21-Jun-1999  thorpej Sync w/ -current.
 1.4.148.1 19-Oct-2008  haad Sync with HEAD.
 1.4.144.1 18-Sep-2008  wrstuden Sync with wrstuden-revivesa-base-2.
 1.4.142.1 04-May-2009  yamt sync with head.
 1.4.138.1 28-Sep-2008  mjf Sync with HEAD.
 1.5.24.1 08-Feb-2011  bouyer Sync with HEAD
 1.5.22.1 06-Jun-2011  jruoho Sync with HEAD.
 1.5.16.1 05-Mar-2011  rmind sync with head
 1.5.12.1 29-Apr-2011  matt Pull in true (128-bit) long double support for MIPS from -current.
 1.6.8.1 05-Apr-2012  mrg sync to latest -current.
 1.6.4.1 17-Apr-2012  yamt sync with head
 1.7.16.2 28-Aug-2017  skrll Sync with HEAD
 1.7.16.1 27-Dec-2015  skrll Sync with HEAD (as of 26th Dec)
 1.7.2.1 03-Dec-2017  jdolecek update from HEAD
 1.8.4.1 21-Apr-2017  bouyer Sync with HEAD
 1.8.2.2 26-Apr-2017  pgoyette Sync with HEAD
 1.8.2.1 20-Mar-2017  pgoyette Sync with HEAD
 1.6 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.5 13-Aug-2014  matt Include <sys/common_int_const.h> if __INTMAX_C_SUFFIX__ is defined.
 1.4 29-May-2010  tnozaki branches: 1.4.18;
fix wrong integer promotion rule(removed U suffix from UINT{8,16}_C).
see ISO/IEC 9899:1999 7.18.4.3.
 1.3 28-Apr-2008  martin branches: 1.3.20; 1.3.22;
Remove clause 3 and 4 from TNF licenses
 1.2 03-Nov-2002  thorpej branches: 1.2.108; 1.2.110; 1.2.112;
Add LP64 macros.
 1.1 14-Apr-2001  kleink branches: 1.1.2; 1.1.4; 1.1.12;
Add definitions of C99 integer constant macros.
 1.1.12.2 11-Nov-2002  nathanw Catch up to -current
 1.1.12.1 14-Apr-2001  nathanw file int_const.h was added on branch nathanw_sa on 2002-11-11 22:00:27 +0000
 1.1.4.1 21-Jun-2001  nathanw Catch up to -current.
 1.1.2.2 21-Apr-2001  bouyer Sync with HEAD
 1.1.2.1 14-Apr-2001  bouyer file int_const.h was added on branch thorpej_scsipi on 2001-04-21 17:54:01 +0000
 1.2.112.2 11-Aug-2010  yamt sync with head.
 1.2.112.1 16-May-2008  yamt sync with head.
 1.2.110.1 18-May-2008  yamt sync with head.
 1.2.108.1 02-Jun-2008  mjf Sync with HEAD.
 1.3.22.1 30-May-2010  rmind sync with head
 1.3.20.1 17-Aug-2010  uebayasi Sync with HEAD.
 1.4.18.1 03-Dec-2017  jdolecek update from HEAD
 1.7 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.6 13-Aug-2014  matt include <sys/common_int_fmtio.h> if __INTPTR_FMTd__ is defined
 1.5 14-Dec-2009  matt branches: 1.5.22;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.4 28-Apr-2008  martin branches: 1.4.18;
Remove clause 3 and 4 from TNF licenses
 1.3 03-Nov-2002  thorpej branches: 1.3.108; 1.3.110; 1.3.112;
Add LP64 types, limits, formats.
 1.2 26-Apr-2001  kleink branches: 1.2.2; 1.2.10;
Add definitions for C99 fastest minimum-width integer types.
 1.1 15-Apr-2001  kleink branches: 1.1.2;
Add definitions of C99 integer format conversion macros.
XXX Fastest minimum-width integer types haven't been decided upon yet.
 1.1.2.2 21-Apr-2001  bouyer Sync with HEAD
 1.1.2.1 15-Apr-2001  bouyer file int_fmtio.h was added on branch thorpej_scsipi on 2001-04-21 17:54:01 +0000
 1.2.10.2 11-Nov-2002  nathanw Catch up to -current
 1.2.10.1 26-Apr-2001  nathanw file int_fmtio.h was added on branch nathanw_sa on 2002-11-11 22:00:27 +0000
 1.2.2.1 21-Jun-2001  nathanw Catch up to -current.
 1.3.112.2 11-Mar-2010  yamt sync with head
 1.3.112.1 16-May-2008  yamt sync with head.
 1.3.110.1 18-May-2008  yamt sync with head.
 1.3.108.1 02-Jun-2008  mjf Sync with HEAD.
 1.4.18.1 11-Dec-2009  matt Unless we are in O32, use long int for size_t/ptrdiff_t/intptr_t. This
allows N32 and N64 use both use the same type.
 1.5.22.1 03-Dec-2017  jdolecek update from HEAD
 1.10 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.9 13-Aug-2014  matt Include <sys/common_init_limits.h> if __SIG_ATOMIC_MAX__ is defined.
 1.8 28-Apr-2008  martin branches: 1.8.44;
Remove clause 3 and 4 from TNF licenses
 1.7 17-Oct-2007  garbled branches: 1.7.16; 1.7.18; 1.7.20;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.6 31-Aug-2007  drochner Fix definitions of UCHAR_MAX/USHRT_MAX and related
types. C99 requires that these definitions promote to (signed/unsigned)
integer the same way as the types the definition is for. And since
unsigned char/short fit into an "int" on all our archs and thus promote
to signed int, the definitions must not be unsigned.
Fixes PR lib/31306 by Neil Booth.
 1.5 11-Dec-2005  christos branches: 1.5.30; 1.5.38; 1.5.44; 1.5.48; 1.5.50;
merge ktrace-lwp.
 1.4 08-May-2004  kleink branches: 1.4.12;
Factor out W{CHAR,INT}_{MAX,MIN} into their own header file.
 1.3 03-Nov-2002  thorpej branches: 1.3.6;
Add LP64 types, limits, formats.
 1.2 26-Apr-2001  kleink branches: 1.2.2; 1.2.10;
Add definitions for C99 fastest minimum-width integer types.
 1.1 15-Apr-2001  kleink branches: 1.1.2;
Add definitions of C99 specified-width integer type limits.
XXX Fastest minimum-width integer types haven't been decided upon yet.
 1.1.2.2 21-Apr-2001  bouyer Sync with HEAD
 1.1.2.1 15-Apr-2001  bouyer file int_limits.h was added on branch thorpej_scsipi on 2001-04-21 17:54:01 +0000
 1.2.10.2 11-Nov-2002  nathanw Catch up to -current
 1.2.10.1 26-Apr-2001  nathanw file int_limits.h was added on branch nathanw_sa on 2002-11-11 22:00:27 +0000
 1.2.2.1 21-Jun-2001  nathanw Catch up to -current.
 1.3.6.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.3.6.2 18-Sep-2004  skrll Sync with HEAD.
 1.3.6.1 03-Aug-2004  skrll Sync with HEAD
 1.4.12.1 03-Sep-2007  yamt sync with head.
 1.5.50.1 06-Nov-2007  matt sync with HEAD
 1.5.48.1 03-Sep-2007  jmcneill Sync with HEAD.
 1.5.44.1 03-Sep-2007  skrll Sync with HEAD.
 1.5.38.1 03-Oct-2007  garbled Sync with HEAD
 1.5.30.1 09-Oct-2007  ad Sync with head.
 1.7.20.1 16-May-2008  yamt sync with head.
 1.7.18.1 18-May-2008  yamt sync with head.
 1.7.16.1 02-Jun-2008  mjf Sync with HEAD.
 1.8.44.1 03-Dec-2017  jdolecek update from HEAD
 1.7 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.6 13-Aug-2014  matt include <sys/common_int_mwgwtypes.h> if __UINT_FAST64_TYPE__ is defined.
 1.5 28-Apr-2008  martin branches: 1.5.44;
Remove clause 3 and 4 from TNF licenses
 1.4 24-Dec-2005  perry branches: 1.4.74; 1.4.76; 1.4.78;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.
 1.3 03-Nov-2002  thorpej branches: 1.3.22;
Add LP64 types, limits, formats.
 1.2 26-Apr-2001  kleink branches: 1.2.2; 1.2.10;
Add definitions for C99 fastest minimum-width integer types.
 1.1 14-Apr-2001  kleink branches: 1.1.2;
Add definitions of C99 minimum-width and greatest-width integer types.
XXX Fastest minimum-width integer types haven't been decided upon yet.
 1.1.2.2 21-Apr-2001  bouyer Sync with HEAD
 1.1.2.1 14-Apr-2001  bouyer file int_mwgwtypes.h was added on branch thorpej_scsipi on 2001-04-21 17:54:01 +0000
 1.2.10.2 11-Nov-2002  nathanw Catch up to -current
 1.2.10.1 26-Apr-2001  nathanw file int_mwgwtypes.h was added on branch nathanw_sa on 2002-11-11 22:00:28 +0000
 1.2.2.1 21-Jun-2001  nathanw Catch up to -current.
 1.3.22.1 21-Jun-2006  yamt sync with head.
 1.4.78.1 16-May-2008  yamt sync with head.
 1.4.76.1 18-May-2008  yamt sync with head.
 1.4.74.1 02-Jun-2008  mjf Sync with HEAD.
 1.5.44.1 03-Dec-2017  jdolecek update from HEAD
 1.12 13-Aug-2014  matt Include <sys/common_int_types.h> if __UINTPTR_TYPE__ is defined.
 1.11 14-Dec-2009  matt branches: 1.11.22;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.10 24-Dec-2005  perry branches: 1.10.78; 1.10.96;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.
 1.9 11-Dec-2005  christos merge ktrace-lwp.
 1.8 25-May-2005  kleink branches: 1.8.2;
Include <sys/cdefs.h> for __signed; related to lib/30072.
 1.7 07-Aug-2003  agc branches: 1.7.6; 1.7.14;
Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.6 03-Nov-2002  thorpej branches: 1.6.6;
Add LP64 types.
 1.5 28-Apr-2001  kleink branches: 1.5.8;
* Move definitions of exact-width integer types from <machine/types.h>
to <sys/types.h> and <sys/stdint.h>.
* Add a new C99 <stdint.h> header, which provides integer types of
explicit width, related limits and integer constant macros.
* Extend <inttypes.h> to provide <stdint.h> definitions and format
macros for printf() and scanf().
* Add C99 strtoimax() and strtoumax() functions.
* Use the latter within scanf().
* Add C99 %j, %t and %z printf()/scanf() conversions for
intmax_t, pointer-type and size_t arguments.
 1.4 12-Apr-2001  kleink Replace the 'unsigned __COMPILER_INT64__' construct with a new name,
__COMPILER_UINT64__, to be supplied - if such a case is made, it shouldn't
be assumed that the unsigned type-specifier may be applied to it.
 1.3 03-Jan-2001  takemura branches: 1.3.2;
replace 'long long' with int64_t to compile stand alone program with
compiler other than GCC.
 1.2 27-Jun-2000  kleink branches: 1.2.2;
Resolve some formatting nits; add __intptr_t and __uintptr_t.
 1.1 26-Jun-2000  kleink Add <machine/int_types.h>, which provides namespace-pure definitions
of exact-width integer types.
 1.2.2.4 21-Apr-2001  bouyer Sync with HEAD
 1.2.2.3 05-Jan-2001  bouyer Sync with HEAD
 1.2.2.2 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.2.2.1 27-Jun-2000  bouyer file int_types.h was added on branch thorpej_scsipi on 2000-11-20 20:13:31 +0000
 1.3.2.1 21-Jun-2001  nathanw Catch up to -current.
 1.5.8.2 11-Nov-2002  nathanw Catch up to -current
 1.5.8.1 28-Apr-2001  nathanw file int_types.h was added on branch nathanw_sa on 2002-11-11 22:00:28 +0000
 1.6.6.4 10-Nov-2005  skrll Sync with HEAD. Here we go again...
 1.6.6.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.6.6.2 18-Sep-2004  skrll Sync with HEAD.
 1.6.6.1 03-Aug-2004  skrll Sync with HEAD
 1.7.14.1 28-May-2005  tron Pull up revision 1.8 (requested by klein in ticket #346):
Include <sys/cdefs.h> for __signed; related to lib/30072.
 1.7.6.1 29-May-2005  riz Pull up revision 1.8 (requested by kleink in ticket #1555):
Include <sys/cdefs.h> for __signed; related to lib/30072.
 1.8.2.1 21-Jun-2006  yamt sync with head.
 1.10.96.1 11-Dec-2009  matt Unless we are in O32, use long int for size_t/ptrdiff_t/intptr_t. This
allows N32 and N64 use both use the same type.
 1.10.78.1 11-Mar-2010  yamt sync with head
 1.11.22.1 03-Dec-2017  jdolecek update from HEAD
 1.13 16-Feb-2021  simonb Add no-profiled attribute for splhigh_noprof() and splx_noprof().
 1.12 17-Aug-2020  skrll branches: 1.12.2;
Disable __HAVE_PREEMPTION. It is currently marked

#if defined(MULTIPROCESSOR) && defined(__HAVE_FAST_SOFTINTS)

but has no chance of working on OCTEON due to at least the spl functions
 1.11 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.10 06-Jun-2015  matt Add a IPI for watchdogs.
 1.9 01-Jun-2015  matt Rework cavium support in preparation for MULTIPROCESSOR support
 1.8 19-May-2014  rmind branches: 1.8.4;
Implement MI IPI interface with cross-call support.
 1.7 11-Mar-2012  mrg branches: 1.7.2; 1.7.12;
normalise RCSID handling some.
 1.6 03-Mar-2012  matt define IPL_SAFEPRI which will be used by kern_synch.c to initialize safepri.
 1.5 02-May-2011  matt branches: 1.5.4; 1.5.8;
Add an IPI for xcalls.
 1.4 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.3 11-Apr-2000  nisimura branches: 1.3.96; 1.3.98; 1.3.104; 1.3.106;
Introduce cpu_intr() whose body is now provided by target ports in
their own ways. Ugly fixup #define in machine/intr.h have gone.
mips_hardware_intr global variable patch work has gone.
 1.2 28-Mar-2000  simonb Don't `extern' function declarations. While we're there, remove trailing
blank lines and white space.
 1.1 26-Mar-1998  jonathan branches: 1.1.16;
* Create /sys/arch/mips/include/intr.h, with extern declaration of
interrupt-callout vector from mips locore dispatch code to port code.
* Move branch-emulation declaration to mips/include/trap.h.
* Garbage-collect pmax/pmax/trap.h.
Not needed now pmax/pmax_trap.c is gone, and after above tidy-up.
 1.1.16.1 20-Nov-2000  bouyer Remove files that are no longer on the trunck
 1.3.106.1 05-Mar-2011  bouyer Sync with HEAD
 1.3.104.1 06-Jun-2011  jruoho Sync with HEAD.
 1.3.98.2 31-May-2011  rmind sync with head
 1.3.98.1 05-Mar-2011  rmind sync with head
 1.3.96.18 19-Jan-2012  matt When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses. There are exceptions.
bus_space_handles are now register_t instead of intptr_t. This allows them
to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address. This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs. If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.
 1.3.96.17 31-Dec-2011  matt Add IST_EDGE_RISING and IST_EDGE_FALLING.
 1.3.96.16 05-Feb-2011  cliff - protect option includes ("opt_multiprocessor.h") with #ifdef _KERNEL_OPT
 1.3.96.15 05-Feb-2011  cliff - include opt_multiprocessor.h for MULTIPROCESSOR dependency
- add IPI tag defines for SUSPEND, HALT, and bump NIPIS
 1.3.96.14 22-Dec-2010  matt Cleanup definition of __HAVE_PREEMPTION
 1.3.96.13 09-Jun-2010  matt Add a _IPL_NAMES(pfx) which is a list of strings corresponding to the
IPL names.
 1.3.96.12 16-May-2010  matt Add IPL_DDB. This is needed for watchdog on sbmips and for IPIs used by DDB.
It's above IPL_SCHED but below IPL_HIGH.
 1.3.96.11 15-May-2010  matt Make sure we have a spare cell at the sr_map to make splintr will stop.
 1.3.96.10 24-Mar-2010  cliff - add IPI_AST variant of IPI_NOP to allow seperate event counting
 1.3.96.9 21-Mar-2010  cliff - if __INTR_PRIVATE is not defined, declare (but do not define) struct splsw
 1.3.96.8 11-Mar-2010  matt s/IPI_ISYNC/IPI_SYNCICACHE/
 1.3.96.7 28-Feb-2010  matt Split FPU support into separate file and keep internals private to that file.
Make it MPSAFE. Change interface to be very similar to what's used on other
architectures.
Add l_md.md_fpcpu to mdlwp (needed for MPSAFE)
Move pridtab from <mips/cpu.h> to <mips/locore.h>
Add initial common IPI dispatcher.
Split cpu_* routines from mips_machdep.c into cpu_subr.c
Add cpu_startup_common which has the code replicated in half-dozen
plus machdep.c files.
 1.3.96.6 28-Feb-2010  matt Now that we use stubs for the spl* calls, we no longer need to export
struct splsw or struct ipl_sr_map to the world. So we protect those with
__INTR_PRIVATE.
 1.3.96.5 23-Feb-2010  matt Instead of a read-only ipl_sr_bits, define a ipl_sr_map struct and fill that
in the interrupt init routine. There's a default ipl_sr_map will operate
correctly, but isn't performant.
 1.3.96.4 22-Feb-2010  matt Add initial list of IPIs for MIPS SMP.
 1.3.96.3 16-Feb-2010  matt Add __HAVE_PREEMPTION support for NetBSD/mips. Kill IPL_PREEMPT since it
isn't needed.
 1.3.96.2 15-Feb-2010  matt Completely redo how interrupts and SPL are handled in NetBSD/mips.
[XXX locore_mips1.S still needs to adapted.]

Nested interrupts now work. Except for MIPS_SOFT_MASK and MIPS_SR_INT_IE,
how interrupts work is completely abstracted. spl is handled through the
mips_splsw table. Direct manipulation of the status register is no longer
done (except for MIPS_SR_INT_IE). A new <mips/intr.h> contains the common
IPL/IST/spl* definitions for all ports.

Interrupt delivery is completely different. Clock interrupts may interrupt
device interrupts. ci_idepth is now handled by the caller of cpu_intr as
are softints (both can be optimized/simplified in the case of interrupts of
usermode code). cpu_intr has new arguments and now get called at IPL_HIGH
with MIPS_SR_INT_IE set and its logic is:

void
cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
int ipl;
uint32_t pending;
while (ppl < (ipl = splintr(&pending))) {
splx(ipl); /* enable interrupts */
<handle pending interrupts>
(void)splhigh(); /* disable interrupts */
}
}

mipsX_subr.S has been reworked. All user handlers (user_intr, systemcall,
user_gen_exception) now use common return to usermode code in lwp_trampoline.
ast() has changed to void ast(void) since the previous pc argument was never
used.

The playstation IPL_ICU_MASK support has been nuked.
MIPS_DYNAMIC_STATUS_MASK may soon be nuked soon.

A bunch of debugging code was left conditionalized by PARANOIA. If this
code detects a bug, it will enter an infinite loop. It is expected that
the kernel will be debugged in a simulator or with a hardware debugger so
that the state at that point can be analyzed.
 1.3.96.1 11-Apr-2000  matt file intr.h was added on branch matt-nb5-mips64 on 2010-02-15 07:36:03 +0000
 1.5.8.3 06-Mar-2012  mrg sync to -current
 1.5.8.2 06-Mar-2012  mrg sync to -current
 1.5.8.1 04-Mar-2012  mrg sync to latest -current.
 1.5.4.1 17-Apr-2012  yamt sync with head
 1.7.12.1 10-Aug-2014  tls Rebase.
 1.7.2.2 03-Dec-2017  jdolecek update from HEAD
 1.7.2.1 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.8.4.1 06-Jun-2015  skrll Sync with HEAD
 1.12.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.9 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.8 18-Oct-2016  jdolecek add isa_intr_establish_xname() to MD isa headers so that it can be used
by MI drivers
 1.7 30-Mar-2014  macallan branches: 1.7.6; 1.7.10;
catch up with *_intr_string() changes
 1.6 29-Mar-2014  christos make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.
 1.5 14-Dec-2009  matt branches: 1.5.12; 1.5.22; 1.5.26;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.4 19-Aug-2009  dyoung (Re-)define isa_detach_hook(), and define isa_dmadestroy(). Update
some isa_chipset_tag_t->ic_detach_hook() definitions.
 1.3 28-Apr-2008  martin branches: 1.3.18;
Remove clause 3 and 4 from TNF licenses
 1.2 09-May-2003  fvdl branches: 1.2.104; 1.2.106; 1.2.108;
A few ISA sound drivers like to share dma channels, and hence deferred
isa_dmamap_create() calls to their open/close entrypoints. This worked
with some luck, but broke on i386 when _bus_dmamap_create started
to allocate bounce buffers upfront, since memory below 16M may well
not be available when the sound devices is opened for the Nth time.

To fix this, create a new simple interface, isa_drq_alloc/isa_drq_free,
wrappers around already existing bitmask macros. These are expected
to be used before an isa_dmamap_create call, and after an
isa_dmamap_destroy call, respectively. For the sb and ad1848 drivers,
they're deferred until open/close.

All isa_dmamap_create calls can now use BUS_DMA_ALLOCNOW and be done
at attach time.
 1.1 18-Mar-2002  simonb branches: 1.1.4; 1.1.10;
Generic PCI/ISA machdep headers for mips; copied from the algor port.
 1.1.10.2 23-Jun-2002  jdolecek catch up with -current on kqueue branch
 1.1.10.1 18-Mar-2002  jdolecek file isa_machdep.h was added on branch kqueue on 2002-06-23 17:38:02 +0000
 1.1.4.2 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.1.4.1 18-Mar-2002  nathanw file isa_machdep.h was added on branch nathanw_sa on 2002-04-01 07:40:58 +0000
 1.2.108.3 11-Mar-2010  yamt sync with head
 1.2.108.2 19-Aug-2009  yamt sync with head.
 1.2.108.1 16-May-2008  yamt sync with head.
 1.2.106.1 18-May-2008  yamt sync with head.
 1.2.104.1 02-Jun-2008  mjf Sync with HEAD.
 1.3.18.1 16-Aug-2009  matt Kill use of _MIPS_BSD_ABI - switch to __mips_<abi>
Use device_t where appropriate.
Remove magic numbers.
 1.5.26.1 18-May-2014  rmind sync with head
 1.5.22.2 03-Dec-2017  jdolecek update from HEAD
 1.5.22.1 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.5.12.1 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.7.10.1 04-Nov-2016  pgoyette Sync with HEAD
 1.7.6.1 05-Dec-2016  skrll Sync with HEAD
 1.4 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.3 12-Jun-2015  matt Add back sysmapsize
 1.2 11-Jun-2015  matt u_int32_t -> uint32_t
 1.1 19-Feb-1998  thorpej branches: 1.1.174; 1.1.200; 1.1.220;
New crash dump format definition for NetBSD/mips.
 1.1.220.1 22-Sep-2015  skrll Sync with HEAD
 1.1.200.1 03-Dec-2017  jdolecek update from HEAD
 1.1.174.1 27-Dec-2011  matt Add pg_size to the cpu_kcore_hdr_t as well support for ksegx.
 1.9 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.8 11-Dec-2005  christos merge ktrace-lwp.
 1.7 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.6 05-Mar-2002  simonb branches: 1.6.14;
ANSIfy.
 1.5 22-Jun-1997  jonathan branches: 1.5.38; 1.5.42;
* Change Sprite MACH_xxx prefix to MIPS_xxx.

* Use standard mips terminology (xxx_KSEG0, xxx_KSEG1) instead of the
(more meaningful) Sprite names (xxx_CACHED, xxx_UNCACHED).
 1.4 26-Oct-1994  cgd new RCS ID format.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.5.42.1 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.5.38.1 16-Mar-2002  jdolecek Catch up with -current.
 1.6.14.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.6.14.2 18-Sep-2004  skrll Sync with HEAD.
 1.6.14.1 03-Aug-2004  skrll Sync with HEAD
 1.29 16-Mar-2024  christos make all QUAD constants look the same.
 1.28 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.27 21-Jan-2019  dholland Fix wrong scoping of {U,}LLONG_MAX. More cases, not just amd64.
PR 53298 from Roberto E. Vargas Caballero.
 1.26 21-Apr-2014  matt branches: 1.26.26; 1.26.28;
Since all our compilers support __DBL_* and __FLT_*, use them to define
{DBL,FLT}_{DIG,MIN,MAX}
 1.25 11-Apr-2013  christos branches: 1.25.4; 1.25.8;
add missing SSIZE_MIN
 1.24 28-Mar-2012  christos branches: 1.24.2;
- Normalize inclusion protection (remove)
- Move CHAR_{MIN,MAX} to a common file.
- Fix broken comments
 1.23 07-Jun-2010  tnozaki branches: 1.23.8; 1.23.12;
1. MB_LEN_MAX switch MD to MI.
2. unfortunately hppa's MB_LEN_MAX is defined incorrectly 6 instead of 32
so we have to add more setlocale(3) __RENAME func, __setlocale50.
3. move setlocale1.c and setlocale32.c to lib/libc/compat/locale/*
prepareing for next libc major crunk.
4. bump libc minor version.
 1.22 17-Oct-2007  garbled branches: 1.22.20; 1.22.40; 1.22.42;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.21 31-Aug-2007  drochner Fix definitions of UCHAR_MAX/USHRT_MAX and related
types. C99 requires that these definitions promote to (signed/unsigned)
integer the same way as the types the definition is for. And since
unsigned char/short fit into an "int" on all our archs and thus promote
to signed int, the definitions must not be unsigned.
Fixes PR lib/31306 by Neil Booth.
 1.20 11-Dec-2005  christos branches: 1.20.30; 1.20.38; 1.20.44; 1.20.48; 1.20.50;
merge ktrace-lwp.
 1.19 07-Aug-2003  agc branches: 1.19.16;
Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.18 28-Apr-2003  bjh21 branches: 1.18.2;
Add a new feature-test macro, _NETBSD_SOURCE. If this is defined
by the application, all NetBSD interfaces are made visible, even
if some other feature-test macro (like _POSIX_C_SOURCE) is defined.
<sys/featuretest.h> defined _NETBSD_SOURCE if none of _ANSI_SOURCE,
_POSIX_C_SOURCE and _XOPEN_SOURCE is defined, so as to preserve
existing behaviour.

This has two major advantages:
+ Programs that require non-POSIX facilities but define _POSIX_C_SOURCE
can trivially be overruled by putting -D_NETBSD_SOURCE in their CFLAGS.
+ It makes most of the #ifs simpler, in that they're all now ORs of the
various macros, rather than having checks for (!defined(_ANSI_SOURCE) ||
!defined(_POSIX_C_SOURCE) || !defined(_XOPEN_SOURCE)) all over the place.

I've tried not to change the semantics of the headers in any case where
_NETBSD_SOURCE wasn't defined, but there were some places where the
current semantics were clearly mad, and retaining them was harder than
correcting them. In particular, I've mostly normalised things so that
_ANSI_SOURCE gets you the smallest set of stuff, then _POSIX_C_SOURCE,
_XOPEN_SOURCE and _NETBSD_SOURCE in that order.

Tested by building for vax, encouraged by thorpej, and uncontested in
tech-userlevel for a week.
 1.17 30-Nov-2002  simonb Standardise on #ifdef _MIPS_<header>_H_ for multiple inclusion tests.
 1.16 03-Nov-2002  thorpej Add LP64 limits.
 1.15 04-May-2001  simonb branches: 1.15.8;
Be consistent with limit constants:
- use "U" suffix for unsigned constants
- use "L" suffix for long constants
- use "UL" suffix for unsigned long constants
- use hexadecimal instead of decimal

Fixes build problems with vi (now that warnings/errors are enabled) on
mips, powerpc and arm platforms.
 1.14 08-Aug-2000  tshiozak branches: 1.14.2;
Preparation for the future introduction of multibyte locale.
- MB_LEN_MAX is increased to 32.
- To ensure binary compatibility for old executables
under multibyte locale, versioned setlocale is added.
- __mb_len_cur definision is added in setlocale.c
and enable it in stdlib.h .
It is also important for multibyte locale stuffs,
but I just forgot.
 1.13 07-Mar-2000  kleink branches: 1.13.2; 1.13.4;
Define ISO C99 (unsigned) long long (min, max) symbols.
VS: ----------------------------------------------------------------------
 1.12 06-Aug-1998  kleink branches: 1.12.14;
_POSIX_SOURCE -> _POSIX_C_SOURCE
 1.11 21-Feb-1998  jonathan Pull up duplicated CPP definitions from float.h rev 1.10:
>DBL_MIN and DBL_MAX were less precise than they should have been.
 1.10 09-Jan-1998  perry multiple include protect machine/limits.h, fixes pr 4473 (from Mika Nystrom)
 1.9 19-Mar-1996  jonathan branches: 1.9.16;
Remove pmax-specific CLK_TICK to prepare for moving to sys/arch/mips.
 1.8 28-Mar-1995  jtc KERNEL -> _KERNEL
 1.7 15-Nov-1994  dean put #ifdef KERNEL around CLK_TCK define
 1.6 26-Oct-1994  cgd new RCS ID format.
 1.5 05-Oct-1994  jtc Add constants required by XPG3
 1.4 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.3 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.2 14-Jan-1994  deraadt some pmax updating (Terry Friedrichsen is helping on this now).
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.9.16.1 10-May-1998  mycroft Pull up 1.11, per request of mhitch.
 1.12.14.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.13.4.1 09-Aug-2000  tshiozak pull up the following changes (approved by thorpej):
> cvs rdiff -r1.9 -r1.10 basesrc/include/locale.h
> cvs rdiff -r1.45 -r1.46 basesrc/include/stdlib.h
> cvs rdiff -r1.16 -r1.17 basesrc/lib/libc/locale/Makefile.inc
> cvs rdiff -r1.17 -r1.18 basesrc/lib/libc/locale/setlocale.c
> cvs rdiff -r0 -r1.2 basesrc/lib/libc/locale/setlocale_sb.c
> cvs rdiff -r1.6 -r1.7 syssrc/sys/arch/alpha/include/limits.h
> cvs rdiff -r1.1 -r1.2 syssrc/sys/arch/arm26/include/limits.h
> cvs rdiff -r1.7 -r1.8 syssrc/sys/arch/arm32/include/limits.h
> cvs rdiff -r1.14 -r1.15 syssrc/sys/arch/i386/include/limits.h
> cvs rdiff -r1.12 -r1.13 syssrc/sys/arch/m68k/include/limits.h
> cvs rdiff -r1.13 -r1.14 syssrc/sys/arch/mips/include/limits.h
> cvs rdiff -r1.10 -r1.11 syssrc/sys/arch/pc532/include/limits.h
> cvs rdiff -r1.6 -r1.7 syssrc/sys/arch/powerpc/include/limits.h
> cvs rdiff -r1.2 -r1.3 syssrc/sys/arch/sh3/include/limits.h
> cvs rdiff -r1.11 -r1.12 syssrc/sys/arch/sparc/include/limits.h
> cvs rdiff -r1.7 -r1.8 syssrc/sys/arch/sparc64/include/limits.h
> cvs rdiff -r1.9 -r1.10 syssrc/sys/arch/vax/include/limits.h
>
> Outline:
>
> Preparation for the future introduction of multibyte locale.
> - MB_LEN_MAX is increased to 32.
> - To ensure binary compatibility for old executables
> under multibyte locale, versioned setlocale is added.
> - __mb_len_cur definision is added in setlocale.c
> and enable it in stdlib.h .
> It is also important for multibyte locale stuffs,
> but I just forgot.
 1.13.2.1 28-May-2000  minoura Citrus Project XPG4DL, an implementation of I18N (locale) framework,
is imported.
 1.14.2.1 21-Jun-2001  nathanw Catch up to -current.
 1.15.8.3 11-Dec-2002  thorpej Sync with HEAD.
 1.15.8.2 11-Nov-2002  nathanw Catch up to -current
 1.15.8.1 04-May-2001  nathanw file limits.h was added on branch nathanw_sa on 2002-11-11 22:00:28 +0000
 1.18.2.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.18.2.2 18-Sep-2004  skrll Sync with HEAD.
 1.18.2.1 03-Aug-2004  skrll Sync with HEAD
 1.19.16.1 03-Sep-2007  yamt sync with head.
 1.20.50.1 06-Nov-2007  matt sync with HEAD
 1.20.48.1 03-Sep-2007  jmcneill Sync with HEAD.
 1.20.44.1 03-Sep-2007  skrll Sync with HEAD.
 1.20.38.1 03-Oct-2007  garbled Sync with HEAD
 1.20.30.1 09-Oct-2007  ad Sync with head.
 1.22.42.1 03-Jul-2010  rmind sync with head
 1.22.40.1 17-Aug-2010  uebayasi Sync with HEAD.
 1.22.20.1 11-Aug-2010  yamt sync with head.
 1.23.12.1 05-Apr-2012  mrg sync to latest -current.
 1.23.8.2 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.23.8.1 17-Apr-2012  yamt sync with head
 1.24.2.2 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.24.2.1 23-Jun-2013  tls resync from head
 1.25.8.1 10-Aug-2014  tls Rebase.
 1.25.4.1 18-May-2014  rmind sync with head
 1.26.28.1 10-Jun-2019  christos Sync with HEAD
 1.26.26.1 26-Jan-2019  pgoyette Sync with HEAD
 1.23 09-Apr-2022  riastradh mips: Convert lock.h to membar_release/acquire.
 1.22 12-Feb-2022  riastradh mips: Brush up __cpu_simple_lock.

- Eradicate last vestiges of mb_* barriers.

- In __cpu_simple_lock_init, omit needless barrier. It is the
caller's responsibility to ensure __cpu_simple_lock_init happens
before other operations on it anyway, so there was never any need
for a barrier here.

- In __cpu_simple_lock_try, leave comments about memory ordering
guarantees of the kernel's _atomic_cas_uint, which are inexplicably
different from the non-underscored atomic_cas_uint.

- In __cpu_simple_unlock, use membar_exit instead of mb_memory, and do
it unconditionally.

This ensures that in __cpu_simple_lock/.../__cpu_simple_unlock, all
memory operations in the ellipsis happen before the store that
releases the lock.

- On Octeon, the barrier was omitted altogether, which is a bug --
it needs to be there or else there is no happens-before relation
and whoever takes the lock next might see stale values stored or
even stomp over the unlocking CPU's delayed loads.

- On non-Octeon, the mb_memory was sync. Using membar_exit
preserves this.

XXX On Octeon, membar_exit only issues syncw -- this seems wrong,
only store-before-store and not load/store-before-store, unless the
CNMIPS architecture guarantees it is sufficient here like
SPARCv8/v9 PSO (`Partial Store Order').

- Leave an essay with citations about why we have an apparently
pointless syncw _after_ releasing a lock, to work around a design
bug^W^Wquirk in cnmips which sometimes buffers stores for hundreds
of thousands of cycles for fun unless you issue syncw.
 1.21 05-Aug-2020  simonb Indent branch delay slots in asm code (from skrll@).
Be consistent within this file with how asm code is formatted.
 1.20 17-Sep-2017  christos more const.
 1.19 01-Jun-2015  matt Rework cavium support in preparation for MULTIPROCESSOR support
 1.18 20-Feb-2011  matt branches: 1.18.14; 1.18.32;
Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.17 12-Jan-2009  pooka branches: 1.17.6; 1.17.8; 1.17.10;
Use userspace version unless _HARDKERNEL. Otherwise we use atomic
cas to implement spinlocks and spinlocks to implement atomic cas....
which might suck.

Since the userspace version uses ll/sc, which doesn't exist on
R2000/R3000, rump will not work on those platforms. *snif* (well,
pthread in general AFAICT).
 1.16 28-Apr-2008  martin branches: 1.16.8; 1.16.16;
Remove clause 3 and 4 from TNF licenses
 1.15 29-Nov-2007  ad branches: 1.15.14; 1.15.16; 1.15.18;
- Change _lock_cas and friends to do "compare and swap" instead of "compare
and set".
- Rename them to _atomic_cas_uint, _atomic_cas_ulong etc and provide strong
aliases for the other names CAS goes by.
 1.14 17-Oct-2007  garbled branches: 1.14.2;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.13 10-Sep-2007  skrll Merge nick-csl-alignment.
 1.12 15-Feb-2007  ad branches: 1.12.6; 1.12.14; 1.12.18; 1.12.22; 1.12.24;
Pacify lint/gcc.
 1.11 10-Feb-2007  nakayama s/___asm/__asm/
 1.10 09-Feb-2007  ad Merge newlock2 to head.
 1.9 03-Jun-2006  simonb branches: 1.9.6;
Adjust asm constraints for more pickier gcc4.
 1.8 28-Dec-2005  perry branches: 1.8.4; 1.8.6; 1.8.8; 1.8.14;
inline -> __inline
 1.7 24-Dec-2005  perry Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.
 1.6 11-Dec-2005  christos merge ktrace-lwp.
 1.5 26-Sep-2003  nathanw branches: 1.5.16;
Move __cpu_simple_lock_t and __SIMPLELOCK_{UN,}LOCKED to machine/types.h
so that they can be used in a namespace-friendly way.
 1.4 05-Dec-2002  simonb branches: 1.4.6;
Drop the _KERNEL test; these functions are needed for SMP and other ports
don't bother with a _KERNEL check.
 1.3 16-Sep-2002  gmcgarry Bring down from nathanw_sa branch.
 1.2 02-May-2000  thorpej branches: 1.2.6; 1.2.10; 1.2.14;
Let each platform typedef the new __cpu_simple_lock_t, which should
be the most efficient type used for the atomic operations in the
simplelock structure, and should also be __volatile.
 1.1 29-Apr-2000  thorpej Require that each each MACHINE/MACHINE_ARCH supply a lock.h. This file
contains the values __SIMPLELOCK_LOCKED and __SIMPLELOCK_UNLOCKED, which
replace the old SIMPLELOCK_LOCKED and SIMPLELOCK_UNLOCKED. These files
are also required to supply inline functions __cpu_simple_lock(),
__cpu_simple_lock_try(), and __cpu_simple_unlock() if locking is to be
supported on that platform (i.e. if MULTIPROCESSOR is defined in the
_KERNEL case). Change these functions to take an int * (&alp->lock_data)
rather than the struct simplelock * itself.

These changes make it possible for userland to use the locking primitives
by including <machine/lock.h>.
 1.2.14.4 11-Dec-2002  thorpej Sync with HEAD.
 1.2.14.3 14-Jul-2002  gmcgarry Can't load the lock in the delay slot of its test. Also explicitly
include delay slots according to common convention.
 1.2.14.2 29-Nov-2001  wdk Fix branch instruction in delay slot. Ooops!!
 1.2.14.1 28-Nov-2001  wdk Add support for R4x00 locks using LL/SC. Needed by new libpthread

As discussed on Mips mailing list there is no equivalent functionality
for R3000 processors. Restartable Atomic Sequences will be implemented
in the future to provide similar functionality on R3000 uniprocessor
machines.
 1.2.10.1 10-Oct-2002  jdolecek sync kqueue with -current; this includes merge of gehenna-devsw branch,
merge of i386 MP branch, and part of autoconf rototil work
 1.2.6.2 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.2.6.1 02-May-2000  bouyer file lock.h was added on branch thorpej_scsipi on 2000-11-20 20:13:31 +0000
 1.4.6.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.4.6.2 18-Sep-2004  skrll Sync with HEAD.
 1.4.6.1 03-Aug-2004  skrll Sync with HEAD
 1.5.16.4 07-Dec-2007  yamt sync with head
 1.5.16.3 27-Oct-2007  yamt sync with head.
 1.5.16.2 26-Feb-2007  yamt sync with head.
 1.5.16.1 21-Jun-2006  yamt sync with head.
 1.8.14.1 19-Jun-2006  chap Sync with head.
 1.8.8.1 26-Jun-2006  yamt sync with head.
 1.8.6.1 07-Jun-2006  kardel Sync with head.
 1.8.4.1 09-Sep-2006  rpaulo sync with head
 1.9.6.2 27-Jan-2007  ad Make mips systems work.
 1.9.6.1 29-Dec-2006  ad Checkpoint work in progress.
 1.12.24.2 09-Jan-2008  matt sync with HEAD
 1.12.24.1 06-Nov-2007  matt sync with HEAD
 1.12.22.2 03-Dec-2007  joerg Sync with HEAD.
 1.12.22.1 02-Oct-2007  joerg Sync with HEAD.
 1.12.18.1 15-Aug-2007  skrll Provide __SIMPLELOCK_{UN,}LOCKED_P and __cpu_simple_lock_{set,clear}
for all architectures.
 1.12.14.1 03-Oct-2007  garbled Sync with HEAD
 1.12.6.2 03-Dec-2007  ad Sync with HEAD.
 1.12.6.1 09-Oct-2007  ad Sync with head.
 1.14.2.1 08-Dec-2007  mjf Sync with HEAD.
 1.15.18.2 04-May-2009  yamt sync with head.
 1.15.18.1 16-May-2008  yamt sync with head.
 1.15.16.1 18-May-2008  yamt sync with head.
 1.15.14.2 17-Jan-2009  mjf Sync with HEAD.
 1.15.14.1 02-Jun-2008  mjf Sync with HEAD.
 1.16.16.1 15-Feb-2010  matt In SIMPLELOCK_LOCKED_P check against != UNLOCKED instead of == LOCKED.
This is so the compiler can emit a bnez instead of loading 1 into a register
and then doing beq.
 1.16.8.1 19-Jan-2009  skrll Sync with HEAD.
 1.17.10.1 05-Mar-2011  bouyer Sync with HEAD
 1.17.8.1 06-Jun-2011  jruoho Sync with HEAD.
 1.17.6.1 05-Mar-2011  rmind sync with head
 1.18.32.1 06-Jun-2015  skrll Sync with HEAD
 1.18.14.1 03-Dec-2017  jdolecek update from HEAD
 1.119 27-May-2021  simonb Rename the unhelpfully named mips_emul_lwc0() and mips_emul_swc0() to
mips_emul_ll() and mips_emul_sc(); make these static to mips_emul.c.
 1.118 12-May-2021  simonb Whitespace nit.
 1.117 02-Mar-2021  skrll branches: 1.117.4; 1.117.6;
Ensure the "memory" clobber is on inline assembly store operations

No binary change of note with this change in MALTA32
 1.116 22-Aug-2020  simonb branches: 1.116.2;
Invert the MIPS-I non-4kB page size check. The previous check doesn't
fail if both MIPS1 and MIPS3_PLUS are defined. Explictly check against
MIPS1.
 1.115 17-Aug-2020  mrg port crash(8) to mips. (most of the kernel side.)

- expose parts of _KERNEL to _KMEMUSER as well
- hide more things for _KERNEL
- avoid DB_MACHINE_COMMANDS in crash(8)
- XXX add mips_label_t for !_KERNEL and use it in the pcb to
avoid conflicting with the ddb/crash one
- enable dumppcb

some changes to make stack trace fail instead of SEGV and
the userland changes to crash itself not part of this change.
 1.114 15-Aug-2020  mrg move stacktrace_subr() from trap.c into new mips_stacktrace.c so
it can be shared between ddb, other mips kernel components (see
locore), and an upcoming crash(8) port.

remove second copy of kdbpeek() (hidden by old DDB_TRACE
option, but they're functionally equivalent.)

tested on octeon.

ok simonb@
 1.113 31-Jul-2020  simonb Fix a tyop. Thankfully this #define was unused.
 1.112 31-Jul-2020  simonb CP0 Config6 and Config7 aren't probeable. Adjust comments for these two.
 1.111 27-Jul-2020  skrll Fix typo _MODULAR -> _MODULE. Hopefully this fixes the builds.
 1.110 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.109 23-Jul-2020  skrll unifdef -U_LKM
 1.108 23-Jul-2020  skrll Trailing whitespace
 1.107 14-Jun-2020  simonb Retire MIPS_CP0FL_USERLOCAL and MIPS_CP0FL_HWRENA and the flawed
logic that tried to deal with a MIPS processor that supports the ULR
CP0 register. Probe correctly and save probed info somewhere we can
actually use it. Avoids problems where libc expects ULR set to a
value but the CPU definition in the CPU table didn't have the right
combination of magic flags and thus never set ULR in the first place.
 1.106 13-Jun-2020  simonb Note some hard-coded capabilties that can be probed.

XXX: Fix this and CPU table in mips/mips_machdep.c one day...
 1.105 24-May-2020  simonb Add mipsNN_cp0_rdhwr_cpunum() which returns the current CPU number
read from the CPUNum hardware register on MIPS{32,64}R2.
 1.104 06-Apr-2019  thorpej Overhaul the API used to fetch and store individual memory cells in
userspace. The old fetch(9) and store(9) APIs (fubyte(), fuword(),
subyte(), suword(), etc.) are retired and replaced with new ufetch(9)
and ustore(9) APIs that can return proper error codes, etc. and are
implemented consistently across all platforms. The interrupt-safe
variants are no longer supported (and several of the existing attempts
at fuswintr(), etc. were buggy and not actually interrupt-safe).

Also augmement the ucas(9) API, making it consistently available on
all plaforms, supporting uniprocessor and multiprocessor systems, even
those that do not have CAS or LL/SC primitives.

Welcome to NetBSD 8.99.37.
 1.103 08-Feb-2018  bouyer branches: 1.103.4;
Allow kdbpeek() to return failure. If it does, stop the stack trace.
Prevents an infinite loop in ddb if something goes wrong.
 1.102 16-Mar-2017  chs allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.
 1.101 13-Oct-2016  macallan branches: 1.101.2;
sprinkle #ifndef __ASSEMBLER__ to make this file usable from .S - mostly for
macros like MIPS3_PLUS
 1.100 11-Jul-2016  matt branches: 1.100.2;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.99 09-Jun-2015  matt Fix mips_fixup_zero_relative to have a third argument (ignored).
When reading COP0 EBASE, verify that the fixed bits have the right value.
 1.98 01-Jun-2015  matt Rework cavium support in preparation for MULTIPROCESSOR support
 1.97 02-May-2015  matt mips_{l,s}d_a64 only valid for !O32
 1.96 01-May-2015  christos change #error to KASSERT
 1.95 29-Apr-2015  hikaru Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.
 1.94 22-Nov-2014  macallan branches: 1.94.2;
deal with Ingenic XBurst CPUs
 1.93 19-Feb-2012  rmind branches: 1.93.2;
Remove COMPAT_SA / KERN_SA. Welcome to 6.99.3!
Approved by core@.
 1.92 17-Aug-2011  matt branches: 1.92.2; 1.92.6;
Redo mips_fixup so that it can handle indirect loads and deal with loongson2
extra instructions.
 1.91 01-Jul-2011  dyoung Don't #include "opt_cputype.h" unless _KERNEL_OPT is #defined.
 1.90 29-Apr-2011  matt ras atomicvec is no more.
 1.89 14-Apr-2011  matt Fix printing of watch{lo,hi} and make mipsNN_watchlo_* use intptr_t so that
sign extention happens.
 1.88 14-Apr-2011  cliff - add lsw_cpu_run function pointer to struct locoresw
 1.87 12-Apr-2011  matt Add prototypes for mipsNN_cp0_watch{lo,hi}_{read,write}
 1.86 06-Apr-2011  matt Add a tiny bit of whitespace.
 1.85 15-Mar-2011  matt Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.
 1.84 03-Mar-2011  matt Change MIPS_CP0FL_CONFIG*
Add MIPS_CP0FL_HWRENA and USERLOCAL
 1.83 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.82 26-Jan-2011  pooka Add support for the Extensible MIPS ("eMIPS") platform. The
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the
Giano system simulator.

eMIPS is a platform developed at Microsoft Research for researching
reconfigurable computing. eMIPS allows dynamic loading and scheduling
of application-specific circuits for the purpose of accelerating
computations based on the current workload.

NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research
by Alessandro Forin and Neil Pittman. Microsoft Corporation has
donated full copyright to The NetBSD Foundation.

Platform support for eMIPS is the first part of Microsoft's
contribution. The second part includes the hardware accelerator
framework and will be proposed on tech-kern soon.
 1.81 27-Feb-2010  snj branches: 1.81.2; 1.81.4; 1.81.6;
Fix a couple old typos in comments.
 1.80 14-Dec-2009  matt branches: 1.80.2;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.79 30-May-2009  martin Do not use the same trampoline for cpu_lwp_fork and cpu_setfunc - only
the former needs to call lwp_startup().
 1.78 17-Oct-2007  garbled branches: 1.78.20; 1.78.30; 1.78.36;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.77 17-Jun-2007  tsutsui branches: 1.77.10;
Move declaretions of _spl*() and _{clr,set}softintr() functions
(which are in mips/locore.S) into <mips/locore.h>
from various MD files.
 1.76 17-May-2007  yamt merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.
 1.75 04-Mar-2007  christos branches: 1.75.2; 1.75.4; 1.75.10;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.
 1.74 16-Feb-2006  perry branches: 1.74.20;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.
 1.73 24-Dec-2005  perry branches: 1.73.2; 1.73.4; 1.73.6;
__asm__ -> __asm
__const__ -> const
__inline__ -> inline
__volatile__ -> volatile
 1.72 11-Dec-2005  christos merge ktrace-lwp.
 1.71 05-Nov-2005  tsutsui Add MI mips3 wired map functions based on patch in port-mips/31915
from Garrett D'Amore of Tadpole Computer Inc.
Please refer discussion filed in the PR for details.
 1.70 30-Oct-2005  tsutsui Use #define<space> for consistency.
 1.69 08-Sep-2005  tsutsui branches: 1.69.2;
Add mips3_cp0_pg_mask_write() to initialize pagemask register.
 1.68 13-Feb-2004  wiz branches: 1.68.6; 1.68.14; 1.68.16;
Uppercase CPU, plural is CPUs.
 1.67 29-Oct-2003  simonb Add some more MIPS vendor IDs.
 1.66 05-Oct-2003  tsutsui No need to include opt_mips_cache.h here.
 1.65 04-Nov-2002  thorpej branches: 1.65.6;
Use named indices for RA, SR, MULLO, MULHI, and EPC in the
trapframe.
 1.64 04-Nov-2002  thorpej Define named constants for the trapframe register idices (they
are different from the normal register numbers). Use these names
in genassym.cf. (Wow, how ever did that test kernel boot before...)
 1.63 03-Jun-2002  simonb Add prototypes for the 64-bit pagezero functions.
Bracket some function prototypes with #ifdef/#endif.
 1.62 01-Jun-2002  simonb Use CPU_MIPS_USE_WAIT and CPU_MIPS_NO_WAIT in the CPU table, and use
the generic name "mips_wait_idle" for the old function that had both
rm52xx_idle and mipsNN_idle entry points.
 1.61 13-May-2002  simonb branches: 1.61.2;
Add a comment after an #endif to match up with an #ifdef.
 1.60 11-Mar-2002  uch make this compile and work with MIPS3_5900.
 1.59 05-Mar-2002  simonb Add support for MIPS32 and MIPS64 architectures:
- Add mips32 and mips64 locore function prototypes.
- Add mips3_lw_a64() and mips3_sw_a64() for access data at any
64bit address (from Broadcom Corp).
- Add Broadcom and Sandcraft CPU company ids.
 1.58 14-Nov-2001  thorpej branches: 1.58.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.
 1.57 16-Oct-2001  uch branches: 1.57.2;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.
 1.56 18-Aug-2001  simonb Reorder some function prototypes more logically.
 1.55 15-Aug-2001  simonb Add Alchemy and SiByte company IDs (from oss.sgi.com).
 1.54 15-Aug-2001  simonb Remove parameter names from function prototypes.
 1.53 11-Jun-2001  thorpej branches: 1.53.2;
Always indirect through the "locoresw" to get the cache ops, since
there are just far too many combinations to handle with magic
#ifdefs in any sane way. Also, add a HitFlushDCache op to the
"locoresw", and fill it in as appropriate (it's NULL on MIPS-I,
so watch out).

These changes ensure that my R4600 Indy (with 2-way cache) gets
the correct cache ops when the kernel is built with only MIPS3
support, resulting in a kernel that is significantly more stable.
 1.52 31-Oct-2000  jeffs branches: 1.52.2;
Add mips_pagecopy/zero assembly loops for use by pmap_copy/zero_page*()
to allow the almost-64-bit compilation use ld/sd.
 1.51 31-Oct-2000  jeffs Add mips_indexof() macro to make code for checking the cache index
easier to read.
 1.50 09-Oct-2000  nisimura mips1_ConfigCache() has gone.
 1.49 05-Oct-2000  cgd clean up and consistency for CP0 Count, Compare, Wired, and Config
access function names and prototypes.
 1.48 05-Oct-2000  cgd nuke mips3_clearBEV(). There's really no point in coding a
special-purpose assembly routine for things like this.
 1.47 05-Oct-2000  cgd tweak cpu_arch. Eliminate all direct checks of it (making them
use the macro CPUISMIPS3 -- which is badly misnamed), and set it
from #defines named CPU_ARCH_N (where N is 1..5, 32, 64).
 1.46 04-Oct-2000  cgd rename mips_read_causereg -> mips_cp0_cause_read. nuke prototype
for mips_read_statusreg (which was apparently never implemented).
Provide prototypes and implementations for mips_cp0_cause_write,
mips_cp0_status_read, and mips_cp0_status_write. (Writing can, of
course, be quite dangerous.)
 1.45 03-Oct-2000  cgd add some additional info re: MIPS32 PRID encoding, derived from
the ``MIPS32 4K Processor Core Family Software User's Manual
Revision 01.07 June 19, 2000", available on the web from:
http://www.mips.com/declassified/Declassified_2000/MD00016-2B-4K-SUM-01.07.pdf
 1.44 02-Oct-2000  cgd provide mips3_ld() and mips3_sd(), functions which provide safe wrappers
for mips3 (and later) 'ld' and 'sd' instructions. These currently
only are properly implemented for the _MIPS_BSD_API_LP32 and
_MIPS_BSD_API_LP32_64CLEAN 'API's. They're pretty messy, but when you
need them, you really need them.
 1.43 16-Sep-2000  nisimura Introduce new MIPS1 direct mapped cache capacity detection logics.
 1.42 16-Sep-2000  chuck IDT32364's Config register uses a different base for IC/DC (instruction
and data cache sizes). R4000 uses 2^(12+IC) and 2^(12+DC). IDT32364
uses 2^(9+IC) and 2^(9+DC).

abstract around the problem by making the base a parameter to the
MIPS3_CONFIG_CACHE_SIZE macro. we pass the base down from mips_vector_init
to mips3_vector_init and to mips3_ConfigCache (where it is used).

XXX: someone with an MIPS3_4100 should switch to this and get rid
of the ugly ifdefs in cpuregs.h
 1.41 13-Sep-2000  chuck kill mips3_write_xcontext_upper
 1.40 27-Jul-2000  cgd convert PRID handling to use macros on an int, not bit-fields.
there's no reason to use bit-fields, and they just complexity to
the header.
 1.39 20-Jul-2000  jeffs Make pmap_prefer() use a global setting based on cache size
instead of assuming 64KB. This allows best fit and will
support bigger caches.
 1.38 29-Jun-2000  cgd un-__P, clean up spacing a little bit, put fwd struct decl(s) near top
rather than embedded. no functional changes.
 1.37 26-Jun-2000  nisimura Abandon {mips1,mips3}_TBRPL()s which have little gain. They were
expected to be better than MachTLBUpdate(). After all, TLBUpdate()
is rather harmful and should be replaced with TBIS().
 1.36 20-Jun-2000  soda branches: 1.36.2;
3rd argument of TBRPL() is not paddr_t but PTE.
XXX - mips3_TBRPL seems to be never called.
 1.35 20-Jun-2000  soren Add mips3_write_config().
 1.34 06-Jun-2000  soren Rename RM5200 cache ops to mips3_*_2way in anticipation of using them
for other CPUs with 2-way set associative L1 caches as well.
 1.33 23-May-2000  soren branches: 1.33.2;
MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.
 1.32 21-May-2000  soren Include opt_cputype.h.
 1.31 10-May-2000  nisimura Have mips_locoresw[] of 3 entry pointer array for different
implementation of locore routines between MIPS1 and MIPS3. It's
independent from mips_locore_jumpvec_t which is for cache/TLB
manipulating routines peculiar to processor designs. mips_locore_jumpvec_t
will be replaced with "processor closures" encapsulating implementation
parameters (cpuinfo) and pointers to conventaion routines (cpuops),
eventually.
 1.30 12-Apr-2000  nisimura - Implement mips3_TBIAP().
- Remove obsoluted routines in locore_mips3.S
- addiu -> addu, andi -> and, ori -> or.
 1.29 28-Mar-2000  simonb Don't `extern' function declarations. While we're there, remove trailing
blank lines and white space.
 1.28 27-Mar-2000  nisimura Have TBIA/TBIAP an argument refering to a global variable instead
of a compile time constant.
 1.27 27-Mar-2000  nisimura - Rename some of TLB ops to have handy abbrivations hired from VAX and
ALPHA; mips1_TBIA, mips1_TBIAP, mips1_TBIS.
- Make sure TBIA and TBIAP ops to have an argument for the size of TLB
which varies across even for MIPS1 implementations.
- Nuke the unused cpu_isa field from processor personality list.

- XXX XXX XXX
it's less-than-optimal and likely a mistake to have TLBUpdate().
It's costy to try to invalidate a single TLB entry whenver a certain
PTE is going to be modified by traversing the entire TLB looking
for the modified PTE because the PTE in question is not in TLB in
most cases. ASID bump could do the invalidation smartly. Solution
is planned for now.
 1.26 23-Mar-2000  soren Make MIPS1+MIPS3 compile again.
 1.25 19-Mar-2000  soren Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast.
Many thanks.
 1.24 28-Jan-2000  takemura CPU specific idle hook and VR idle routine.
 1.23 09-Jan-2000  simonb Prototype stacktrace() and logstacktrace().
 1.22 12-Nov-1999  nisimura Make sure wbflush symbol treated as a C function call.
 1.21 25-Sep-1999  shin branches: 1.21.2; 1.21.4; 1.21.8;
Changes for NetBSD/hpcmips.

Support VR4100.
Support 16KB page.
Support CPU without FPU.

Fix virtual alias problem(physio() case).

[new options]

options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */
 1.20 24-Apr-1999  simonb Nuke register and remove trailling white space.
 1.19 27-Feb-1999  jonathan branches: 1.19.4;
Define C structures (struct kernframe, struct trapframe)
for kernel-to-user trapframe. Use C structs in genassym.cf.
 1.18 15-Jan-1999  castor * Add prototype for mips1_clean_tlb
* Add the correct version of locore_mips1.S [ See previous revision for
description of changes ]
* Use defopt'ed MIPS3_L2CACHE_ABSENT in mips_machdep.c and pmap.c
to avoid generating extraneous code.
* GC pmap_set_referenced in pmap.c
 1.17 15-Jan-1999  castor Protect defopt against -D_LKM
 1.16 14-Jan-1999  castor * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.15 06-Jan-1999  nisimura - Complete vm_offset_t purge for mips processor.
- bzero() -> memset() and bcopy() -> memcpy().
- Garbage collection in trap.c and db_interface.c.
 1.14 11-Sep-1998  jonathan branches: 1.14.2;
Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.

* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.
 1.13 23-Apr-1998  jonathan Commit change missed during Decsystem 5100 chagnes:

prototype declearation for method to override wbflush() callback
vector with model-specific code. Used on DEC r2000a machines with
writebuffers which indicate writebuffer drain via cp0 usability bit.
 1.12 22-Jun-1997  jonathan Fix typo mips3_mips_switch_exit.
 1.11 22-Jun-1997  jonathan Final changes for configuring MIPS1 and MIPS3 in a single kernel.

* cpuregs.h:
rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx.
Add compile-time MIPS3-only, compile-time MIPS1-only, and
runtime (both) definitions for number of TLB ASIDs (tlb pids)
and shift count to extract a TLB pid.

* locore.h:
Delete unused vector slot for indexed TLB writes.
mips1 and mips3 TLBs are different enough that we have
to break them out at the caller anyway.

* Add compile-time MIPS3-only andcompile-time MIPS1-only
macros to call locore functions directly by name.
Use the existing method table only if

* mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c:
Use MIPS3_ or MIPS1_ specific names for TLB pids in
mips3 and mips1 specific code paths (e.g., creating the kernel stack
for process 0).

Add `options MIPS3' to pmax/conf/GENERIC.
 1.10 21-Jun-1997  mhitch MachHitFlushDCache is gone.
 1.9 19-Jun-1997  mhitch More merged mips1/mips3 support:
Remove cpu-specific routines from locore.S and add them to locore_r2000.S
and locore_r4000.S. Add entries in locore jump vector table for switch_exit()
and the cpu_switch() context resume.
Add offsets into the jump vector to genassym.cf for use in locore.S.
 1.8 16-Jun-1997  jonathan Changes for configuring both MIPS1 and MIPS3, from a merge of
similar design and code by Jason Thorpe and Jonathan Stone.

NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.

mips/include/cpu.h:
Add CPUISMIPS3 for run-time tests of what CPU architecture level
we're running on.

mips/include/locore.h:
Add declarations of locore cache-size variables for ref/def toolchain.

mips/include/mips1_pte.h:
mips1 TLB bit definitions.

mips/include/mips3_pte.h:
mips3 TLB bit definitions.

mips/include/pte.h:
define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
that expand to CPU constants if only one CPU arch is configured,
or to inline functions if both MIPS1 and MIPS3 are configured.

mips/mips/locore_r2000.S:
Use MIPS1_PG_xxx constants inside mips1-specific code.

mips/mips/locore_r4000.S:
Use MIPS3_PG_xxx constants inside mips3-specific code.

mips/mips/locore.S:
Use MIPS1_PG_xxx constants inside mips3-specific code.
Use MIPS1_PG_xxx constants inside mips1-specific code.
(Needs more work!)

mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
Use MIPS3_PG_xxx constants inside mips3-specific functions,
and MIPS1_PG_XXX inside mips1-specific code.
Otherwise, use mips_pg_XXX_bit() macros where they apply,
and use "if (CPUISMIPS3) { ... } else {... }" where they don't.

mips/mips/mips_machdep.c:
Import Michael Hitch's fixes from the pmax locore-init code
into mips_vector_init().

pmax/pmax/machdep.c:
Use generic mips_vector_init() locore vector-init function.
 1.7 16-Jun-1997  jonathan Garbage-collect redundant declarations:
mips/include/locore.h:
Add prototypes for HitFlushDCache() functions. Moe cpu_prid definition here.
mips/include/cpu.h:
remove cpu_prid definition.
pmax/pmax/machdep.c:
remove local protoypes of HitFlushDCache() functions.
mips/mips/vm_machdep.c, mips/mips/vm_machdep.c::
remove local protoypes of HitFlushDCache() functions.
 1.6 16-Jun-1997  jonathan Yet more merging:
* Move declaration of locore communcation variables (CPU family,
cache sizes, etc) to mips/include/locore.h. Delete from
pmax/include/cpu.h and older versions from pica/include/cpu.h.

* Move definitions of CLKF_BASEPRI, CLKF_USERMODE to mips/include/cpu.
* Delete duplicate definitions in pica/include/cpu.h, pmax/include/cpu.h.
 1.5 15-Jun-1997  mhitch DECstation MIPS3 support: wbflush() is cpu-dependent, need declaration from
machine/locore.h.
From Toru Nishimura: _FORKBRAINDAMAGE is gone, user process entered through
proc_trampoline() [also cpu-dependent].
 1.4 25-May-1997  jonathan lint: prototype blkclr __P((caddr_t val, int size)). Used in pmap code.
 1.3 13-Oct-1996  jonathan Rename mips CPU-family locore prefixes for case-consistency:
mips_r2000_, mips_R2000_ -> mips1_
mips_r4000_, mips_R4000_ -> mips3_
(which are also, for mnemonic reasons, consistent with gcc flag usage,
rather than using mipsI_ and mipsIII_).
 1.2 20-May-1996  jonathan * Move the declarations of mips locore functions from the pmax tree
to the mips tree.
* Add declarations of functions used by vm_machdep.c.
* Add declarations of functions printed by name in stack tracebacks.
* Add declarations of functions used by the model-independnet mips machdep.c
code.
 1.1 19-May-1996  jonathan Define the conventional pmax locore entry-point names to be calls through
an vector (struct) of function pointers. Add prototype declarations for
each vector entry.
Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore
versions of the relevant functions.
 1.14.2.1 19-Nov-1998  nisimura - Forgot to commit many files for vm_offset_t purge last Monday.
 1.19.4.1 21-Jun-1999  thorpej Sync w/ -current.
 1.21.8.1 27-Dec-1999  wrstuden Pull up to last week's -current.
 1.21.4.1 15-Nov-1999  fvdl Sync with -current
 1.21.2.2 22-Nov-2000  bouyer Sync with HEAD.
 1.21.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.33.2.1 22-Jun-2000  minoura Sync w/ netbsd-1-5-base.
 1.36.2.3 22-Jun-2000  soren Apply lost section from previous pull-up.
 1.36.2.2 22-Jun-2000  soren Pull-up from trunk: correct _TBRPL() prototype and remove from pmap.c.
 1.36.2.1 20-Jun-2000  soren file locore.h was added on branch netbsd-1-5 on 2000-06-22 05:11:20 +0000
 1.52.2.1 21-Jun-2001  nathanw Catch up to -current.
 1.53.2.4 23-Jun-2002  jdolecek catch up with -current on kqueue branch
 1.53.2.3 16-Mar-2002  jdolecek Catch up with -current.
 1.53.2.2 10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.53.2.1 25-Aug-2001  thorpej Merge Aug 24 -current into the kqueue branch.
 1.57.2.1 24-Oct-2001  thorpej Update for the new cache code. Some careful code review is needed
here, esp. by people who have done recent MIPS pmap hacking.
 1.58.2.4 11-Nov-2002  nathanw Catch up to -current
 1.58.2.3 20-Jun-2002  nathanw Catch up to -current.
 1.58.2.2 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.58.2.1 14-Nov-2001  nathanw file locore.h was added on branch nathanw_sa on 2002-04-01 07:40:58 +0000
 1.61.2.1 14-Jul-2002  gehenna catch up with -current.
 1.65.6.4 10-Nov-2005  skrll Sync with HEAD. Here we go again...
 1.65.6.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.65.6.2 18-Sep-2004  skrll Sync with HEAD.
 1.65.6.1 03-Aug-2004  skrll Sync with HEAD
 1.68.16.2 03-Sep-2007  yamt sync with head.
 1.68.16.1 21-Jun-2006  yamt sync with head.
 1.68.14.1 11-Sep-2005  tron Pull up following revision(s) (requested by tsutsui in ticket #758):
sys/arch/mips/include/locore.h: revision 1.69
sys/arch/mips/mips/locore_mips3.S: revision 1.87
Add mips3_cp0_pg_mask_write() to initialize pagemask register.
 1.68.6.1 13-Sep-2005  riz Pull up following revision(s) (requested by tsutsui in ticket #5829):
sys/arch/mips/include/locore.h: revision 1.69
sys/arch/mips/mips/locore_mips3.S: revision 1.87
Add mips3_cp0_pg_mask_write() to initialize pagemask register.
 1.69.2.1 02-Nov-2005  yamt sync with head.
 1.73.6.1 22-Apr-2006  simonb Sync with head.
 1.73.4.1 09-Sep-2006  rpaulo sync with head
 1.73.2.1 18-Feb-2006  yamt sync with head.
 1.74.20.2 18-Apr-2007  ad - Further adaptations to MIPS for the yamt-idlelwp branch.
- Make curlwp a register variable on MIPS.
 1.74.20.1 12-Mar-2007  rmind Sync with HEAD.
 1.75.10.2 26-Jun-2007  garbled Sync with HEAD.
 1.75.10.1 22-May-2007  matt Update to HEAD.
 1.75.4.1 11-Jul-2007  mjf Sync with head.
 1.75.2.2 15-Jul-2007  ad Sync with head.
 1.75.2.1 27-May-2007  ad Sync with head.
 1.77.10.1 06-Nov-2007  matt sync with HEAD
 1.78.36.1 09-Jun-2009  snj branches: 1.78.36.1.2;
Pull up following revision(s) (requested by martin in ticket #799):
sys/arch/mips/include/locore.h: revision 1.79
sys/arch/mips/mips/locore_mips1.S: revision 1.65
sys/arch/mips/mips/mipsX_subr.S: revision 1.28
sys/arch/mips/mips/mips_machdep.c: revision 1.211
sys/arch/mips/mips/vm_machdep.c: revision 1.123
Do not use the same trampoline for cpu_lwp_fork and cpu_setfunc - only
the former needs to call lwp_startup().
 1.78.36.1.2.36 09-Jul-2012  matt Add mips_cpu_switchto prototype.
 1.78.36.1.2.35 14-Feb-2012  matt Fix various LP64 thinkos.
 1.78.36.1.2.34 13-Feb-2012  matt Add mm_md_direct_mapped_virt (inverse of mm_md_direct_mapped_phys). Add a
third argument, vsize_t *, which, if not NULL, returns the amount of virtual
space left in that direct mapped segment.
Get rid most of the individual direct_mapped assert and use the above
routines instead.
Improve kernel core dump code.
 1.78.36.1.2.33 13-Feb-2012  matt Fix emulation to not panic when it encounters something it doesn't like.
(so running crashme won't crash the system).
Centralize the trapsignal processing so we can print out the trap info if
so desired.
Add a machdep.printfataltraps sysctl knob.
 1.78.36.1.2.32 09-Feb-2012  matt Update mips_fixup.c to version from -HEAD.
Move cpu_switchto to locore jumpvec and create a stub for it.
 1.78.36.1.2.31 23-Dec-2011  matt add more mipsNN_cp0_config{3,4,5,6,7}_{read,write}.
Add mips3_cp0_random_read().
Add L3 encoding for RMI.
 1.78.36.1.2.30 26-May-2011  matt Add MIPS64_RMIXL (XLR/XLS) and MIPS64R2_RMIXL (XLP). This allows the kernel
to treat this special which is needed for MP support. When accessing the TLB,
always lock the TLB before hand. If in the miss handlers, the TLB is already
locked let trap deal with the exeception.
 1.78.36.1.2.29 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.78.36.1.2.28 29-Dec-2010  matt Add wbflush to jumpvec while leaving it in locoresw. This allows to
overwrite wbflush in locoresw but still be able to call it via jumpvec.
 1.78.36.1.2.27 29-Dec-2010  matt Janitorial work.
Move emulation prototypes here and get rid of StudLyCaps.
Remove kludgery for lwp/setfunc trampoline and just grab them of the damn
structure.
Make mips_locore_jumpvec contain the routines that don't get reassigned
and move wbflush to mips_locoresw since it does get overridden.
 1.78.36.1.2.26 22-Dec-2010  matt Rework how fixups are processed. Inside of generating a table, we just
scan kernel text for jumps to locations between (__stub_start, __stub_end]
and if found, we actually decode the instructions in the stub to find out
where the stub would eventually jump to and then patch the original jump
to jump directly to it bypassing the stub. This is slightly slower than
the previous method but it's a simplier and new stubs get automagically
handled.
 1.78.36.1.2.25 10-Jun-2010  cliff - add lsw_bus_error to struct locoresw, provides hook to call
for chip-specific bus error handling/decode from e.g. trap()
 1.78.36.1.2.24 11-May-2010  matt Use assembly since deref a 64bit value as a pointer does not make a
32bit compiler happy.
 1.78.36.1.2.23 11-May-2010  matt Need to turn KX for N32 kernels with mips3_lw_a64 and mips3_sw_a64
 1.78.36.1.2.22 21-Mar-2010  cliff mips_vector_init now takes an argument to specify splsw.
NULL specifies use the default 'std_splsw'
 1.78.36.1.2.21 01-Mar-2010  matt Add a chip-dependent hook to locorew which cpu_hatch will call to do some
initialization that can only be done while running on the local CPU.
 1.78.36.1.2.20 01-Mar-2010  matt Add secondary processor spinup support (cpu_trampoline is in locore_mips3.S).
Nuke lse_boot_secondary_processors (not needed).
Move cpu_info_store to cpu_subr.C
 1.78.36.1.2.19 01-Mar-2010  matt Rework fixups support a bit (add a convience macro, require fixups to be
sorted).
 1.78.36.1.2.18 28-Feb-2010  matt Split FPU support into separate file and keep internals private to that file.
Make it MPSAFE. Change interface to be very similar to what's used on other
architectures.
Add l_md.md_fpcpu to mdlwp (needed for MPSAFE)
Move pridtab from <mips/cpu.h> to <mips/locore.h>
Add initial common IPI dispatcher.
Split cpu_* routines from mips_machdep.c into cpu_subr.c
Add cpu_startup_common which has the code replicated in half-dozen
plus machdep.c files.
 1.78.36.1.2.17 28-Feb-2010  matt Add code which can change a direct jump to stub with an indirect call to
a direct jump to the actual routine.
 1.78.36.1.2.16 27-Feb-2010  matt Add mipsXX_tlb_enter which modifies/sets a specific TLB entry with a new
mapping (useful for wired TLB entries).
Add mips_fixup_exceptions which will walk through the exception vectors
and allows the fixup of any cpu_info references to be changed to a more
MP-friendly incarnation.
Define a common fixup method to use a wired TLB entry at -PAGE_SIZE allowing
direct loads using a negative based from the zero register.
Change varible pmap_tlb_info t pmap_tlb0_info.
 1.78.36.1.2.15 25-Feb-2010  matt Add mipsXX_tlb_record_asids - records what ASIDs have valid TLB entries in
the TLB.
Move some mips3 specific routines from locore.S to locore_mips3.S
 1.78.36.1.2.14 23-Feb-2010  matt Make sure <mips/locore.h> is not included by MI code.
Add send_ipi and cpu_offline_md hooks to locoresw.
Add MP support to pmap (pvlist locking, tlb locking).
Add TLB shootdown support (see comment at the top of mips/pmap_tlb.c).
Add mipsXX_tlb_invalidate_globals routine
 1.78.36.1.2.13 15-Feb-2010  matt Completely redo how interrupts and SPL are handled in NetBSD/mips.
[XXX locore_mips1.S still needs to adapted.]

Nested interrupts now work. Except for MIPS_SOFT_MASK and MIPS_SR_INT_IE,
how interrupts work is completely abstracted. spl is handled through the
mips_splsw table. Direct manipulation of the status register is no longer
done (except for MIPS_SR_INT_IE). A new <mips/intr.h> contains the common
IPL/IST/spl* definitions for all ports.

Interrupt delivery is completely different. Clock interrupts may interrupt
device interrupts. ci_idepth is now handled by the caller of cpu_intr as
are softints (both can be optimized/simplified in the case of interrupts of
usermode code). cpu_intr has new arguments and now get called at IPL_HIGH
with MIPS_SR_INT_IE set and its logic is:

void
cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
int ipl;
uint32_t pending;
while (ppl < (ipl = splintr(&pending))) {
splx(ipl); /* enable interrupts */
<handle pending interrupts>
(void)splhigh(); /* disable interrupts */
}
}

mipsX_subr.S has been reworked. All user handlers (user_intr, systemcall,
user_gen_exception) now use common return to usermode code in lwp_trampoline.
ast() has changed to void ast(void) since the previous pc argument was never
used.

The playstation IPL_ICU_MASK support has been nuked.
MIPS_DYNAMIC_STATUS_MASK may soon be nuked soon.

A bunch of debugging code was left conditionalized by PARANOIA. If this
code detects a bug, it will enter an infinite loop. It is expected that
the kernel will be debugged in a simulator or with a hardware debugger so
that the state at that point can be analyzed.
 1.78.36.1.2.12 05-Feb-2010  matt Add __HAVE_FAST_SOFTINTS support.
Add routine to remap an uarea via a direct-mapped address. This avoids
TLB machinations when swtching to/from the softint thread. This can only
be done for lwp which won't exit.
 1.78.36.1.2.11 01-Feb-2010  matt Merge frame into trapframe. While this costs a bit more stack space on
kernel exceptions, the resulting simplifications are worth it. This is
a step to fast softints and kernel preemption.

trapframe now includes a struct reg instead of a separate array of registers.
 1.78.36.1.2.10 20-Jan-2010  cyber Correct argument to assembly dsrl32 $Lx -> %Lx
 1.78.36.1.2.9 20-Jan-2010  matt Revamp things a bit. Move of the globals mips uses into either cpu_info,
mips_options, or mips_cache_info. Make MALT64 be able to boot MULTIPROCESSOR.
(some pmap MP work).
 1.78.36.1.2.8 15-Jan-2010  matt Get rid of most of the studly caps.
First to MULTIPROCESSOR support for pmap: move some pmap globals to cpu_info.
Define per-cpu ASID number spaces.
Remove some mips1/!mips1 difference in db_interface.c
Add mips32/64 knowledge to stacktrace.
 1.78.36.1.2.7 30-Dec-2009  matt Please segtab lookups into separate file.
Add mips_add_physload
Add mips_init_lwp0_uarea
cleanup lwp0/cpu_info_store initialization.
 1.78.36.1.2.6 13-Dec-2009  matt TLBUpdate (all forms) takes vaddr_t, uint32_t
 1.78.36.1.2.5 23-Nov-2009  matt mips3_ld/mips3_sd need to be passed a volatile uint64_t *
 1.78.36.1.2.4 05-Sep-2009  matt Change padding in kern_frame so it has quad-word (16 bytes) alignment.
Then when allocated on a stack, the stack keeps 16 byte alignment.
 1.78.36.1.2.3 30-Aug-2009  matt Add RMI company id.
Add some RMI processor ids.
Add CP0 EBASE defintion.
 1.78.36.1.2.2 21-Aug-2009  matt Define locoresw struct and use it.
Make tf_pad mips_reg_t since a register is stored in it.
remove argument save area from kernframe on NewABI.
 1.78.36.1.2.1 16-Aug-2009  matt Kill use of _MIPS_BSD_ABI - switch to __mips_<abi>
Use device_t where appropriate.
Remove magic numbers.
 1.78.30.1 09-Jun-2009  snj Pull up following revision(s) (requested by martin in ticket #799):
sys/arch/mips/include/locore.h: revision 1.79
sys/arch/mips/mips/locore_mips1.S: revision 1.65
sys/arch/mips/mips/mipsX_subr.S: revision 1.28
sys/arch/mips/mips/mips_machdep.c: revision 1.211
sys/arch/mips/mips/vm_machdep.c: revision 1.123
Do not use the same trampoline for cpu_lwp_fork and cpu_setfunc - only
the former needs to call lwp_startup().
 1.78.20.2 11-Mar-2010  yamt sync with head
 1.78.20.1 20-Jun-2009  yamt sync with head
 1.80.2.1 30-Apr-2010  uebayasi Sync with HEAD.
 1.81.6.2 05-Mar-2011  bouyer Sync with HEAD
 1.81.6.1 08-Feb-2011  bouyer Sync with HEAD
 1.81.4.1 06-Jun-2011  jruoho Sync with HEAD.
 1.81.2.3 31-May-2011  rmind sync with head
 1.81.2.2 21-Apr-2011  rmind sync with head
 1.81.2.1 05-Mar-2011  rmind sync with head
 1.92.6.1 24-Feb-2012  mrg sync to -current.
 1.92.2.1 17-Apr-2012  yamt sync with head
 1.93.2.1 03-Dec-2017  jdolecek update from HEAD
 1.94.2.5 28-Aug-2017  skrll Sync with HEAD
 1.94.2.4 05-Dec-2016  skrll Sync with HEAD
 1.94.2.3 05-Oct-2016  skrll Sync with HEAD
 1.94.2.2 22-Sep-2015  skrll Sync with HEAD
 1.94.2.1 06-Jun-2015  skrll Sync with HEAD
 1.100.2.2 20-Mar-2017  pgoyette Sync with HEAD
 1.100.2.1 04-Nov-2016  pgoyette Sync with HEAD
 1.101.2.1 21-Apr-2017  bouyer Sync with HEAD
 1.103.4.1 10-Jun-2019  christos Sync with HEAD
 1.116.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.117.6.1 31-May-2021  cjep sync with head
 1.117.4.2 17-Jun-2021  thorpej Sync w/ HEAD.
 1.117.4.1 13-May-2021  thorpej Sync with HEAD.
 1.2 04-Nov-2024  christos Undo previous lwp.h change.
 1.1 03-Nov-2024  christos Split __lwp_getprivate_fast and __lwp_*tcb from mcontext.h into a separate
lwp.h file.
 1.1 30-Nov-2024  christos branches: 1.1.4;
Create a new header lwp_private.h to contain _lwp_getprivate_fast,
_lwp_gettcb_fast, _lwp_settcb and remove them from mcontext.h, so that:
1. we don't need special hacks to hide them
2. we can include <lwp.h> where needed to get the necessary prototypes
without redefining them locally.
 1.1.4.2 02-Aug-2025  perseant Sync with HEAD
 1.1.4.1 30-Nov-2024  perseant file lwp_private.h was added on branch perseant-exfatfs on 2025-08-02 05:55:53 +0000
 1.8 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.7 31-Jan-2014  matt Consolidate the 128-bit long double defintions to <sys/ieee754.h>
Each arch that uses it now defines __HAVE_LONG_DOUBLE to 128.
<machine/ieee.h> is now just include the machine's math.h followed
by <sys/ieee754.h>
 1.6 23-May-2013  christos branches: 1.6.2;
add generic copyrights so FreeBSD can use them.
 1.5 17-Jan-2011  matt branches: 1.5.6; 1.5.16;
Make the MIPS N32/N64 ABIs properly support 128-bit long doubles. With this
change, we should be fully conformant with the N32 and N64 ABIs.
Add {fpclassify,infinity,isnan,ininf,signbit}l_ieee754.c back to lib/libc/gen.
Note that infinityl_ieee754.c will work with either 64-bit, 80-bit, or
128-bit long doubles.
 1.4 19-Feb-2002  simonb branches: 1.4.140; 1.4.144; 1.4.150;
Clean up some rampant code duplication wrt ieee number handling:
- Add alignment-safe double and float unions.
- Use the above for the __infinity and __nan constants on all
architectures that use the standard ieee754 representation of
those constants.
- Add a single copy of various ieee754 math functions (frexp, isinf,
isnan, ldexp and modf) that had numerous duplicates among the
arch-specific directories.
- Use the above functions on all architectures where the generic C
versions where used. Architectures that had local assembly
routines are untouched (for those functions only).
 1.3 05-Feb-2000  kleink branches: 1.3.6; 1.3.10; 1.3.14;
Improve namespace test macros a bit.
 1.2 04-Jan-2000  kleink const -> __const and include <sys/cdefs.h> earlier; fixes PR lib/9052
by Takahiro Kambe.
 1.1 23-Dec-1999  kleink C99: Define a NAN macro in <math.h> which evaulates to a constant expression of
a single-precision quiet NaN; only to be defined on platforms that do support
this value.
 1.3.14.1 28-Feb-2002  nathanw Catch up to -current.
 1.3.10.1 16-Mar-2002  jdolecek Catch up with -current.
 1.3.6.2 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.3.6.1 05-Feb-2000  bouyer file math.h was added on branch thorpej_scsipi on 2000-11-20 20:13:31 +0000
 1.4.150.1 06-Jun-2011  jruoho Sync with HEAD.
 1.4.144.1 05-Mar-2011  rmind sync with head
 1.4.140.1 29-Apr-2011  matt Pull in true (128-bit) long double support for MIPS from -current.
 1.5.16.2 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.5.16.1 23-Jun-2013  tls resync from head
 1.5.6.1 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.6.2.1 18-May-2014  rmind sync with head
 1.28 09-Apr-2025  rin mips/mcontext.h: Fix wrong size in comment for __UCONTEXT_SIZE_N64, NFC

Value itself is confirmed to be correct (also for {O,N}32 variants).
 1.27 30-Nov-2024  christos Create a new header lwp_private.h to contain _lwp_getprivate_fast,
_lwp_gettcb_fast, _lwp_settcb and remove them from mcontext.h, so that:
1. we don't need special hacks to hide them
2. we can include <lwp.h> where needed to get the necessary prototypes
without redefining them locally.
 1.26 04-Nov-2024  christos Undo previous lwp.h change.
 1.25 03-Nov-2024  christos Split __lwp_getprivate_fast and __lwp_*tcb from mcontext.h into a separate
lwp.h file.
 1.24 03-Oct-2020  martin branches: 1.24.26;
Add missing __BEGIN_DECLS/__END_DECLS to force function declarations into
the "C" namespace.
 1.23 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.22 15-Feb-2018  kamil Introduce _UC_MACHINE_FP() as a macro

_UC_MACHINE_FP() is a helper macro to extract from mcontext a frame pointer.

Don't rely on this interface as a compiler might strip frame pointer or
optimize it making this interface unreliable.


For hppa assume a small frame context, for larger frames FP might be located
in a different register (4 instead of 3).

For ia64 there is no strict frame pointer, and registers might rotate.
Reuse 79 following:

./gcc/config/ia64/ia64.h:#define HARD_FRAME_POINTER_REGNUM LOC_REG (79)

Once ia64 will mature, this should be revisited.

A macro can encapsulate a real function for extracting Frame Pointer on
more complex CPUs / ABIs.


For the remaining CPUs, reuse standard register as defined in appropriate ABI.

The direct users of this macro are LLVM and GCC with Sanitizers.

Proposed on tech-userlevel@.

Sponsored by <The NetBSD Foundation>
 1.21 26-May-2015  matt branches: 1.21.10;
Change _lwp_getprivate_fast to use a syscall instead of rdhwr since rdhwr
emulation is problematic for the CN50xx.
 1.20 12-Sep-2012  matt branches: 1.20.14;
N32 uses dadd instructions to manipulate stack (actually, all ABIs except
O32 use dadd).
 1.19 05-Jul-2011  joerg branches: 1.19.2; 1.19.12;
Ensure that _lwp_setprivate has a correct prototype.
 1.18 03-Jul-2011  mrg s/#elif/#else/ -- when there's nothing to check.
 1.17 15-Mar-2011  matt Add MIPS TLS support.
 1.16 25-Feb-2011  joerg Be nicer to software that insists on -ansi and use __inline.
 1.15 24-Feb-2011  joerg Allow storing and receiving the LWP private pointer via ucontext_t
on all platforms except VAX and IA64. Add fast access via register for
AMD64, i386 and SH3 ports. Use this fast access in libpthread to replace
the stack based pthread_self(). Implement skeleton support for Alpha,
HPPA, PowerPC, SPARC and SPARC64, but leave it disabled.

Ports that support this feature provide __HAVE____LWP_GETPRIVATE_FAST in
machine/types.h and a corresponding __lwp_getprivate_fast in
machine/mcontext.h.

This material is based upon work partially supported by
The NetBSD Foundation under a contract with Joerg Sonnenberger.
 1.14 24-Feb-2011  matt make sure to define _UC_MACHINE32_PAD
 1.13 23-Feb-2011  matt Add __UCONTEXT*_SIZE*
 1.12 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.11 14-Dec-2009  matt branches: 1.11.4; 1.11.6; 1.11.8;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.10 26-Nov-2009  matt Back out unintended commit.
 1.9 26-Nov-2009  matt Kill proc0paddr. Use lwp0.l_addr instead.
 1.8 28-Apr-2008  martin branches: 1.8.18;
Remove clause 3 and 4 from TNF licenses
 1.7 11-Dec-2005  christos branches: 1.7.74; 1.7.76; 1.7.78;
merge ktrace-lwp.
 1.6 03-Jul-2004  simonb Drop the "catchall" __fpregset_t, and use either a 32-bit or 64-bit
structure depending on the current ABI.

Part of fix for PR port-mips/25942. Thanks to Christos Zoulas and
Klaus Klein for help with debugging this.
 1.5 29-Oct-2003  christos branches: 1.5.2;
first pass siginfo for mips
 1.4 08-Oct-2003  thorpej Add some accessor macros for the ucontext:
* _UC_MACHINE_PC() - access the program counter
* _UC_MACHINE_INTRV() - access the integer return value register
* _UC_MACHINE_SET_PC() - set the program counter (this requires
special handling on some platforms).
 1.3 01-Oct-2003  simonb Quieten down lint a little with a /* LONGLONG */ comment.
 1.2 17-Jan-2003  thorpej branches: 1.2.2;
Merge the nathanw_sa branch.
 1.1 17-Nov-2001  wdk branches: 1.1.2;
file mcontext.h was initially added on branch nathanw_sa.
 1.1.2.4 17-Dec-2002  thorpej * Always include the SR in the gregset.
* Create space for the 32 64-bit double-precision registers used
in 64-bit ABIs.

This means we don't follow the SVR4 MIPS PS document, but that document
is somewhat out of date with regard to modern MIPS processors.

Per discussion with Chris Demetriou.
 1.1.2.3 28-Dec-2001  nathanw Add a macro, _UC_MACHINE_SP(), to fetch the user stack pointer from
a ucontext_t.
 1.1.2.2 21-Nov-2001  wdk Make __ASSEMBLER__ proof
 1.1.2.1 17-Nov-2001  wdk mcontext support for MIPS based ports.
 1.2.2.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.2.2.2 18-Sep-2004  skrll Sync with HEAD.
 1.2.2.1 03-Aug-2004  skrll Sync with HEAD
 1.5.2.1 04-Jul-2004  he Pull up revision 1.6 (requested by simonb in ticket #589):
Changes fixing PR#25942:
o Drop the ``catchall'' __fpregset_t, and use either a
32-bit or 64-bit structure depending on the current ABI
 1.7.78.2 11-Mar-2010  yamt sync with head
 1.7.78.1 16-May-2008  yamt sync with head.
 1.7.76.1 18-May-2008  yamt sync with head.
 1.7.74.1 02-Jun-2008  mjf Sync with HEAD.
 1.8.18.5 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.8.18.4 30-Apr-2010  matt Define mcontext_o32_t if !O32
 1.8.18.3 13-Sep-2009  matt Use __int32_t instead int32_t to make userland happy.
 1.8.18.2 12-Sep-2009  matt Add COMPAT_NETBSD32 support.
 1.8.18.1 16-Aug-2009  matt Kill use of _MIPS_BSD_ABI - switch to __mips_<abi>
Use device_t where appropriate.
Remove magic numbers.
 1.11.8.1 05-Mar-2011  bouyer Sync with HEAD
 1.11.6.1 06-Jun-2011  jruoho Sync with HEAD.
 1.11.4.2 21-Apr-2011  rmind sync with head
 1.11.4.1 05-Mar-2011  rmind sync with head
 1.19.12.2 03-Dec-2017  jdolecek update from HEAD
 1.19.12.1 20-Nov-2012  tls Resync to 2012-11-19 00:00:00 UTC
 1.19.2.1 30-Oct-2012  yamt sync with head
 1.20.14.1 06-Jun-2015  skrll Sync with HEAD
 1.21.10.3 21-Mar-2018  martin Pull up the following, requested by kamil in ticket #552:

external/gpl3/gcc{.old}/dist/libsanitizer/asan/asan_linux.cc 1.4
sys/arch/aarch64/include/mcontext.h 1.2
sys/arch/alpha/include/mcontext.h 1.9
sys/arch/amd64/include/mcontext.h 1.19
sys/arch/arm/include/mcontext.h 1.19
sys/arch/hppa/include/mcontext.h 1.9
sys/arch/i386/include/mcontext.h 1.14
sys/arch/ia64/include/mcontext.h 1.6
sys/arch/m68k/include/mcontext.h 1.10
sys/arch/mips/include/mcontext.h 1.22
sys/arch/or1k/include/mcontext.h 1.2
sys/arch/powerpc/include/mcontext.h 1.18
sys/arch/riscv/include/mcontext.h 1.5
sys/arch/sh3/include/mcontext.h 1.11
sys/arch/sparc/include/mcontext.h 1.14-1.17
sys/arch/sparc64/include/mcontext.h 1.10
sys/arch/vax/include/mcontext.h 1.9
tests/lib/libc/sys/Makefile 1.50
tests/lib/libc/sys/t_ucontext.c 1.2-1.5
sys/arch/hppa/include/mcontext.h 1.10
sys/arch/ia64/include/mcontext.h 1.7

- Introduce _UC_MACHINE_FP(). _UC_MACHINE_FP() is a helper
macro to extract from mcontext a frame pointer.
- Add new tests in lib/libc/sys/t_ucontext:
* ucontext_sp (testing _UC_MACHINE_SP)
* ucontext_fp (testing _UC_MACHINE_FP)
* ucontext_pc (testing _UC_MACHINE_PC)
* ucontext_intrv (testing _UC_MACHINE_INTRV)

Add a dummy implementation of _UC_MACHINE_INTRV() for ia64.

Implement _UC_MACHINE_INTRV() for hppa.

Make the t_ucontext.c test more portable.

We now have _UC_MACHINE_FP.
 1.21.10.2 26-Feb-2018  snj revert ticket 552, which broke the build
 1.21.10.1 25-Feb-2018  snj Pull up following revision(s) (requested by kamil in ticket #552):
sys/arch/aarch64/include/mcontext.h: 1.2
sys/arch/alpha/include/mcontext.h: 1.9
sys/arch/amd64/include/mcontext.h: 1.19
sys/arch/arm/include/mcontext.h: 1.19
sys/arch/hppa/include/mcontext.h: 1.9
sys/arch/i386/include/mcontext.h: 1.14
sys/arch/ia64/include/mcontext.h: 1.6
sys/arch/m68k/include/mcontext.h: 1.10
sys/arch/mips/include/mcontext.h: 1.22
sys/arch/or1k/include/mcontext.h: 1.2
sys/arch/powerpc/include/mcontext.h: 1.18
sys/arch/riscv/include/mcontext.h: 1.5
sys/arch/sh3/include/mcontext.h: 1.11
sys/arch/sparc/include/mcontext.h: 1.14-1.17
sys/arch/sparc64/include/mcontext.h: 1.10
sys/arch/vax/include/mcontext.h: 1.9
tests/lib/libc/sys/Makefile: 1.50
tests/lib/libc/sys/t_ucontext.c: 1.2
Introduce _UC_MACHINE_FP() as a macro
_UC_MACHINE_FP() is a helper macro to extract from mcontext a frame pointer.
Don't rely on this interface as a compiler might strip frame pointer or
optimize it making this interface unreliable.
For hppa assume a small frame context, for larger frames FP might be located
in a different register (4 instead of 3).
For ia64 there is no strict frame pointer, and registers might rotate.
Reuse 79 following:
./gcc/config/ia64/ia64.h:#define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
Once ia64 will mature, this should be revisited.
A macro can encapsulate a real function for extracting Frame Pointer on
more complex CPUs / ABIs.
For the remaining CPUs, reuse standard register as defined in appropriate ABI.
The direct users of this macro are LLVM and GCC with Sanitizers.
Proposed on tech-userlevel@.
Sponsored by <The NetBSD Foundation>
--
Improve _UC_MACHINE_FP() for SPARC/SPARC64
Introduce a static inline function _uc_machine_fp() that contains improved
caluclation of a frame pointer.
Algorithm:
uptr *stk_ptr;
# if defined (__arch64__)
stk_ptr = (uptr *) (*sp + 2047);
# else
stk_ptr = (uptr *) *sp;
# endif
*bp = stk_ptr[15];
Noted by <mrg>
--
Make _UC_MACHINE_FP() compile again and fix it so that it does not add
the offset twice.
--
fix _UC_MACHINE32_FP() -- use 32 bit pointer value so that [15] is
the right offset. do this by using __greg32_t, which is only in
the sparc64 version, and these are only useful there, so move them.
--
Add new tests in lib/libc/sys/t_ucontext
New tests:
- ucontext_sp
- ucontext_fp
- ucontext_pc
- ucontext_intrv
They test respectively:
- _UC_MACHINE_SP
- _UC_MACHINE_FP
- _UC_MACHINE_PC
- _UC_MACHINE_INTRV
These tests attempt to access and print the values from ucontext, without
interpreting the values.
This is a follow up of the _UC_MACHINE_FP() introduction.
These tests use PRIxREGISTER, and require to be built with -D_KERNTYPES.
Sponsored by <The NetBSD Foundation>
 1.24.26.1 02-Aug-2025  perseant Sync with HEAD
 1.21 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.20 26-Jun-2015  matt ifdef out bitfield struct for pte (not used).
 1.19 20-Feb-2011  matt branches: 1.19.14; 1.19.32;
Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.18 08-Feb-2011  rmind Remove clause 3 (UCB advertising clause) from the University of Utah
copyright. Confirmed by Mike Hibler, mike at cs.utah.edu - thanks!
Also, merge UCB and Utah copyright texts back into one, as they
originally were.

Extra verification by snj@.
 1.17 17-Oct-2007  garbled branches: 1.17.38; 1.17.42; 1.17.48; 1.17.50;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.16 17-Jul-2007  macallan branches: 1.16.10;
add definitions for non-cached pages
 1.15 11-Dec-2005  christos branches: 1.15.30; 1.15.38;
merge ktrace-lwp.
 1.14 07-Aug-2003  agc branches: 1.14.16;
Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.13 09-Jun-2000  soda branches: 1.13.26;
rename
vad_to_pfn() -> mips_paddr_to_tlbpfn()
pfn_to_vad() -> mips_tlbpfn_to_paddr()
as suggested by thorpej on port-mips Mar 27.
 1.12 09-Jun-2000  soda make paddr_t 64bit on arc port by introducing _MIPS_PADDR_T_64BIT.
 1.11 27-May-1999  nisimura branches: 1.11.2; 1.11.10;
- Change a symbolic name of TLB entrylo from 'PG_M' to 'PG_D' to reflect
processor design. MIPS 'dirty bit' is not the same as i386 'dirty bit'.
There is a growing concern of misuse in NetBSD/mips.
 1.10 16-Jun-1997  jonathan branches: 1.10.20;
Changes for configuring both MIPS1 and MIPS3, from a merge of
similar design and code by Jason Thorpe and Jonathan Stone.

NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.

mips/include/cpu.h:
Add CPUISMIPS3 for run-time tests of what CPU architecture level
we're running on.

mips/include/locore.h:
Add declarations of locore cache-size variables for ref/def toolchain.

mips/include/mips1_pte.h:
mips1 TLB bit definitions.

mips/include/mips3_pte.h:
mips3 TLB bit definitions.

mips/include/pte.h:
define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
that expand to CPU constants if only one CPU arch is configured,
or to inline functions if both MIPS1 and MIPS3 are configured.

mips/mips/locore_r2000.S:
Use MIPS1_PG_xxx constants inside mips1-specific code.

mips/mips/locore_r4000.S:
Use MIPS3_PG_xxx constants inside mips3-specific code.

mips/mips/locore.S:
Use MIPS1_PG_xxx constants inside mips3-specific code.
Use MIPS1_PG_xxx constants inside mips1-specific code.
(Needs more work!)

mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
Use MIPS3_PG_xxx constants inside mips3-specific functions,
and MIPS1_PG_XXX inside mips1-specific code.
Otherwise, use mips_pg_XXX_bit() macros where they apply,
and use "if (CPUISMIPS3) { ... } else {... }" where they don't.

mips/mips/mips_machdep.c:
Import Michael Hitch's fixes from the pmax locore-init code
into mips_vector_init().

pmax/pmax/machdep.c:
Use generic mips_vector_init() locore vector-init function.
 1.9 15-Jun-1997  mhitch More merged MIPS1/MIPS3 support. The pte definitions still need work before
they can be support both MIPS1 and MIPS3.
 1.8 13-Oct-1996  jonathan Add (missing) PAGE_IS_RDONLY() macro to test for readonly pages,
in both mips-I and mips-II versions, and use it in arch/mips/mips/trap.c.
 1.7 13-Oct-1996  jonathan Merge mips1 and mips3 pte/pmap code, pass 0;
* Move mips-I pte (TLBlo) definitions from pmax/include/pte.h
to mips/include/mips1_pte.h

* Move mips-III pte (TLBlo) definitions from pica/include/pte.h
to mips/include/mips3_pte.h

* Add new mips/include/pte.h, which includes exactly one of
mips1_pte.h or mips3_pte.h (which still have namespace collisions),
depending on "options MIPS1" or "options MIPS3". (hack).
Move soft kvtopte(), ptetovk() definitions to mips/include/pte.h

* Add macro PTE_TO_PADDR() to hide the different hardware TLB formats
when mapping from pte to physical address.

* Add macro PTE_READONLY() to hide lack of SW read-only bit in mips-III
tlb. (mips1 pmap uses a sw bit in the PTE, mips3 looks up RO bit in
the kernel pmap.)

* Use macros (not direct TLB frobbing) in mips/trap.c, to make it
mips-1/mips-III indepenndet.

* Change {pmax,pica}/include/pte.h to just do #include <mips/pte.h>.
 1.6 01-Feb-1996  mycroft LOCORE -> _LOCORE
 1.5 28-Mar-1995  jtc KERNEL -> _KERNEL
 1.4 26-Oct-1994  cgd new RCS ID format.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.10.20.1 21-Jun-1999  thorpej Sync w/ -current.
 1.11.10.1 22-Jun-2000  minoura Sync w/ netbsd-1-5-base.
 1.11.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.13.26.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.13.26.2 18-Sep-2004  skrll Sync with HEAD.
 1.13.26.1 03-Aug-2004  skrll Sync with HEAD
 1.14.16.1 03-Sep-2007  yamt sync with head.
 1.15.38.1 03-Oct-2007  garbled Sync with HEAD
 1.15.30.1 20-Aug-2007  ad Sync with HEAD.
 1.16.10.1 06-Nov-2007  matt sync with HEAD
 1.17.50.2 05-Mar-2011  bouyer Sync with HEAD
 1.17.50.1 17-Feb-2011  bouyer Sync with HEAD
 1.17.48.1 06-Jun-2011  jruoho Sync with HEAD.
 1.17.42.1 05-Mar-2011  rmind sync with head
 1.17.38.1 22-Dec-2009  matt Add multiple inclusion protection.
 1.19.32.1 22-Sep-2015  skrll Sync with HEAD
 1.19.14.1 03-Dec-2017  jdolecek update from HEAD
 1.5 08-Jan-2008  joerg Remove __HAVE_TIMECOUNTER conditionals.
 1.4 10-Sep-2006  tsutsui branches: 1.4.6; 1.4.32; 1.4.38; 1.4.46;
Change mips3_clockintr() to take (struct clockframe *) rather than
pc and status since it calls hardclock(9) anyway.
OK'ed by gdamore on port-mips.
 1.3 08-Sep-2006  gdamore branches: 1.3.2;
Various improvements to make the common mips3 clock handling more generally
useful. The functions delay, cpu_initclocks, and setstatclcokrate have been
renamed to mips3_delay, mips3_initclocks, and mips3_setstatclockrate.

We provide weak aliases for the original names, so machdep code doesn't have
to provide wrapper routines. (Giving good performance.)

I've moved mips3_clockintr, mips3_initclocks, and mips3_setstatclockrate to
their own mips3_clockintr file, because some ports may not be able to use
these, and its senseless to carry that baggage.
 1.2 08-Sep-2006  gdamore Rename init_mips3_tc to mips3_init_tc() for consistency, and make it
extern.
 1.1 02-Sep-2006  gdamore branches: 1.1.2; 1.1.4;
Provide a common implementation for ports that use the MIPS CP0 counter
based clock interrupt.

This provides common implementations of: delay(), cpu_initclocks(), and a
timecounter based on the MIPS3 CP0. It also provides a new function,
mips3_clockintr(), that is intended to be called from a port's cpu_intr()
routine when INT5 is raised.

Hopefully many MIPS3 based machines can adopt this common interrupt framework.
The evbmips conversion will be committed separately, shortly.
 1.1.4.1 18-Nov-2006  ad Sync with head.
 1.1.2.3 14-Sep-2006  yamt sync with head.
 1.1.2.2 03-Sep-2006  yamt sync with head.
 1.1.2.1 02-Sep-2006  yamt file mips3_clock.h was added on branch yamt-pdpolicy on 2006-09-03 15:23:21 +0000
 1.3.2.2 09-Sep-2006  rpaulo sync with head
 1.3.2.1 08-Sep-2006  rpaulo file mips3_clock.h was added on branch rpaulo-netinet-merge-pcb on 2006-09-09 02:41:26 +0000
 1.4.46.1 08-Jan-2008  bouyer Sync with HEAD
 1.4.38.1 18-Feb-2008  mjf Sync with HEAD.
 1.4.32.1 09-Jan-2008  matt sync with HEAD
 1.4.6.3 21-Jan-2008  yamt sync with head
 1.4.6.2 30-Dec-2006  yamt sync with head.
 1.4.6.1 10-Sep-2006  yamt file mips3_clock.h was added on branch yamt-lazymbuf on 2006-12-30 20:46:32 +0000
 1.32 09-Sep-2023  andvar change #define to #error for MIPS3_4100i 8KB page size build protection.
 1.31 17-Aug-2020  mrg port crash(8) to mips. (most of the kernel side.)

- expose parts of _KERNEL to _KMEMUSER as well
- hide more things for _KERNEL
- avoid DB_MACHINE_COMMANDS in crash(8)
- XXX add mips_label_t for !_KERNEL and use it in the pcb to
avoid conflicting with the ddb/crash one
- enable dumppcb

some changes to make stack trace fail instead of SEGV and
the userland changes to crash itself not part of this change.
 1.30 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.29 11-Jul-2016  matt Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.28 22-Sep-2011  macallan branches: 1.28.12; 1.28.30;
support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory and
DMA buffers with cacheing disabled but things like write combining, relaxed
ordering etc. allowed when the CPU supports it
so far enabled only on Loongson, should work on R1xk and probably newer CPUs
 1.27 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.26 08-Feb-2011  rmind Remove clause 3 (UCB advertising clause) from the University of Utah
copyright. Confirmed by Mike Hibler, mike at cs.utah.edu - thanks!
Also, merge UCB and Utah copyright texts back into one, as they
originally were.

Extra verification by snj@.
 1.25 14-Dec-2009  matt branches: 1.25.4; 1.25.6; 1.25.8;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.24 09-Aug-2009  matt Add 16KB variants of MIPS3_PG_{ODDPG,HVN,SVN}
 1.23 17-Oct-2007  garbled branches: 1.23.20; 1.23.38;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.22 17-Jul-2007  macallan branches: 1.22.10;
add definitions for non-cached pages
 1.21 11-Dec-2005  christos branches: 1.21.30; 1.21.38;
merge ktrace-lwp.
 1.20 05-Nov-2005  tsutsui Make MIPS3_PG_SHIFT a variable and initialize it accordingly
in mips_vector_init() if options MIPS3_4100 is specified
so that kernels which have options MIPS3_4100 also work
on other MIPS3 CPUs.

XXX: now should we rename options MIPS3_4100 to options ENABLE_MIPS_R4100,
XXX: or just make MIPS3_PG_SHIFT always a variable?
 1.19 05-Nov-2005  tsutsui Add MI mips3 wired map functions based on patch in port-mips/31915
from Garrett D'Amore of Tadpole Computer Inc.
Please refer discussion filed in the PR for details.
 1.18 10-Oct-2005  tsutsui Define MIPS3_PG_SIZE_MASK_TO_SIZE() macro in the MI mips header.
 1.17 08-Sep-2005  tsutsui Add definitions of Vr41xx specific pagemask values.
It supports 1k-256kbytes/page.
 1.16 07-Aug-2003  agc branches: 1.16.6; 1.16.14; 1.16.16;
Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.15 24-Jun-2002  simonb branches: 1.15.6;
Add 64MB and 256MB tlb page masks.
 1.14 05-Mar-2002  simonb branches: 1.14.6;
Add support for MIPS32 and MIPS64 architectures:
Better cache coherency attribute macros (from Broadcom Corp).
 1.13 09-Jun-2000  soda branches: 1.13.6; 1.13.10;
rename
vad_to_pfn() -> mips_paddr_to_tlbpfn()
pfn_to_vad() -> mips_tlbpfn_to_paddr()
as suggested by thorpej on port-mips Mar 27.
 1.12 09-Jun-2000  soda make paddr_t 64bit on arc port by introducing _MIPS_PADDR_T_64BIT.
 1.11 27-Mar-2000  nisimura branches: 1.11.2;
Nuke MIPS_16K_PAGE conditional which should be commited in. It
was used for debugg'n purposes which only make senses on particular
hardware configurations and has never been intended to extend pagesize
of NetBSD/mips.
 1.10 25-Sep-1999  shin branches: 1.10.2;
Changes for NetBSD/hpcmips.

Support VR4100.
Support 16KB page.
Support CPU without FPU.

Fix virtual alias problem(physio() case).

[new options]

options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */
 1.9 27-May-1999  nisimura - Change a symbolic name of TLB entrylo from 'PG_M' to 'PG_D' to reflect
processor design. MIPS 'dirty bit' is not the same as i386 'dirty bit'.
There is a growing concern of misuse in NetBSD/mips.
 1.8 11-Sep-1998  jonathan branches: 1.8.10;
Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.

* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.
 1.7 16-Jun-1997  jonathan Changes for configuring both MIPS1 and MIPS3, from a merge of
similar design and code by Jason Thorpe and Jonathan Stone.

NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.

mips/include/cpu.h:
Add CPUISMIPS3 for run-time tests of what CPU architecture level
we're running on.

mips/include/locore.h:
Add declarations of locore cache-size variables for ref/def toolchain.

mips/include/mips1_pte.h:
mips1 TLB bit definitions.

mips/include/mips3_pte.h:
mips3 TLB bit definitions.

mips/include/pte.h:
define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
that expand to CPU constants if only one CPU arch is configured,
or to inline functions if both MIPS1 and MIPS3 are configured.

mips/mips/locore_r2000.S:
Use MIPS1_PG_xxx constants inside mips1-specific code.

mips/mips/locore_r4000.S:
Use MIPS3_PG_xxx constants inside mips3-specific code.

mips/mips/locore.S:
Use MIPS1_PG_xxx constants inside mips3-specific code.
Use MIPS1_PG_xxx constants inside mips1-specific code.
(Needs more work!)

mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
Use MIPS3_PG_xxx constants inside mips3-specific functions,
and MIPS1_PG_XXX inside mips1-specific code.
Otherwise, use mips_pg_XXX_bit() macros where they apply,
and use "if (CPUISMIPS3) { ... } else {... }" where they don't.

mips/mips/mips_machdep.c:
Import Michael Hitch's fixes from the pmax locore-init code
into mips_vector_init().

pmax/pmax/machdep.c:
Use generic mips_vector_init() locore vector-init function.
 1.6 15-Jun-1997  mhitch More merged MIPS1/MIPS3 support. The pte definitions still need work before
they can be support both MIPS1 and MIPS3.
 1.5 13-Oct-1996  jonathan Add (missing) PAGE_IS_RDONLY() macro to test for readonly pages,
in both mips-I and mips-II versions, and use it in arch/mips/mips/trap.c.
 1.4 13-Oct-1996  jonathan Merge mips1 and mips3 pte/pmap code, pass 0;
* Move mips-I pte (TLBlo) definitions from pmax/include/pte.h
to mips/include/mips1_pte.h

* Move mips-III pte (TLBlo) definitions from pica/include/pte.h
to mips/include/mips3_pte.h

* Add new mips/include/pte.h, which includes exactly one of
mips1_pte.h or mips3_pte.h (which still have namespace collisions),
depending on "options MIPS1" or "options MIPS3". (hack).
Move soft kvtopte(), ptetovk() definitions to mips/include/pte.h

* Add macro PTE_TO_PADDR() to hide the different hardware TLB formats
when mapping from pte to physical address.

* Add macro PTE_READONLY() to hide lack of SW read-only bit in mips-III
tlb. (mips1 pmap uses a sw bit in the PTE, mips3 looks up RO bit in
the kernel pmap.)

* Use macros (not direct TLB frobbing) in mips/trap.c, to make it
mips-1/mips-III indepenndet.

* Change {pmax,pica}/include/pte.h to just do #include <mips/pte.h>.
 1.3 11-Aug-1996  jonathan * Apply LOCORE -> _LOCORE change so locore.S doesn't #include struct
definitions.

* Include <mips/cpuregs.h> in <cpu.h> so kern_clock.c has user/kernel
status bits in scope. Still needs work; r2k/r4k previous-mode bits
are different.

* Include <mips/mips_param.h> in pica/include/param.h, for locore declarations,
and definitions of vm and other constants that should be shared across
NetBSD/mips systems to esnsure user-level binary compatibility.
 1.2 16-Jul-1996  thorpej RCS id police.
 1.1 13-Mar-1996  jonathan branches: 1.1.1;
Initial revision
 1.1.1.1 13-Mar-1996  jonathan First commit of Per Fogelstrom's port to the Acer pica r4400/isa machine.
 1.8.10.1 21-Jun-1999  thorpej Sync w/ -current.
 1.10.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.11.2.1 22-Jun-2000  minoura Sync w/ netbsd-1-5-base.
 1.13.10.2 01-Aug-2002  nathanw Catch up to -current.
 1.13.10.1 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.13.6.2 06-Sep-2002  jdolecek sync kqueue branch with HEAD
 1.13.6.1 16-Mar-2002  jdolecek Catch up with -current.
 1.14.6.1 16-Jul-2002  gehenna catch up with -current.
 1.15.6.4 10-Nov-2005  skrll Sync with HEAD. Here we go again...
 1.15.6.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.15.6.2 18-Sep-2004  skrll Sync with HEAD.
 1.15.6.1 03-Aug-2004  skrll Sync with HEAD
 1.16.16.2 03-Sep-2007  yamt sync with head.
 1.16.16.1 21-Jun-2006  yamt sync with head.
 1.16.14.1 11-Sep-2005  tron Pull up following revision(s) (requested by tsutsui in ticket #758):
sys/arch/mips/include/mips3_pte.h: revision 1.17
Add definitions of Vr41xx specific pagemask values.
It supports 1k-256kbytes/page.
 1.16.6.1 13-Sep-2005  riz Pull up following revision(s) (requested by tsutsui in ticket #5829):
sys/arch/mips/include/mips3_pte.h: revision 1.17
Add definitions of Vr41xx specific pagemask values.
It supports 1k-256kbytes/page.
 1.21.38.1 03-Oct-2007  garbled Sync with HEAD
 1.21.30.1 20-Aug-2007  ad Sync with HEAD.
 1.22.10.1 06-Nov-2007  matt sync with HEAD
 1.23.38.8 23-Dec-2011  matt Base various #defines, etc. on PAGE_SHIFT instead of using separate
ENABLE_MIPS_*_PAGE defines.
 1.23.38.7 02-Dec-2011  matt Add support for 8KB pages.
 1.23.38.6 26-Jan-2010  matt Revamp pmap. Add exec page caching logic from powerpc oea pmap. Shrink struct
vm_page by placing the first pv_entry in it. Remove pv_flags since nothing
really needed it. Add pmap counters. Rework virtual cache alias logic.
Allow pmap_copy_page and pmap_zero_page to deal with non-KSEG0 mappable pages.
 1.23.38.5 20-Jan-2010  matt Revamp things a bit. Move of the globals mips uses into either cpu_info,
mips_options, or mips_cache_info. Make MALT64 be able to boot MULTIPROCESSOR.
(some pmap MP work).
 1.23.38.4 15-Jan-2010  matt Get rid of most of the studly caps.
First to MULTIPROCESSOR support for pmap: move some pmap globals to cpu_info.
Define per-cpu ASID number spaces.
Remove some mips1/!mips1 difference in db_interface.c
Add mips32/64 knowledge to stacktrace.
 1.23.38.3 22-Dec-2009  matt Add multiple inclusion protection.
 1.23.38.2 08-Sep-2009  matt Add and optimize MIPS_PHYS_TO_XKPHYS_{UN,}CACHED(pa).
Treat like mips3_pg_cached: add mips3_xkphys_cached which contains the
starting address of the cached XKPHYS region. It also respects SPECIAL_CCA.
 1.23.38.1 20-Aug-2009  matt Add a MIPS3_PG_TO_CCA() macro to get the CCA out of the saved page attributes.
 1.23.20.2 11-Mar-2010  yamt sync with head
 1.23.20.1 19-Aug-2009  yamt sync with head.
 1.25.8.2 05-Mar-2011  bouyer Sync with HEAD
 1.25.8.1 17-Feb-2011  bouyer Sync with HEAD
 1.25.6.1 06-Jun-2011  jruoho Sync with HEAD.
 1.25.4.1 05-Mar-2011  rmind sync with head
 1.28.30.1 05-Oct-2016  skrll Sync with HEAD
 1.28.12.1 03-Dec-2017  jdolecek update from HEAD
 1.14 06-May-2023  andvar s/Regiser/Register/ and s/regester/register/ in comments.
 1.13 08-Nov-2022  simonb Fix tyop in __BITS for the MIPSNN_MTI_CFG7_PREF_MASK macro.
 1.12 02-Aug-2020  simonb Document the PerfCntCrl registers (CP0 Register 25, Selects 0, 2, 4, 6).
 1.11 31-Jul-2020  simonb Rename MIPSNN_CFG4_MMU_EXT_DEF_MMU_SIZE_EXT to MIPSNN_CFG4_MMU_SIZE_EXT.
 1.10 31-Jul-2020  simonb Bit definitions Config4 and Config5 registers.
 1.9 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.8 13-Jun-2020  simonb Move MIPSNN_CFG3_ULRI so that it doesn't appear in some random position
among the other config3 register definitions.
 1.7 13-Jun-2020  simonb Use the correct config3 field name (ULRI) for UserLocal register is
implemented bit.
 1.6 11-Jul-2016  matt Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.5 16-Aug-2011  matt branches: 1.5.12; 1.5.30;
Add support for the MIPS DSP ASE (as a second PCU).
 1.4 20-Mar-2006  gdamore branches: 1.4.84;
Added support for MIPS architecture revision 2.
Added definitions for various rev 2 CP0 configuration register bits.
Added support for MIPS 4KEc Rev 2 (found in Atheros AR2316, for example).
 1.3 07-Feb-2003  cgd branches: 1.3.18; 1.3.32; 1.3.34; 1.3.36; 1.3.38; 1.3.40;
Update to consistently use Broadcom GPL-compatible license on all SiByte code.
 1.2 24-Nov-2002  simonb Add the VI bit in config 0.
 1.1 05-Mar-2002  simonb branches: 1.1.4; 1.1.8;
Values related to the MIPS32/MIPS64 Privileged Resource Architecture
(from Broadcom Corp).
 1.1.8.3 11-Dec-2002  thorpej Sync with HEAD.
 1.1.8.2 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.1.8.1 05-Mar-2002  nathanw file mipsNN.h was added on branch nathanw_sa on 2002-04-01 07:40:59 +0000
 1.1.4.2 16-Mar-2002  jdolecek Catch up with -current.
 1.1.4.1 05-Mar-2002  jdolecek file mipsNN.h was added on branch kqueue on 2002-03-16 15:58:35 +0000
 1.3.40.1 28-Mar-2006  tron Merge 2006-03-28 NetBSD-current into the "peter-altq" branch.
 1.3.38.1 19-Apr-2006  elad sync with head - hopefully this will work
 1.3.36.1 01-Apr-2006  yamt sync with head.
 1.3.34.1 22-Apr-2006  simonb Sync with head.
 1.3.32.1 09-Sep-2006  rpaulo sync with head
 1.3.18.1 21-Jun-2006  yamt sync with head.
 1.4.84.1 23-Dec-2011  matt Add CFG6/7 definitions for MIPS 24K/74K/34K/1004K/1074K and RMI XLP.
 1.5.30.1 05-Oct-2016  skrll Sync with HEAD
 1.5.12.1 03-Dec-2017  jdolecek update from HEAD
 1.5 11-Nov-1998  nisimura - Withdraw a duplicated file. This has never been a part of distribution.
 1.4 26-Sep-1998  nisimura branches: 1.4.2;
Add one more new MIPS processor PRid 0x30 for IDT RC64474/64475. These
are successors of RC4640/RC4650, but fully brewed MIPS, then capable of
running NetBSD/mips.
 1.3 26-Sep-1998  nisimura Update the list of MIPS processor revision ID. PRids of Toshiba TX3900
and QED R4650 comflict each other.
 1.2 07-Sep-1998  nisimura Added more MIPS processor IDs.
 1.1 03-Sep-1998  nisimura An include file describes MIPS processor hardware nature, which will
supercedes cpuregs.h eventually.
 1.4.2.1 15-Oct-1998  nisimura - cpuregs.h was modifed a bit, then renamed with cpuarch.h.
- mips_cpu.h has gone.
- CPU's register mnemonics in regdef.h is now a part of asm.h.
 1.26 05-Apr-2021  simonb Some QED instructions are included in MIPS32 and MIPS64 instruction sets.
Update a few comments.
 1.25 05-Apr-2021  simonb Tidy up NOP disassembly, handle "pause" as well.
 1.24 17-Aug-2020  mrg branches: 1.24.4;
add a "special3 offset" type of decode to ddb disasm so we see the
offsets properly decoded. add mips r6 "cache" insn.

avoid signed/unsigned compare and ufetch_32() for upcoming crash(8).
 1.23 15-Aug-2020  simonb Fix value for SCE/SWE instructions.
Problem noticed by mrg@.
 1.22 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.21 27-Jun-2015  matt More instructions
 1.20 04-Jun-2015  matt Add a lot of missing mipsNNr2 instruction + cavium specific instructions.
 1.19 01-Jun-2015  matt Rework cavium support in preparation for MULTIPROCESSOR support
 1.18 18-Aug-2011  matt branches: 1.18.12; 1.18.30;
Change bcond/BCOND to regimm/REGIMM to better match the MIPS nomenclature.
 1.17 17-Aug-2011  matt emulate the special3 opcode LX (lwx, ldx, lhx, lbux) instructions.
 1.16 15-Mar-2011  matt Remove redundant lines.
 1.15 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.14 07-Jul-2010  chs branches: 1.14.2; 1.14.4;
implement emulation of the "rdhwr" instruction for mips TLS.
 1.13 06-Aug-2009  msaitoh branches: 1.13.2; 1.13.4;
Add disassemble code for DMT, DMF, MTH and MFH.
 1.12 11-Dec-2005  christos branches: 1.12.78; 1.12.96;
merge ktrace-lwp.
 1.11 15-Oct-2003  simonb One defintion of OP_SYNC should be enough.
 1.10 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.9 06-Jul-2002  gmcgarry branches: 1.9.6;
Overhaul the emulation facility. We do this by:

- accumulating all emulation code (including floating-point) in one place
- steal MachFPInterrupt() back from SOFTFLOAT for use only with interrupts
and traps from *real* FPUs
- introducing MachEmulateInst() as a common dispatch point for all
emulated instructions
- cleaning up emulation dispatch in trap()

Also, while we're here, implement MIPS2 LL/SC/SYNC emulation for MIPS1.

Tested on r3k with and without SOFTFLOAT enabled.
 1.8 13-Aug-2001  soda branches: 1.8.6; 1.8.14;
OP_BLTZAL was defined twice.
 1.7 11-Jul-2000  jeffs branches: 1.7.4;
Add support for 3 QED special2 opcodes.
 1.6 17-Oct-1997  jonathan branches: 1.6.18;
Add bi-endian support to mips locore, <mips/endian.h>, and mips_opcode.h.
Derived from a change request (PR port-mips/4277) from
Tsubai Masanari, (tsubai@iri.co.jp).
 1.5 23-Mar-1996  jonathan Merge in additions of missing MIPS-I opcodes, and r4000-in-32-bit mode
opcodes from the Pica port. Per Fogelstrom claims the latter are all
supposedly MIPS-II (r6000) instructions, rather than MIPS-III (R4000),
but we haven't checked to be sure. Are LL/SC really in MIPS-II?
CVS:: ----------------------------------------------------------------------
 1.4 26-Oct-1994  cgd new RCS ID format.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.6.18.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.7.4.2 06-Sep-2002  jdolecek sync kqueue branch with HEAD
 1.7.4.1 25-Aug-2001  thorpej Merge Aug 24 -current into the kqueue branch.
 1.8.14.1 16-Jul-2002  gehenna catch up with -current.
 1.8.6.2 01-Aug-2002  nathanw Catch up to -current.
 1.8.6.1 13-Aug-2001  nathanw file mips_opcode.h was added on branch nathanw_sa on 2002-08-01 02:42:31 +0000
 1.9.6.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.9.6.2 18-Sep-2004  skrll Sync with HEAD.
 1.9.6.1 03-Aug-2004  skrll Sync with HEAD
 1.12.96.4 04-Aug-2012  matt disasm special2 and special3 opcodes (and ehb and ssnop too).
 1.12.96.3 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.12.96.2 29-Dec-2010  matt Add OPC_PREF and OPC_RSVD073
 1.12.96.1 15-May-2010  matt Add kernel support for MIPS TLS. Use rdhwr rt, $29 as defined by the MIPS
TLS spec so that Linux MIPS binaries will work. Use sysarch(MIPS_TINFOSET, v)
to set the pointer.
 1.12.78.2 11-Aug-2010  yamt sync with head.
 1.12.78.1 19-Aug-2009  yamt sync with head.
 1.13.4.2 21-Apr-2011  rmind sync with head
 1.13.4.1 05-Mar-2011  rmind sync with head
 1.13.2.1 17-Aug-2010  uebayasi Sync with HEAD.
 1.14.4.1 05-Mar-2011  bouyer Sync with HEAD
 1.14.2.1 06-Jun-2011  jruoho Sync with HEAD.
 1.18.30.2 22-Sep-2015  skrll Sync with HEAD
 1.18.30.1 06-Jun-2015  skrll Sync with HEAD
 1.18.12.1 03-Dec-2017  jdolecek update from HEAD
 1.24.4.1 17-Apr-2021  thorpej Sync with HEAD.
 1.56 03-May-2025  riastradh mips_param.h: Add include guard.

Prompted by nearby fix for:

PR port-evbmips/59385: PGSHIFT is inconsistently defined on MIPS
 1.55 03-May-2025  riastradh mips: Include opt_cputype.h before any of the flags it defines.

PR port-evbmips/59385: PGSHIFT is inconsistently defined on MIPS
 1.54 25-Apr-2025  riastradh mips: Align stack pointer on entry to signal handler.

Based on a patch by rin@. The variant approach I took puts the stack
frame allocation and alignment logic in one place (getframe, used by
sendsig_siginfo for native (n64, on mips), netbsd32_sendsig_siginfo
for compat32 (n32/o32, on mips), and sendsig_sigcontext (compat 1.6))
and reduces the chance of provoking compiler exploitation of
undefined behaviour by doing arithmetic in uintptr_t rather than in
pointers to large aligned structs. This also ensures the resulting
pointer is aligned for the object (struct siginfo_sigframe, struct
siginfo_sigframe32, struct sigcontext), not just for the ABI stack
alignment.

PR kern/59327: user stack pointer is not aligned properly
 1.53 20-Apr-2025  riastradh t_signal_and_sp: Add mips support.

PR kern/59327: user stack pointer is not aligned properly

PR kern/58149: Cannot return from a signal handler if SP was
misaligned when the signal arrived

Stack pointer misaligment in some cases hypothesized to be a possible
cause of:

PR port-evbmips/59236: Multiple segfaults in erlite3 boot
 1.52 04-Oct-2021  andvar branches: 1.52.10;
remove duplicate the article in comments.
 1.51 31-May-2021  simonb Include "opt_param.h" (ifdef _KERNEL_OPT) everywhere that MSGBUFSIZE is
referenced since some sources include <machine/param.h>.
 1.50 23-May-2021  mrg fix "uname -p" on mips n32.

this has been returning "mipsn64eb" on my edgerouter4 with the
32 bit uname binary.

introduce o32, n32, and n64 versions of MACHINE_ARCH, and use
them appropriately in PROC_MACHINE_ARCH32(). now o32, n32 and
n64 "uname -p" all return different values.
 1.49 08-May-2021  skrll branches: 1.49.2;
KNG
 1.48 26-Apr-2021  christos Make MACHINE_ARCH for n64 binaries mipsn64e[bl] instead of mips64e[bl] to
differentiate them from n32/o32 binaries.
 1.47 26-Aug-2020  simonb branches: 1.47.6;
Define a UPAGES_MAX constant to size the a md_upte array in MIPS's
struct mdlwp. This is exposed to userland, so we can't use something
based on PAGE_SIZE.
 1.46 23-Aug-2020  simonb Use a 16kB USPACE (and larger kernel stack) for LP64 kernels. Invert
the logic for setting the USPACE size. Define a desired USPACE size
(16kB for LP64, 8kB otherwise) then divide by PAGE_SIZE to get UPAGES.

Fixes random segmap lossage, since the uarea usually sits immediately
above the segmap for a process. Thanks to mrg@, skrll@ and dholland@
for testing, debugging and general help tracking down this problem.
 1.45 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.44 26-Jul-2020  simonb Add a space in a comment.
 1.43 23-Jul-2020  skrll Add a comment to CACHE_LINE_SIZE / COHERENCY_UNIT size defines
 1.42 23-Jul-2020  skrll On second thoughts this can't be conditional so define CACHE_LINE_SIZE /
COHERENCY_UNIT as 128 for all mips.
 1.41 23-Jul-2020  skrll Define CACHE_LINE_SIZE / COHERENCY_UNIT as 128 for MIPS64_OCTEON
 1.40 19-Jun-2019  skrll Whitespace and whitespace consistency
 1.39 11-May-2019  skrll #define<tab> for consistency
 1.38 11-Jul-2016  matt branches: 1.38.18;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.37 11-Jun-2015  matt Use (uint64_t) to avoid 32-bit overflow
 1.36 11-Jun-2015  matt Don't include <machine/param.h> in .S files, get the needed values from assym.h
Define NBPG as UL to avoid integer over with NBXSEG on LP64 systems.
(.S files don't like numbers with UL appended to them).
 1.35 07-Jun-2015  matt assembly no longer include <machine/cpu.h>. Instead MIPS_CURLWP is gotten
from regdef.h and everything else from assym.h. <mips/mips_param.h> no
longer include <machine/cpu.h>
 1.34 23-May-2013  christos branches: 1.34.10;
add generic copyrights so FreeBSD can use them.
 1.33 01-Feb-2012  matt branches: 1.33.6;
Add ALIGNBYTES32/ALIGN32 for netbsd32.
 1.32 24-Jan-2012  christos Use and define ALIGN() ALIGN_POINTER() and STACK_ALIGN() consistently,
and avoid definining them in 10 different places if not needed.
 1.31 20-Jan-2012  joerg Change CMSG_SPACE and CMSG_LEN to provide Integer Constant Expressions
again. This was changed in sys/socket.h r1.51 to work around fallout
from the IPv6 aux data migration. It broke the historic ABI on some
platforms. This commit restores compatibility for netbsd32 code on such
platforms and provides a template for future changes to the CMSG_*
alignment. Revert PCC/Clang workarounds in postfix and tmux.
 1.30 19-Jan-2012  matt Add ALIGNBYTES32/ALIGN32 (same as ALIGNBYTES/ALIGN).
 1.29 05-Mar-2011  matt branches: 1.29.4; 1.29.8;
If _KERNEL is not defined, force MACHINE to be "mips". Userland should be
using uname/sysctl to get this value.
 1.28 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.27 08-Feb-2010  joerg branches: 1.27.2; 1.27.4; 1.27.6;
Remove separate mb_map. The nmbclusters is computed at boot time based
on the amount of physical memory and limited by NMBCLUSTERS if present.
Architectures without direct mapping also limit it based on the kmem_map
size, which is used as backing store. On i386 and ARM, the maximum KVA
used for mbuf clusters is limited to 64MB by default.

The old default limits and limits based on GATEWAY have been removed.
key_registered_sb_max is hard-wired to a value derived from 2048
clusters.
 1.26 14-Dec-2009  matt branches: 1.26.2;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.25 13-Aug-2009  matt Move MID_MACHINE to <mips/mips_param.h> and use local values so we don't
need to include exec_aout.h
 1.24 09-Aug-2009  matt Beginning of large-page support.
 1.23 28-Aug-2006  yamt branches: 1.23.60; 1.23.78;
- remove unused bdbtofsb.
- move the following macros from MD headers to sys/param.h.
ctod
dtoc
ctob
btoc
dbtob
btodb
 1.22 26-Aug-2006  matt Don't cast pointers using unsigned and/or int. Use intptr_t or uintptr_t
as appropriate.
 1.21 11-Dec-2000  tsutsui branches: 1.21.40; 1.21.54; 1.21.58;
space -> TAB
 1.20 09-Jun-2000  soda make paddr_t 64bit on arc port by introducing _MIPS_PADDR_T_64BIT.
 1.19 27-Mar-2000  nisimura branches: 1.19.2;
Nuke MIPS_16K_PAGE conditional which should be commited in. It
was used for debugg'n purposes which only make senses on particular
hardware configurations and has never been intended to extend pagesize
of NetBSD/mips.
 1.18 19-Feb-2000  mycroft Don't pull in cpu.h in non-kernel code.
 1.17 11-Feb-2000  thorpej Update for the NKMEMPAGES changes.
 1.16 09-Jan-2000  simonb Use the badaddr() prototype in mips/include/cpu.h by including
<machine/cpu.h> in mips/include/mips_param.h. Remove duplicate
badaddr() prototypes from some pmax header files.
 1.15 04-Dec-1999  ragge CL* discarding.
 1.14 25-Sep-1999  shin branches: 1.14.2; 1.14.8;
Changes for NetBSD/hpcmips.

Support VR4100.
Support 16KB page.
Support CPU without FPU.

Fix virtual alias problem(physio() case).

[new options]

options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */
 1.13 24-Apr-1999  simonb Nuke register and remove trailling white space.
 1.12 09-Feb-1999  tv branches: 1.12.4;
Split the "mips" MACHINE_ARCH for 1.4. newsmips is "mipseb"; pmax is
"mipsel".
 1.11 14-Jan-1999  castor * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.10 11-Sep-1998  jonathan Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.

* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.
 1.9 25-Aug-1998  nisimura Make spl(9) rountines target port dependent. delay() is also port
dependent anticipating a target with high resolution timer available
for on-the-fly re-programming. Enum decstation_t was removed from MI
trap.c.
 1.8 19-Feb-1998  thorpej Use a reasonable default for NKMEMCLUSTERS. Previous default value wouldn't
run multi-user for very long at all, and every kernel configuration file
overrides it!
 1.7 20-Sep-1997  leo Move the definition of MSGBUFSIZE up to the machine-arch level if
possible. Pointed out by Bernd Ernesti.
 1.6 20-Aug-1997  jonathan Move SSIZE and DELAY() definitions to sys/arch/mips/include/mips_param.h.
Update comment in pmax/include/param.h (pr 3988).
 1.5 07-Jul-1997  jonathan branches: 1.5.2;
DDB for mips.
Add DDB interface to /sys/arch/mips/mips..
Rework heuristic stack traceback to work with DDB.
Add hooks to print exception log from DDB.
Add hooks from pmax console drivers: call Debugger()
after break from serial console, or 'DO' key from LK-xxx.
 1.4 16-Jun-1997  jonathan Garbage-collect non-jumptable prototype for wbflush().
 1.3 08-Jun-1997  jonathan Move MACHINE_ARCH and _MACHINE_ARCH from pmax/include/param.h to
mips/include/mips_param.h. (They should be common to all mips ports.)
 1.2 28-Feb-1997  jonathan Define ALIGNED_POINTER
(missed when other <arch>/include/param.h files were updated)
 1.1 19-May-1996  jonathan branches: 1.1.8;
Remove common-across-all-MIPS-cpu definitions (e.g., user-level-visible
page/segment size definitions and macros) from pmax/include/param.h,
and move them to mips/include/mips_param.h.
 1.1.8.1 12-Mar-1997  is Merge in changes from Trunk
 1.5.2.2 22-Sep-1997  thorpej Update marc-pcmcia branch from trunk.
 1.5.2.1 23-Aug-1997  thorpej Update marc-pcmcia branch from trunk.
 1.12.4.1 21-Jun-1999  thorpej Sync w/ -current.
 1.14.8.1 27-Dec-1999  wrstuden Pull up to last week's -current.
 1.14.2.2 13-Dec-2000  bouyer Sync with HEAD (for UBC fixes).
 1.14.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.19.2.1 22-Jun-2000  minoura Sync w/ netbsd-1-5-base.
 1.21.58.1 03-Sep-2006  yamt sync with head.
 1.21.54.1 09-Sep-2006  rpaulo sync with head
 1.21.40.1 30-Dec-2006  yamt sync with head.
 1.23.78.13 04-Aug-2012  matt Make MIPS use a multi-level page table for the kernel address space.
(just like the user address does). XXX fix mips1
 1.23.78.12 27-Feb-2012  matt Make sure we don't overflow a 32-bit integer.
 1.23.78.11 27-Dec-2011  matt Deal with not defining PAGE_SIZE or PAGE_SHIFT for non-kernel inclusion.
 1.23.78.10 27-Dec-2011  matt Make these play nice with modules.
 1.23.78.9 23-Dec-2011  matt Use MIPS_PAGE_SHIFT to define the page size to be used from a config file.
Add support for tracking which colors have been used for an EXECPAGE.
 1.23.78.8 03-Dec-2011  matt Add __cacheline_aligned and __read_mostly from -HEAD.
 1.23.78.7 02-Dec-2011  matt Add support for 8KB pages.
 1.23.78.6 16-Aug-2010  matt Support user VAs > 4GB (but less than 1TB for now) using a 3 level page table.
Add debug code to help find redundant faults (PMAP_FAULTINFO).
 1.23.78.5 05-Feb-2010  matt Add __HAVE_FAST_SOFTINTS support.
Add routine to remap an uarea via a direct-mapped address. This avoids
TLB machinations when swtching to/from the softint thread. This can only
be done for lwp which won't exit.
 1.23.78.4 12-Sep-2009  matt Add MACHINE32_ARCH definitions.
 1.23.78.3 07-Sep-2009  matt Derive NBSEG and SEGSHIFT from NBPG and PGSHIFT.
 1.23.78.2 22-Aug-2009  matt Move MACHINE_ARCH definition to <mips/mips_param.h>
Move mbuf related defines to <mips/mips_param.h>
 1.23.78.1 20-Aug-2009  matt Add a default MSIZE/MCLBYTES block here since each mips port does the same
thing.
 1.23.60.2 11-Mar-2010  yamt sync with head
 1.23.60.1 19-Aug-2009  yamt sync with head.
 1.26.2.1 30-Apr-2010  uebayasi Sync with HEAD.
 1.27.6.1 05-Mar-2011  bouyer Sync with HEAD
 1.27.4.1 06-Jun-2011  jruoho Sync with HEAD.
 1.27.2.2 06-Mar-2011  rmind sync with head (and fix few botches with this)
 1.27.2.1 05-Mar-2011  rmind sync with head
 1.29.8.1 18-Feb-2012  mrg merge to -current.
 1.29.4.2 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.29.4.1 17-Apr-2012  yamt sync with head
 1.33.6.2 03-Dec-2017  jdolecek update from HEAD
 1.33.6.1 23-Jun-2013  tls resync from head
 1.34.10.2 05-Oct-2016  skrll Sync with HEAD
 1.34.10.1 22-Sep-2015  skrll Sync with HEAD
 1.38.18.2 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.38.18.1 10-Jun-2019  christos Sync with HEAD
 1.47.6.2 17-Jun-2021  thorpej Sync w/ HEAD.
 1.47.6.1 13-May-2021  thorpej Sync with HEAD.
 1.49.2.1 31-May-2021  cjep sync with head
 1.52.10.1 02-Aug-2025  perseant Sync with HEAD
 1.11 12-Jul-2023  riastradh machine/mutex.h: Sprinkle sys/types.h, omit machine/lock.h.

Turns out machine/lock.h is not needed for __cpu_simple_lock_t, which
always comes from sys/types.h. And, really, sys/types.h (or at least
sys/stdint.h) is needed for uintN_t and uintptr_t.
 1.10 09-Jul-2023  riastradh machine/mutex.h: Sprinkle includes so this can be used by crash(8).

XXX pullup-10
 1.9 25-Aug-2021  thorpej branches: 1.9.4;
- In kern_mutex.c, if MUTEX_CAS() is not defined, define it in terms of
atomic_cas_ulong().
- For arm, ia64, m68k, mips, or1k, riscv, vax: don't define our own
MUTEX_CAS(), as they either use atomic_cas_ulong() or equivalent
(atomic_cas_uint() on m68k).
- For alpha and sparc64, don't define MUTEX_CAS() in terms of their own
_lock_cas(), which has its own memory barriers; the call sites in
kern_mutex.c already have the appropriate memory barrier calls. Thus,
alpha and sparc64 can use default definition.
- For sh3, don't define MUTEX_CAS() in terms of its own _lock_cas();
atomic_cas_ulong() is strong-aliased to _lock_cas(), therefore defining
our own MUTEX_CAS() is redundant.

Per thread:
https://mail-index.netbsd.org/tech-kern/2021/07/25/msg027562.html
 1.8 29-Nov-2019  riastradh Nix now-unused definitions of MUTEX_GIVE/MUTEX_RECEIVE.
 1.7 20-Feb-2011  matt branches: 1.7.56;
Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.6 28-Apr-2008  martin branches: 1.6.22; 1.6.28; 1.6.30;
Remove clause 3 and 4 from TNF licenses
 1.5 04-Jan-2008  ad branches: 1.5.6; 1.5.8; 1.5.10;
Use new style memory barriers.
 1.4 29-Nov-2007  ad branches: 1.4.6;
- Change _lock_cas and friends to do "compare and swap" instead of "compare
and set".
- Rename them to _atomic_cas_uint, _atomic_cas_ulong etc and provide strong
aliases for the other names CAS goes by.
 1.3 21-Nov-2007  yamt make kmutex_t and krwlock_t smaller by killing lock id.
ok'ed by Andrew Doran.
 1.2 09-Feb-2007  ad branches: 1.2.4; 1.2.8; 1.2.24; 1.2.26; 1.2.30; 1.2.32;
Merge newlock2 to head.
 1.1 11-Jan-2007  ad branches: 1.1.2;
file mutex.h was initially added on branch newlock2.
 1.1.2.3 01-Feb-2007  ad Header file cleanup.
 1.1.2.2 27-Jan-2007  ad Make mips systems work.
 1.1.2.1 11-Jan-2007  ad Checkpoint work in progress.
 1.2.32.2 18-Feb-2008  mjf Sync with HEAD.
 1.2.32.1 08-Dec-2007  mjf Sync with HEAD.
 1.2.30.1 21-Nov-2007  bouyer Sync with HEAD
 1.2.26.1 09-Jan-2008  matt sync with HEAD
 1.2.24.2 03-Dec-2007  joerg Sync with HEAD.
 1.2.24.1 21-Nov-2007  joerg Sync with HEAD.
 1.2.8.1 03-Dec-2007  ad Sync with HEAD.
 1.2.4.4 21-Jan-2008  yamt sync with head
 1.2.4.3 07-Dec-2007  yamt sync with head
 1.2.4.2 26-Feb-2007  yamt sync with head.
 1.2.4.1 09-Feb-2007  yamt file mutex.h was added on branch yamt-lazymbuf on 2007-02-26 09:07:27 +0000
 1.4.6.1 08-Jan-2008  bouyer Sync with HEAD
 1.5.10.1 16-May-2008  yamt sync with head.
 1.5.8.1 18-May-2008  yamt sync with head.
 1.5.6.1 02-Jun-2008  mjf Sync with HEAD.
 1.6.30.1 05-Mar-2011  bouyer Sync with HEAD
 1.6.28.1 06-Jun-2011  jruoho Sync with HEAD.
 1.6.22.1 05-Mar-2011  rmind sync with head
 1.7.56.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.9.4.1 09-Aug-2023  martin Pull up following revision(s) (requested by maya in ticket #316):

sys/arch/m68k/include/mutex.h: revision 1.13
sys/arch/arm/include/cpu.h: revision 1.125
sys/arch/sun68k/include/intr.h: revision 1.21
sys/arch/arm/include/mutex.h: revision 1.28
sys/sys/rwlock.h: revision 1.18
sys/arch/powerpc/include/mutex.h: revision 1.7
sys/arch/arm/include/mutex.h: revision 1.29
sys/arch/powerpc/include/mutex.h: revision 1.8
sys/uvm/uvm_param.h: revision 1.42
sys/sys/ksem.h: revision 1.16
sys/arch/x86/include/mutex.h: revision 1.10
sys/sys/proc.h: revision 1.372
sys/sys/ksem.h: revision 1.17
sys/arch/ia64/include/mutex.h: revision 1.8
sys/arch/evbarm/include/intr.h: revision 1.29
sys/sys/lua.h: revision 1.9
sys/arch/next68k/include/intr.h: revision 1.23
sys/arch/ia64/include/mutex.h: revision 1.9
sys/arch/hp300/include/intr.h: revision 1.35
sys/arch/hp300/include/intr.h: revision 1.36
sys/arch/sparc/include/cpu.h: revision 1.111
sys/arch/hppa/include/mutex.h: revision 1.16
sys/arch/vax/include/intr.h: revision 1.31
sys/arch/hppa/include/mutex.h: revision 1.17
sys/arch/news68k/include/intr.h: revision 1.28
sys/arch/hppa/include/mutex.h: revision 1.18
sys/arch/hppa/include/intr.h: revision 1.3
sys/arch/hppa/include/mutex.h: revision 1.19
sys/arch/hppa/include/intr.h: revision 1.4
sys/sys/sched.h: revision 1.92
sys/opencrypto/cryptodev.h: revision 1.51
sys/arch/vax/include/mutex.h: revision 1.20
sys/arch/sparc64/include/mutex.h: revision 1.10
sys/arch/ia64/include/sapicvar.h: revision 1.2
sys/arch/riscv/include/mutex.h: revision 1.5
sys/arch/amiga/dev/grfabs_cc.c: revision 1.39
sys/external/bsd/drm2/include/linux/idr.h: revision 1.11
sys/arch/riscv/include/mutex.h: revision 1.6
sys/ddb/files.ddb: revision 1.16
sys/arch/mac68k/include/intr.h: revision 1.32
share/man/man4/ddb.4: revision 1.203
sys/ddb/db_command.c: revision 1.183
sys/arch/mips/include/mutex.h: revision 1.10
sys/ddb/db_command.c: revision 1.184
sys/arch/x68k/include/intr.h: revision 1.22
sys/arch/sparc/include/psl.h: revision 1.51
sys/arch/or1k/include/mutex.h: revision 1.4
sys/arch/mips/include/mutex.h: revision 1.11
sys/arch/arm/xscale/pxa2x0_intr.h: revision 1.16
sys/arch/sparc64/include/cpu.h: revision 1.134
sys/arch/sparc/include/psl.h: revision 1.52
sys/arch/or1k/include/mutex.h: revision 1.5
sys/arch/mvme68k/include/intr.h: revision 1.22
sys/arch/luna68k/include/intr.h: revision 1.16
external/cddl/osnet/sys/sys/kcondvar.h: revision 1.6
sys/arch/sparc/include/mutex.h: revision 1.12
sys/arch/sparc/include/mutex.h: revision 1.13
sys/arch/usermode/include/mutex.h: revision 1.5
sys/arch/usermode/include/mutex.h: revision 1.6
sys/kern/kern_core.c: revision 1.38
usr.sbin/crash/Makefile: revision 1.49
sys/arch/amiga/include/intr.h: revision 1.23
sys/arch/alpha/include/mutex.h: revision 1.12
sys/arch/alpha/include/mutex.h: revision 1.13
sys/arch/evbarm/lubbock/sacc_obio.c: revision 1.16
sys/ddb/ddb.h: revision 1.6
sys/arch/sparc64/include/mutex.h: revision 1.8
sys/arch/sh3/include/mutex.h: revision 1.12
sys/arch/evbarm/lubbock/sacc_obio.c: revision 1.17
sys/ddb/db_syncobj.c: revision 1.1
sys/arch/vax/include/mutex.h: revision 1.18
sys/arch/sparc64/include/psl.h: revision 1.63
sys/arch/sparc64/include/mutex.h: revision 1.9
sys/arch/sh3/include/mutex.h: revision 1.13
sys/arch/evbarm/lubbock/obio.c: revision 1.13
sys/arch/atari/include/intr.h: revision 1.23
sys/ddb/db_syncobj.c: revision 1.2
sys/arch/vax/include/mutex.h: revision 1.19
sys/arch/evbarm/g42xxeb/obio.c: revision 1.14
sys/arch/evbarm/g42xxeb/obio.c: revision 1.15
sys/arch/cesfic/include/intr.h: revision 1.14
sys/ddb/db_syncobj.h: revision 1.1
sys/arch/x86/include/cpu.h: revision 1.134
sys/arch/evbarm/g42xxeb/obio.c: revision 1.16
sys/arch/cesfic/include/intr.h: revision 1.15
sys/arch/arm/xscale/pxa2x0_intr.c: revision 1.26
sys/sys/cpu_data.h: revision 1.54
sys/arch/m68k/include/mutex.h: revision 1.12
sys/arch/ia64/acpi/madt.c: revision 1.6

sys/rwlock.h: Make this more self-contained for bool.

machine/mutex.h: Sprinkle includes so this can be used by crash(8).

ddb: New `show all tstiles' command.
Shows who's waiting for which locks and what the owner is up to.

Include psl.h for ipl_cookie_t if __MUTEX_PRIVATE

sys: Rip <sys/resourcevar.h> out of <uvm/uvm_param.h>.

And thus out of <sys/param.h>, which is exceedingly overused and
fragile and delenda est.

Should fix (some) issues with the recent inclusion of machine/lock.h
in various machine/mutex.h files.

arm/mutex.h: Need machine/intr.h, machine/lock.h.

For ipl_cookie_t and __cpu_simple_lock_t.
evbarm/intr.h: Define ipl_cookie_t before including ARM_INTR_IMPL.

Otherwise arm/mutex.h doesn't work, due to a cyclic dependency which
should really be fixed.
opencrypto/cryptodev.h: Fix includes.
- Move sys/condvar.h under #ifdef _KERNEL.
- Add some other necessary includes and forward declarations.
- Sort.

hp300/intr.h: Fix missing includes.
linux/idr.h: Need <sys/mutex.h> for kmutex_t.
amiga/intr.h: Don't define spl*() functions if !_KERNEL.

This is used by crash(8) now, and what's important is ipl_cookie_t.
cesfic/intr.h: Expose ipl_cookie_t to userland for crash(8).
cesfic/intr.h: Expose ipl_cookie_t to userland only with _KMEMUSER.

Probably not necessary but let's be a little more cautious about
this.

atari/intr.h: Expose ipl_cookie_t with _KMEMUSER for crash(8).

arm/cpu.h: Need sys/param.h for COHERENCY_UNIT.

Nix machine/param.h -- not meant to be used directly, pulled in by
sys/param.h.

Move the definition of ipl_cookie_t out of the kernel-only sections,
some _KMEMUSER applications need it.

ddb: Cast pointer to uintptr_t first before db_expr_t.

hppa/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

luna68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

mvme68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

news68k/intr.h: Fix includes. Put some definitions under _KERNEL.

next68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

sys/ksem.h: Hack around fstat(8) abuse of _KERNEL.

sun68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

vax/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

x68k/intr.h: Put functions under _KERNEL so crash(8) can use this.

Make ipl_cookie_t visible for _KMEMUSER userland applications.

fix editor mishap in previous

Explicitly include <sys/mutex.h> for kmutex_t.

Replace kmutex_t * (which may be undefined here) with struct kmutex *,
suggested by Taylor.

hp300/intr.h: Put most of this under #ifdef _KERNEL.
Only ipl_cookie_t really needs to be exposed now, for crash(8).

mac68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).
Make inclusion of sys/intr.h explicit for spl*.

fix hppa and vax builds.

machine/lock.h isn't necessary for __cpu_simple_lock_t, it's in
sys/types.h. avoids cpu_data.h vs sched.h include order issues.

move the hppa ipl_t typedef with the moved usage of it.
machine/mutex.h: Sprinkle sys/types.h, omit machine/lock.h.

Turns out machine/lock.h is not needed for __cpu_simple_lock_t, which
always comes from sys/types.h. And, really, sys/types.h (or at least
sys/stdint.h) is needed for uintN_t and uintptr_t.

ddb: Cast pointer to uintptr_t, then to db_expr_t.
Avoids warnings about conversion between pointer and integer of
different size on some architectures.

re-fix hppa builds.

this file uses __cpu_simple_lock(), not just the underlying type,
so it does need machine/lock.h.

Break cycle by using `struct kmutex *' instead of `kmutex_t *'.
sys/sched.h included sys/mutex.h
which includes sys/intr.h
which includes machine/intr.h
which on cats includes arm/footbridge/footbridge_intr.h
which includes arm/cpu.h
which includes sys/cpu_data.h
which includes sys/sched.h

But there was never any real need for sys/mutex.h in sys/sched.h,
because it only uses pointers to the opaque struct kmutex. Cycle
broken by using `struct kmutex *' instead of pulling in sys/mutex.h
for the definition of kmutex_t.

Side effect: This revealed that sys/cpu_data.h needed sys/intr.h
(which was pulled in accidentally by sys/mutex.h via sys/sched.h) for
SOFTINT_COUNT. Also revealed some other machine/cpu.h header files
were missing includes of sys/mutex.h for kmutex_t.

ia64: Need sys/types.h for u_int, vaddr_t; sys/mutex.h for kmutex_t.

explicitly include no longer implicitly included sys/mutex.h.

arm/xscale: Use sys/bitops.h fls32 - 1 instead of 31 - __builtin_clz.
Sidesteps namespace collision with `#define bits ...' in net/zlib.c.

complete the previous - there were two calls to find_first_bit() to fix.

arm/xscale: Missed a spot with previous find_first_bit commit.

evbarm/g42xxeb: Fix off-by-one in previous.

The original find_first_bit(x) was 31 - __builtin_clz((uint32_t)x),
which is equivalent to fls32(x) - 1, not to fls32(x).

Note that fls32 is 1-based and returns 0 for x=0.
 1.7 23-May-2021  mrg fix "uname -p" on mips n32.

this has been returning "mipsn64eb" on my edgerouter4 with the
32 bit uname binary.

introduce o32, n32, and n64 versions of MACHINE_ARCH, and use
them appropriately in PROC_MACHINE_ARCH32(). now o32, n32 and
n64 "uname -p" all return different values.
 1.6 26-Jul-2020  simonb branches: 1.6.6; 1.6.8;
#define<tab>
Nuke trailing whitespace.
 1.5 31-Oct-2017  martin Allow architectures to define a macro PROC_MACHINE_ARCH(P) and
PROC_MACHINE_ARCH32(P) to override the value for sysctl hw.machine_arch
(native and netbsd32 commpat resp.).

Use these for arm and mips instead of the (not working, noisy, in case
of arm) sysctl override and #ifdef __mips__ in architecture neutral
code.
 1.4 17-May-2015  matt machine_arch on mips depends on the ABI so we need a routine to return
the right value.
 1.3 19-Feb-2012  rmind branches: 1.3.2; 1.3.16;
Remove COMPAT_SA / KERN_SA. Welcome to 6.99.3!
Approved by core@.
 1.2 14-Dec-2009  matt branches: 1.2.4; 1.2.14; 1.2.18;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.1 12-Sep-2009  matt branches: 1.1.2;
file netbsd32_machdep.h was initially added on branch matt-nb5-mips64.
 1.1.2.1 12-Sep-2009  matt Add support for COMPAT_NETBSD32
 1.2.18.1 24-Feb-2012  mrg sync to -current.
 1.2.14.1 17-Apr-2012  yamt sync with head
 1.2.4.2 11-Mar-2010  yamt sync with head
 1.2.4.1 14-Dec-2009  yamt file netbsd32_machdep.h was added on branch yamt-nfs-mp on 2010-03-11 15:02:38 +0000
 1.3.16.1 06-Jun-2015  skrll Sync with HEAD
 1.3.2.1 03-Dec-2017  jdolecek update from HEAD
 1.6.8.1 31-May-2021  cjep sync with head
 1.6.6.1 17-Jun-2021  thorpej Sync w/ HEAD.
 1.28 13-Mar-2021  skrll s/pfi_faultpte/&p/ for consistency with arm / other uses of ptep
 1.27 26-Sep-2020  simonb branches: 1.27.2;
Whitespace consistency nit.
 1.26 17-Aug-2020  mrg mostly complete basic port of crash(8) to mips.

tested on mipsel and mips64eb. basic functionality works
on the running kernel, not yet tested on crash dumps.
 1.25 17-Aug-2020  mrg port crash(8) to mips. (most of the kernel side.)

- expose parts of _KERNEL to _KMEMUSER as well
- hide more things for _KERNEL
- avoid DB_MACHINE_COMMANDS in crash(8)
- XXX add mips_label_t for !_KERNEL and use it in the pcb to
avoid conflicting with the ddb/crash one
- enable dumppcb

some changes to make stack trace fail instead of SEGV and
the userland changes to crash itself not part of this change.
 1.24 16-Aug-2011  matt Add support for the MIPS DSP ASE (as a second PCU).
 1.23 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.22 08-Feb-2011  rmind Remove clause 3 (UCB advertising clause) from the University of Utah
copyright. Confirmed by Mike Hibler, mike at cs.utah.edu - thanks!
Also, merge UCB and Utah copyright texts back into one, as they
originally were.

Extra verification by snj@.
 1.21 14-Dec-2009  matt branches: 1.21.4; 1.21.6; 1.21.8;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.20 04-Mar-2007  christos branches: 1.20.44; 1.20.62;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.
 1.19 11-Dec-2005  christos branches: 1.19.26;
merge ktrace-lwp.
 1.18 26-Nov-2003  he branches: 1.18.16;
Hide the register number constants behind an _R_ prefix, and also
rename FPBASE to _FPBASE, so that we avoid polluting the user's
name space when e.g. <sys/ptrace.h> is included. Previously, the
PC symbol in mips/regnum.h would conflict with the declaration of
the external variable by the same name in termcap.h, as discovered
by the ``okheaders'' regression test.
 1.17 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.16 30-Nov-2002  tsutsui branches: 1.16.6;
Fix botch in previous. This is pcb.h, not reg.h.
 1.15 30-Nov-2002  simonb Add multiple-inclusion protection.
 1.14 24-Nov-2002  simonb Move the curpcb and segbase extern decls to cpu.h to better group together
what will need to change for SMP.
Hide 'struct cpu_info' and some macros in #ifdef _KERNEL/#endif.
 1.13 12-Jan-2002  enami Define new macro to access FSR register and use it.
 1.12 16-Oct-2001  uch branches: 1.12.4;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.
 1.11 13-Sep-2000  nisimura branches: 1.11.4;
Introduce 'segbase' global variable to hold the pointer to current
process's segtab, retiring 'pcb_segtab' field from 'struct pcb'.
This would be another MULTIPROCESSOR unfriendly and the necessity
might be eliminated when the way to hold PTE is redesigned.
 1.10 28-Mar-2000  simonb Make declaration of curpcb variable extern.
 1.9 16-Jan-1999  nisimura branches: 1.9.8;
- User mode context held with pcb_regs[38] in 'struct pcb' was relocated
at the very bottom of process kernel stack. The address is pointed with
'curproc->p_md.md_regs'.
- Define 'struct md_coredump'.
 1.8 14-Jan-1999  castor * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.7 15-Jun-1997  mhitch branches: 1.7.12;
From Toru Nishimura: user pcb/proc changes for exception handling and
removing access through UADDR.
 1.6 19-Mar-1996  jonathan Change "pmax" -> "mips" before moving to sys/arch/mips/include.
 1.5 18-Jan-1995  mellon Make pcb_regs structure compatible with Ultrix
 1.4 26-Oct-1994  cgd new RCS ID format.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.7.12.1 19-Nov-1998  nisimura - Forgot to commit many files for vm_offset_t purge last Monday.
 1.9.8.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.11.4.2 11-Feb-2002  jdolecek Sync w/ -current.
 1.11.4.1 10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.12.4.3 11-Dec-2002  thorpej Sync with HEAD.
 1.12.4.2 28-Feb-2002  nathanw Catch up to -current.
 1.12.4.1 16-Oct-2001  nathanw file pcb.h was added on branch nathanw_sa on 2002-02-28 04:10:43 +0000
 1.16.6.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.16.6.2 18-Sep-2004  skrll Sync with HEAD.
 1.16.6.1 03-Aug-2004  skrll Sync with HEAD
 1.18.16.1 03-Sep-2007  yamt sync with head.
 1.19.26.1 12-Mar-2007  rmind Sync with HEAD.
 1.20.62.5 16-Aug-2010  matt fix a typo and add a few missing ifdefs.
Only worry about setting seg0tab if the faulting va would use it.
 1.20.62.4 16-Aug-2010  matt Support user VAs > 4GB (but less than 1TB for now) using a 3 level page table.
Add debug code to help find redundant faults (PMAP_FAULTINFO).
 1.20.62.3 15-Feb-2010  matt Put pcb_context first since it has the most interesting data (easier to
dump in debugger).
 1.20.62.2 07-Sep-2009  matt pcb_context is a label_t so use label_t as its type.
 1.20.62.1 20-Aug-2009  matt u_int32_t -> uint32_t
 1.20.44.1 11-Mar-2010  yamt sync with head
 1.21.8.2 05-Mar-2011  bouyer Sync with HEAD
 1.21.8.1 17-Feb-2011  bouyer Sync with HEAD
 1.21.6.1 06-Jun-2011  jruoho Sync with HEAD.
 1.21.4.1 05-Mar-2011  rmind sync with head
 1.27.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.10 16-Aug-2022  skrll Provide pci_intr_setattr
 1.9 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.8 29-Mar-2014  christos make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.
 1.7 04-Apr-2011  dyoung branches: 1.7.4; 1.7.14; 1.7.18;
Neither pci_dma64_available(), pci_probe_device(), pci_mapreg_map(9),
pci_find_rom(), pci_intr_map(9), pci_enumerate_bus(), nor the match
predicate passed to pciide_compat_intr_establish() should ever modify
their pci_attach_args argument, so make their pci_attach_args arguments
const and deal with the fallout throughout the kernel.

For the most part, these changes add a 'const' where there was no
'const' before, however, some drivers and MD code used to modify
pci_attach_args. Now those drivers either copy their pci_attach_args
and modify the copy, or refrain from modifying pci_attach_args:

Xen: according to Manuel Bouyer, writing to pci_attach_args in
pci_intr_map() was a leftover from Xen 2. Probably a bug. I
stopped writing it. I have not tested this change.

siside(4): sis_hostbr_match() needlessly wrote to pci_attach_args.
Probably a bug. I use a temporary variable. I have not tested this
change.

slide(4): sl82c105_chip_map() overwrote the caller's pci_attach_args.
Probably a bug. Use a local pci_attach_args. I have not tested
this change.

viaide(4): via_sata_chip_map() and via_sata_chip_map_new() overwrote the
caller's pci_attach_args. Probably a bug. Make a local copy of the
caller's pci_attach_args and modify the copy. I have not tested
this change.

While I'm here, make pci_mapreg_submap() static.

With these changes in place, I have tested the compilation of these
kernels:

alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-eb NSLU2
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE GUMSTIX
HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321 IXDP425 IXM1200
KUROBOX_PRO LUBBOCK MARVELL_NAS NAPPI SHEEVAPLUG SMDK2800 TEAMASA_NPWR
TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sgimips GENERIC32_IP2x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

As of Sun Apr 3 15:26:26 CDT 2011, I could not compile these kernels
with or without my patches in place:

### evbmips-el GDIUM

nbmake: nbmake: don't know how to make /home/dyoung/pristine-nbsd/src/sys/arch/mips/mips/softintr.c. Stop

### evbarm-el MPCSA_GENERIC
src/sys/arch/evbarm/conf/MPCSA_GENERIC:318: ds1672rtc*: unknown device `ds1672rtc'

### ia64 GENERIC

/tmp/genassym.28085/assym.c: In function 'f111':
/tmp/genassym.28085/assym.c:67: error: invalid application of 'sizeof' to incomplete type 'struct pcb'
/tmp/genassym.28085/assym.c:76: error: dereferencing pointer to incomplete type

### sgimips GENERIC32_IP3x

crmfb.o: In function `crmfb_attach':
crmfb.c:(.text+0x2304): undefined reference to `ddc_read_edid'
crmfb.c:(.text+0x2304): relocation truncated to fit: R_MIPS_26 against `ddc_read_edid'
crmfb.c:(.text+0x234c): undefined reference to `edid_parse'
crmfb.c:(.text+0x234c): relocation truncated to fit: R_MIPS_26 against `edid_parse'
crmfb.c:(.text+0x2354): undefined reference to `edid_print'
crmfb.c:(.text+0x2354): relocation truncated to fit: R_MIPS_26 against `edid_print'
 1.6 14-Dec-2009  matt branches: 1.6.4; 1.6.6;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.5 09-Aug-2009  matt s/struct device */device_t /;g
 1.4 11-Dec-2005  christos branches: 1.4.78; 1.4.96;
merge ktrace-lwp.
 1.3 29-Jul-2004  drochner remove now unnecessary "pci_enumerate_bus" definitions
 1.2 15-May-2002  thorpej branches: 1.2.6; 1.2.12;
Let machine-dependent code specify how to enumerate the bus.
Currently, everyone uses pci_enumerate_bus_generic().
 1.1 18-Mar-2002  simonb branches: 1.1.4;
Generic PCI/ISA machdep headers for mips; copied from the algor port.
 1.1.4.3 20-Jun-2002  nathanw Catch up to -current.
 1.1.4.2 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.1.4.1 18-Mar-2002  nathanw file pci_machdep.h was added on branch nathanw_sa on 2002-04-01 07:40:59 +0000
 1.2.12.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.2.12.2 18-Sep-2004  skrll Sync with HEAD.
 1.2.12.1 03-Aug-2004  skrll Sync with HEAD
 1.2.6.2 23-Jun-2002  jdolecek catch up with -current on kqueue branch
 1.2.6.1 15-May-2002  jdolecek file pci_machdep.h was added on branch kqueue on 2002-06-23 17:38:02 +0000
 1.4.96.3 23-Dec-2011  matt Add conditional support for __PCI_BUS_DEVORDER, __HAVE_PCI_CONF_HOOK, and
__PCI_DEV_FUNCORDER (new).
 1.4.96.2 13-Sep-2009  cliff #ifdef to protect against recursive #include
 1.4.96.1 16-Aug-2009  matt Kill use of _MIPS_BSD_ABI - switch to __mips_<abi>
Use device_t where appropriate.
Remove magic numbers.
 1.4.78.2 11-Mar-2010  yamt sync with head
 1.4.78.1 19-Aug-2009  yamt sync with head.
 1.6.6.1 06-Jun-2011  jruoho Sync with HEAD.
 1.6.4.1 21-Apr-2011  rmind sync with head
 1.7.18.1 18-May-2014  rmind sync with head
 1.7.14.1 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.7.4.1 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.77 26-Oct-2022  skrll MI PMAP hardware page table walker support.

This is based on code given to me by Matt Thomas a long time ago with
many updates and bugs fixes from me.
 1.76 04-Jan-2022  skrll consistency. NFCI.
 1.75 20-Dec-2020  skrll Support __HAVE_PMAP_PV_TRACK in sys/uvm/pmap based pmaps (aka common pmap)
 1.74 17-Aug-2020  mrg branches: 1.74.2;
port crash(8) to mips. (most of the kernel side.)

- expose parts of _KERNEL to _KMEMUSER as well
- hide more things for _KERNEL
- avoid DB_MACHINE_COMMANDS in crash(8)
- XXX add mips_label_t for !_KERNEL and use it in the pcb to
avoid conflicting with the ddb/crash one
- enable dumppcb

some changes to make stack trace fail instead of SEGV and
the userland changes to crash itself not part of this change.
 1.73 07-Aug-2020  skrll Provide a pmap_segtab_deactivate for symmetry with pmap_segtab_activate
and use it in pmap_deactivate

Call pmap_md_xtab_{,de}activate from pmap_segtab_{,de}activate to be used
for PMAP_HWPAGEWALKER and any caches ops that might be required.

Provide empty (for now) pmap_md_xtab_{,de}activate functions on the
platforms that use sys/uvm/pmap
 1.72 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.71 01-Apr-2019  msaitoh s/adddress/address/
 1.70 24-Jul-2017  mrg branches: 1.70.4;
mostly converted sbmips -> evbmips. the SBMIPS kernel builds fully
sans disksubr.c. intr.h does not need any additional fixes now,
only disklabel.h.

also test-built some other mips kernels.
 1.69 23-Dec-2016  cherry branches: 1.69.8;
"Make NetBSD great again!"

Introduce uvm_hotplug(9) to the kernel.

Many thanks, in no particular order to:

TNF, for funding the project.

Chuck Silvers - for multiple API reviews and feedback.
Nick Hudson - for testing on multiple architectures and bugfix patches.
Everyone who helped with boot testing.

KeK (http://www.kek.org.in) for hosting the primary developers.
 1.68 11-Jul-2016  matt branches: 1.68.2;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.67 11-Jun-2015  matt Define (but not use) separate kernel and user pagetables.
Move to the new names.
 1.66 11-Jun-2015  matt Add struct pmap_limits and pm_{min,max}addr from uvm/pmap/map.h and use it to
store avail_start, avail_end, virtual_start, and virtual_end.
Remove iospace and let emips just bump pmap_limits.virtual_start to get the
VA space it needs.
pmap_segtab.c is almost identical to uvm/pmap/pmap_segtab.c now. It won't
be long until we switch to the uvm/pmap one.
 1.65 10-Jun-2015  matt Transition from __cpuset_t to kcpuset_t *. This brings the local pmap one
step closer to uvm/pmap, its eventual replacement. Tested on ERLITE MP kernel.
 1.64 07-Jun-2015  matt assembly no longer include <machine/cpu.h>. Instead MIPS_CURLWP is gotten
from regdef.h and everything else from assym.h. <mips/mips_param.h> no
longer include <machine/cpu.h>
 1.63 11-May-2014  skrll branches: 1.63.4;
Deal with incompatible cache aliases. Specifically,

- always flush an ephemeral page on unmap
- track unmanaged mappings (mappings entered via pmap_kenter_pa) for
aliases where required and handle appropriately (via pmap_enter_pv)

Hopefully this (finally) addresses the instability reported in the
following PRs:

PR/44900 - R5000/Rm5200 mips ports are broken
PR/46890 - upcoming NetBSD 6.0 release is very unstable / unusable on cobalt qube 2
PR/48628 - cobalt and hpcmips ports are dead
 1.62 05-Jul-2012  matt branches: 1.62.2; 1.62.4; 1.62.12;
Change lockless segtab management to use a mutex for protection. Some minor
changes to make this closer to common/pmap/tlb/pmap_segtab.c
 1.61 22-Sep-2011  macallan branches: 1.61.2; 1.61.8;
support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory and
DMA buffers with cacheing disabled but things like write combining, relaxed
ordering etc. allowed when the CPU supports it
so far enabled only on Loongson, should work on R1xk and probably newer CPUs
 1.60 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.59 14-Nov-2010  uebayasi branches: 1.59.2; 1.59.4;
Move struct vm_page_md definition from vmparam.h to pmap.h, because
it's used only by pmap. vmparam.h has definitions for wider
audience.

All GENERIC kernels build tested, except ia64.

powerpc/include/booke/vmparam.h has one too, but it has no pmap.h,
so it's left as is.
 1.58 06-Jul-2010  cegger Turn PMAP_NOCACHE into MI flag.
Add MI flags PMAP_WRITE_COMBINE, PMAP_WRITE_BACK, PMAP_NOCACHE_OVR.
Update pmap(9) manpage.

hppa: Remove MD PMAP_NOCACHE flag as it exists as MI flag
mips: Rename MD PMAP_NOCACHE to PGC_NOCACHE.

x86: Implement new MI flags using Page-Attribute Tables.
x86: Implement BUS_SPACE_MAP_PREFETCHABLE.

Patch presented on tech-kern@:
http://mail-index.netbsd.org/tech-kern/2010/06/30/msg008458.html

No comments on this last version.
 1.57 14-Dec-2009  matt branches: 1.57.2; 1.57.4;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.56 29-Jun-2009  tsutsui Since pmap.c rev 1.163, page attributes of PV_MODIFIED and PV_REFERENCED
have beem moved from pv_flags in struct pv_entry to pvh_attrs in
struct vm_page_md, so no need to copy pv_flags to keep these flags
in pv header in pmap_remove_pv(). Pointed out by uebayasi@ on port-mips.
Also rename those page attribute flags from PV_FOO to PGA_FOO like alpha.
While here, make pv_flags unsigned.

Briefly tested on sgimips O2.
 1.55 09-Dec-2008  pooka Make pmap_kernel() a MI macro for struct pmap *kernel_pmap_ptr,
which is now the "API" provided by the pmap module. pmap_kernel()
remains as the syntactic sugar.

Bonus cosmetics round: move all the pmap_t pointer typedefs into
uvm_pmap.h.

Thanks to Greg Oster for providing cpu muscle for doing test builds.
 1.54 26-Dec-2007  ad branches: 1.54.6; 1.54.10; 1.54.16; 1.54.18; 1.54.26;
Merge more changes from vmlocking2, mainly:

- Locking improvements.
- Use pool_cache for more items.
 1.53 17-Oct-2007  garbled branches: 1.53.2; 1.53.4; 1.53.8;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.52 17-Jul-2007  macallan branches: 1.52.10;
if we have 64bit paddr_t add a flag which indicates non-cachable for use
with mmap*() and pmap_enter()
Mainly for allowing userland to mmap() the O2's framebuffer uncached
 1.51 16-Jul-2007  macallan change pmap_phys_address()s parameter to paddr_t since that's what it gets
fed from mmap*() anyway
approved by gimpy
 1.50 16-Feb-2006  perry branches: 1.50.24; 1.50.32;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.
 1.49 24-Dec-2005  perry branches: 1.49.2; 1.49.4; 1.49.6;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.
 1.48 11-Dec-2005  christos merge ktrace-lwp.
 1.47 26-Mar-2005  tsutsui branches: 1.47.2;
Add a workaround to handle virtual alias which may cause data corruption
on R5000/Rm52xx machines:
- Add a new global variable mips_cache_virtual_alias in mips/cache.c,
which indicates that VIPT cache on the CPU could cause virtual alias
and software support is required to handle it. (i.e. no VCED/VCEI)
- Add several cache flush/invalidate ops around KSEG0 access which
might cause virtual alias if mips_cache_virtual_alias is true.
(note checking mips_sdcache_line_size isn't valid for R5000/Rm52xx
because only R4000/R4400 with L2 cache have VCED/VCEI)
- Remove a global variable mips_sdcache_forceinv, which is now superseded
by new mips_cache_virtual_alias.

While here, also change some R4000/R4400 cache ops:
- Don't override mips_cache_alias_mask and mips_cache_prefer_mask with
values based on MIPS3_MAX_PCACHE_SIZE for R4000/R4400 with L2 cache
because it's still worth to reduce VCED/VCEI.
- Flush dcache in pmap_zero_page(9) unconditionally on all MIPS_HAS_R4K_MMU
CPUs and remove cache flush code from cpu_lwp_fork() in vm_machdep.c.

Thanks to Markus W Kilbinger for testing patches on port-cobalt/port-mips.


XXX This fix is just a workaround because it doesn't handle all possible
XXX virtual aliases. As discussed on port-mips, maybe the real fix
XXX for virtual alias is to change MI UVM to adapt it to VIPT cache.
XXX (all VA mappings against the same PA must have the same VAC index etc.)
 1.46 17-Jan-2005  atatat branches: 1.46.2; 1.46.6;
Teach mips pmap_prefer() to deal with topdown.

Tested by simonb.
 1.45 17-Jan-2005  atatat Convert the PMAP_PREFER() macro from two arguments (offset and hint)
to four (adding size and direction).

In order for topdown uvm to be an option on ports using PMAP_PREFER,
they will need to "prefer" lower addresses if topdown is being used.
Additionally, at least one port also needs to know the size.
 1.44 07-Aug-2003  agc branches: 1.44.8;
Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.43 09-Apr-2003  thorpej branches: 1.43.2;
Cast the arg to MIPS_KSEG0_TO_PHYS() in POOL_VTOPHYS() (thanks, nathan!).
 1.42 09-Apr-2003  thorpej Add the ability for pool caches to cache the physical address of
objects. Clients of the pool_cache API must consistently use
the "paddr" variants or not, otherwise behavior is undefined.

Enable this on Alpha, ARM, MIPS, and x86. Other platforms must
define POOL_VTOPHYS() in the appropriate manner in order to enable
the feature.

Part 1 of a series of simple patches contributed by Wasabi Systems
to improve network performance.
 1.41 30-Nov-2002  simonb Standardise on #ifdef _MIPS_<header>_H_ for multiple inclusion tests.
 1.40 22-Sep-2002  chs it really helps to get the stub right before cutting + pasting it 27 times.
alas, I did not. doh.
 1.39 22-Sep-2002  chs add pmap_remove_all() hook (empty on most platforms so far).
 1.38 05-Mar-2002  simonb Add support for MIPS32 and MIPS64 architectures:
Better cache coherency attribute macros (from Broadcom Corp).
 1.37 10-Sep-2001  chris branches: 1.37.4;
Update pmap_update to now take the updated pmap as an argument.
This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.

Currently this is a no-op on most platforms, so they should see no difference.

Reviewed by Jason.
 1.36 04-Aug-2001  chs branches: 1.36.2;
remove the uncached idle-loop page zeroing.
(to be replaced by a version that uses the cache...)
 1.35 26-May-2001  chs branches: 1.35.2;
replace vm_page_t with struct vm_page *.
 1.34 26-May-2001  chs replace {simple_,}lock{_data,}_t with struct {simple,}lock {,*}.
 1.33 22-Apr-2001  thorpej Undo a misguided previous change to the pmap_update() API.
 1.32 22-Apr-2001  thorpej Give pmap_update() an argument (a pmap_t) so that it knows which
pmap it should be updating.
 1.31 21-Apr-2001  thorpej #define away pmap_update() in <machine/pmap.h> so that no function
call overhead is incurred as we start sprinkling pmap_update() calls
throughout the source tree (no pmaps currently defer operations, but
we are adding the infrastructure to allow them to do so).
 1.30 25-Dec-2000  nisimura branches: 1.30.2;
- fix typos in mips_user_cacheflush() and mips_user_cachectl().
- relocate those function declarations from include/pmap.h.
 1.29 21-Sep-2000  thorpej Make PMAP_PAGEIDLEZERO() return a boolean value. FALSE indidcates
that the page being zero'd was not completed and that page zeroing
should be aborted. This may be used by machine-dependent code doing
slow page access to reduce the latency of running a process that has
become runnable while in the middle of doing a slow page zero.
 1.28 28-Apr-2000  soren Zero free pages in the idle loop.
 1.27 18-May-1999  nisimura branches: 1.27.2;
- Move MachSetPID(1) call to pmap_bootstrap() adajacent to kernel pmap
initialization code.
- Abandon mips_init_proc0() and do the 4 lines straightly in MD mach_init().
- Restore a block of code accidentally lost in prevous commit.
- Change the term 'tlbpid' to a MIPS3 nomenclature 'asid'.
- Hide PTE size exposures by symbolic names in locore.S
 1.26 24-Apr-1999  simonb Nuke register and remove trailling white space.
 1.25 26-Feb-1999  is branches: 1.25.4;
MIPS part of fix for PR 6152, sligtly changed from M.Hitch's version
 1.24 18-Jan-1999  castor Remove vestiges of cpuarch.h. Revert to using cpuregs.h instead.
 1.23 14-Jan-1999  castor * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.22 06-Jan-1999  nisimura - Complete vm_offset_t purge for mips processor.
- bzero() -> memset() and bcopy() -> memcpy().
- Garbage collection in trap.c and db_interface.c.
 1.21 29-Nov-1998  jonathan Add PV_REFERENCED and track as for PV_MODIFIED,.

UVM relies on pmap modules keeping track of modified/referenced bits
after a page has been removed from all mappings. So *dont* clear
PV_REFERENCED or PV_MODIFIED flags in pmap_remove().
 1.20 15-Nov-1998  mhitch Change page modification emulation: don't fiddle with VM flags directly.
Track page modification status in the PV entry like the alpha, and let
pmap_is_modified() return current status back to the VM system. UVM now
works reliably.

Garbage collect the old pmap_attribute[] stuff.
 1.19 26-Jul-1998  simonb branches: 1.19.4;
Fix typo with new poolpage stuff
 1.18 24-Jul-1998  thorpej Provide PMAP_{,UN}MAP_POOLPAGE().
 1.17 25-Feb-1998  thorpej Implement and switch to MACHINE_NEW_NONCONTIG.
 1.16 03-Jan-1998  thorpej Now that all ports have pmap_activate(), and it has an identical interface,
prototype it in <vm/pmap.h>
 1.15 09-Aug-1997  jonathan mips pmap_activate:
* prototype and definition for pmap_activate(p). Updates the segtab,
and changes the active ASID if p == curproc.
* Make reserved fixed-address (UADDR) kernelstack PTEs global,
so we still have a kernel stack after pmap_activate() on curproc.
* make KSEG2 mappings for p_addr global (see above.)

Seems to detune contextswitch and NTP resolution (by 60 ms), but
thepmap_activate() interface is mandatory. Needs more thought.
 1.14 29-Jul-1997  mhitch branches: 1.14.2;
Resident count in pmap is now valid. I can now see RSS in ps.
 1.13 16-Jun-1997  jonathan Yet more mips1/mips3 merging:

Move mips-specific pmap definitions (PMAP_PREFER for mips3, declaratin
of pmap_bootstrap() for the system-specific machdep.c) from
arch/pmax/include/pmap.h to arch/mips/include/pmap.h.
 1.12 09-Jun-1997  jonathan Add sys_sysarch() calls for the standard mips userspace cache-control calls.
 1.11 18-May-1997  mhitch Eliminate vm_pmap.
 1.10 16-May-1997  gwr Add #define __VM_PMAP_HACK as a temporary measure.
 1.9 19-Mar-1996  jonathan Change "pmax_xxx" macros to "mips_xxx" macros, in preparation
for moving to src/sys/arch/mips/include/pmap.h.
 1.8 12-Apr-1995  mellon Use _KERNEL, not KERNEL
 1.7 10-Apr-1995  mycroft Bring back pmap_kernel(), for now always inlined as a pointer to
kernel_pmap_store.
 1.6 28-Mar-1995  jtc KERNEL -> _KERNEL
 1.5 26-Oct-1994  cgd new RCS ID format.
 1.4 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.3 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.2 15-Oct-1993  deraadt update from rick, tarfile of Oct 11 10:46
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.14.2.1 23-Aug-1997  thorpej Update marc-pcmcia branch from trunk.
 1.19.4.4 06-Dec-1998  drochner pull up 1.21 - PV_REFERENCED
 1.19.4.3 16-Nov-1998  nisimura - Step forward to MIPS64 support. Incorporate partially Caster Fu's
patches. Still some work is missing to satisfy his QED 5230 port.

- More symbolic definitions in genassym.cf which improve possible 64bit-ness
of locore_mips{1,3}.S.

- Fix mips3 L1 cache line size detection logic in cpuarch.h as pointed by
Caster.

- Fix a bug in proc_trampoline() code in locore_mips3.S as pointed by Caster.

- Replace vm_offset_t with vaddr_t/paddr_t entirely. Note that
NetBSD/newsmips has purged vm_offset_t too.

- Synchronize various files according to recent changes made in main trunk.
 1.19.4.2 15-Nov-1998  drochner sync to trunk (page modified bit handling, needed for UVM)
 1.19.4.1 15-Oct-1998  nisimura - cpuregs.h was modifed a bit, then renamed with cpuarch.h.
- mips_cpu.h has gone.
- CPU's register mnemonics in regdef.h is now a part of asm.h.
 1.25.4.1 21-Jun-1999  thorpej Sync w/ -current.
 1.27.2.3 23-Apr-2001  bouyer Sync with HEAD.
 1.27.2.2 05-Jan-2001  bouyer Sync with HEAD
 1.27.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.30.2.1 21-Jun-2001  nathanw Catch up to -current.
 1.35.2.4 10-Oct-2002  jdolecek sync kqueue with -current; this includes merge of gehenna-devsw branch,
merge of i386 MP branch, and part of autoconf rototil work
 1.35.2.3 16-Mar-2002  jdolecek Catch up with -current.
 1.35.2.2 13-Sep-2001  thorpej Update the kqueue branch to HEAD.
 1.35.2.1 25-Aug-2001  thorpej Merge Aug 24 -current into the kqueue branch.
 1.36.2.1 01-Oct-2001  fvdl Catch up with -current.
 1.37.4.4 11-Dec-2002  thorpej Sync with HEAD.
 1.37.4.3 18-Oct-2002  nathanw Catch up to -current.
 1.37.4.2 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.37.4.1 10-Sep-2001  nathanw file pmap.h was added on branch nathanw_sa on 2002-04-01 07:40:59 +0000
 1.43.2.5 01-Apr-2005  skrll Sync with HEAD.
 1.43.2.4 17-Jan-2005  skrll Sync with HEAD.
 1.43.2.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.43.2.2 18-Sep-2004  skrll Sync with HEAD.
 1.43.2.1 03-Aug-2004  skrll Sync with HEAD
 1.44.8.1 29-Apr-2005  kent sync with -current
 1.46.6.1 21-Nov-2005  tron Pull up following revision(s) (requested by tsutsui in ticket #961):
sys/arch/mips/mips/cache.c: revision 1.27
sys/arch/mips/include/cache.h: revision 1.8
sys/arch/mips/mips/pmap.c: revision 1.158
sys/arch/mips/mips/vm_machdep.c: revision 1.106
sys/arch/mips/mips/mem.c: revision 1.30
sys/arch/mips/include/pmap.h: revision 1.47
Add a workaround to handle virtual alias which may cause data corruption
on R5000/Rm52xx machines:
- Add a new global variable mips_cache_virtual_alias in mips/cache.c,
which indicates that VIPT cache on the CPU could cause virtual alias
and software support is required to handle it. (i.e. no VCED/VCEI)
- Add several cache flush/invalidate ops around KSEG0 access which
might cause virtual alias if mips_cache_virtual_alias is true.
(note checking mips_sdcache_line_size isn't valid for R5000/Rm52xx
because only R4000/R4400 with L2 cache have VCED/VCEI)
- Remove a global variable mips_sdcache_forceinv, which is now superseded
by new mips_cache_virtual_alias.
While here, also change some R4000/R4400 cache ops:
- Don't override mips_cache_alias_mask and mips_cache_prefer_mask with
values based on MIPS3_MAX_PCACHE_SIZE for R4000/R4400 with L2 cache
because it's still worth to reduce VCED/VCEI.
- Flush dcache in pmap_zero_page(9) unconditionally on all MIPS_HAS_R4K_MMU
CPUs and remove cache flush code from cpu_lwp_fork() in vm_machdep.c.
Thanks to Markus W Kilbinger for testing patches on port-cobalt/port-mips.
XXX This fix is just a workaround because it doesn't handle all possible
XXX virtual aliases. As discussed on port-mips, maybe the real fix
XXX for virtual alias is to change MI UVM to adapt it to VIPT cache.
XXX (all VA mappings against the same PA must have the same VAC index etc.)
 1.46.2.1 26-Mar-2005  yamt sync with head.
 1.47.2.2 21-Jan-2008  yamt sync with head
 1.47.2.1 03-Sep-2007  yamt sync with head.
 1.49.6.1 22-Apr-2006  simonb Sync with head.
 1.49.4.1 09-Sep-2006  rpaulo sync with head
 1.49.2.1 18-Feb-2006  yamt sync with head.
 1.50.32.1 03-Oct-2007  garbled Sync with HEAD
 1.50.24.2 20-Aug-2007  ad Sync with HEAD.
 1.50.24.1 15-Jul-2007  ad Get pmax working.
 1.52.10.2 09-Jan-2008  matt sync with HEAD
 1.52.10.1 06-Nov-2007  matt sync with HEAD
 1.53.8.1 02-Jan-2008  bouyer Sync with HEAD
 1.53.4.1 04-Dec-2007  ad Pull the vmlocking changes into a new branch.
 1.53.2.1 18-Feb-2008  mjf Sync with HEAD.
 1.54.26.28 08-Aug-2012  matt Fix some LP64 bugs
 1.54.26.27 04-Aug-2012  matt Make MIPS use a multi-level page table for the kernel address space.
(just like the user address does). XXX fix mips1
 1.54.26.26 09-Jul-2012  matt Use a spinlock to protect the segtab queues. Use union pmap_segmap and
pmap_segmap_t to track -HEAD. Use KERNEL_PID for the same reason.
 1.54.26.25 27-Feb-2012  matt Add a page-table-page cache to keep reuse just released page table tables.
Actually remove the addresses in pmap_remove_all.
 1.54.26.24 16-Feb-2012  matt Move the ksegx tlb init code into its own function.
Fix a problem with concurrent shootdowns by tracking what cpus want a
shootdown for a pmap, and if anoter cpu wants a shootdown, perform the
shootdown on ourselves.
 1.54.26.23 19-Jan-2012  matt When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses. There are exceptions.
bus_space_handles are now register_t instead of intptr_t. This allows them
to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address. This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs. If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.
 1.54.26.22 27-Dec-2011  matt Deal with not defining PAGE_SIZE or PAGE_SHIFT for non-kernel inclusion.
 1.54.26.21 27-Dec-2011  matt Make these play nice with modules.
 1.54.26.20 23-Dec-2011  matt Split syncicache functions into separate file: pmap_syncicache.
Support up to 1024 ASIDs.
Always use atomic ops for manipulating pm_shootdown_pending
Nuke PMAP_POOLPAGE_DEBUG
defparam MIPS_PAGE_SHIFT
Track colors of execpages.
 1.54.26.19 03-Dec-2011  matt Rework things a bit for the XLR/XLS/XLP TLB. Before dealing with the TLB when
MP on the XL?, disable interrupts and take out a lock to prevent concurrent
updates to the TLB. In the TLB miss and invalid exception handlers, if the
lock is already owned by another CPU, simply return from the exception and
let it continue or restart as appropriate. This prevents concurrent TLB
exceptions in multiple threads from possibly updating the TLB multiple times
for a single address.
 1.54.26.18 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.54.26.17 05-Feb-2011  cliff - protect option includes ("opt_multiprocessor.h") with #ifdef _KERNEL_OPT
 1.54.26.16 05-Feb-2011  cliff - include opt_multiprocessor.h for explicit MULTIPROCESSOR dependency
 1.54.26.15 22-Dec-2010  matt Add a pmap_asid_check which verifies the current ASID is in COP0 ENTRY_HI
 1.54.26.14 16-Aug-2010  matt Support user VAs > 4GB (but less than 1TB for now) using a 3 level page table.
Add debug code to help find redundant faults (PMAP_FAULTINFO).
 1.54.26.13 04-May-2010  matt Add pm_flags and PMAP_DEFERRED_ACTIVATE
 1.54.26.12 11-Mar-2010  matt Add MP-aware icache support.
 1.54.26.11 27-Feb-2010  matt Add mipsXX_tlb_enter which modifies/sets a specific TLB entry with a new
mapping (useful for wired TLB entries).
Add mips_fixup_exceptions which will walk through the exception vectors
and allows the fixup of any cpu_info references to be changed to a more
MP-friendly incarnation.
Define a common fixup method to use a wired TLB entry at -PAGE_SIZE allowing
direct loads using a negative based from the zero register.
Change varible pmap_tlb_info t pmap_tlb0_info.
 1.54.26.10 25-Feb-2010  matt Make the UP and MP ASID allocation algorithm common. Significantly improve
the algorithm. Now when we exhaust the ASIDs, interrogate the TLB for active
ASIDS and release all the other for future allocations. This leaves the
TLB entries with ASIDs valid avoiding the need to re-incur TLB misses for
them.
 1.54.26.9 23-Feb-2010  matt Make sure <mips/locore.h> is not included by MI code.
Add send_ipi and cpu_offline_md hooks to locoresw.
Add MP support to pmap (pvlist locking, tlb locking).
Add TLB shootdown support (see comment at the top of mips/pmap_tlb.c).
Add mipsXX_tlb_invalidate_globals routine
 1.54.26.8 26-Jan-2010  matt Revamp pmap. Add exec page caching logic from powerpc oea pmap. Shrink struct
vm_page by placing the first pv_entry in it. Remove pv_flags since nothing
really needed it. Add pmap counters. Rework virtual cache alias logic.
Allow pmap_copy_page and pmap_zero_page to deal with non-KSEG0 mappable pages.
 1.54.26.7 22-Jan-2010  matt Seperate the pmap TLB functions into their own file.
For 32 bit kernels, make sure that mips_virtual_end doesn't go past
VM_MAX_KERNEL_ADDRESS.
 1.54.26.6 20-Jan-2010  matt Revamp things a bit. Move of the globals mips uses into either cpu_info,
mips_options, or mips_cache_info. Make MALT64 be able to boot MULTIPROCESSOR.
(some pmap MP work).
 1.54.26.5 15-Jan-2010  matt Get rid of most of the studly caps.
First to MULTIPROCESSOR support for pmap: move some pmap globals to cpu_info.
Define per-cpu ASID number spaces.
Remove some mips1/!mips1 difference in db_interface.c
Add mips32/64 knowledge to stacktrace.
 1.54.26.4 10-Jan-2010  matt Add generic support for DMA bounce buffers and real version of
bus_dmatag_subregion. MALTA uses it for ISADMA. Make RMIXL use
for creating 32bit and 29bit subregions.
 1.54.26.3 31-Dec-2009  matt Use mips_page_physload and mips_init_lwp0_uarea.
 1.54.26.2 30-Dec-2009  matt Please segtab lookups into separate file.
Add mips_add_physload
Add mips_init_lwp0_uarea
cleanup lwp0/cpu_info_store initialization.
 1.54.26.1 07-Sep-2009  matt Cleanup for LP64. XXX pv_entry needs work.
 1.54.18.1 19-Jan-2009  skrll Sync with HEAD.
 1.54.16.1 13-Dec-2008  haad Update haad-dm branch to haad-dm-base2.
 1.54.10.4 11-Aug-2010  yamt sync with head.
 1.54.10.3 11-Mar-2010  yamt sync with head
 1.54.10.2 18-Jul-2009  yamt sync with head.
 1.54.10.1 04-May-2009  yamt sync with head.
 1.54.6.1 17-Jan-2009  mjf Sync with HEAD.
 1.57.4.1 05-Mar-2011  rmind sync with head
 1.57.2.2 16-Nov-2010  uebayasi Sync with HEAD.
 1.57.2.1 17-Aug-2010  uebayasi Sync with HEAD.
 1.59.4.1 05-Mar-2011  bouyer Sync with HEAD
 1.59.2.1 06-Jun-2011  jruoho Sync with HEAD.
 1.61.8.2 11-Jun-2014  msaitoh Pull up following revision(s) (requested by skrll in ticket #1068):
sys/arch/mips/mips/pmap.c: revision 1.214
sys/arch/mips/include/pmap.h: revision 1.63
sys/arch/mips/mips/pmap_segtab.c: revision 1.8
Deal with incompatible cache aliases. Specifically,
- always flush an ephemeral page on unmap
- track unmanaged mappings (mappings entered via pmap_kenter_pa) for
aliases where required and handle appropriately (via pmap_enter_pv)
Hopefully this (finally) addresses the instability reported in the
following PRs:
PR/44900 - R5000/Rm5200 mips ports are broken
PR/46890 - upcoming NetBSD 6.0 release is very unstable/unusable on cobalt qube2
PR/48628 - cobalt and hpcmips ports are dead
 1.61.8.1 05-Jul-2012  riz branches: 1.61.8.1.4; 1.61.8.1.6;
Pull up following revision(s) (requested by matt in ticket #406):
sys/arch/mips/include/pmap.h: revision 1.62
sys/arch/mips/mips/pmap.c: revision 1.208
sys/arch/mips/mips/pmap_segtab.c: revision 1.5
Change lockless segtab management to use a mutex for protection. Some =
minor
changes to make this closer to common/pmap/tlb/pmap_segtab.c
=20
=20
 1.61.8.1.6.1 08-Nov-2017  snj Pull up following revision(s) (requested by skrll in ticket #1068):
sys/arch/mips/include/pmap.h: revision 1.63
sys/arch/mips/mips/pmap.c: revision 1.214
sys/arch/mips/mips/pmap_segtab.c: revision 1.8
Deal with incompatible cache aliases. Specifically,
- always flush an ephemeral page on unmap
- track unmanaged mappings (mappings entered via pmap_kenter_pa) for
aliases where required and handle appropriately (via pmap_enter_pv)
Hopefully this (finally) addresses the instability reported in the
following PRs:
PR/44900 - R5000/Rm5200 mips ports are broken
PR/46890 - upcoming NetBSD 6.0 release is very unstable / unusable on cobalt qube 2
PR/48628 - cobalt and hpcmips ports are dead
 1.61.8.1.4.1 08-Nov-2017  snj Pull up following revision(s) (requested by skrll in ticket #1068):
sys/arch/mips/include/pmap.h: revision 1.63
sys/arch/mips/mips/pmap.c: revision 1.214
sys/arch/mips/mips/pmap_segtab.c: revision 1.8
Deal with incompatible cache aliases. Specifically,
- always flush an ephemeral page on unmap
- track unmanaged mappings (mappings entered via pmap_kenter_pa) for
aliases where required and handle appropriately (via pmap_enter_pv)
Hopefully this (finally) addresses the instability reported in the
following PRs:
PR/44900 - R5000/Rm5200 mips ports are broken
PR/46890 - upcoming NetBSD 6.0 release is very unstable / unusable on cobalt qube 2
PR/48628 - cobalt and hpcmips ports are dead
 1.61.2.2 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.61.2.1 30-Oct-2012  yamt sync with head
 1.62.12.1 10-Aug-2014  tls Rebase.
 1.62.4.1 18-May-2014  rmind sync with head
 1.62.2.2 03-Dec-2017  jdolecek update from HEAD
 1.62.2.1 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.63.4.4 28-Aug-2017  skrll Sync with HEAD
 1.63.4.3 05-Feb-2017  skrll Sync with HEAD
 1.63.4.2 05-Oct-2016  skrll Sync with HEAD
 1.63.4.1 22-Sep-2015  skrll Sync with HEAD
 1.68.2.1 07-Jan-2017  pgoyette Sync with HEAD. (Note that most of these changes are simply $NetBSD$
tag issues.)
 1.69.8.1 30-Aug-2017  martin Pull up following revision(s) (requested by mrg in ticket #231):
distrib/sets/lists/base/md.evbmips 1.3
doc/CHANGES 1.2303-1.2304
etc/etc.evbmips/MAKEDEV.conf 1.8
etc/etc.evbmips/Makefile.inc 1.22
etc/mtree/Makefile 1.37
etc/mtree/NetBSD.dist.evbmips 1.1
sys/arch/evbmips/Makefile 1.9
sys/arch/evbmips/conf/SBMIPS upto 1.2
sys/arch/evbmips/conf/SBMIPS.MP upto 1.2
sys/arch/evbmips/conf/SBMIPS64 upto 1.2
sys/arch/evbmips/conf/SBMIPS64.MP upto 1.2
sys/arch/evbmips/conf/files.sbmips upto 1.2
sys/arch/evbmips/conf/std.sbmips upto 1.2
sys/arch/evbmips/include/disklabel.h 1.6
sys/arch/evbmips/include/loadfile_machdep.h
sys/arch/evbmips/include/param.h 1.10
sys/arch/evbmips/include/pci_machdep.h 1.3
sys/arch/evbmips/sbmips/TODO
sys/arch/evbmips/sbmips/autoconf.c
sys/arch/evbmips/sbmips/autoconf.h
sys/arch/evbmips/sbmips/console.c
sys/arch/evbmips/sbmips/cpu.c upto 1.3
sys/arch/evbmips/sbmips/cpuvar.h
sys/arch/evbmips/sbmips/disksubr.c
sys/arch/evbmips/sbmips/leds.h
sys/arch/evbmips/sbmips/locore_machdep.S
sys/arch/evbmips/sbmips/machdep.c upto 1.2
sys/arch/evbmips/sbmips/rtc.c upto 1.2
sys/arch/evbmips/sbmips/sb1250_icu.c upto 1.2
sys/arch/evbmips/sbmips/swarm.h
sys/arch/evbmips/sbmips/systemsw.c upto 1.2
sys/arch/evbmips/sbmips/systemsw.h
sys/arch/evbmips/sbmips/zbbus.c upto 1.2
sys/arch/evbmips/stand/Makefile 1.1
sys/arch/evbmips/stand/sbmips/Makefile
sys/arch/evbmips/stand/sbmips/Makefile.bootprogs upto 1.2
sys/arch/evbmips/stand/sbmips/Makefile.bootprogs 1.3
sys/arch/evbmips/stand/sbmips/Makefile.bootxx
sys/arch/evbmips/stand/sbmips/Makefile.inc upto 1.3
sys/arch/evbmips/stand/sbmips/boot/Makefile
sys/arch/evbmips/stand/sbmips/boot/filesystem.c
sys/arch/evbmips/stand/sbmips/boot/version
sys/arch/evbmips/stand/sbmips/bootxx_cd9660/Makefile
sys/arch/evbmips/stand/sbmips/bootxx_ffs/Makefile
sys/arch/evbmips/stand/sbmips/bootxx_lfs/Makefile
sys/arch/evbmips/stand/sbmips/common/bbinfo.h
sys/arch/evbmips/stand/sbmips/common/blkdev.c upto 1.2
sys/arch/evbmips/stand/sbmips/common/blkdev.h
sys/arch/evbmips/stand/sbmips/common/boot.c upto 1.2
sys/arch/evbmips/stand/sbmips/common/boot.ldscript
sys/arch/evbmips/stand/sbmips/common/booted_dev.c upto 1.2
sys/arch/evbmips/stand/sbmips/common/bootxx.c
sys/arch/evbmips/stand/sbmips/common/cfe.c
sys/arch/evbmips/stand/sbmips/common/cfe_api.c
sys/arch/evbmips/stand/sbmips/common/cfe_api.h
sys/arch/evbmips/stand/sbmips/common/cfe_api_int.h
sys/arch/evbmips/stand/sbmips/common/cfe_error.h
sys/arch/evbmips/stand/sbmips/common/cfe_ioctl.h
sys/arch/evbmips/stand/sbmips/common/checksize.sh
sys/arch/evbmips/stand/sbmips/common/common.h
sys/arch/evbmips/stand/sbmips/common/panic_putstr.c
sys/arch/evbmips/stand/sbmips/common/putstr.c
sys/arch/evbmips/stand/sbmips/common/start.S
sys/arch/evbmips/stand/sbmips/netboot/Makefile
sys/arch/evbmips/stand/sbmips/netboot/conf.c
sys/arch/evbmips/stand/sbmips/netboot/dev_net.c
sys/arch/evbmips/stand/sbmips/netboot/devopen.c
sys/arch/evbmips/stand/sbmips/netboot/getsecs.c upto 1.2
sys/arch/evbmips/stand/sbmips/netboot/if_cfe.c upto 1.2
sys/arch/evbmips/stand/sbmips/netboot/version
sys/arch/mips/conf/files.sibyte 1.8
sys/arch/mips/include/pmap.h 1.70
sys/arch/mips/sibyte/dev/sbbuswatch.c 1.4
sys/arch/mips/sibyte/dev/sbmac.c 1.49
sys/arch/mips/sibyte/dev/sbscn.c 1.43
sys/arch/mips/sibyte/dev/sbsmbus.c 1.17
sys/arch/mips/sibyte/dev/sbtimer.c 1.21
sys/arch/mips/sibyte/dev/sbwdog.c 1.15
sys/arch/mips/sibyte/pci/sbbrz_pci.c 1.8
usr.sbin/installboot/installboot.8 1.94

Move sys/arch/sbmips/* into sys/arch/evbmips/*/sbmips.
 1.70.4.1 10-Jun-2019  christos Sync with HEAD
 1.74.2.1 03-Jan-2021  thorpej Sync w/ HEAD.
 1.2 12-Jul-2018  maxv Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.
 1.1 07-Aug-2002  briggs branches: 1.1.2; 1.1.4; 1.1.6; 1.1.202; 1.1.204;
Implement pmc(9) -- An interface to hardware performance monitoring
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.
 1.1.204.1 10-Jun-2019  christos Sync with HEAD
 1.1.202.1 28-Jul-2018  pgoyette Sync with HEAD
 1.1.6.2 06-Sep-2002  jdolecek sync kqueue branch with HEAD
 1.1.6.1 07-Aug-2002  jdolecek file pmc.h was added on branch kqueue on 2002-09-06 08:37:31 +0000
 1.1.4.2 31-Aug-2002  gehenna catch up with -current.
 1.1.4.1 07-Aug-2002  gehenna file pmc.h was added on branch gehenna-devsw on 2002-08-31 13:45:20 +0000
 1.1.2.2 13-Aug-2002  nathanw Catch up to -current.
 1.1.2.1 07-Aug-2002  nathanw file pmc.h was added on branch nathanw_sa on 2002-08-13 02:18:29 +0000
 1.33 06-Dec-2020  christos don't expose vaddr_t to userland.
 1.32 04-Sep-2020  mrg branches: 1.32.2;
include machine/vmparam.h vs mips/vmparam.h to make sure we get
platform-specific defines first.

fixes build issue for playstation2.
 1.31 26-Aug-2020  simonb Define a UPAGES_MAX constant to size the a md_upte array in MIPS's
struct mdlwp. This is exposed to userland, so we can't use something
based on PAGE_SIZE.
 1.30 23-Aug-2020  simonb Use a 16kB USPACE (and larger kernel stack) for LP64 kernels. Invert
the logic for setting the USPACE size. Define a desired USPACE size
(16kB for LP64, 8kB otherwise) then divide by PAGE_SIZE to get UPAGES.

Fixes random segmap lossage, since the uarea usually sits immediately
above the segmap for a process. Thanks to mrg@, skrll@ and dholland@
for testing, debugging and general help tracking down this problem.
 1.29 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.28 30-Jun-2015  matt Make vmparam.h change work with RUMP
 1.27 20-Feb-2011  matt branches: 1.27.14; 1.27.32;
Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.26 14-Jan-2011  rmind branches: 1.26.2; 1.26.4;
Retire struct user, remove sys/user.h inclusions. Note sys/user.h header
as obsolete. Remove USER_TO_UAREA/UAREA_TO_USER macros.

Various #include fixes and review by matt@.
 1.25 14-Dec-2009  matt branches: 1.25.4;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.24 21-Nov-2009  rmind Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.
 1.23 20-Aug-2009  cliff include mips/vmparam.h to get PAGE_SIZE
 1.22 17-Aug-2009  matt Only include md_uptes if USPACE > PAGE_SIZE
 1.21 16-Nov-2007  skrll branches: 1.21.18; 1.21.36;
s/proc/lwp/ in comment
 1.20 09-Feb-2007  ad branches: 1.20.6; 1.20.16; 1.20.22; 1.20.24; 1.20.28; 1.20.30;
Merge newlock2 to head.
 1.19 24-Dec-2005  perry branches: 1.19.20;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.
 1.18 11-Dec-2005  christos merge ktrace-lwp.
 1.17 07-Aug-2003  agc branches: 1.17.16;
Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.16 17-Jan-2003  thorpej branches: 1.16.2;
Merge the nathanw_sa branch.
 1.15 09-Nov-2002  thorpej Make md_ss_addr a vaddr_t.
 1.14 05-Mar-2002  simonb ANSIfy.
 1.13 16-Oct-2001  uch branches: 1.13.4;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.
 1.12 16-Jan-2001  thorpej branches: 1.12.4;
New syscall entry implementation based on the Alpha version
as hacked by mycroft.
- Use syscall_intern() to give a process a plain or fancy
syscall based on ktrace flags.
- Avoid copying from the trapframe into a local array as much
as possible.

Yields roughly 5% improvement on a 25MHz R3000 (DECstation 5000/200)
on a simple syscall benchmark.

There's still some work that can be done using __HAVE_MINIMAL_EMUL.
 1.11 14-Jan-2001  thorpej Make the astpending flag per-process.
 1.10 28-Mar-2000  simonb Don't `extern' function declarations. While we're there, remove trailing
blank lines and white space.
 1.9 14-Jan-1999  castor branches: 1.9.8;
* Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.8 07-Jul-1997  jonathan branches: 1.8.10;
DDB for mips.
Add DDB interface to /sys/arch/mips/mips..
Rework heuristic stack traceback to work with DDB.
Add hooks to print exception log from DDB.
Add hooks from pmax console drivers: call Debugger()
after break from serial console, or 'DO' key from LK-xxx.
 1.7 15-Jun-1997  mhitch From Toru Nishimura: user pcb/proc changes for exception handling and
removing access through UADDR.
 1.6 02-Jun-1997  jonathan Add #ifdef _KERNEL/#endif around prototype of mips single-step emulator.

Add "struct proc;" inside the ifdef: <sys/proc.h> includes <machine/proc.h>
before declaring struct proc.
 1.5 25-May-1997  jonathan Rename cpu_singlstep() to mips_singlestep() and add prototype.
(it's not part of the standard interface to MD code.)

XXX Consider moving into process_machdep.c when the mips3 changes are merged.
 1.4 26-Oct-1994  cgd new RCS ID format.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.8.10.1 19-Nov-1998  nisimura - Forgot to commit many files for vm_offset_t purge last Monday.
 1.9.8.2 18-Jan-2001  bouyer Sync with head (for UBC+NFS fixes, mostly).
 1.9.8.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.12.4.2 16-Mar-2002  jdolecek Catch up with -current.
 1.12.4.1 10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.13.4.7 20-Nov-2002  wdk md_ss_addr is now vaddr_t.
 1.13.4.6 11-Nov-2002  nathanw Catch up to -current
 1.13.4.5 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.13.4.4 28-Nov-2001  wdk #include <sys/param.h> which is required for definition of UPAGES
 1.13.4.3 19-Nov-2001  wdk forward decl of "struct proc" should be "struct lwp"
 1.13.4.2 17-Nov-2001  wdk Split mdproc components into lwp-specific structure struct mdlwp
 1.13.4.1 16-Oct-2001  wdk file proc.h was added on branch nathanw_sa on 2001-11-17 23:18:22 +0000
 1.16.2.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.16.2.2 18-Sep-2004  skrll Sync with HEAD.
 1.16.2.1 03-Aug-2004  skrll Sync with HEAD
 1.17.16.3 07-Dec-2007  yamt sync with head
 1.17.16.2 26-Feb-2007  yamt sync with head.
 1.17.16.1 21-Jun-2006  yamt sync with head.
 1.19.20.3 02-Feb-2007  ad The TLB miss handler doesn't need to worry about RAS, oops.
 1.19.20.2 27-Jan-2007  ad Make mips systems work.
 1.19.20.1 29-Dec-2006  ad Checkpoint work in progress.
 1.20.30.1 19-Nov-2007  mjf Sync with HEAD.
 1.20.28.1 18-Nov-2007  bouyer Sync with HEAD
 1.20.24.1 09-Jan-2008  matt sync with HEAD
 1.20.22.1 21-Nov-2007  joerg Sync with HEAD.
 1.20.16.1 18-Jul-2007  matt Change last argument for plain/fancy syscall to vaddr_t (since it's the
address of the opcode). Add a md_abi field.
 1.20.6.1 03-Dec-2007  ad Sync with HEAD.
 1.21.36.11 27-Dec-2011  matt Make these play nice with modules.
 1.21.36.10 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.21.36.9 09-Jun-2010  matt Add support for setting/clearing PK_32 on _LP64 kernels. Make cpu_proc_fork
a real function and add it to vm_machdep.c and let it copy PK_32 on fork.
Properly clear/set PK_32 depending on ABI in setregs. Lack of PX_32 use
tracked down by Cliff Neighbors. [Ya! ps now works!]
 1.21.36.8 15-May-2010  matt Add kernel support for MIPS TLS. Use rdhwr rt, $29 as defined by the MIPS
TLS spec so that Linux MIPS binaries will work. Use sysarch(MIPS_TINFOSET, v)
to set the pointer.
 1.21.36.7 11-Mar-2010  matt Change md_astpending to u_int
 1.21.36.6 28-Feb-2010  matt Split FPU support into separate file and keep internals private to that file.
Make it MPSAFE. Change interface to be very similar to what's used on other
architectures.
Add l_md.md_fpcpu to mdlwp (needed for MPSAFE)
Move pridtab from <mips/cpu.h> to <mips/locore.h>
Add initial common IPI dispatcher.
Split cpu_* routines from mips_machdep.c into cpu_subr.c
Add cpu_startup_common which has the code replicated in half-dozen
plus machdep.c files.
 1.21.36.5 01-Feb-2010  matt Merge frame into trapframe. While this costs a bit more stack space on
kernel exceptions, the resulting simplifications are worth it. This is
a step to fast softints and kernel preemption.

trapframe now includes a struct reg instead of a separate array of registers.
 1.21.36.4 30-Dec-2009  matt Please segtab lookups into separate file.
Add mips_add_physload
Add mips_init_lwp0_uarea
cleanup lwp0/cpu_info_store initialization.
 1.21.36.3 05-Sep-2009  matt Make sure this is quad-word (16 byte) aligned. Thus when one is allocated
on the stack, the stack stays 16 byte aligned.
 1.21.36.2 21-Aug-2009  matt No need for md_fancy anymore since p_trace_enabled already has what we want.
 1.21.36.1 20-Aug-2009  matt Change md_regs in mdlwp to struct frame * from void *. Every use just casts
it to struct frame * anyways so enforce the type.
Add p_abi which indicates the ABI of the process.
 1.21.18.3 11-Mar-2010  yamt sync with head
 1.21.18.2 16-Sep-2009  yamt sync with head
 1.21.18.1 19-Aug-2009  yamt sync with head.
 1.25.4.1 05-Mar-2011  rmind sync with head
 1.26.4.1 05-Mar-2011  bouyer Sync with HEAD
 1.26.2.1 06-Jun-2011  jruoho Sync with HEAD.
 1.27.32.1 22-Sep-2015  skrll Sync with HEAD
 1.27.14.1 03-Dec-2017  jdolecek update from HEAD
 1.32.2.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.25 18-Feb-2021  skrll Revert previous... somehow the register names aren't available apparently
 1.24 17-Feb-2021  skrll Use the register name and not its number in _PROF_CPLOAD.

"yes please!" from simon@
 1.23 16-Feb-2021  simonb Working kernel profiling for n32/n64:
- Different MCOUNT and _KERN_MCOUNT macros for n32/n64.
- Don't profile mipsXX_lwp_trampoline().
- Allow a few new instructions in the stub fixups.
 1.22 26-Jul-2020  simonb branches: 1.22.2;
#define<tab>
Nuke trailing whitespace.
 1.21 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.20 24-Dec-2005  perry branches: 1.20.96; 1.20.100; 1.20.106; 1.20.108;
__asm__ -> __asm
__const__ -> const
__inline__ -> inline
__volatile__ -> volatile
 1.19 11-Dec-2005  christos merge ktrace-lwp.
 1.18 07-Aug-2003  agc branches: 1.18.16;
Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.17 05-Mar-2002  simonb branches: 1.17.14;
ANSIfy.
 1.16 05-Feb-2002  thorpej Don't put `frompc' into a0 in the delay slot of the __mcount
call; `jal __mcount' might be expanded by the assembler, and
thus a bogus `frompc' value could be passed.
 1.15 18-Jul-2000  jeffs branches: 1.15.4; 1.15.8;
Use spl*_noprof routines to raise and lower spl for kernel profiling.
This keeps the SR management more contained in locore, and should
be roughly the same performance as the .text size is less. Talked
to simonb and he was ok with this change.
 1.14 25-May-2000  simonb Fix kernel profiling so that it actually works:
- Add 16 bytes to the stack on entry to _mcount so we don't
overflow it.
- Use inline interrupt {dis,en}abling instead of calling
profiled function in locore.
 1.13 28-Mar-2000  simonb Don't `extern' function declarations. While we're there, remove trailing
blank lines and white space.
 1.12 11-Sep-1998  jonathan branches: 1.12.14;
Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.

* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.
 1.11 05-Nov-1997  thorpej asm -> __asm__
 1.10 18-Oct-1997  jonathan branches: 1.10.2;
Make the __mcount entrypoint non-static for kernels, to avoid any
chance of gprof mis-report profile ticks in __mcount to the following
function in libkern (currently _qdivrem).
 1.9 20-Jul-1997  jonathan Use __attribute__((unused). From Chris G. Demetriou <cgd@pa.dec.com>.
 1.8 19-Jul-1997  jonathan Add pointer to _mcount to avoid bogus warnings about unused static function.
(calls from interpolated assembler are invisible to gcc.)

If _KERNEL, add prototypes for non-profiled entrypoints _splhigh(), _splx().
 1.7 11-Nov-1996  jonathan Change "___mcount" -> "__mcount" in asm() code in arch/mips/include/profile.h.
Fixes profiling for non-underscore-prepending toolchains
(elf, e.g., shared libs), and breaks a.out/ecoff toolchains.

May break mips kernel profiling too. Needs more thought, since the
original intent of __mcount vs ___mcount on mips date back to pre-1.0 days.
 1.6 31-May-1995  jonathan Change reference in asm code from ``__mcount'' to ``___mcount'', to be
consistent with the (default) prepending of underscores to identifiers.

Because this reference is inside an ASM string it's too hairy to
conditionalize to support different toolchains that don't prepend underscores.
(Just don't do profiling with such toolchains.)
 1.5 28-Mar-1995  jtc KERNEL -> _KERNEL
 1.4 26-Oct-1994  cgd new RCS ID format.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.10.2.1 05-Nov-1997  thorpej Update from trunk: asm -> __asm__
 1.12.14.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.15.8.2 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.15.8.1 28-Feb-2002  nathanw Catch up to -current.
 1.15.4.2 16-Mar-2002  jdolecek Catch up with -current.
 1.15.4.1 11-Feb-2002  jdolecek Sync w/ -current.
 1.17.14.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.17.14.2 18-Sep-2004  skrll Sync with HEAD.
 1.17.14.1 03-Aug-2004  skrll Sync with HEAD
 1.18.16.1 21-Jun-2006  yamt sync with head.
 1.20.108.1 05-Mar-2011  bouyer Sync with HEAD
 1.20.106.1 06-Jun-2011  jruoho Sync with HEAD.
 1.20.100.1 05-Mar-2011  rmind sync with head
 1.20.96.1 15-Feb-2010  matt Completely redo how interrupts and SPL are handled in NetBSD/mips.
[XXX locore_mips1.S still needs to adapted.]

Nested interrupts now work. Except for MIPS_SOFT_MASK and MIPS_SR_INT_IE,
how interrupts work is completely abstracted. spl is handled through the
mips_splsw table. Direct manipulation of the status register is no longer
done (except for MIPS_SR_INT_IE). A new <mips/intr.h> contains the common
IPL/IST/spl* definitions for all ports.

Interrupt delivery is completely different. Clock interrupts may interrupt
device interrupts. ci_idepth is now handled by the caller of cpu_intr as
are softints (both can be optimized/simplified in the case of interrupts of
usermode code). cpu_intr has new arguments and now get called at IPL_HIGH
with MIPS_SR_INT_IE set and its logic is:

void
cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
int ipl;
uint32_t pending;
while (ppl < (ipl = splintr(&pending))) {
splx(ipl); /* enable interrupts */
<handle pending interrupts>
(void)splhigh(); /* disable interrupts */
}
}

mipsX_subr.S has been reworked. All user handlers (user_intr, systemcall,
user_gen_exception) now use common return to usermode code in lwp_trampoline.
ast() has changed to void ast(void) since the previous pc argument was never
used.

The playstation IPL_ICU_MASK support has been nuked.
MIPS_DYNAMIC_STATUS_MASK may soon be nuked soon.

A bunch of debugging code was left conditionalized by PARANOIA. If this
code detects a bug, it will enter an infinite loop. It is expected that
the kernel will be debugged in a simulator or with a hardware debugger so
that the state at that point can be analyzed.
 1.22.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.19 30-Jul-2016  matt KX needs to set on !O32 kernels
 1.18 14-Dec-2009  matt branches: 1.18.22; 1.18.40; 1.18.44;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.17 11-Dec-2005  christos branches: 1.17.78; 1.17.96;
merge ktrace-lwp.
 1.16 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.15 05-Mar-2002  simonb branches: 1.15.14;
Add support for MIPS32 and MIPS64 architectures:
Remove the unused PSL_USERCLR and BASEPRI macros.
 1.14 11-Jul-2000  jeffs branches: 1.14.4; 1.14.8;
For 64b clean 32b compilation, do not bother setting SX And KX.
The current code does not maintain these in SR, and they are not
needed by 32b kernel code for mips3/4 instructions.
 1.13 15-May-2000  nisimura branches: 1.13.4;
Remove unused PSL_USERCLR defines for processor status register.
 1.12 31-Jan-1999  castor branches: 1.12.8;
Remove genpubassym.cf stuff. The macro _MIPS_BSD_API allows selection of a
64-bit clean compilation model.
 1.11 18-Jan-1999  castor Remove vestiges of cpuarch.h. Revert to using cpuregs.h instead.
 1.10 14-Jan-1999  castor * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.9 11-Sep-1998  jonathan branches: 1.9.2;
Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.

* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.
 1.8 22-Jun-1997  jonathan * Change Sprite MACH_xxx prefix to MIPS_xxx.

* Use standard mips terminology (xxx_KSEG0, xxx_KSEG1) instead of the
(more meaningful) Sprite names (xxx_CACHED, xxx_UNCACHED).
 1.7 21-Jun-1997  jonathan More mips1/mips3 changes to cpuregs.h and psl.h:
* cpuregs.h:
Delete unused VMMACH_ names (e.g., duplicates of PTE bits in pte.h).
Change remaining VMMACH_xxx names to MIPS1_xxx or MIPS3_xx.
Fold remaining compile-time definitions into a single #ifdef MIPS3.

* Use MIPS1_ names in locore_r2000.S, mips3_ names in locore_r4000.S

* Garbage-collect MachHitFlushDCache()

* psl.h:
use MIPS1_, MIPS3_ symbolic names for Cause register bits.
change _R3K to MIPS1_, _R4K to MIPS3. Conditionalize for mips1 only,
mips3 only, or when both are defined, use runtime CPUISMIPS3 test.
 1.6 16-Jun-1997  jonathan Move merged pmax psl.h with mips1/mips3 support to mips/include/psl.h.
Change pmax/include/psl.h to just do #include <mips/psl.h>.

pmax/include/psl.h would go away completely if it wasn't stil required
by compat/common/kern_exit_43.c.
 1.5 15-Jun-1997  mhitch More merged MIPS1/MIPS3 support for DECstations.
 1.4 26-Oct-1994  cgd new RCS ID format.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.9.2.2 19-Nov-1998  nisimura - Forgot to commit many files for vm_offset_t purge last Monday.
 1.9.2.1 15-Oct-1998  nisimura - cpuregs.h was modifed a bit, then renamed with cpuarch.h.
- mips_cpu.h has gone.
- CPU's register mnemonics in regdef.h is now a part of asm.h.
 1.12.8.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.13.4.1 18-Jul-2000  jeffs Pull up revision 1.14 (approved by cgd).
Remove extraneous bits from MIPS3_PSL_XFLAGS.
 1.14.8.1 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.14.4.1 16-Mar-2002  jdolecek Catch up with -current.
 1.15.14.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.15.14.2 18-Sep-2004  skrll Sync with HEAD.
 1.15.14.1 03-Aug-2004  skrll Sync with HEAD
 1.17.96.3 19-Jan-2012  matt When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses. There are exceptions.
bus_space_handles are now register_t instead of intptr_t. This allows them
to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address. This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs. If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.
 1.17.96.2 07-Sep-2009  matt Add MIPS_SR_KX to PSL_USERSET if _LP64
 1.17.96.1 16-Aug-2009  matt Kill use of _MIPS_BSD_ABI - switch to __mips_<abi>
Use device_t where appropriate.
Remove magic numbers.
 1.17.78.1 11-Mar-2010  yamt sync with head
 1.18.44.1 06-Aug-2016  pgoyette Sync with HEAD
 1.18.40.1 05-Oct-2016  skrll Sync with HEAD
 1.18.22.1 03-Dec-2017  jdolecek update from HEAD
 1.27 22-Aug-2020  skrll Remove pte_zero_p and simply check against 0.
 1.26 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.25 24-Jun-2017  skrll Provide pte_set
 1.24 04-Sep-2016  skrll Fix pte_cached_p for MIPS_HAS_R4K_MMU
 1.23 11-Jul-2016  matt Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.22 27-Jun-2015  matt Remove unused struct pt_entry_t union.
 1.21 11-Jun-2015  matt Add struct pmap_limits and pm_{min,max}addr from uvm/pmap/map.h and use it to
store avail_start, avail_end, virtual_start, and virtual_end.
Remove iospace and let emips just bump pmap_limits.virtual_start to get the
VA space it needs.
pmap_segtab.c is almost identical to uvm/pmap/pmap_segtab.c now. It won't
be long until we switch to the uvm/pmap one.
 1.20 20-Feb-2011  matt branches: 1.20.14; 1.20.32;
Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.19 28-Apr-2008  martin branches: 1.19.18; 1.19.22; 1.19.28; 1.19.30;
Remove clause 3 and 4 from TNF licenses
 1.18 17-Oct-2007  garbled branches: 1.18.16; 1.18.18; 1.18.20;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.17 17-Jul-2007  macallan branches: 1.17.10;
add definitions for non-cached pages
 1.16 16-Feb-2006  perry branches: 1.16.24; 1.16.32;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.
 1.15 24-Dec-2005  perry branches: 1.15.2; 1.15.4; 1.15.6;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.
 1.14 25-Nov-2005  simonb More KNF.
 1.13 14-Oct-2002  chs branches: 1.13.6; 1.13.22; 1.13.30;
eliminate PT_ENTRY_NULL in favor of plain old NULL.
 1.12 05-Mar-2002  simonb Add support for MIPS32 and MIPS64 architectures:
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 1.11 23-Mar-2001  simonb branches: 1.11.2; 1.11.8;
Delete unused uvtopte() macro.
 1.10 09-Jun-2000  soda branches: 1.10.4;
rename
vad_to_pfn() -> mips_paddr_to_tlbpfn()
pfn_to_vad() -> mips_tlbpfn_to_paddr()
as suggested by thorpej on port-mips Mar 27.
 1.9 09-Jun-2000  soda make paddr_t 64bit on arc port by introducing _MIPS_PADDR_T_64BIT.
 1.8 28-May-1999  nisimura branches: 1.8.2; 1.8.10;
- Make this compilable with MIPS1 or MIPS3 only configuration.
 1.7 27-May-1999  nisimura - Change a symbolic name of TLB entrylo from 'PG_M' to 'PG_D' to reflect
processor design. MIPS 'dirty bit' is not the same as i386 'dirty bit'.
There is a growing concern of misuse in NetBSD/mips.
 1.6 06-Jan-1999  nisimura branches: 1.6.4;
- Complete vm_offset_t purge for mips processor.
- bzero() -> memset() and bcopy() -> memcpy().
- Garbage collection in trap.c and db_interface.c.
 1.5 21-Jun-1997  mhitch branches: 1.5.12;
Cast mips1-only and mips3-only pfn_to_vad() macros to match the mips1/mips3
merged inline function. Fixes inconsist printf format usage in trap.c.
 1.4 17-Jun-1997  mhitch Remove stray macro definition; didn't hurt for MIPS1 only, but wrong for
MIPS3.
 1.3 16-Jun-1997  jonathan Changes for configuring both MIPS1 and MIPS3, from a merge of
similar design and code by Jason Thorpe and Jonathan Stone.

NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.

mips/include/cpu.h:
Add CPUISMIPS3 for run-time tests of what CPU architecture level
we're running on.

mips/include/locore.h:
Add declarations of locore cache-size variables for ref/def toolchain.

mips/include/mips1_pte.h:
mips1 TLB bit definitions.

mips/include/mips3_pte.h:
mips3 TLB bit definitions.

mips/include/pte.h:
define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
that expand to CPU constants if only one CPU arch is configured,
or to inline functions if both MIPS1 and MIPS3 are configured.

mips/mips/locore_r2000.S:
Use MIPS1_PG_xxx constants inside mips1-specific code.

mips/mips/locore_r4000.S:
Use MIPS3_PG_xxx constants inside mips3-specific code.

mips/mips/locore.S:
Use MIPS1_PG_xxx constants inside mips3-specific code.
Use MIPS1_PG_xxx constants inside mips1-specific code.
(Needs more work!)

mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
Use MIPS3_PG_xxx constants inside mips3-specific functions,
and MIPS1_PG_XXX inside mips1-specific code.
Otherwise, use mips_pg_XXX_bit() macros where they apply,
and use "if (CPUISMIPS3) { ... } else {... }" where they don't.

mips/mips/mips_machdep.c:
Import Michael Hitch's fixes from the pmax locore-init code
into mips_vector_init().

pmax/pmax/machdep.c:
Use generic mips_vector_init() locore vector-init function.
 1.2 15-Jun-1997  mhitch More merged MIPS1/MIPS3 support. The pte definitions still need work before
they can be support both MIPS1 and MIPS3.
 1.1 13-Oct-1996  jonathan Merge mips1 and mips3 pte/pmap code, pass 0;
* Move mips-I pte (TLBlo) definitions from pmax/include/pte.h
to mips/include/mips1_pte.h

* Move mips-III pte (TLBlo) definitions from pica/include/pte.h
to mips/include/mips3_pte.h

* Add new mips/include/pte.h, which includes exactly one of
mips1_pte.h or mips3_pte.h (which still have namespace collisions),
depending on "options MIPS1" or "options MIPS3". (hack).
Move soft kvtopte(), ptetovk() definitions to mips/include/pte.h

* Add macro PTE_TO_PADDR() to hide the different hardware TLB formats
when mapping from pte to physical address.

* Add macro PTE_READONLY() to hide lack of SW read-only bit in mips-III
tlb. (mips1 pmap uses a sw bit in the PTE, mips3 looks up RO bit in
the kernel pmap.)

* Use macros (not direct TLB frobbing) in mips/trap.c, to make it
mips-1/mips-III indepenndet.

* Change {pmax,pica}/include/pte.h to just do #include <mips/pte.h>.
 1.5.12.2 19-Nov-1998  nisimura - And one more line escaped.
 1.5.12.1 19-Nov-1998  nisimura - Forgot to commit many files for vm_offset_t purge last Monday.
 1.6.4.1 21-Jun-1999  thorpej Sync w/ -current.
 1.8.10.1 22-Jun-2000  minoura Sync w/ netbsd-1-5-base.
 1.8.2.2 27-Mar-2001  bouyer Sync with HEAD.
 1.8.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.10.4.1 09-Apr-2001  nathanw Catch up with -current.
 1.11.8.3 18-Oct-2002  nathanw Catch up to -current.
 1.11.8.2 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.11.8.1 23-Mar-2001  nathanw file pte.h was added on branch nathanw_sa on 2002-04-01 07:40:59 +0000
 1.11.2.1 16-Mar-2002  jdolecek Catch up with -current.
 1.13.30.1 29-Nov-2005  yamt sync with head.
 1.13.22.2 03-Sep-2007  yamt sync with head.
 1.13.22.1 21-Jun-2006  yamt sync with head.
 1.13.6.1 11-Dec-2005  christos Sync with head.
 1.15.6.1 22-Apr-2006  simonb Sync with head.
 1.15.4.1 09-Sep-2006  rpaulo sync with head
 1.15.2.1 18-Feb-2006  yamt sync with head.
 1.16.32.1 03-Oct-2007  garbled Sync with HEAD
 1.16.24.1 20-Aug-2007  ad Sync with HEAD.
 1.17.10.1 06-Nov-2007  matt sync with HEAD
 1.18.20.1 16-May-2008  yamt sync with head.
 1.18.18.1 18-May-2008  yamt sync with head.
 1.18.16.1 02-Jun-2008  mjf Sync with HEAD.
 1.19.30.1 05-Mar-2011  bouyer Sync with HEAD
 1.19.28.1 06-Jun-2011  jruoho Sync with HEAD.
 1.19.22.1 05-Mar-2011  rmind sync with head
 1.19.18.5 04-Aug-2012  matt Make MIPS use a multi-level page table for the kernel address space.
(just like the user address does). XXX fix mips1
 1.19.18.4 11-Mar-2010  matt Mark some inlines as __pure.
 1.19.18.3 23-Feb-2010  matt Make sure <mips/locore.h> is not included by MI code.
Add send_ipi and cpu_offline_md hooks to locoresw.
Add MP support to pmap (pvlist locking, tlb locking).
Add TLB shootdown support (see comment at the top of mips/pmap_tlb.c).
Add mipsXX_tlb_invalidate_globals routine
 1.19.18.2 26-Jan-2010  matt Revamp pmap. Add exec page caching logic from powerpc oea pmap. Shrink struct
vm_page by placing the first pv_entry in it. Remove pv_flags since nothing
really needed it. Add pmap counters. Rework virtual cache alias logic.
Allow pmap_copy_page and pmap_zero_page to deal with non-KSEG0 mappable pages.
 1.19.18.1 30-Dec-2009  matt Please segtab lookups into separate file.
Add mips_add_physload
Add mips_init_lwp0_uarea
cleanup lwp0/cpu_info_store initialization.
 1.20.32.3 28-Aug-2017  skrll Sync with HEAD
 1.20.32.2 05-Oct-2016  skrll Sync with HEAD
 1.20.32.1 22-Sep-2015  skrll Sync with HEAD
 1.20.14.1 03-Dec-2017  jdolecek update from HEAD
 1.19 18-Mar-2021  simonb Add PTRACE_ILLEGAL_ASM using the MIPS32r6/MIPS64r6 backwards and
forwards compatible "sigrie" instruction to generate a Reserved
Instruction trap.
 1.18 26-Jul-2020  simonb branches: 1.18.2;
#define<tab>
Nuke trailing whitespace.
 1.17 18-Jun-2019  kamil Introduce PTRACE_REG_FP() a helper macro to retrieve the frame pointer

The macro is dummy for ia64 (the FP register is unknown and can change
freely) and sparc/sparc64 (not stored in struct reg).
 1.16 12-Apr-2017  kamil branches: 1.16.12;
Add new macro PTRACE_BREAKPOINT_ASM in <sys/ptrace.h> MD part

This macro ships with a MD-specific assembly instruction triggering
a software breakpoint.

Missing instruction for powerpc targets.

This code is used in ATF tests (lib/libc/sys/t_ptrace_wait).

Original patch by Nick Hudson, thanks!
 1.15 08-Apr-2017  kamil Add new ptrace(2) API: PT_SETSTEP & PT_CLEARSTEP

These operations allow to mark thread as a single-stepping one.

This allows to i.a.:
- single step and emit a signal (PT_SETSTEP & PT_CONTINUE)
- single step and trace syscall entry and exit (PT_SETSTEP & PT_SYSCALL)

The former is useful for debuggers like GDB or LLDB. The latter can be used
to singlestep a usermode kernel. These examples don't limit use-cases of
this interface.

Define PT_*STEP only for platforms defining PT_STEP.

Add new ATF tests setstep[1234].

These ptrace(2) operations first appeared in FreeBSD.

Sponsored by <The NetBSD Foundation>
 1.14 25-Sep-2015  christos branches: 1.14.2; 1.14.4;
For processors that have memory breakpoints, add macros for them to help
libproc
 1.13 15-Sep-2015  christos Provide access to pc/sp/syscall-return registers like we have for mcontext
 1.12 25-Jan-2008  skrll branches: 1.12.54; 1.12.74;
Define PT_MACHDEP_STRINGS
 1.11 11-Dec-2005  christos branches: 1.11.50; 1.11.56;
merge ktrace-lwp.
 1.10 07-Aug-2003  agc branches: 1.10.16;
Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.9 20-Oct-1997  jonathan branches: 1.9.52;
Comment out PT_STEP for 1.3. Defining it causes gdb 4.16 to break.
(inferior debugee children die immediately with SIGTRAP.)
 1.8 19-Oct-1997  jonathan Define PT_STEP.
 1.7 19-Oct-1997  jonathan Add PT_GETFPREGS, PT_SETFPREGS and process_{read,write}_fpregs.
 1.6 21-Dec-1995  jonathan Reserve a number in the machine-dependent range for PT_STEP, in
case the kernel-debugger implementation of single-stepping ever works
with user code.
 1.5 20-Dec-1995  jonathan Add support for ptrace PT_GETREGS and PT_SETREGS for NetBSD/pmax:
* define PT_GETREGS and PT_SETREGS in pmax/include/ptrace.h
* Flesh out the stubs in pmax/pmax/process_machdep.c to handle
those requests.
* Now that "struct reg" is actually used, remove the bogus
#ifdef LANGUAGE_C around its definition, and redo pmax/include/reg.h
so that the definitions needed by locore.S are in a separate file,
pmax/include/regnum.h.
* update locore.S to match.
 1.4 26-Oct-1994  cgd new RCS ID format.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.9.52.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.9.52.2 18-Sep-2004  skrll Sync with HEAD.
 1.9.52.1 03-Aug-2004  skrll Sync with HEAD
 1.10.16.1 04-Feb-2008  yamt sync with head.
 1.11.56.1 18-Feb-2008  mjf Sync with HEAD.
 1.11.50.1 23-Mar-2008  matt sync with HEAD
 1.12.74.3 28-Aug-2017  skrll Sync with HEAD
 1.12.74.2 27-Dec-2015  skrll Sync with HEAD (as of 26th Dec)
 1.12.74.1 22-Sep-2015  skrll Sync with HEAD
 1.12.54.1 03-Dec-2017  jdolecek update from HEAD
 1.14.4.1 21-Apr-2017  bouyer Sync with HEAD
 1.14.2.1 26-Apr-2017  pgoyette Sync with HEAD
 1.16.12.1 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.18.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.8 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.7 28-Apr-2008  martin Remove clause 3 and 4 from TNF licenses
 1.6 05-Mar-2002  simonb branches: 1.6.116; 1.6.118; 1.6.120;
Remove the number of TLB entries for different rx39 CPUs - this info
is in the table in mips_machdep.c now.
 1.5 02-Dec-2001  uch TX39, R5900 cache configuration.
 1.4 24-Aug-2000  uch branches: 1.4.2; 1.4.6; 1.4.10;
Rewrote TX39 series cache routines.
 1.3 10-Jul-2000  uch use mips3 cache op.
invalidate -> write-back invalidate
(although NetBSD/hpcmips run on write-through mode.)
suggested by cgd.
 1.2 23-May-2000  soren MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.
 1.1 29-Nov-1999  uch branches: 1.1.2;
TX3912/22 specific register defines.
 1.1.2.1 27-Dec-1999  wrstuden Pull up to last week's -current.
 1.4.10.2 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.4.10.1 08-Jan-2002  nathanw Catch up to -current.
 1.4.6.2 16-Mar-2002  jdolecek Catch up with -current.
 1.4.6.1 10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.4.2.2 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.4.2.1 24-Aug-2000  bouyer file r3900regs.h was added on branch thorpej_scsipi on 2000-11-20 20:13:32 +0000
 1.6.120.1 16-May-2008  yamt sync with head.
 1.6.118.1 18-May-2008  yamt sync with head.
 1.6.116.1 02-Jun-2008  mjf Sync with HEAD.
 1.4 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.3 28-Apr-2008  martin branches: 1.3.18; 1.3.22; 1.3.28; 1.3.30;
Remove clause 3 and 4 from TNF licenses
 1.2 15-Nov-2002  simonb branches: 1.2.108; 1.2.110; 1.2.112;
White space nits.
 1.1 05-Mar-2002  simonb branches: 1.1.4; 1.1.8;
Rename <mips/r5900/cpuregs.h> to <mips/r5900regs.h> and remove some
content no longer needed.
 1.1.8.3 11-Dec-2002  thorpej Sync with HEAD.
 1.1.8.2 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.1.8.1 05-Mar-2002  nathanw file r5900regs.h was added on branch nathanw_sa on 2002-04-01 07:40:59 +0000
 1.1.4.2 16-Mar-2002  jdolecek Catch up with -current.
 1.1.4.1 05-Mar-2002  jdolecek file r5900regs.h was added on branch kqueue on 2002-03-16 15:58:36 +0000
 1.2.112.1 16-May-2008  yamt sync with head.
 1.2.110.1 18-May-2008  yamt sync with head.
 1.2.108.1 02-Jun-2008  mjf Sync with HEAD.
 1.3.30.1 05-Mar-2011  bouyer Sync with HEAD
 1.3.28.1 06-Jun-2011  jruoho Sync with HEAD.
 1.3.22.1 05-Mar-2011  rmind sync with head
 1.3.18.1 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.19 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.18 29-Dec-2017  maya Simplify, don't use ifdefs to optimize out DIAGNOSTIC assertions.
Make the test for the n32/n64 case meaningful.

tested on pmax (o32).
 1.17 09-Dec-2017  christos provide 32 and 64 bit register struct definitions.
 1.16 24-Jan-2016  christos use namespace protected types.
 1.15 16-Aug-2011  matt branches: 1.15.12; 1.15.30;
Add support for the MIPS DSP ASE (as a second PCU).
 1.14 08-Feb-2011  rmind Remove clause 3 (UCB advertising clause) from the University of Utah
copyright. Confirmed by Mike Hibler, mike at cs.utah.edu - thanks!
Also, merge UCB and Utah copyright texts back into one, as they
originally were.

Extra verification by snj@.
 1.13 14-Dec-2009  matt branches: 1.13.4; 1.13.6; 1.13.8;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.12 11-Dec-2005  christos branches: 1.12.78; 1.12.96;
merge ktrace-lwp.
 1.11 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.10 30-Nov-2002  simonb branches: 1.10.6;
Standardise on #ifdef _MIPS_<header>_H_ for multiple inclusion tests.
 1.9 14-Jan-1999  castor branches: 1.9.26;
* Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.8 19-Jul-1997  jonathan branches: 1.8.10;
* Re-apply changes from rev 1.6 of sys/arch/mips/include/reg.h accidentally
undone by rev 1.7:
>redo pmax/include/reg.h
>so that the definitions needed by locore.S are in a separate file,
>pmax/include/regnum.h.

* Add explicit `#include <mips/regnum.h>' where symbolic offsets
into a mips trapframe or struct reg are used..
 1.7 15-Jun-1997  mhitch From Toru Nishimura: exception trapframe changes.
 1.6 20-Dec-1995  jonathan Add support for ptrace PT_GETREGS and PT_SETREGS for NetBSD/pmax:
* define PT_GETREGS and PT_SETREGS in pmax/include/ptrace.h
* Flesh out the stubs in pmax/pmax/process_machdep.c to handle
those requests.
* Now that "struct reg" is actually used, remove the bogus
#ifdef LANGUAGE_C around its definition, and redo pmax/include/reg.h
so that the definitions needed by locore.S are in a separate file,
pmax/include/regnum.h.
* update locore.S to match.
 1.5 18-Jan-1995  mellon Make register definitions compatible with Ultrix
 1.4 26-Oct-1994  cgd new RCS ID format.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.8.10.1 19-Nov-1998  nisimura - Forgot to commit many files for vm_offset_t purge last Monday.
 1.9.26.1 11-Dec-2002  thorpej Sync with HEAD.
 1.10.6.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.10.6.2 18-Sep-2004  skrll Sync with HEAD.
 1.10.6.1 03-Aug-2004  skrll Sync with HEAD
 1.12.96.1 23-Aug-2009  matt Add a fpreg_oabi for the O32/O64 version of fpreg.
 1.12.78.1 11-Mar-2010  yamt sync with head
 1.13.8.1 17-Feb-2011  bouyer Sync with HEAD
 1.13.6.1 06-Jun-2011  jruoho Sync with HEAD.
 1.13.4.1 05-Mar-2011  rmind sync with head
 1.15.30.1 19-Mar-2016  skrll Sync with HEAD
 1.15.12.1 03-Dec-2017  jdolecek update from HEAD
 1.14 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.13 07-Jun-2015  matt assembly no longer include <machine/cpu.h>. Instead MIPS_CURLWP is gotten
from regdef.h and everything else from assym.h. <mips/mips_param.h> no
longer include <machine/cpu.h>
 1.12 11-Dec-2005  christos branches: 1.12.122; 1.12.142;
merge ktrace-lwp.
 1.11 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.10 04-Nov-2002  thorpej branches: 1.10.6;
Add SGI-compatible ta0-ta3 register names. These allow one to write
asm code which can be built easily in old-ABI and new-ABI environemnts.

In old-ABI, they map to t4-t7, and in new-ABI, they map to a4-a7. This
means that t0-t3,ta0-ta3,t8,t9 are available in both ABIs.

Because ta0-ta3 overlap with arg regs (albeit arg slots which are usually
unused), they should be used only if t0-t3,t8,t9 isn't enough.
 1.9 02-Nov-2002  thorpej Define N32/N64 register usage.
 1.8 05-Mar-2002  simonb Include <machine/cdefs.h> to select 32/64bit APIs.
 1.7 30-Mar-1999  soda branches: 1.7.22; 1.7.26;
- protect from multiple inclusion
- incorporate changes to comments from asm.h
 1.6 24-Mar-1999  drochner regdef.h is back
 1.5 13-Mar-1999  drochner g/c regdef.h (went into asm.h)
 1.4 26-Oct-1994  cgd branches: 1.4.20;
new RCS ID format.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.4.20.1 15-Oct-1998  nisimura - cpuregs.h was modifed a bit, then renamed with cpuarch.h.
- mips_cpu.h has gone.
- CPU's register mnemonics in regdef.h is now a part of asm.h.
 1.7.26.2 11-Nov-2002  nathanw Catch up to -current
 1.7.26.1 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.7.22.1 16-Mar-2002  jdolecek Catch up with -current.
 1.10.6.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.10.6.2 18-Sep-2004  skrll Sync with HEAD.
 1.10.6.1 03-Aug-2004  skrll Sync with HEAD
 1.12.142.1 22-Sep-2015  skrll Sync with HEAD
 1.12.122.1 03-Dec-2017  jdolecek update from HEAD
 1.12 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.11 16-Aug-2011  matt Add support for the MIPS DSP ASE (as a second PCU).
 1.10 08-Feb-2011  rmind Remove clause 3 (UCB advertising clause) from the University of Utah
copyright. Confirmed by Mike Hibler, mike at cs.utah.edu - thanks!
Also, merge UCB and Utah copyright texts back into one, as they
originally were.

Extra verification by snj@.
 1.9 14-Dec-2009  matt branches: 1.9.4; 1.9.6; 1.9.8;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.8 11-Dec-2005  christos branches: 1.8.78; 1.8.96;
merge ktrace-lwp.
 1.7 26-Nov-2003  he Hide the register number constants behind an _R_ prefix, and also
rename FPBASE to _FPBASE, so that we avoid polluting the user's
name space when e.g. <sys/ptrace.h> is included. Previously, the
PC symbol in mips/regnum.h would conflict with the declaration of
the external variable by the same name in termcap.h, as discovered
by the ``okheaders'' regression test.
 1.6 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.5 04-Nov-2002  thorpej branches: 1.5.6;
Add TA0-TA3 register indices.
 1.4 02-Nov-2002  thorpej Define N32/N64 register usage.
 1.3 05-Jul-1998  jonathan branches: 1.3.34;
"PS" alias for "SR" clashes with netccitt/pk.h. ifdef out.
 1.2 19-Mar-1996  jonathan Remove #ifdef LANGUAGE_C - protected definition of "struct reg".
(It was a duplicate of the real definition reg.h and was never used.)
 1.1 20-Dec-1995  jonathan Add support for ptrace PT_GETREGS and PT_SETREGS for NetBSD/pmax:
* define PT_GETREGS and PT_SETREGS in pmax/include/ptrace.h
* Flesh out the stubs in pmax/pmax/process_machdep.c to handle
those requests.
* Now that "struct reg" is actually used, remove the bogus
#ifdef LANGUAGE_C around its definition, and redo pmax/include/reg.h
so that the definitions needed by locore.S are in a separate file,
pmax/include/regnum.h.
* update locore.S to match.
 1.3.34.1 11-Nov-2002  nathanw Catch up to -current
 1.5.6.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.5.6.2 18-Sep-2004  skrll Sync with HEAD.
 1.5.6.1 03-Aug-2004  skrll Sync with HEAD
 1.8.96.1 16-Aug-2009  matt Kill use of _MIPS_BSD_ABI - switch to __mips_<abi>
Use device_t where appropriate.
Remove magic numbers.
 1.8.78.1 11-Mar-2010  yamt sync with head
 1.9.8.1 17-Feb-2011  bouyer Sync with HEAD
 1.9.6.1 06-Jun-2011  jruoho Sync with HEAD.
 1.9.4.1 05-Mar-2011  rmind sync with head
 1.10 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.9 11-Dec-2005  christos merge ktrace-lwp.
 1.8 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.7 03-Apr-2000  simonb branches: 1.7.28;
Removing trailing comma from enum declaration.
 1.6 07-Oct-1996  jonathan branches: 1.6.30;
Fix for elf{32,64} changes: make <mips/reloc.h> re-includable,
Use elf_xxx section names (not elf32_xxx)in mips/mips/elf.c
 1.5 19-Mar-1996  jonathan Change "XXX_pmax" to "XXX_mips" in preparation for merging with
Pica reloc.h.
 1.4 26-Oct-1994  cgd new RCS ID format.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.6.30.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.7.28.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.7.28.2 18-Sep-2004  skrll Sync with HEAD.
 1.7.28.1 03-Aug-2004  skrll Sync with HEAD
 1.5 05-Feb-2003  nakayama Replace machine/rnd.h with more appropriate name to share it
with cycle counter based microtime in kern/kern_microtime.c.
 1.4 05-Mar-2002  simonb Add support for MIPS32 and MIPS64 architectures:
- move away from using CPUISMIPS3; use MIPS_HAS_CLOCK instead.
 1.3 05-Oct-2000  cgd branches: 1.3.2; 1.3.6; 1.3.10;
clean up and consistency for CP0 Count, Compare, Wired, and Config
access function names and prototypes.
 1.2 09-Jun-2000  soda branches: 1.2.4;
this header don't have to include <machine/locore.h>,
include <mips/locore.h> instead.
 1.1 06-Jun-2000  soren Add rnd(4) glue for the MIPS3 cycle counter.
 1.2.4.2 22-Jun-2000  minoura Sync w/ netbsd-1-5-base.
 1.2.4.1 09-Jun-2000  minoura file rnd.h was added on branch minoura-xpg4dl on 2000-06-22 17:01:31 +0000
 1.3.10.1 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.3.6.1 16-Mar-2002  jdolecek Catch up with -current.
 1.3.2.2 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.3.2.1 05-Oct-2000  bouyer file rnd.h was added on branch thorpej_scsipi on 2000-11-20 20:13:32 +0000
 1.9 29-Nov-2019  riastradh Largely eliminate the MD rwlock.h header file.

This was full of definitions that have been obsolete for over a
decade. The file still remains for __HAVE_RW_STUBS but that's all.
Used only internally in kern_rwlock.c now, not by <sys/rwlock.h>.
 1.8 20-Feb-2011  matt branches: 1.8.56;
Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.7 28-Apr-2008  martin branches: 1.7.22; 1.7.28; 1.7.30;
Remove clause 3 and 4 from TNF licenses
 1.6 04-Jan-2008  ad branches: 1.6.6; 1.6.8; 1.6.10;
Use new style memory barriers.
 1.5 29-Nov-2007  ad branches: 1.5.6;
RW_GIVE() needs to do a mb_memory() now.
 1.4 29-Nov-2007  ad - Change _lock_cas and friends to do "compare and swap" instead of "compare
and set".
- Rename them to _atomic_cas_uint, _atomic_cas_ulong etc and provide strong
aliases for the other names CAS goes by.
 1.3 21-Nov-2007  yamt make kmutex_t and krwlock_t smaller by killing lock id.
ok'ed by Andrew Doran.
 1.2 09-Feb-2007  ad branches: 1.2.4; 1.2.8; 1.2.24; 1.2.26; 1.2.30; 1.2.32;
Merge newlock2 to head.
 1.1 29-Dec-2006  ad branches: 1.1.2;
file rwlock.h was initially added on branch newlock2.
 1.1.2.1 29-Dec-2006  ad Checkpoint work in progress.
 1.2.32.2 18-Feb-2008  mjf Sync with HEAD.
 1.2.32.1 08-Dec-2007  mjf Sync with HEAD.
 1.2.30.1 21-Nov-2007  bouyer Sync with HEAD
 1.2.26.1 09-Jan-2008  matt sync with HEAD
 1.2.24.2 03-Dec-2007  joerg Sync with HEAD.
 1.2.24.1 21-Nov-2007  joerg Sync with HEAD.
 1.2.8.1 03-Dec-2007  ad Sync with HEAD.
 1.2.4.4 21-Jan-2008  yamt sync with head
 1.2.4.3 07-Dec-2007  yamt sync with head
 1.2.4.2 26-Feb-2007  yamt sync with head.
 1.2.4.1 09-Feb-2007  yamt file rwlock.h was added on branch yamt-lazymbuf on 2007-02-26 09:07:27 +0000
 1.5.6.1 08-Jan-2008  bouyer Sync with HEAD
 1.6.10.1 16-May-2008  yamt sync with head.
 1.6.8.1 18-May-2008  yamt sync with head.
 1.6.6.1 02-Jun-2008  mjf Sync with HEAD.
 1.7.30.1 05-Mar-2011  bouyer Sync with HEAD
 1.7.28.1 06-Jun-2011  jruoho Sync with HEAD.
 1.7.22.1 05-Mar-2011  rmind sync with head
 1.8.56.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1 15-Nov-2002  simonb branches: 1.1.2;
Declare some CP0 hazards for the SB1 core.
 1.1.2.2 11-Dec-2002  thorpej Sync with HEAD.
 1.1.2.1 15-Nov-2002  thorpej file sb1regs.h was added on branch nathanw_sa on 2002-12-11 06:11:05 +0000
 1.10 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.9 14-Dec-2009  matt Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.8 12-Aug-2009  matt If using the N32 ABI, define _BSD_JBSLOT_T as long long. Keep _JBLEN
constant since _BSD_JBSLOT_T will now change in size so _JBLEN doesn't
have to.
 1.7 05-Mar-2002  simonb branches: 1.7.120; 1.7.138;
Include <machine/cdefs.h> to select 32/64bit APIs.
 1.6 24-Apr-1999  simonb branches: 1.6.16; 1.6.20;
Nuke register and remove trailling white space.
 1.5 31-Jan-1999  castor branches: 1.5.4;
Remove genpubassym.cf stuff. The macro _MIPS_BSD_API allows selection of a
64-bit clean compilation model.
 1.4 15-Jan-1999  castor Avoid introducing new prefix '__JB' -- '_JB' is fine.
 1.3 14-Jan-1999  castor * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.2 16-Sep-1998  thorpej Need 87 longs for a jmp_buf now (we use sigcontext, which grew).
 1.1 20-Dec-1994  cgd make the definition of _JBLEN mach. dep. header-dependent.
 1.5.4.1 21-Jun-1999  thorpej Sync w/ -current.
 1.6.20.1 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.6.16.1 16-Mar-2002  jdolecek Catch up with -current.
 1.7.138.2 21-Aug-2009  matt Fix _JBLEN to be correct (why was i thinking mips64 has 64 fp regs?).
 1.7.138.1 16-Aug-2009  matt Kill use of _MIPS_BSD_ABI - switch to __mips_<abi>
Use device_t where appropriate.
Remove magic numbers.
 1.7.120.2 11-Mar-2010  yamt sync with head
 1.7.120.1 19-Aug-2009  yamt sync with head.
 1.33 30-Oct-2021  thorpej Adjust the rules for sigcontext visibility on MIPS:
- Define __HAVE_STRUCT_SIGCONTEXT if _KERNEL (because it's needed for
32-bit binary compatibility) or if the O32 ABI is active (because
that's the only ABI that ever used sigcontext for signal delivery).
- For _KERNEL, define a "struct sigcontext" suitable only for 32-bit
compatible signal delivery.
- For userspace, define a "struct sigcontext" appropriate for any ABI
if _LIBC is defined (it's used for setjmp / longjmp) or if O32 is
the active ABI (because it was part of the old BSD signal API).
 1.32 27-Oct-2021  thorpej Define __HAVE_STRUCT_SIGCONTEXT for _KERNEL in addition to _LIBC.
 1.31 26-Oct-2021  christos Merge all MD __sigaction14_sigtramp.c copies into one:
- sparc and sparc64 were not using version 0 sigcontext when there were
no arguments in the signal version. This was probably a bug.
- vax is using +1 the version numbers of the other archs.
- Only hppa was defining __LIBC12_SOURCE__ so it was getting a working
sigcontext before. all the other ports that supported sigcontext had
the compat code disabled.
[pointed out by thorpej, thanks!]
If we want to remove sigcontext support from userland at least now there
is less work to do so.
 1.30 24-Jan-2016  christos use namespace protected types.
 1.29 14-Dec-2009  matt branches: 1.29.22; 1.29.40;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.28 19-Nov-2008  ad Make the emulations, exec formats, coredump, NFS, and the NFS server
into modules. By and large this commit:

- shuffles header files and ifdefs
- splits code out where necessary to be modular
- adds module glue for each of the components
- adds/replaces hooks for things that can be installed at runtime
 1.27 11-Dec-2005  christos branches: 1.27.74; 1.27.78; 1.27.84; 1.27.86; 1.27.92;
merge ktrace-lwp.
 1.26 24-Jan-2005  drochner -remove definition of "struct sigframe" -- haven't found a use of it
(should fix build problems w/o COMPAT_16 reported by Markus W Kilbinger
per PR port-mips/29041 and by Havard Eidnes)
-further shuffle COMPAT_* conditionals to allow COMPAT_ULTRIX
w/o COMPAT_16
 1.25 20-Jan-2005  drochner restrict visibility of sigcontext* as much as it appears
sensible for now
XXX there is more cleanup needed to make COMPAT_ULTRIX build
w/o COMPAT_16)
 1.24 10-May-2004  drochner branches: 1.24.4;
SIGTRAMP_VALID() should not pollute the user namespace
 1.23 26-Mar-2004  drochner nothing cares about __HAVE_SIGINFO anymore, so nuke it
 1.22 25-Nov-2003  christos bye, bye _MCONTEXT_TO_SIGCONTEXT and vice versa.
 1.21 29-Oct-2003  christos first pass siginfo for mips
 1.20 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.19 28-Apr-2003  bjh21 branches: 1.19.2;
Add a new feature-test macro, _NETBSD_SOURCE. If this is defined
by the application, all NetBSD interfaces are made visible, even
if some other feature-test macro (like _POSIX_C_SOURCE) is defined.
<sys/featuretest.h> defined _NETBSD_SOURCE if none of _ANSI_SOURCE,
_POSIX_C_SOURCE and _XOPEN_SOURCE is defined, so as to preserve
existing behaviour.

This has two major advantages:
+ Programs that require non-POSIX facilities but define _POSIX_C_SOURCE
can trivially be overruled by putting -D_NETBSD_SOURCE in their CFLAGS.
+ It makes most of the #ifs simpler, in that they're all now ORs of the
various macros, rather than having checks for (!defined(_ANSI_SOURCE) ||
!defined(_POSIX_C_SOURCE) || !defined(_XOPEN_SOURCE)) all over the place.

I've tried not to change the semantics of the headers in any case where
_NETBSD_SOURCE wasn't defined, but there were some places where the
current semantics were clearly mad, and retaining them was harder than
correcting them. In particular, I've mostly normalised things so that
_ANSI_SOURCE gets you the smallest set of stuff, then _POSIX_C_SOURCE,
_XOPEN_SOURCE and _NETBSD_SOURCE in that order.

Tested by building for vax, encouraged by thorpej, and uncontested in
tech-userlevel for a week.
 1.18 20-Jan-2003  thorpej Fix typo in sigcontext conversion macros. From Christopher SEKIYA.
 1.17 18-Jan-2003  tsutsui Add '#define' for _MCONTEXT_TO_SIGCONTEXT().
 1.16 17-Jan-2003  thorpej Merge the nathanw_sa branch.
 1.15 05-Mar-2002  simonb Include <machine/cdefs.h> to select 32/64bit APIs.
 1.14 24-Apr-1999  simonb branches: 1.14.16; 1.14.20;
Nuke register and remove trailling white space.
 1.13 31-Jan-1999  castor branches: 1.13.4;
Remove genpubassym.cf stuff. The macro _MIPS_BSD_API allows selection of a
64-bit clean compilation model.
 1.12 14-Jan-1999  castor * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.11 14-Sep-1998  thorpej branches: 1.11.2;
sigset13_t -> int.
 1.10 13-Sep-1998  thorpej Make signal delivery work again.
 1.9 25-May-1998  kleink Protect against multiple inclusions.
 1.8 25-May-1998  kleink If any of _ANSI_SOURCE, _POSIX_C_SOURCE or _XOPEN_SOURCE are defined, don't
provide any identifiers other than sig_atomic_t.
 1.7 19-Mar-1996  jonathan Add eight 32-bit (XXX) words of reserved space to struct sigcontext,
for binary compatibilty with the pica port.
 1.6 18-Jan-1995  mellon break mullo and mulhi out of gp regs in sigcontext
 1.5 10-Jan-1995  jtc Only define sig_atomic_t when _ANSI_SOURCE is defined.
 1.4 26-Oct-1994  cgd new RCS ID format.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.11.2.1 19-Nov-1998  nisimura - Forgot to commit many files for vm_offset_t purge last Monday.
 1.13.4.1 21-Jun-1999  thorpej Sync w/ -current.
 1.14.20.2 16-Jan-2003  thorpej * Include <sys/sigtypes.h> rather than <sys/signal.h> in <sys/ucontext.h>.
* Define _UCONTEXT_TO_SIGCONTEXT() and _SIGCONTEXT_TO_UCONTEXT()
macros for converting a ucontext -> sigcontext and back again.
These macros in turn use machine-dependent macros _MCONTEXT_TO_SIGCONTEXT()
and _SIGCONTEXT_TO_MCONTEXT() provided by <machine/signal.h>.

The conversion process is not 100% accurate, but should be close enough.

Also note that the mcontext conversion may not be enough for all platforms
(m68k is a good example of this). These macros should be used only if
you really know what you're doing.
 1.14.20.1 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.14.16.1 16-Mar-2002  jdolecek Catch up with -current.
 1.19.2.5 04-Feb-2005  skrll Sync with HEAD.
 1.19.2.4 24-Jan-2005  skrll Sync with HEAD.
 1.19.2.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.19.2.2 18-Sep-2004  skrll Sync with HEAD.
 1.19.2.1 03-Aug-2004  skrll Sync with HEAD
 1.24.4.1 29-Apr-2005  kent sync with -current
 1.27.92.3 27-Aug-2009  matt For the kernel (since we only use it in compability with O32) define
sigcontext with ints. For libc, define the way we want to use it for
jmpbuf since that will be the only consumer of it.
 1.27.92.2 23-Aug-2009  matt In non-O32 kernels, make these syscalls return ENOSYS or sigexit(l, SIGILL)
when called by non-O32 programs. Marshall the 64bits registers to and from
their 32bit equivs and deal with FP differences.
 1.27.92.1 16-Aug-2009  matt Kill use of _MIPS_BSD_ABI - switch to __mips_<abi>
Use device_t where appropriate.
Remove magic numbers.
 1.27.86.1 19-Jan-2009  skrll Sync with HEAD.
 1.27.84.1 13-Dec-2008  haad Update haad-dm branch to haad-dm-base2.
 1.27.78.2 11-Mar-2010  yamt sync with head
 1.27.78.1 04-May-2009  yamt sync with head.
 1.27.74.1 17-Jan-2009  mjf Sync with HEAD.
 1.29.40.1 19-Mar-2016  skrll Sync with HEAD
 1.29.22.1 03-Dec-2017  jdolecek update from HEAD
 1.2 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.1 23-Jul-2014  alnsn branches: 1.1.2; 1.1.6;
Rename sljitarch.h to sljit_machdep.h.
 1.1.6.2 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.1.6.1 23-Jul-2014  tls file sljit_machdep.h was added on branch tls-maxphys on 2014-08-20 00:03:12 +0000
 1.1.2.2 10-Aug-2014  tls Rebase.
 1.1.2.1 23-Jul-2014  tls file sljit_machdep.h was added on branch tls-earlyentropy on 2014-08-10 06:54:02 +0000
 1.5 23-Jul-2014  alnsn Rename sljitarch.h to sljit_machdep.h.
 1.4 22-Jul-2014  alnsn Define SLJIT_CACHE_FLUSH() for mips.
 1.3 17-Nov-2013  alnsn branches: 1.3.2;
Always define SLJIT_CACHE_FLUSH(), start include guards with '_' and use _LP64 guard.
 1.2 25-Nov-2012  alnsn branches: 1.2.2; 1.2.4; 1.2.6;
EVPMIPS -> MIPS in include guard.
 1.1 25-Nov-2012  alnsn Add sljitarch.h to all mips machines.
 1.2.6.3 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.2.6.2 25-Feb-2013  tls resync with head
 1.2.6.1 25-Nov-2012  tls file sljitarch.h was added on branch tls-maxphys on 2013-02-25 00:28:51 +0000
 1.2.4.1 18-May-2014  rmind sync with head
 1.2.2.3 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.2.2.2 16-Jan-2013  yamt sync with (a bit old) head
 1.2.2.1 25-Nov-2012  yamt file sljitarch.h was added on branch yamt-pagecache on 2013-01-16 05:33:01 +0000
 1.3.2.1 10-Aug-2014  tls Rebase.
 1.5 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.4 28-Apr-2008  martin branches: 1.4.18; 1.4.22; 1.4.28; 1.4.30;
Remove clause 3 and 4 from TNF licenses
 1.3 03-Dec-2007  ad branches: 1.3.14; 1.3.16; 1.3.18;
Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.
 1.2 21-Dec-2006  yamt branches: 1.2.6; 1.2.22; 1.2.24; 1.2.30;
merge yamt-splraiseipl branch.

- finish implementing splraiseipl (and makeiplcookie).
http://mail-index.NetBSD.org/tech-kern/2006/07/01/0000.html
- complete workqueue(9) and fix its ipl problem, which is reported
to cause audio skipping.
- fix netbt (at least compilation problems) for some ports.
- fix PR/33218.
 1.1 25-May-2003  tsutsui branches: 1.1.18; 1.1.48; 1.1.50;
Prepare common routines for MIPS generic software interrupt.
 1.1.50.1 22-Sep-2006  yamt fix softintr for following ports. (hopefully)
hpcmips
evbmips
algor
arc
ews4800mips
newsmips
 1.1.48.1 12-Jan-2007  ad Sync with head.
 1.1.18.2 07-Dec-2007  yamt sync with head
 1.1.18.1 30-Dec-2006  yamt sync with head.
 1.2.30.1 08-Dec-2007  mjf Sync with HEAD.
 1.2.24.1 09-Jan-2008  matt sync with HEAD
 1.2.22.1 09-Dec-2007  jmcneill Sync with HEAD.
 1.2.6.2 03-Dec-2007  ad Sync with HEAD.
 1.2.6.1 15-Jul-2007  ad Get pmax working.
 1.3.18.1 16-May-2008  yamt sync with head.
 1.3.16.1 18-May-2008  yamt sync with head.
 1.3.14.1 02-Jun-2008  mjf Sync with HEAD.
 1.4.30.1 05-Mar-2011  bouyer Sync with HEAD
 1.4.28.1 06-Jun-2011  jruoho Sync with HEAD.
 1.4.22.1 05-Mar-2011  rmind sync with head
 1.4.18.1 06-Feb-2010  matt <mips/softintr.h> is no longer needed.
 1.2 11-Dec-2021  mrg remove clause 3 from all my licenses that aren't conflicting with
another copyright claim line. again. (i did this in 2008 and then
did not update all of my personal templates.)
 1.1 15-Aug-2020  mrg move stacktrace_subr() from trap.c into new mips_stacktrace.c so
it can be shared between ddb, other mips kernel components (see
locore), and an upcoming crash(8) port.

remove second copy of kdbpeek() (hidden by old DDB_TRACE
option, but they're functionally equivalent.)

tested on octeon.

ok simonb@
 1.31 17-Jul-2011  joerg Retire varargs.h support. Move machine/stdarg.h logic into MI
sys/stdarg.h and expect compiler to provide proper builtins, defaulting
to the GCC interface. lint still has a special fallback.
Reduce abuse of _BSD_VA_LIST_ by defining __va_list by default and
derive va_list as required by standards.
 1.30 03-Jul-2011  mrg add GCC 4.5 support.
 1.29 14-Dec-2009  matt Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.28 21-Jun-2008  gmcgarry branches: 1.28.14;
Add stdargs support for pcc.
 1.27 27-Aug-2006  matt branches: 1.27.56; 1.27.60; 1.27.62; 1.27.64;
The prohibition about 64bit ABIs only applies to pre-gcc3 so move it there.
 1.26 11-Dec-2005  christos branches: 1.26.4; 1.26.8;
merge ktrace-lwp.
 1.25 25-Oct-2003  mycroft branches: 1.25.16;
Update for GCC3 (basically, use the __builtin_va_* implementation).
 1.24 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.23 28-Apr-2003  bjh21 branches: 1.23.2;
Add a new feature-test macro, _NETBSD_SOURCE. If this is defined
by the application, all NetBSD interfaces are made visible, even
if some other feature-test macro (like _POSIX_C_SOURCE) is defined.
<sys/featuretest.h> defined _NETBSD_SOURCE if none of _ANSI_SOURCE,
_POSIX_C_SOURCE and _XOPEN_SOURCE is defined, so as to preserve
existing behaviour.

This has two major advantages:
+ Programs that require non-POSIX facilities but define _POSIX_C_SOURCE
can trivially be overruled by putting -D_NETBSD_SOURCE in their CFLAGS.
+ It makes most of the #ifs simpler, in that they're all now ORs of the
various macros, rather than having checks for (!defined(_ANSI_SOURCE) ||
!defined(_POSIX_C_SOURCE) || !defined(_XOPEN_SOURCE)) all over the place.

I've tried not to change the semantics of the headers in any case where
_NETBSD_SOURCE wasn't defined, but there were some places where the
current semantics were clearly mad, and retaining them was harder than
correcting them. In particular, I've mostly normalised things so that
_ANSI_SOURCE gets you the smallest set of stuff, then _POSIX_C_SOURCE,
_XOPEN_SOURCE and _NETBSD_SOURCE in that order.

Tested by building for vax, encouraged by thorpej, and uncontested in
tech-userlevel for a week.
 1.22 05-Mar-2002  simonb The 64-bit safe, ILP32 o32 model is safe with the current stdarg
implementation.
 1.21 18-Aug-2001  simonb branches: 1.21.6;
Fix lint problem introduced in last change - if `lint' is defined,
#define away __alignof__. Still produces some warnings, but at least
they're not fatal anymore.

Problem noted by Rafal Boni in private mail.
 1.20 17-Aug-2001  simonb Fix va_arg() problem when adjusting argument pointer when a structure is
passed which is larger than an int but has int alignment. As well as
fixing the described problem, this is the same way it is handled in the
Irix and Ultrix header files.

Problem and suggested solution by Uros Prestor in port-mips mailling
list.
 1.19 19-Feb-2000  mycroft branches: 1.19.8;
Add some CONSTCONDs to make lint happier.
 1.18 03-Feb-2000  kleink Add a C99-style va_copy macro.
 1.17 08-Jun-1999  nisimura branches: 1.17.2;
- Exterminate haunted evil soul of MIPS va_arg(). Verified OK with
either endian. Not a perfect solution which would be revealed on
a certain condition when va_arg() is applied to magical struct
arguments passed by value. format_bytes() is now saved. With the
help from Noriyuki Soda and Masanari Tsubai.
 1.16 03-May-1999  christos Define __builtin_*() for lint
 1.15 24-Apr-1999  simonb Nuke register and remove trailling white space.
 1.14 22-Jan-1999  mycroft branches: 1.14.4;
Use __builtin_next_arg(). Fixed PR 6862.
 1.13 11-Sep-1998  jonathan Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.

* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.
 1.12 27-Jul-1998  mycroft Delint.
 1.11 26-Feb-1996  jonathan branches: 1.11.16;
Revert pmax stdarg.h and varargs.h to versions from 1995-11-13. Those
versions work correctly; at some point between then and the immediately
preceding revisions, the "stylistic" changes to one (or both) stdarg.h
and varargs.h broke passing doubles to printf().
 1.10 25-Dec-1995  mycroft Stylistic changes.
 1.9 25-Dec-1995  mycroft Stylistic changes.
 1.8 25-Dec-1995  mycroft Update for GCC 2.7, and fix bugs.
 1.7 28-Mar-1995  jtc KERNEL -> _KERNEL
 1.6 28-Jan-1995  jtc ANSI says that <stdarg.h>'s va_end macro must expand to a void expression.
For consistancy, I'm changing <varargs.h> too.
 1.5 26-Oct-1994  cgd new RCS ID format.
 1.4 15-Oct-1994  cgd make <stdarg.h> a symlink, and clean up ports' stdarg.h and varargs.h files.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.11.16.1 01-Feb-1999  cgd pull up revs 1.12-1.14 from trunk (PR#6862). (mycroft)
 1.14.4.1 21-Jun-1999  thorpej Sync w/ -current.
 1.17.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.19.8.2 16-Mar-2002  jdolecek Catch up with -current.
 1.19.8.1 25-Aug-2001  thorpej Merge Aug 24 -current into the kqueue branch.
 1.21.6.2 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.21.6.1 18-Aug-2001  nathanw file stdarg.h was added on branch nathanw_sa on 2002-04-01 07:41:00 +0000
 1.23.2.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.23.2.2 18-Sep-2004  skrll Sync with HEAD.
 1.23.2.1 03-Aug-2004  skrll Sync with HEAD
 1.25.16.1 30-Dec-2006  yamt sync with head.
 1.26.8.1 03-Sep-2006  yamt sync with head.
 1.26.4.1 09-Sep-2006  rpaulo sync with head
 1.27.64.1 27-Jun-2008  simonb Sync with head.
 1.27.62.1 23-Jun-2008  wrstuden Sync w/ -current. 34 merge conflicts to follow.
 1.27.60.2 11-Mar-2010  yamt sync with head
 1.27.60.1 04-May-2009  yamt sync with head.
 1.27.56.1 29-Jun-2008  mjf Sync with HEAD.
 1.28.14.1 16-Aug-2009  matt Kill use of _MIPS_BSD_ABI - switch to __mips_<abi>
Use device_t where appropriate.
Remove magic numbers.
 1.7 19-Dec-2018  maxv Remove compat_svr4 and compat_svr4_32, as discussed on tech-kern@ recently,
but also as discussed several times in the past.
 1.6 30-Jul-2017  maxv branches: 1.6.2; 1.6.4;
Remove references to COMPAT_IRIX - does not exist anymore.

I believe svr4_machdep.h should be removed when the option is not
implemented on the target architecture; and we should also remove the
associated md.* entries.
 1.5 28-Apr-2008  martin branches: 1.5.44; 1.5.64;
Remove clause 3 and 4 from TNF licenses
 1.4 17-Aug-2006  christos branches: 1.4.56; 1.4.58; 1.4.60;
Fix all the -D*DEBUG* code that it was rotting away and did not even compile.
Mostly from Arnaud Lacombe, many thanks!
 1.3 22-Jan-2003  rafal branches: 1.3.18; 1.3.32; 1.3.36;
LWP'ify the svr4_mcontext stuff.
 1.2 05-Mar-2002  simonb ANSIfy.
 1.1 28-Nov-2001  manu branches: 1.1.2; 1.1.4;
Added support for COMPAT_IRIX
 1.1.4.3 16-Mar-2002  jdolecek Catch up with -current.
 1.1.4.2 10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.1.4.1 28-Nov-2001  thorpej file svr4_machdep.h was added on branch kqueue on 2002-01-10 19:46:02 +0000
 1.1.2.3 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.1.2.2 08-Jan-2002  nathanw Catch up to -current.
 1.1.2.1 28-Nov-2001  nathanw file svr4_machdep.h was added on branch nathanw_sa on 2002-01-08 00:26:17 +0000
 1.3.36.1 03-Sep-2006  yamt sync with head.
 1.3.32.1 09-Sep-2006  rpaulo sync with head
 1.3.18.1 30-Dec-2006  yamt sync with head.
 1.4.60.1 16-May-2008  yamt sync with head.
 1.4.58.1 18-May-2008  yamt sync with head.
 1.4.56.1 02-Jun-2008  mjf Sync with HEAD.
 1.5.64.1 28-Aug-2017  skrll Sync with HEAD
 1.5.44.1 03-Dec-2017  jdolecek update from HEAD
 1.6.4.1 10-Jun-2019  christos Sync with HEAD
 1.6.2.1 26-Dec-2018  pgoyette Sync with HEAD, resolve a few conflicts
 1.11 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.10 23-May-2013  christos add generic copyrights so FreeBSD can use them.
 1.9 20-Feb-2011  matt branches: 1.9.4; 1.9.14;
Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.8 11-Dec-2005  christos branches: 1.8.96; 1.8.106;
merge ktrace-lwp.
 1.7 06-Nov-2004  christos Don't use "int" to represent lengths; this is what size_t is for. This
does not change the ABI since we don't have 64 bit mips yet.
 1.6 11-Sep-2003  kleink __{BEGIN,END}_DECLS-wrap prototypes.
 1.5 19-Jul-2002  simonb branches: 1.5.6;
White space nits, add a #endif comment.
 1.4 05-Mar-2002  simonb branches: 1.4.6;
ANSIfy.
 1.3 06-Jan-1999  nisimura branches: 1.3.22; 1.3.26;
- Complete vm_offset_t purge for mips processor.
- bzero() -> memset() and bcopy() -> memcpy().
- Garbage collection in trap.c and db_interface.c.
 1.2 25-Feb-1998  perry branches: 1.2.4;
change second parm of sysarch() from char * to void *
 1.1 09-Jun-1997  jonathan Add sys_sysarch() calls for the standard mips userspace cache-control calls.
 1.2.4.1 19-Nov-1998  nisimura - Forgot to commit many files for vm_offset_t purge last Monday.
 1.3.26.2 01-Aug-2002  nathanw Catch up to -current.
 1.3.26.1 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.3.22.2 06-Sep-2002  jdolecek sync kqueue branch with HEAD
 1.3.22.1 16-Mar-2002  jdolecek Catch up with -current.
 1.4.6.1 21-Jul-2002  gehenna catch up with -current.
 1.5.6.4 14-Nov-2004  skrll Sync with HEAD.
 1.5.6.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.5.6.2 18-Sep-2004  skrll Sync with HEAD.
 1.5.6.1 03-Aug-2004  skrll Sync with HEAD
 1.8.106.1 06-Jun-2011  jruoho Sync with HEAD.
 1.8.96.2 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.8.96.1 15-May-2010  matt Add kernel support for MIPS TLS. Use rdhwr rt, $29 as defined by the MIPS
TLS spec so that Linux MIPS binaries will work. Use sysarch(MIPS_TINFOSET, v)
to set the pointer.
 1.9.14.1 23-Jun-2013  tls resync from head
 1.9.4.1 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.19 06-Jun-2015  matt Add missing but now defined trap types. (use define<tab> consistently)
 1.18 16-Aug-2011  matt branches: 1.18.12; 1.18.30;
Add support for the MIPS DSP ASE (as a second PCU).
 1.17 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.16 08-Feb-2011  rmind Remove clause 3 (UCB advertising clause) from the University of Utah
copyright. Confirmed by Mike Hibler, mike at cs.utah.edu - thanks!
Also, merge UCB and Utah copyright texts back into one, as they
originally were.

Extra verification by snj@.
 1.15 11-Dec-2005  christos branches: 1.15.96; 1.15.100; 1.15.106; 1.15.108;
merge ktrace-lwp.
 1.14 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.13 15-Sep-2000  jeffs branches: 1.13.24;
Handle R4K trap faults in user mode like overflows (deliver SIGFPE). This
prevents a panic running crashme. Better comment for VCE define.
 1.12 14-Jan-1999  castor branches: 1.12.8;
* Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.11 06-Jan-1999  nisimura - Complete vm_offset_t purge for mips processor.
- bzero() -> memset() and bcopy() -> memcpy().
- Garbage collection in trap.c and db_interface.c.
 1.10 24-Oct-1998  jonathan Cleanup kdbpeek() definition as noted in PR port-mips/5252.
 1.9 01-Oct-1998  jonathan branches: 1.9.2;
More patches for ARC from Noriyuki Soda:
* commit isapnpvar.h changes required for ARC to support plain isa.
* fixup mistake over mips/include/cpuregs.h.
* mips/mips_machdep.c:
set L2 cache-size for arc, cleanup use of L2cache present
vs L2 cache-size variables. check for no L2 cache on kernels
configured to require one. misc cleanups.
* mips/mpis/trap.c: more locore stack-traceback label cleanup.
XXX Locore callbacks for mips3, mips4, r4600 cacheflush need more work.
 1.8 19-May-1998  simonb Change external declaration of kdbpeek to match reality.
 1.7 26-Mar-1998  jonathan * Create /sys/arch/mips/include/intr.h, with extern declaration of
interrupt-callout vector from mips locore dispatch code to port code.
* Move branch-emulation declaration to mips/include/trap.h.
* Garbage-collect pmax/pmax/trap.h.
Not needed now pmax/pmax_trap.c is gone, and after above tidy-up.
 1.6 24-Mar-1996  jonathan Change pmax T_USER bit (software only) to be 0x20, the same as the
Pica port. (The r4000 CPU used in the pica has more hardware execption types.)
 1.5 19-Mar-1996  jonathan Add trap definitions added for the r4000 port.
Note: T_USER is different in the pmax and pica ports!
 1.4 26-Oct-1994  cgd new RCS ID format.
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.9.2.1 15-Oct-1998  nisimura - cpuregs.h was modifed a bit, then renamed with cpuarch.h.
- mips_cpu.h has gone.
- CPU's register mnemonics in regdef.h is now a part of asm.h.
 1.12.8.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.13.24.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.13.24.2 18-Sep-2004  skrll Sync with HEAD.
 1.13.24.1 03-Aug-2004  skrll Sync with HEAD
 1.15.108.2 05-Mar-2011  bouyer Sync with HEAD
 1.15.108.1 17-Feb-2011  bouyer Sync with HEAD
 1.15.106.1 06-Jun-2011  jruoho Sync with HEAD.
 1.15.100.1 05-Mar-2011  rmind sync with head
 1.15.96.2 23-Dec-2011  matt Add various new exceptions from MTE/32R2/64R2/DSP.
 1.15.96.1 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.18.30.1 06-Jun-2015  skrll Sync with HEAD
 1.18.12.1 03-Dec-2017  jdolecek update from HEAD
 1.78 28-Mar-2023  nakayama Add missing PRIuBUSSIZE to mips.
 1.77 07-Jul-2022  martin branches: 1.77.4;
Add PRIuVSIZE
 1.76 15-May-2021  simonb The MIPS O64 ABI uses full 64-bit FP regs.
 1.75 29-Mar-2021  simonb branches: 1.75.2; 1.75.4;
Provide vm_offset_t and vm_size_t typedefs - used by dtrace.
 1.74 23-Jan-2021  christos branches: 1.74.2;
Document via __HAVE_BUS_SPACE_8 platforms that implement bus_space_*_8
 1.73 06-Dec-2020  christos don't expose vaddr_t to userland.
 1.72 17-Aug-2020  mrg branches: 1.72.2;
port crash(8) to mips. (most of the kernel side.)

- expose parts of _KERNEL to _KMEMUSER as well
- hide more things for _KERNEL
- avoid DB_MACHINE_COMMANDS in crash(8)
- XXX add mips_label_t for !_KERNEL and use it in the pcb to
avoid conflicting with the ddb/crash one
- enable dumppcb

some changes to make stack trace fail instead of SEGV and
the userland changes to crash itself not part of this change.
 1.71 30-Jul-2020  skrll Sort the #define __HAVEs. NFCI.
 1.70 30-Apr-2020  skrll G/C __HAVE_AST_PERPROC
 1.69 22-Mar-2020  ad Temporarily mark hppa, mips, powerpc and riscv with __HAVE_UNLOCKED_PMAP,
for the benefit of UVM.

These need some pmap changes to support concurrent faults on the same
object. I have changes to do just that, but they're a work in progress.
 1.68 06-Apr-2019  thorpej Overhaul the API used to fetch and store individual memory cells in
userspace. The old fetch(9) and store(9) APIs (fubyte(), fuword(),
subyte(), suword(), etc.) are retired and replaced with new ufetch(9)
and ustore(9) APIs that can return proper error codes, etc. and are
implemented consistently across all platforms. The interrupt-safe
variants are no longer supported (and several of the existing attempts
at fuswintr(), etc. were buggy and not actually interrupt-safe).

Also augmement the ucas(9) API, making it consistently available on
all plaforms, supporting uniprocessor and multiprocessor systems, even
those that do not have CAS or LL/SC primitives.

Welcome to NetBSD 8.99.37.
 1.67 09-Dec-2017  christos branches: 1.67.4;
provide 32 and 64 bit register struct definitions.
 1.66 27-Jan-2017  christos remove __HAVE_COMPAT_NETBSD32
 1.65 26-Jan-2017  christos provide __HAVE_COMPAT_NETBSD32 and fix multiple include protection consistently.
 1.64 11-Jul-2016  matt branches: 1.64.2; 1.64.4;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.63 24-Jan-2016  christos expose label_t for _KMEMUSER
 1.62 24-Jan-2016  christos expose __fpregister_t too, merge definitions.
 1.61 23-Jan-2016  christos expose the kernel types for standalone code.
 1.60 23-Jan-2016  christos Hide {p,v}{addr,size}_t and register_t (and a couple more types that
are machine-specific) from userland unless _KERNEL/_KMEMUSER and a
new _KERNTYPES variables is defined. The _KERNTYPES should be fixed
for many subsystems that should not be using it (rump)...
 1.59 27-Aug-2015  pooka Fix PTHREAD_FOO_INITIALIZER for C++ by not using volatile in the relevant
pthread types in C++ builds, attempt 2.

The problem with attempt 1 was making assumptions of what the MD
__cpu_simple_lock_t (declared volatile) looks like. To get a same type
except non-volatile, we change the MD type to __cpu_simple_lock_nv_t
and typedef __cpu_simple_lock_t as a volatile __cpu_simple_lock_nv_t.
IMO, __cpu_simple_lock_t should not be volatile at all, but changing it
now is too risky.

Fixes at least Rumprun w/ gcc 5.1/5.2. Furthermore, the mpd application
(and possibly others) will no longer require NetBSD-specific patches.

Tested: build.sh for i386, Rumprun for x86_64 w/ gcc 5.2.

Based on the patch from Christos in lib/49989.
 1.58 11-Jun-2015  matt Add tlb_asid_t
 1.57 10-Jun-2015  matt Transition from __cpuset_t to kcpuset_t *. This brings the local pmap one
step closer to uvm/pmap, its eventual replacement. Tested on ERLITE MP kernel.
 1.56 06-Jun-2015  macallan introduce PRIxCPUSET to deal with 32bit __cpuset_t on o32
 1.55 29-Mar-2015  macallan use 32bit __cpuset_t in o32 kernels
ok matt@
 1.54 04-Jan-2014  dsl branches: 1.54.6;
Remove __HAVE_PROCESS_XFPREGS and add the extra parameter for the size
of the fp save area to all the process_read_fpregs() and
process_write_fpregs() functions.
None of the functions have been modified to use the new parameters.
The size is set for all the writes, but some of the arch-specific reads
just pass NULL.
The amd64 (and i386) need variable sized fp register save areas in order
to support AVX and other enhanced register areas.
These functions are rarely called - so the extra argument won't matter.
 1.53 16-Aug-2011  matt branches: 1.53.2; 1.53.12; 1.53.16;
Add support for the MIPS DSP ASE (as a second PCU).
 1.52 12-Jun-2011  rmind Welcome to 5.99.53! Merge rmind-uvmplock branch:

- Reorganize locking in UVM and provide extra serialisation for pmap(9).
New lock order: [vmpage-owner-lock] -> pmap-lock.

- Simplify locking in some pmap(9) modules by removing P->V locking.

- Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share
the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs).

- Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner.
Add TLBSTATS option for x86 to collect statistics about TLB shootdowns.

- Unify /dev/mem et al in MI code and provide required locking (removes
kernel-lock on some ports). Also, avoid cache-aliasing issues.

Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches
formed the core changes of this branch.
 1.51 29-Apr-2011  matt branches: 1.51.2;
define<space> -> define<tab>
 1.50 15-Mar-2011  matt Add MIPS TLS support.
 1.49 24-Feb-2011  joerg Allow storing and receiving the LWP private pointer via ucontext_t
on all platforms except VAX and IA64. Add fast access via register for
AMD64, i386 and SH3 ports. Use this fast access in libpthread to replace
the stack based pthread_self(). Implement skeleton support for Alpha,
HPPA, PowerPC, SPARC and SPARC64, but leave it disabled.

Ports that support this feature provide __HAVE____LWP_GETPRIVATE_FAST in
machine/types.h and a corresponding __lwp_getprivate_fast in
machine/mcontext.h.

This material is based upon work partially supported by
The NetBSD Foundation under a contract with Joerg Sonnenberger.
 1.48 20-Feb-2011  rmind Minor fix of previous: remove __SWAP_BROKEN (it is no more in -current).
 1.47 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.46 22-Dec-2010  matt branches: 1.46.2; 1.46.4;
Add a define __HAVE_CPU_DATA_FIRST which means that cpu_data is the first
member in struct cpu_info.
 1.45 14-Dec-2009  matt branches: 1.45.4;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.44 21-Oct-2009  rmind Remove uarea swap-out functionality:

- Addresses the issue described in PR/38828.
- Some simplification in threading and sleepq subsystems.
- Eliminates pmap_collect() and, as a side note, allows pmap optimisations.
- Eliminates XS_CTL_DATA_ONSTACK in scsipi code.
- Avoids few scans on LWP list and thus potentially long holds of proc_lock.
- Cuts ~1.5k lines of code. Reduces amd64 kernel size by ~4k.
- Removes __SWAP_BROKEN cases.

Tested on x86, mips, acorn32 (thanks <mpumford>) and partly tested on
acorn26 (thanks to <bjh21>).

Discussed on <tech-kern>, reviewed by <ad>.
 1.43 29-Nov-2007  ad branches: 1.43.18; 1.43.36;
__HAVE_ATOMIC64_OPS if 64-bit
 1.42 24-Dec-2005  perry branches: 1.42.30; 1.42.42; 1.42.48; 1.42.50; 1.42.56;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.
 1.41 11-Dec-2005  christos merge ktrace-lwp.
 1.40 18-Jan-2004  martin branches: 1.40.16;
Do not export __HAVE_RAS to userland. Applications are supposed to try
rasctl() and detect failure with EOPNOTSUPP.
 1.39 26-Sep-2003  nathanw Move __cpu_simple_lock_t and __SIMPLELOCK_{UN,}LOCKED to machine/types.h
so that they can be used in a namespace-friendly way.
 1.38 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.37 28-Apr-2003  bjh21 branches: 1.37.2;
Add a new feature-test macro, _NETBSD_SOURCE. If this is defined
by the application, all NetBSD interfaces are made visible, even
if some other feature-test macro (like _POSIX_C_SOURCE) is defined.
<sys/featuretest.h> defined _NETBSD_SOURCE if none of _ANSI_SOURCE,
_POSIX_C_SOURCE and _XOPEN_SOURCE is defined, so as to preserve
existing behaviour.

This has two major advantages:
+ Programs that require non-POSIX facilities but define _POSIX_C_SOURCE
can trivially be overruled by putting -D_NETBSD_SOURCE in their CFLAGS.
+ It makes most of the #ifs simpler, in that they're all now ORs of the
various macros, rather than having checks for (!defined(_ANSI_SOURCE) ||
!defined(_POSIX_C_SOURCE) || !defined(_XOPEN_SOURCE)) all over the place.

I've tried not to change the semantics of the headers in any case where
_NETBSD_SOURCE wasn't defined, but there were some places where the
current semantics were clearly mad, and retaining them was harder than
correcting them. In particular, I've mostly normalised things so that
_ANSI_SOURCE gets you the smallest set of stuff, then _POSIX_C_SOURCE,
_XOPEN_SOURCE and _NETBSD_SOURCE in that order.

Tested by building for vax, encouraged by thorpej, and uncontested in
tech-userlevel for a week.
 1.36 03-Nov-2002  thorpej In the _MIPS_PADDR_T_64BIT case, only use "unsigned long long" if _LP64
is not defined.
 1.35 03-Nov-2002  nisimura Retire __HAVE_MD_RUNQUEUE from MD types.h and remove
setrunqueue/remrunqueue from locore.S. C codes are
compiled a bit shorter and provide better DIAGNOSTICs.
 1.34 02-Nov-2002  thorpej Make register_t == long long for N32, and == long for everthing else.
Use register_t in label_t.
 1.33 22-Sep-2002  simonb Use "#define\t" instead of "#define ".
 1.32 22-Sep-2002  gmcgarry Add __HAVE_MD_RUNQUEUE flag for MD code to override MI run queue primitives.
 1.31 28-Aug-2002  gmcgarry RAS support for MIPS. Tested on R3000.
 1.30 05-Mar-2002  simonb branches: 1.30.6;
Change a MIPS3 check to a MIPS3_PLUS check (XXX - still bogus!).
 1.29 28-Feb-2002  simonb Use "#define<tab>".
 1.28 28-Apr-2001  kleink branches: 1.28.2; 1.28.8;
* Move definitions of exact-width integer types from <machine/types.h>
to <sys/types.h> and <sys/stdint.h>.
* Add a new C99 <stdint.h> header, which provides integer types of
explicit width, related limits and integer constant macros.
* Extend <inttypes.h> to provide <stdint.h> definitions and format
macros for printf() and scanf().
* Add C99 strtoimax() and strtoumax() functions.
* Use the latter within scanf().
* Add C99 %j, %t and %z printf()/scanf() conversions for
intmax_t, pointer-type and size_t arguments.
 1.27 16-Jan-2001  thorpej branches: 1.27.2;
New syscall entry implementation based on the Alpha version
as hacked by mycroft.
- Use syscall_intern() to give a process a plain or fancy
syscall based on ktrace flags.
- Avoid copying from the trapframe into a local array as much
as possible.

Yields roughly 5% improvement on a 25MHz R3000 (DECstation 5000/200)
on a simple syscall benchmark.

There's still some work that can be done using __HAVE_MINIMAL_EMUL.
 1.26 14-Jan-2001  thorpej Define __HAVE_AST_PERPROC.
 1.25 03-Jan-2001  takemura replace 'long long' with int64_t to compile stand alone program with
compiler other than GCC.
 1.24 09-Jun-2000  soda make paddr_t 64bit on arc port by introducing _MIPS_PADDR_T_64BIT.
 1.23 06-Jun-2000  soren Add rnd(4) glue for the MIPS3 cycle counter.
 1.22 22-Feb-2000  soda branches: 1.22.2;
mips is now vm_offset_t/vm_size_t clean
 1.21 09-Dec-1999  castor Fix typo on _MIPS_BSD_API switch.
 1.20 24-Apr-1999  simonb branches: 1.20.2; 1.20.8;
Nuke register and remove trailling white space.
 1.19 31-Jan-1999  castor branches: 1.19.4;
Remove genpubassym.cf stuff. The macro _MIPS_BSD_API allows selection of a
64-bit clean compilation model.
 1.18 14-Jan-1999  castor * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.17 06-Jan-1999  nisimura - Complete vm_offset_t purge for mips processor.
- bzero() -> memset() and bcopy() -> memcpy().
- Garbage collection in trap.c and db_interface.c.
 1.16 13-Aug-1998  eeh branches: 1.16.2;
Merge paddr_t changes into the main branch.
 1.15 14-Jun-1998  kleink branches: 1.15.2;
GC the unused `physadr' type, which was not able to hold a complete physical
address on 2 architectures anyhow. Also, move the definition of the `label_t'
type inside _KERNEL protection, since it is specific to the in-kernel
setjmp()/longjmp() implementations.
 1.14 05-Nov-1997  thorpej Mark uses of long long with /* LONGLONG */ for lint. From
Chris Demetriou <cgd@pa.dec.com>.
 1.13 15-Jun-1997  mhitch branches: 1.13.8;
From Toru Nishimura: _FORKBRAINDAMAGE is gone, user process entered through
proc_trampoline().
 1.12 09-Apr-1996  jonathan Fixes for -Wall -Wmissing-prototypes:
Do not define __BDEVSW_DUMP_OLD_TYPE, as it breaks prototyping
of device dump functions, and should be port-dependent in any case.
The pmax 4.4bsd/pmax-derived drivers are being fixed, and the pica port
uses the MI scsi drivers already.
 1.11 09-Dec-1995  mycroft Define __FORK_BRAINDAMAGE.
 1.10 06-Jul-1995  cgd add <sys/cdefs.h> inclusions. namsspace-protect physadr, label_t
def'ns against _POSIX_SOURCE and _ANSI_SOURCE.
 1.9 28-Jun-1995  cgd remove unused cpu_exec() definitions. moved "broken swap" markers, for
ports that still need it, to types.h.
 1.8 26-Jun-1995  cgd define __BDEVSW_DUMP_OLD_TYPE for ports where it's true. clean up
some m68k ports inclusion of common header.
 1.7 26-Oct-1994  cgd new RCS ID format.
 1.6 20-Oct-1994  cgd update for new syscall args description mechanism
 1.5 20-Jul-1994  cgd define __BIT_TYPES_DEFINED__ for compatibility with things like BIND and nvi
 1.4 27-May-1994  glass branches: 1.4.2;
bsd 4.4-lite pmax port as ported to NetBSD
 1.3 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.2 14-Mar-1994  cgd add basic integral types (a la sparc port) that new nvi wants.
mark old 'basic integral types' as XXX -- they should be squished
when whoever gets this port working.
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.4.2.1 20-Jul-1994  cgd update from trunk.
 1.13.8.1 05-Nov-1997  thorpej Update from trunk: Mark usese of long long with /* LONGLONG */ for lint.
 1.15.2.2 12-Aug-1998  eeh Protect XOPEN and POSIX code from vm_offset_t, paddr_t, vaddr_t, vm_size_t, psize_t, and vsize_t.
 1.15.2.1 30-Jul-1998  eeh Split vm_offset_t and vm_size_t into paddr_t, psize_t, vaddr_t, and vsize_t.
 1.16.2.1 19-Nov-1998  nisimura - Forgot to commit most important changes.
 1.19.4.1 21-Jun-1999  thorpej Sync w/ -current.
 1.20.8.1 27-Dec-1999  wrstuden Pull up to last week's -current.
 1.20.2.3 18-Jan-2001  bouyer Sync with head (for UBC+NFS fixes, mostly).
 1.20.2.2 05-Jan-2001  bouyer Sync with HEAD
 1.20.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.22.2.1 22-Jun-2000  minoura Sync w/ netbsd-1-5-base.
 1.27.2.1 21-Jun-2001  nathanw Catch up to -current.
 1.28.8.5 11-Nov-2002  nathanw Catch up to -current
 1.28.8.4 18-Oct-2002  nathanw Catch up to -current.
 1.28.8.3 17-Sep-2002  nathanw Catch up to -current.
 1.28.8.2 01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.28.8.1 28-Apr-2001  nathanw file types.h was added on branch nathanw_sa on 2002-04-01 07:41:00 +0000
 1.28.2.3 10-Oct-2002  jdolecek sync kqueue with -current; this includes merge of gehenna-devsw branch,
merge of i386 MP branch, and part of autoconf rototil work
 1.28.2.2 06-Sep-2002  jdolecek sync kqueue branch with HEAD
 1.28.2.1 16-Mar-2002  jdolecek Catch up with -current.
 1.30.6.1 31-Aug-2002  gehenna catch up with -current.
 1.37.2.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.37.2.2 18-Sep-2004  skrll Sync with HEAD.
 1.37.2.1 03-Aug-2004  skrll Sync with HEAD
 1.40.16.2 07-Dec-2007  yamt sync with head
 1.40.16.1 21-Jun-2006  yamt sync with head.
 1.42.56.1 08-Dec-2007  mjf Sync with HEAD.
 1.42.50.1 09-Jan-2008  matt sync with HEAD
 1.42.48.1 03-Dec-2007  joerg Sync with HEAD.
 1.42.42.1 18-Jul-2007  matt Deal with n32/n64 ABIs too.
 1.42.30.2 03-Dec-2007  ad Sync with HEAD.
 1.42.30.1 03-Dec-2007  ad Sync with HEAD.
 1.43.36.17 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.43.36.16 19-Aug-2010  matt Use __HAVE_CPU_VMSPACE_EXEC instead of a mips-specific #ifdef.
 1.43.36.15 28-Feb-2010  matt Split FPU support into separate file and keep internals private to that file.
Make it MPSAFE. Change interface to be very similar to what's used on other
architectures.
Add l_md.md_fpcpu to mdlwp (needed for MPSAFE)
Move pridtab from <mips/cpu.h> to <mips/locore.h>
Add initial common IPI dispatcher.
Split cpu_* routines from mips_machdep.c into cpu_subr.c
Add cpu_startup_common which has the code replicated in half-dozen
plus machdep.c files.
 1.43.36.14 23-Feb-2010  matt Make sure <mips/locore.h> is not included by MI code.
Add send_ipi and cpu_offline_md hooks to locoresw.
Add MP support to pmap (pvlist locking, tlb locking).
Add TLB shootdown support (see comment at the top of mips/pmap_tlb.c).
Add mipsXX_tlb_invalidate_globals routine
 1.43.36.13 05-Feb-2010  matt Add __HAVE_FAST_SOFTINTS support.
Add routine to remap an uarea via a direct-mapped address. This avoids
TLB machinations when swtching to/from the softint thread. This can only
be done for lwp which won't exit.
 1.43.36.12 30-Jan-2010  matt Change MIPS_CURLWP from s7 to t8. In a MALTA64 kernel, s6 is used 9155 times
which means the compiler could really use s7 is was free to do so. The least
used temporary was t8 (288 times). Once the kernel was switched to use t8 for
MIPS_CURLWP, s7 was used 7524 times.

Additionally a MALTA32 kernel shrunk by 6205 instructions (24820 bytes) or
about 1% of its text size.

[For some reason, pre-change t1 was never used and post change t2 was never
used. Not sure why.]
 1.43.36.11 20-Jan-2010  matt Revamp things a bit. Move of the globals mips uses into either cpu_info,
mips_options, or mips_cache_info. Make MALT64 be able to boot MULTIPROCESSOR.
(some pmap MP work).
 1.43.36.10 12-Sep-2009  matt Because of the N32 support, register32_t on mips is really 64-bits wide.
 1.43.36.9 09-Sep-2009  matt Expose label_t if NETBSD_SOURCE to make libkvm happy when including <mips/pcb.h>
 1.43.36.8 07-Sep-2009  matt Add symbolic constants for what's stored in label_t.
 1.43.36.7 06-Sep-2009  matt make label_t 2 registers larger.
 1.43.36.6 05-Sep-2009  matt ATOMIC64_OPS are available for all kernels except O32 ones.
 1.43.36.5 23-Aug-2009  matt Fix LP64 botch with vaddr_t/vsize_t
 1.43.36.4 23-Aug-2009  matt PRIxVADDR, PRIdVSIZE, PRIxVSIZE, or PRIxPADDR as appropriate.
Use __intXX_t or __uintXX_t as appropriate in <mips/types.h>
 1.43.36.3 23-Aug-2009  matt Change lazy fp load/save is done. fpcurlwp is never NULL.
If no current lwp has the FP, then fpcurlwp is set to lwp0.
this allows many check for NULL and avoids a few null-derefs.
Since savefpregs clear COP1, loadfpregs can be called to reload
fpregs. If it notices that situation, it just sets COP1 and returns
Save does not reset fpcurlwp, just clears COP1. load does set fpcurlwp.

If MIPS3_SR_FR is set, all 32 64-bit FP registers are saved/restored via Xdc1.
If MIPS3_SR_FR is clear, only 32 32-bit FP register are saved/restore via Xwc1.
This preserves the existing ABI.
 1.43.36.2 21-Aug-2009  matt Adapt to ABI variations. Make sure mips_reg_t == register_t.
Add PRIx{{P,V}{ADDR,SIZE}} and PRIxREGISTER{,32} macros to assist
printing out above types.
 1.43.36.1 16-Aug-2009  matt Kill use of _MIPS_BSD_ABI - switch to __mips_<abi>
Use device_t where appropriate.
Remove magic numbers.
 1.43.18.1 11-Mar-2010  yamt sync with head
 1.45.4.5 31-May-2011  rmind sync with head
 1.45.4.4 21-Apr-2011  rmind sync with head
 1.45.4.3 05-Mar-2011  rmind sync with head
 1.45.4.2 02-Jun-2010  rmind Add code, dev_mem_getva() and dev_mem_relva(), to deal with cache-aliasing
issues by allocating an appropriate KVA from physical address, according to
the colour. Used by architectures, which have such requirement. For now,
enable only for MIPS, others will follow. This renames previously invented
mm_md_getva() and mm_md_relva(), since we do this in MI way, instead of MD.
Architectures just need to define __HAVE_MM_MD_CACHE_ALIASING as indicator.

Reviewed by Matt Thomas.
 1.45.4.1 18-Mar-2010  rmind Unify /dev/{mem,kmem,zero,null} implementations in MI code. Based on patch
from Joerg Sonnenberger, proposed on tech-kern@, in February 2008.

Work and depression still in progress.
 1.46.4.1 05-Mar-2011  bouyer Sync with HEAD
 1.46.2.1 06-Jun-2011  jruoho Sync with HEAD.
 1.51.2.1 23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.53.16.1 18-May-2014  rmind sync with head
 1.53.12.2 03-Dec-2017  jdolecek update from HEAD
 1.53.12.1 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.53.2.1 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.54.6.5 05-Feb-2017  skrll Sync with HEAD
 1.54.6.4 05-Oct-2016  skrll Sync with HEAD
 1.54.6.3 19-Mar-2016  skrll Sync with HEAD
 1.54.6.2 22-Sep-2015  skrll Sync with HEAD
 1.54.6.1 06-Apr-2015  skrll Sync with HEAD
 1.64.4.1 21-Apr-2017  bouyer Sync with HEAD
 1.64.2.1 20-Mar-2017  pgoyette Sync with HEAD
 1.67.4.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.67.4.1 10-Jun-2019  christos Sync with HEAD
 1.72.2.2 03-Apr-2021  thorpej Sync with HEAD.
 1.72.2.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.74.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.75.4.1 31-May-2021  cjep sync with head
 1.75.2.1 17-Jun-2021  thorpej Sync w/ HEAD.
 1.77.4.1 03-Apr-2023  martin Additionally pull up following revision(s) for ticket #128
to unbreak the build:

sys/arch/mips/include/types.h: revision 1.78
sys/arch/mips/include/bus_space_defs.h: revision 1.5

Add missing PRIuBUSSIZE to mips.
 1.13 08-Feb-2011  rmind Remove clause 3 (UCB advertising clause) from the University of Utah
copyright. Confirmed by Mike Hibler, mike at cs.utah.edu - thanks!
Also, merge UCB and Utah copyright texts back into one, as they
originally were.

Extra verification by snj@.
 1.12 05-Nov-2007  ad branches: 1.12.42; 1.12.48; 1.12.50;
Don't set l_usrpri / spc_curpriority here. mi_userret() does it.
 1.11 16-Feb-2006  perry branches: 1.11.24; 1.11.42; 1.11.44; 1.11.48;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.
 1.10 24-Dec-2005  perry branches: 1.10.2; 1.10.4; 1.10.6;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.
 1.9 11-Dec-2005  christos merge ktrace-lwp.
 1.8 31-Oct-2003  cl branches: 1.8.16;
Reduce code duplication by adding mi_userret() in sys/userret.h
containing signal posting, kernel-exit handling and sa_upcall processing.

XXX the pc532, sparc, sparc64 and vax ports should have their
XXX userret() code rearranged to use this.
 1.7 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.6 17-Jan-2003  thorpej branches: 1.6.2;
Merge the nathanw_sa branch.
 1.5 18-Jan-2001  tv branches: 1.5.8;
No-op commit to force update to a non-"-kk" revision.
 1.4 14-Jan-2001  thorpej branches: 1.4.2;
Now that we won't lose signotify()'s while we're asleep, go ahead
and to signal processing in ast() again.
 1.3 14-Jan-2001  thorpej Put signal posting back in userret() for now; for it to work
properly, we need to make astpending a per-process variable.

Pointed out by mycroft.
 1.2 14-Jan-2001  thorpej - Make ast() loop around astpending; it's possible for a new
AST to be posted when delivering signals, or after a process
is preempted.
- Move all signal posting to ast(). userret() is now a one-liner.
 1.1 11-Jan-2001  thorpej Move userret() into a header file, in preparation for splitting
syscall() into plain and fancy.
 1.4.2.2 18-Jan-2001  bouyer Sync with head (for UBC+NFS fixes, mostly).
 1.4.2.1 14-Jan-2001  bouyer file userret.h was added on branch thorpej_scsipi on 2001-01-18 09:22:43 +0000
 1.5.8.3 26-Sep-2002  nathanw Change "if (l->l_flag & L_SA_UPCALL)" to "while (l->l_flag & L_SA_UPCALL)"
in userret() functions or equivalent, to permit delivery of multiple upcalls
in a single kernel entry.

XXX It's getting crowded in here. Collapsing posting signals, upcalls, and
XXX kernel-exit handling into one mechanism would be nice.
 1.5.8.2 17-Dec-2001  nathanw cpu_upcall() -> sa_upcall_userret().
 1.5.8.1 17-Nov-2001  wdk Inital support for Scheduler Activation on MIPS architectures.

Compiles for sgimips. Needs more work in locore.S in order to reach
single user and beyond.
 1.6.2.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.6.2.2 18-Sep-2004  skrll Sync with HEAD.
 1.6.2.1 03-Aug-2004  skrll Sync with HEAD
 1.8.16.1 15-Nov-2007  yamt sync with head.
 1.10.6.1 22-Apr-2006  simonb Sync with head.
 1.10.4.1 09-Sep-2006  rpaulo sync with head
 1.10.2.1 18-Feb-2006  yamt sync with head.
 1.11.48.1 13-Nov-2007  bouyer Sync with HEAD
 1.11.44.1 06-Nov-2007  matt sync with HEAD
 1.11.42.1 06-Nov-2007  joerg Sync with HEAD.
 1.11.24.1 03-Dec-2007  ad Sync with HEAD.
 1.12.50.1 17-Feb-2011  bouyer Sync with HEAD
 1.12.48.1 06-Jun-2011  jruoho Sync with HEAD.
 1.12.42.1 05-Mar-2011  rmind sync with head
 1.19 17-Jul-2011  joerg Retire varargs.h support. Move machine/stdarg.h logic into MI
sys/stdarg.h and expect compiler to provide proper builtins, defaulting
to the GCC interface. lint still has a special fallback.
Reduce abuse of _BSD_VA_LIST_ by defining __va_list by default and
derive va_list as required by standards.
 1.18 11-Dec-2005  christos merge ktrace-lwp.
 1.17 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.16 22-Jan-1999  mycroft branches: 1.16.42;
Clean up.
 1.15 11-Sep-1998  jonathan Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.

* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.
 1.14 27-Jul-1998  mycroft Delint.
 1.13 26-Feb-1996  jonathan branches: 1.13.16;
Revert pmax stdarg.h and varargs.h to versions from 1995-11-13. Those
versions work correctly; at some point between then and the immediately
preceding revisions, the "stylistic" changes to one (or both) stdarg.h
and varargs.h broke passing doubles to printf().
 1.12 26-Dec-1995  mycroft Make the type of __builtin_va_list a long.
 1.11 26-Dec-1995  mycroft Use __builtin_va_alist.
 1.10 25-Dec-1995  mycroft Stylistic changes.
 1.9 25-Dec-1995  mycroft Update for GCC 2.7, and fix bugs.
 1.8 28-Mar-1995  jtc KERNEL -> _KERNEL
 1.7 28-Jan-1995  jtc ANSI says that <stdarg.h>'s va_end macro must expand to a void expression.
For consistancy, I'm changing <varargs.h> too.
 1.6 26-Oct-1994  cgd new RCS ID format.
 1.5 15-Oct-1994  cgd make <stdarg.h> a symlink, and clean up ports' stdarg.h and varargs.h files.
 1.4 29-Jun-1994  deraadt _MACHINE_VARGS_H_
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.13.16.1 01-Feb-1999  cgd pull up revs 1.14-1.16 from trunk (PR#6862). (mycroft)
 1.16.42.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.16.42.2 18-Sep-2004  skrll Sync with HEAD.
 1.16.42.1 03-Aug-2004  skrll Sync with HEAD
 1.67 14-May-2023  he Bump MAXTSIZ from 64MB to 128MB also for o32.

This so that the rather large cc1 from gcc12 can be run.
OK'ed by simonb@
 1.66 23-Jun-2021  simonb branches: 1.66.10;
Remove an unused #define.
 1.65 26-Feb-2021  simonb branches: 1.65.4;
Drop 64-bit default stack sizes back to 4MB.
 1.64 06-Oct-2020  christos branches: 1.64.2;
GC unused MAXTSIZ32
 1.63 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.62 05-May-2019  christos PR/54133: Sevan Janiyan: Binaries fail to execute
Define M{IN,AX}_PAGE_SHIFT to cover all page possibilities
 1.61 31-May-2018  mrg branches: 1.61.2;
it's called VM_MAXUSER_ADDRESS32 not VM_MAXUSER32_ADDRESS.

fixes mips64 builds, and likely fixes riscv when it happens again.
 1.60 07-Sep-2017  skrll branches: 1.60.2;

Don't define UVM_KM_VMFREELIST on mips as it excludes some memory
ranges unnecessarily.

PR/52501 - erlite quickly fails to allocate memory and processes wedge
 1.59 24-Jun-2017  joerg Update VM_DEFAULT_ADDRESS32_TOPDOWN to include guard area.
 1.58 23-Jun-2017  joerg Recommit exec_subr.c revision 1.79:
Always include a 1MB guard area beyond the end of stack. While ASLR will
normally create a guard area as well, this provides a deterministic area
for all binaries.

Mitigates the rest of CVE-2017-1000374 and CVE-2017-1000375 from
Qualys.

Additionally, change VM_DEFAULT_ADDRESS_TOPDOWN to include
user_stack_guard_size in the size reservation.
 1.57 22-Nov-2016  skrll branches: 1.57.8;
1TB is enough UVA for anyone... plus not all cpus can support more.
 1.56 04-Nov-2016  skrll Cmoment formatting. No functional change.
 1.55 11-Jul-2016  matt branches: 1.55.2;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.54 30-Jun-2015  matt Make vmparam.h change work with RUMP
 1.53 30-Jun-2015  matt We support multiple page sizes so let modules know it.
 1.52 25-Jan-2014  christos branches: 1.52.4; 1.52.6; 1.52.8; 1.52.10;
delete VM_DEFAULT_ADDRESS; some of those should be GC'ed because they match
the default definition.
 1.51 22-Jan-2014  christos remove dup define (already defined in mips_param.h)
 1.50 24-Aug-2011  matt branches: 1.50.2; 1.50.12; 1.50.16;
When using 16KB pages in a 64 bit kernel, the amount of address space our page
table can address can be larger than the amount of address space the CPU
implementation supports. This change limits the amount address space to what
the CPU implementation provides.
 1.49 21-Jul-2011  macallan #include "opt_cputype.h"
for ENABLE_MIPS_16KB_PAGE
 1.48 20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.47 08-Feb-2011  rmind Remove clause 3 (UCB advertising clause) from the University of Utah
copyright. Confirmed by Mike Hibler, mike at cs.utah.edu - thanks!
Also, merge UCB and Utah copyright texts back into one, as they
originally were.

Extra verification by snj@.
 1.46 14-Nov-2010  uebayasi branches: 1.46.2; 1.46.4;
Move struct vm_page_md definition from vmparam.h to pmap.h, because
it's used only by pmap. vmparam.h has definitions for wider
audience.

All GENERIC kernels build tested, except ia64.

powerpc/include/booke/vmparam.h has one too, but it has no pmap.h,
so it's left as is.
 1.45 06-Nov-2010  uebayasi Remove incomplete, never worked dynamic run-time memory registration
(uvm_page_physload(9)). This functionality will be re-added later.
 1.44 14-Dec-2009  matt branches: 1.44.2; 1.44.4;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.43 09-Aug-2009  matt Beginning of large-page support.
 1.42 06-Mar-2009  joerg Remove SHMMAXPGS from all kernel configs. Dynamically compute the
initial limit as 1/4 of the physical memory. Ensure the limit is at
least 1024 pages, the old default on most platforms.
 1.41 26-Dec-2007  ad branches: 1.41.10; 1.41.18; 1.41.24; 1.41.28;
Merge more changes from vmlocking2, mainly:

- Locking improvements.
- Use pool_cache for more items.
 1.40 03-Dec-2007  ad branches: 1.40.2; 1.40.6;
Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.
 1.39 13-Dec-2005  tsutsui branches: 1.39.30; 1.39.48; 1.39.50; 1.39.56;
Move pv_entry stuff from MD pmap_physseg to MD vm_page.
Suggested and OK'ed by thorpej, and tested on R3000/R4400/R5000/Rm5200 CPUs.
 1.38 11-Dec-2005  christos merge ktrace-lwp.
 1.37 17-Jan-2005  simonb branches: 1.37.8;
Now that countless UVM bugs have been fixed and the MIPS pmap_prefer()
can deal with topdown for CPUs that need to deal with cache alias
conflicts (thanks Andrew Brown!), enable "topdown" memory allocation by
default.
 1.36 14-Jan-2005  simonb branches: 1.36.2;
Revert the previous change of making topdown VM the default. While
topdown VM works on a MIPS64 bcm1125, it doesn't work on a Cobalt
(rm5231?) and a DEC 5000/260 (r4400). On both of these init dies and
we panic.
 1.35 11-Jan-2005  simonb Now that countless UVM bugs have been fixed, enable "topdown" memory
allocation by default.
 1.34 26-Apr-2004  simonb Enable top-down VM if USE_TOPDOWN_VM is defined.
 1.33 07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.32 02-Apr-2003  thorpej branches: 1.32.2;
Use PAGE_SIZE rather than NBPG.
 1.31 10-Dec-2002  thorpej Use __LDPGSZ (which must be == USRTEXT) as the text address for a.out
executables, and eliminate the USRTEXT constant, which was only used
by the a.out exec code.
 1.30 15-Nov-2001  soren MAXSLP is defined to be a machine-independent scheduling parameter,
so move it into sys/param.h.
 1.29 18-Jul-2001  simonb branches: 1.29.6;
Modernise data and stack size limits.
 1.28 01-May-2001  thorpej branches: 1.28.2;
Per discussion w/ chuck and chuck, restructure the md page stuff
to use a structure called "vm_page_md", and use __HAVE_VM_PAGE_MD
and __HAVE_PMAP_PHYSSEG.
 1.27 29-Apr-2001  thorpej Add a VM_MDPAGE_MEMBERS macro that defines pmap-specific data for
each vm_page structure. Add a VM_MDPAGE_INIT() macro to init this
data when pages are initialized by UVM. These macros are mandatory,
but ports may #define them to nothing if they are not needed/used.

This deprecates struct pmap_physseg. As a transitional measure,
allow a port to #define PMAP_PHYSSEG so that it can continue to
use it until its pmap is converted to use VM_MDPAGE_MEMBERS.

Use all this stuff to eliminate a lot of extra work in the Alpha
pmap module (it's smaller and faster now). Changes to other pmap
modules will follow.
 1.26 11-Dec-2000  tsutsui branches: 1.26.2;
Set USPACE_ALIGN to USPACE on mips.
 1.25 14-Nov-2000  thorpej We use 4K pages on MIPS systems (see mips_param.h), so override
PAGE_SIZE and friends to be compile-time constants.
 1.24 09-Jun-2000  soda USRIOSIZE had to be changed from 32 to 128,
when MAXBSIZE was changed from 16KB to 64KB(MAXPHYS)
on <sys/param.h> revision 1.28.
 1.23 06-May-2000  nisimura branches: 1.23.2;
Remove unused mapin(pte, v, pfnum, prot) macro.
 1.22 13-Apr-2000  soren Typo; user stack only needs to start one page below 0x80000000.
 1.21 07-Apr-2000  soren Move the start of the user stack down a little to account for the
virtual address checking done by the R8000 and some QED CPUs.

From Jeff Smith.
 1.20 11-Feb-2000  thorpej Update for the NKMEMPAGES changes.
 1.19 26-Jan-2000  tsutsui Remove obsoleted macros.
 1.18 09-Jan-2000  simonb Clear up a comment a little.
 1.17 04-Dec-1999  ragge CL* discarding.
 1.16 29-Nov-1999  uch TX3912/22 support. ENABLE_MIPS_TX3900 enables it.
 1.15 24-Apr-1999  simonb branches: 1.15.2; 1.15.8;
Nuke register and remove trailling white space.
 1.14 26-Mar-1999  thorpej branches: 1.14.4;
Don't bother allocating mb_map on these systems. Mbuf clusters are
allocated from a pool, and the MIPS and Alpha use KSEG to map pool
pages. So, mb_map wasn't actually being used. Saves around 4MB of
kernel virtual address space in a typical configuration.

Garbage-collect the related VM_MBUF_SIZE constant.
 1.13 18-Jan-1999  nisimura - Nuke 90 lines of dead code inherited from 4.4BSD. They were mostly for
VAX BSD VM.
 1.12 16-Jan-1999  chuck MNN is no longer optional
 1.11 06-Jan-1999  nisimura - Complete vm_offset_t purge for mips processor.
- bzero() -> memset() and bcopy() -> memcpy().
- Garbage collection in trap.c and db_interface.c.
 1.10 25-Feb-1998  thorpej branches: 1.10.4;
Implement and switch to MACHINE_NEW_NONCONTIG.
 1.9 02-Feb-1998  jonathan garbage-collect unused MMSEG. From PR# 3898.
 1.8 12-Jul-1997  perry update comment from 1981 on memory and disk prices -- pr-2754 from Curt Sampson
 1.7 12-Jun-1997  mrg bring mrg-vm-swap2 onto mainilne.
 1.6 16-Oct-1996  jonathan branches: 1.6.4; 1.6.8;
Increase MAXDSIZE to 256Mbytes.
 1.5 26-Oct-1994  cgd new RCS ID format.
 1.4 01-Jun-1994  glass VM_MIN_ADDR -> 0
 1.3 27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2 27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1 12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1 12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.6.8.1 04-May-1997  mrg re-merge mrg-vm-swap into -current, and call it mrg-vm-swap2.
 1.6.4.1 12-Feb-1997  mrg initial work for dynamic swap additions.
 1.10.4.1 19-Nov-1998  nisimura - Forgot to commit many files for vm_offset_t purge last Monday.
 1.14.4.2 06-Aug-1999  chs take an initial guess at UBC parameters.
 1.14.4.1 21-Jun-1999  thorpej Sync w/ -current.
 1.15.8.1 27-Dec-1999  wrstuden Pull up to last week's -current.
 1.15.2.3 13-Dec-2000  bouyer Sync with HEAD (for UBC fixes).
 1.15.2.2 22-Nov-2000  bouyer Sync with HEAD.
 1.15.2.1 20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.23.2.1 22-Jun-2000  minoura Sync w/ netbsd-1-5-base.
 1.26.2.1 21-Jun-2001  nathanw Catch up to -current.
 1.28.2.2 10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.28.2.1 03-Aug-2001  lukem update to -current
 1.29.6.3 11-Dec-2002  thorpej Sync with HEAD.
 1.29.6.2 08-Jan-2002  nathanw Catch up to -current.
 1.29.6.1 18-Jul-2001  nathanw file vmparam.h was added on branch nathanw_sa on 2002-01-08 00:26:17 +0000
 1.32.2.4 17-Jan-2005  skrll Sync with HEAD.
 1.32.2.3 21-Sep-2004  skrll Fix the sync with head I botched.
 1.32.2.2 18-Sep-2004  skrll Sync with HEAD.
 1.32.2.1 03-Aug-2004  skrll Sync with HEAD
 1.36.2.1 29-Apr-2005  kent sync with -current
 1.37.8.3 21-Jan-2008  yamt sync with head
 1.37.8.2 07-Dec-2007  yamt sync with head
 1.37.8.1 21-Jun-2006  yamt sync with head.
 1.39.56.2 18-Feb-2008  mjf Sync with HEAD.
 1.39.56.1 08-Dec-2007  mjf Sync with HEAD.
 1.39.50.1 09-Jan-2008  matt sync with HEAD
 1.39.48.1 09-Dec-2007  jmcneill Sync with HEAD.
 1.39.30.2 03-Dec-2007  ad Sync with HEAD.
 1.39.30.1 15-Jul-2007  ad Get pmax working.
 1.40.6.1 02-Jan-2008  bouyer Sync with HEAD
 1.40.2.2 24-Dec-2007  ad Fix merge error.
 1.40.2.1 04-Dec-2007  ad Pull the vmlocking changes into a new branch.
 1.41.28.28 04-Aug-2012  matt Make MIPS use a multi-level page table for the kernel address space.
(just like the user address does). XXX fix mips1
 1.41.28.27 16-Feb-2012  matt Add extern int mips_ksegx_tlb_slot;
 1.41.28.26 09-Feb-2012  matt Add mips_page_to_pggroup which return what pggroup a page belongs to.
Eradicate VM_FREELIST_MAX
When adding pages to the system, track what freelists get pages.
 1.41.28.25 27-Dec-2011  matt Deal with not defining PAGE_SIZE or PAGE_SHIFT for non-kernel inclusion.
 1.41.28.24 27-Dec-2011  matt Make these play nice with modules.
 1.41.28.23 23-Dec-2011  matt Use MIPS_PAGE_SHIFT to define the page size to be used from a config file.
Add support for tracking which colors have been used for an EXECPAGE.
 1.41.28.22 02-Dec-2011  matt Add support for 8KB pages.
 1.41.28.21 29-Nov-2011  matt Take part of the KSEG2 space and use it to "almost" direct another 256MB
of memory so that N32 kernels can make use of ram outside of KSEG0. This
allows N32 kernels to be useful on systems with 4GB of RAM or more.
 1.41.28.20 29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.41.28.19 05-Feb-2011  cliff - protect option includes ("opt_multiprocessor.h") with #ifdef _KERNEL_OPT
 1.41.28.18 05-Feb-2011  cliff - include opt_multiprocessor.h for explicit MULTIPROCESSOR dependency
 1.41.28.17 19-Aug-2010  matt Redefine VM_MAXUSER_ADDRESS in terms of PGSHIFT (no functional changes)
 1.41.28.16 16-Aug-2010  matt Support user VAs > 4GB (but less than 1TB for now) using a 3 level page table.
Add debug code to help find redundant faults (PMAP_FAULTINFO).
 1.41.28.15 29-May-2010  matt Increase *SSIZ/*DSIZ/*TSIZ for non-O32 environments since they will use
more stack and data than the old O32 environments.
 1.41.28.14 28-May-2010  matt Make sure that user stack starts 32KB below maximum so that accesses with
displacements will never cross the VM_MAXUSER_ADDRESS boundary.
 1.41.28.13 11-Mar-2010  matt Add MP-aware icache support.
 1.41.28.12 23-Feb-2010  matt Make sure <mips/locore.h> is not included by MI code.
Add send_ipi and cpu_offline_md hooks to locoresw.
Add MP support to pmap (pvlist locking, tlb locking).
Add TLB shootdown support (see comment at the top of mips/pmap_tlb.c).
Add mipsXX_tlb_invalidate_globals routine
 1.41.28.11 06-Feb-2010  matt Allow uvm_km_alloc to allocate from a specific vm freelist if the port wants
it to.
 1.41.28.10 26-Jan-2010  matt Revamp pmap. Add exec page caching logic from powerpc oea pmap. Shrink struct
vm_page by placing the first pv_entry in it. Remove pv_flags since nothing
really needed it. Add pmap counters. Rework virtual cache alias logic.
Allow pmap_copy_page and pmap_zero_page to deal with non-KSEG0 mappable pages.
 1.41.28.9 20-Jan-2010  matt Revamp things a bit. Move of the globals mips uses into either cpu_info,
mips_options, or mips_cache_info. Make MALT64 be able to boot MULTIPROCESSOR.
(some pmap MP work).
 1.41.28.8 30-Dec-2009  matt Please segtab lookups into separate file.
Add mips_add_physload
Add mips_init_lwp0_uarea
cleanup lwp0/cpu_info_store initialization.
 1.41.28.7 11-Dec-2009  matt Use the default set of VM_FREELISTs in <mips/vmparam.h> but allow them to
be overridden (for pmax).
 1.41.28.6 08-Dec-2009  matt Define various vm freelists for different classes of memory.
 1.41.28.5 09-Nov-2009  cliff - fix definition of VM_MAXUSER32_ADDRESS as per Matt
 1.41.28.4 12-Sep-2009  matt Add some COMPAT_NETBSD32 definitions of common macros.
 1.41.28.3 08-Sep-2009  matt On LP64 kernels, move kernel mapped to XKSEG.
 1.41.28.2 03-Sep-2009  matt Double the default stack size to 4MB (since N32/N64 will use double the stack
space).
 1.41.28.1 21-Aug-2009  matt Define manifest kernel addresses as negative so that proper sign extension
happens. This gives proper results for both 32bit and 64bit kernels.
 1.41.24.1 13-May-2009  jym Sync with HEAD.

Commit is split, to avoid a "too many arguments" protocol error.
 1.41.18.1 28-Apr-2009  skrll Sync with HEAD.
 1.41.10.3 11-Mar-2010  yamt sync with head
 1.41.10.2 19-Aug-2009  yamt sync with head.
 1.41.10.1 04-May-2009  yamt sync with head.
 1.44.4.1 05-Mar-2011  rmind sync with head
 1.44.2.3 16-Nov-2010  uebayasi Sync with HEAD.
 1.44.2.2 26-Apr-2010  uebayasi Remove the unfinished code to add a memory segment after uvm_page_init().
It doesn't even compile.

(In the future, we should allocate struct vm_page [] on the added memory
segment for NUMA's sake.)
 1.44.2.1 23-Feb-2010  uebayasi Convert all VM_MDPAGE_INIT()'s to take struct vm_page_md * and paddr_t.
 1.46.4.2 05-Mar-2011  bouyer Sync with HEAD
 1.46.4.1 17-Feb-2011  bouyer Sync with HEAD
 1.46.2.1 06-Jun-2011  jruoho Sync with HEAD.
 1.50.16.1 18-May-2014  rmind sync with head
 1.50.12.2 03-Dec-2017  jdolecek update from HEAD
 1.50.12.1 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.50.2.1 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.52.10.1 18-Jan-2017  skrll Sync with netbsd-5
 1.52.8.1 03-Dec-2016  martin Pull up following revision(s) (requested by mrg in ticket #1275):
sys/arch/mips/include/vmparam.h: revision 1.57
sys/uvm/pmap/pmap_segtab.c: revision 1.4
1TB is enough UVA for anyone... plus not all cpus can support more.
fix the start index generation in pmap_segtab_release() to
ensure it fits in the actual array. fixes N64 binaries from
triggering later panic. move the panic check itself into a
common function that is called from a couple of new places too.
 1.52.6.4 28-Aug-2017  skrll Sync with HEAD
 1.52.6.3 05-Dec-2016  skrll Sync with HEAD
 1.52.6.2 05-Oct-2016  skrll Sync with HEAD
 1.52.6.1 22-Sep-2015  skrll Sync with HEAD
 1.52.4.1 03-Dec-2016  martin Pull up following revision(s) (requested by mrg in ticket #1275):
sys/arch/mips/include/vmparam.h: revision 1.57
sys/uvm/pmap/pmap_segtab.c: revision 1.4
1TB is enough UVA for anyone... plus not all cpus can support more.
fix the start index generation in pmap_segtab_release() to
ensure it fits in the actual array. fixes N64 binaries from
triggering later panic. move the panic check itself into a
common function that is called from a couple of new places too.
 1.55.2.2 07-Jan-2017  pgoyette Sync with HEAD. (Note that most of these changes are simply $NetBSD$
tag issues.)
 1.55.2.1 04-Nov-2016  pgoyette Sync with HEAD
 1.57.8.2 11-Sep-2017  snj Pull up following revision(s) (requested by skrll in ticket #267):
sys/arch/mips/include/vmparam.h: revision 1.60
Don't define UVM_KM_VMFREELIST on mips as it excludes some memory
ranges unnecessarily.
PR/52501 - erlite quickly fails to allocate memory and processes wedge
 1.57.8.1 31-Aug-2017  bouyer Pull up following revision(s) (requested by joerg in ticket #234):
sys/arch/amd64/include/vmparam.h: revision 1.43
sys/kern/exec_subr.c: revision 1.79
lib/libpthread/pthread_int.h: revision 1.94
sys/arch/mips/include/vmparam.h: revision 1.58
sys/arch/mips/include/vmparam.h: revision 1.59
lib/libpthread/TODO: revision 1.19
sys/arch/powerpc/include/vmparam.h: revision 1.20
sys/arch/riscv/include/vmparam.h: revision 1.2
sys/arch/riscv/include/vmparam.h: revision 1.3
sys/arch/i386/include/vmparam.h: revision 1.85
tests/lib/libpthread/t_join.c: revision 1.9
sys/uvm/uvm_meter.c: revision 1.66
sys/uvm/uvm_param.h: revision 1.36
sys/kern/exec_subr.c: revision 1.80
sys/uvm/uvm_param.h: revision 1.37
sys/kern/exec_subr.c: revision 1.81
sys/kern/exec_subr.c: revision 1.82
lib/libpthread/pthread_attr_getguardsize.3: revision 1.4
lib/libpthread/pthread.c: revision 1.148
lib/libpthread/pthread_attr.c: revision 1.17
sys/arch/amd64/include/vmparam.h: revision 1.42
Always include a 1MB guard area beyond the end of stack. While ASLR will
normally create a guard area as well, this provides a deterministic area
for all binaries.
Mitigates the rest of CVE-2017-1000374 and CVE-2017-1000375 from
Qualys.
Revert for the moment, creates problems on i386.
Recommit exec_subr.c revision 1.79:
Always include a 1MB guard area beyond the end of stack. While ASLR will
normally create a guard area as well, this provides a deterministic area
for all binaries.
Mitigates the rest of CVE-2017-1000374 and CVE-2017-1000375 from
Qualys.
Additionally, change VM_DEFAULT_ADDRESS_TOPDOWN to include
user_stack_guard_size in the size reservation.
Update VM_DEFAULT_ADDRESS32_TOPDOWN to include guard area.
Export the guard size of the main thread via vm.guard_size. Add a
complementary writable sysctl for the initial guard size of threads
created via pthread_create. Let the existing attribut accessors do the
right thing. Raise the default guard size for threads to 64KB.
 1.60.2.1 25-Jun-2018  pgoyette Sync with HEAD
 1.61.2.1 10-Jun-2019  christos Sync with HEAD
 1.64.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.65.4.1 01-Aug-2021  thorpej Sync with HEAD.
 1.66.10.1 15-May-2023  martin Pull up following revision(s) (requested by he in ticket #169):

sys/arch/mips/include/vmparam.h: revision 1.67

Bump MAXTSIZ from 64MB to 128MB also for o32.

This so that the rather large cc1 from gcc12 can be run.

OK'ed by simonb@
 1.4 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.3 28-Apr-2008  martin Remove clause 3 and 4 from TNF licenses
 1.2 11-Dec-2005  christos branches: 1.2.74; 1.2.76; 1.2.78;
merge ktrace-lwp.
 1.1 08-May-2004  kleink branches: 1.1.2;
Factor out W{CHAR,INT}_{MAX,MIN} into their own header file.
 1.1.2.4 21-Sep-2004  skrll Fix the sync with head I botched.
 1.1.2.3 18-Sep-2004  skrll Sync with HEAD.
 1.1.2.2 03-Aug-2004  skrll Sync with HEAD
 1.1.2.1 08-May-2004  skrll file wchar_limits.h was added on branch ktrace-lwp on 2004-08-03 10:37:39 +0000
 1.2.78.1 16-May-2008  yamt sync with head.
 1.2.76.1 18-May-2008  yamt sync with head.
 1.2.74.1 02-Jun-2008  mjf Sync with HEAD.
 1.5 02-Jun-2024  andvar Fix various typos, mainly triple letters.
 1.4 26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.3 21-Feb-2007  thorpej Replace the Mach-derived boolean_t type with the C99 bool type. A
future commit will replace use of TRUE and FALSE with true and false.
 1.2 11-Dec-2005  christos branches: 1.2.18; 1.2.28;
merge ktrace-lwp.
 1.1 05-Nov-2005  tsutsui branches: 1.1.2;
Add MI mips3 wired map functions based on patch in port-mips/31915
from Garrett D'Amore of Tadpole Computer Inc.
Please refer discussion filed in the PR for details.
 1.1.2.2 10-Nov-2005  skrll Sync with HEAD. Here we go again...
 1.1.2.1 05-Nov-2005  skrll file wired_map.h was added on branch ktrace-lwp on 2005-11-10 13:57:33 +0000
 1.2.28.1 27-Feb-2007  yamt - sync with head.
- move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.
 1.2.18.3 26-Feb-2007  yamt sync with head.
 1.2.18.2 21-Jun-2006  yamt sync with head.
 1.2.18.1 11-Dec-2005  yamt file wired_map.h was added on branch yamt-lazymbuf on 2006-06-21 14:53:38 +0000

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