Create a new header lwp_private.h to contain _lwp_getprivate_fast,
_lwp_gettcb_fast, _lwp_settcb and remove them from mcontext.h, so that:
1. we don't need special hacks to hide them
2. we can include <lwp.h> where needed to get the necessary prototypes
without redefining them locally.

Undo previous lwp.h change.

Split __lwp_getprivate_fast and __lwp_*tcb from mcontext.h into a separate
lwp.h file.

branches: 1.35.22;
Install <mips/frame.h>, now needed for dtrace.

branches: 1.34.12; 1.34.14;
Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.

branches: 1.33.16; 1.33.18;
Add mips fenv.h (From FreeBSD)

branches: 1.32.4;
Rename sljitarch.h to sljit_machdep.h.

branches: 1.31.10;
Add sljitarch.h to all mips machines.

branches: 1.30.2; 1.30.12;
Retire varargs.h support. Move machine/stdarg.h logic into MI
sys/stdarg.h and expect compiler to provide proper builtins, defaulting
to the GCC interface. lint still has a special fallback.
Reduce abuse of _BSD_VA_LIST_ by defining __va_list by default and
derive va_list as required by standards.

Don't install aout_machpep.h and bsd-aout.h

branches: 1.28.48;
Merge newlock2 to head.

branches: 1.27.4;
don't install <machine/db_machdep.h>, this is kernel only

branches: 1.26.4; 1.26.8;
merge ktrace-lwp.

branches: 1.25.12;
Factor out W{CHAR,INT}_{MAX,MIN} into their own header file.

branches: 1.24.2;
Merge the nathanw_sa branch.

Remove KDIR=, since SYS_INCLUDE=symlinks and KDIR are not supported any more.

Implement pmc(9) -- An interface to hardware performance monitoring
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.

branches: 1.21.8;
Back out the copy of theses files to userland

We need to copy new SVR4 header files to /usr/include/sys...

branches: 1.19.2; 1.19.8;
Add definitions of C99 integer format conversion macros.
XXX Fastest minimum-width integer types haven't been decided upon yet.

Add definitions of C99 specified-width integer type limits.
XXX Fastest minimum-width integer types haven't been decided upon yet.

Add definitions of C99 integer constant macros.
Tidy Makefiles up a little.

Add definitions of C99 minimum-width and greatest-width integer types.
XXX Fastest minimum-width integer types haven't been decided upon yet.

branches: 1.15.2;
Add <machine/int_types.h>, which provides namespace-pure definitions
of exact-width integer types.

Require that each each MACHINE/MACHINE_ARCH supply a lock.h. This file
contains the values __SIMPLELOCK_LOCKED and __SIMPLELOCK_UNLOCKED, which
replace the old SIMPLELOCK_LOCKED and SIMPLELOCK_UNLOCKED. These files
are also required to supply inline functions __cpu_simple_lock(),
__cpu_simple_lock_try(), and __cpu_simple_unlock() if locking is to be
supported on that platform (i.e. if MULTIPROCESSOR is defined in the
_KERNEL case). Change these functions to take an int * (&alp->lock_data)
rather than the struct simplelock * itself.

These changes make it possible for userland to use the locking primitives
by including <machine/lock.h>.

Install "machineendian_machdep.h".

C99: Define a NAN macro in <math.h> which evaulates to a constant expression of
a single-precision quiet NaN; only to be defined on platforms that do support
this value.

Per discussion on tech-toolchain, remove MIPS-specific <machine/elf.h> header;
all the information is available from <sys/exec_elf.h>.

branches: 1.10.2; 1.10.4; 1.10.8;
install ieee.h

Don't install intr.h - there's only a kernel function prototype in
this file.

- Restore 'regdef.h' lost since last January.

- Eliminate 'conf.h' from MIPS common code.

g/c regdef.h (went into asm.h)

Forgot to also ship out regnum.h

Remove vestiges of cpuarch.h. Revert to using cpuregs.h instead.

Move the bswap functions from libutil to libc (this bups the
minor of libc and the major of libutil). For little-endian architectures
merge the bnswap() assembly versions with nto* and hton* using symbols
aliasing. Use symbol renaming for the bswap function in this case to avoid
namespace pollution.
Declare bswap* in machine/bswap.h, not machine/endian.h. For little-endian
machines, common code for inline macros go in machine/byte_swap.h
Sync libkern with libc.
Adjust #include in kernel sources for machine/bswap.h.

* Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors

Rework the way kernel include files are installed. In the new method,
as with user-land programs, include files are installed by each directory
in the tree that has includes to install. (This allows more flexibility
as to what gets installed, makes 'partial installs' easier, and gives us
more options as to which machines' includes get installed at any given
time.) The old SYS_INCLUDES={symlinks,copies} behaviours are _both_
still supported, though at least one bug in the 'symlinks' case is
fixed by this change. Include files can't be build before installation,
so directories that have includes as targets (e.g. dev/pci) have to move
those targets into a different Makefile.

Remove addition of -msym32 to CFLAGS. Hinders rather than helps build
MIPS modules.

branches: 1.10.30; 1.10.32;
Sync register number for curlwp with the kernel

branches: 1.9.14; 1.9.32;
Switch remaining platforms to modern CPP for assembler.

branches: 1.8.4; 1.8.6; 1.8.8;
Don't build rump kernel with -mno-abicalls, because it's effectively
"no pic".
(should be used only for shared lib rump kernel, but this is just
bandaid for now)

Update flags to match reality.

branches: 1.6.60; 1.6.64; 1.6.72;
remove GCC2 support.

branches: 1.5.2;
retire HAVE_GCC3/HAVE_GCC4 and introduce HAVE_GCC that is set to 2, 3 or 4.

branches: 1.4.4; 1.4.6; 1.4.8; 1.4.10; 1.4.12;
merge ktrace-lwp.

branches: 1.3.16;
introduce an additional switch to enable building GCC3 instead of GCC2:
HAVE_GCC3. if this is set, we also set USE_TOOLS_TOOLCHAIN=no. change
the definition of the former to be restricted to whether tools/toolchain
is used or not.

don't need -mno-half-pic with gcc3

branches: 1.1.2; 1.1.6; 1.1.8; 1.1.24;
This Makefile.inc is used for building LKMS - add the standard MIPS
kernel compile flags as well as "-mlong-calls" so that calls from the
LKM in KSEG2 work to the kernel in KSEG0.

MIPS LKMs now build and can be loaded with the right Magick command line
args to modload(8). Changes to modload coming...

Thanks to Chris Demetriou for pointing out the -mlong-calls gcc option
that had been staring me in the face all along.

Switch all users (except ia64) of custom machine/ansi.h to common_ansi.h

Deduplicate the code among ports and poll definitions of types
directly from a compiler.

This fixes miscompilation of certain programs that instruct compilers
to generate code for different types. This bug has been detected with
-fshort-wchar in EFI firmware.

Proposed and discussed on a mailing list (twice).

Itanium uses custom !ELF fallback switch, temporarily leave it as it is.

branches: 1.29.18;
Make _BSD_CLOCK_T_ unsigned int so it's the same for IPL32 and LP64
environments. We don't really have a powerpc64 native userland
and the mips64 native userland is IPL32 so this shouldn't affect anything.

branches: 1.28.12; 1.28.28; 1.28.30;
Retire varargs.h support. Move machine/stdarg.h logic into MI
sys/stdarg.h and expect compiler to provide proper builtins, defaulting
to the GCC interface. lint still has a special fallback.
Reduce abuse of _BSD_VA_LIST_ by defining __va_list by default and
derive va_list as required by standards.

1. {wctype,wctrans,mbstate}_t: switch MD to MI like other
libc implementation (such as *BSD and glibc2).

2. don't typedef void * wc{type,trans}_t, suggested by soda@-san.
it may pass through compiler type check, it's harmful.
so i introduce dummy struct __tag_wc{type,trans}_t(iconv_t already does).

no ABI change was made.

branches: 1.26.2; 1.26.4;
Fix merge botch (we use 64bit times now).

Merge from matt-nb5-mips64
Merge mips-specific arch files.

merge christos-time_t

branches: 1.23.16; 1.23.18; 1.23.22; 1.23.30; 1.23.38;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

clean up some definitions around rune_t which are not needed anymore

branches: 1.21.8; 1.21.16; 1.21.22; 1.21.26; 1.21.28;
fix gcc -Werror -Wmissing-braces problem
mbstate_t(this is opaque object)'s initializer should be ``{ 0 }'',
so changed 1st field of union from character array to integer.

branches: 1.20.20; 1.20.22;
merge ktrace-lwp.

branches: 1.19.16;
Update for GCC3 (basically, use the __builtin_va_* implementation).

Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

branches: 1.17.2;
#define<tab>

add some ISO C 1995 I18N functions and types:
btowc, wctrans, towctrans, wcscoll, wcsxfrm, wctype_t and wctrans_t.

Add _LP64 types.

branches: 1.14.8;
replace 'long long' with int64_t to compile stand alone program with
compiler other than GCC.

make mbstate_t bigger (32 -> 128 bytes).
XXX if you have libc after citrus locale import, please recompile libc,
and your applications that use mbstate_t (rather rare). really sorry
for the mess.

populate _BSD_MBSTATE_T_. add warning regarding to rune_t.

G/c _BSD_INTPTR_T_ and _BSD_UINTPTR_T_.

branches: 1.10.2; 1.10.10;
Nuke register and remove trailling white space.

branches: 1.9.12;
Provide definitions for intptr_t and uintptr_t, signed resp. unsigned integral
types large enough to hold any pointer.

Add _BSD_SUSECONDS_T_ and _BSD_USECONDS_T_; do some space vs. tab formatting
cleanup

Define _BSD_CLOCKID_T_ and _BSD_TIMER_T_

Add _BSD_WINT_T_ definition so we can handle wint_t type added in NA1.

new RCS ID format.

bsd 4.4-lite pmax port as ported to NetBSD

upgrade to bsd 4.4-lite code base. only mod is rcsids

update from rick, tarfile of Oct 11 10:46

branches: 1.1.1;
Initial revision

Nuke a.out support for MIPS.

branches: 1.8.78; 1.8.92;
merge ktrace-lwp.

Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

branches: 1.6.6;
Rename __LDPGSZ to AOUT_LDPGSZ, to accurately reflect what it is.

branches: 1.5.48;
new RCS ID format.

bsd 4.4-lite pmax port as ported to NetBSD

upgrade to bsd 4.4-lite code base. only mod is rcsids

some pmax updating (Terry Friedrichsen is helping on this now).

branches: 1.1.1;
Initial revision

PR 58960: fix misunderstanding in semantic and provide both the original
id string as well as _NETBSD_REVISIONID.
Do not rely on string concatenation in the inline assembler, use .ascii
and .asciz for individual string parts instead.

PR 58960: mips/asm.h: Respect NETBSD_REVISIONID.

branches: 1.75.6;
mips: Add initial support to gprof(1) for n64 userland

Use gp relative call for _mcount().

Stop using macro name MCOUNT as well for clarity. It has nothing to
do with one provided by <machine/profile.h>.

Now, gprof(1) works just fine for C programs. On the other hand, some
C++ profiling tests of ATF fail as partially observed for n32.

More C++ profile tests become broken for GCC12 in comparison to GCC10.
Something needs to be adjusted for us, or GCC, or both.

mips: Add missing barriers in cpu_switchto.

Details in comments.

PR kern/57240

XXX pullup-8
XXX pullup-9
XXX pullup-10

mips/asm.h: Make membar macros conditional on MULTIPROCESSOR.

For !MULTIPROCESSOR, define them to be empty or nop as appropriate.

mips/asm.h: Cite source for Cavium sync plunger business.

branches: 1.71.4;
mips/cavium: Take advantage of Octeon's guaranteed r/rw ordering.

mips/rmi: Hack to get XLSATX64.MP kernel building again.

Using <mips/asm.h> in a .c file is kinda grody but CALLFRAME_SIZ
doesn't seem to be defined anywhere else. Not sure how this was ever
supposed to work...

mips: Redefine LLSCSYNC as empty on non-Octeon MP.

This change deletes memory barriers on non-Octeon MP. However, all
the appropriate acquire and release barriers are already used in
mutex stubs, and no barriers are needed in atomic_* unless we set
__HAVE_ATOMIC_AS_MEMBAR which we don't on MIPS. So this should be
safe.

Unclear whether we need this even on Octeon -- don't have a clear
reference on why it's here.

mips: Redefine BDSYNC as sync on Octeon, not syncw.

BDSYNC is used for membar_sync, which is supposed to be a full
sequential consistency barrier, which is not provided by syncw, so
this is necessary for correctness.

BDSYNC is not used for anything else, so this can't hurt performance,
except where it was necessary for correctness anyway or where the
semantic choice of membar_sync was too strong anyway.

mips: Omit needless SYNC in mutex_exit.

This change deletes a memory barrier. However, it should be safe:
The semantic requirement for this is already provided by the SYNC_REL
above, before the ll. And as currently defined, SYNC_REL is at least
as strong as SYNC, so this change can't hurt correctness on its own
(barring CPU errata, which would apply to other users of SYNC_REL and
can be addressed in the definition of SYNC_REL).

Later, perhaps we can relax SYNC_REL to syncw on Octeon if we prove
that it is correct (e.g., if Octeon follows the SPARCv9 partial store
order semantics).

Nix now-unused SYNC macro in asm.h.

mips: Membar audit.

This change should be safe because it doesn't remove or weaken any
memory barriers, but does add, clarify, or strengthen barriers.

Goals:

- Make sure mutex_enter/exit and mutex_spin_enter/exit have
acquire/release semantics.

- New macros make maintenance easier and purpose clearer:

. SYNC_ACQ is for load-before-load/store barrier, and BDSYNC_ACQ
for a branch delay slot -- currently defined as plain sync for MP
and nothing, or nop, for UP; thus it is no weaker than SYNC and
BDSYNC as currently defined, which is syncw on Octeon, plain sync
on non-Octeon MP, and nothing/nop on UP.

It is not clear to me whether load-then-syncw or ll/sc-then-syncw
or even bare load provides load-acquire semantics on Octeon -- if
no, this will fix bugs; if yes (like it is on SPARC PSO), we can
relax SYNC_ACQ to be syncw or nothing later.

. SYNC_REL is for load/store-before-store barrier -- currently
defined as plain sync for MP and nothing for UP.

It is not clear to me whether syncw-then-store is enough for
store-release on Octeon -- if no, we can leave this as is; if
yes, we can relax SYNC_REL to be syncw on Octeon.

. SYNC_PLUNGER is there to flush clogged Cavium store buffers, and
BDSYNC_PLUNGER for a branch delay slot -- syncw on Octeon,
nothing or nop on non-Octeon.

=> This is not necessary (or, as far as I'm aware, sufficient)
for acquire semantics -- it serves only to flush store buffers
where stores might otherwise linger for hundreds of thousands
of cycles, which would, e.g., cause spin locks to be held for
unreasonably long durations.

Newerish revisions of the MIPS ISA also have finer-grained sync
variants that could be plopped in here.

Mechanism:

Insert these barriers in the right places, replacing only those where
the definition is currently equivalent, so this change is safe.

- Replace #ifdef _MIPS_ARCH_OCTEONP / syncw / #endif at the end of
atomic_cas_* by SYNC_PLUNGER, which is `sync 4' (a.k.a. syncw) if
__OCTEON__ and empty otherwise.

=> From what I can tell, __OCTEON__ is defined in at least as many
contexts as _MIPS_ARCH_OCTEONP -- i.e., there are some Octeons
with no _MIPS_ARCH_OCTEONP, but I don't know if any of them are
relevant to us or ever saw the light of day outside Cavium; we
seem to buid with `-march=octeonp' so this is unlikely to make a
difference. If it turns out that we do care, well, now there's
a central place to make the distinction for sync instructions.

- Replace post-ll/sc SYNC by SYNC_ACQ in _atomic_cas_*, which are
internal kernel versions used in sys/arch/mips/include/lock.h where
it assumes they have load-acquire semantics. Should move this to
lock.h later, since we _don't_ define __HAVE_ATOMIC_AS_MEMBAR on
MIPS and so the extra barrier might be costly.

- Insert SYNC_REL before ll/sc, and replace post-ll/sc SYNC by
SYNC_ACQ, in _ucas_*, which is used without any barriers in futex
code and doesn't mention barriers in the man page so I have to
assume it is required to be a release/acquire barrier.

- Change BDSYNC to BDSYNC_ACQ in mutex_enter and mutex_spin_enter.
This is necessary to provide load-acquire semantics -- unclear if
it was provided already by syncw on Octeon, but it seems more
likely that either (a) no sync or syncw is needed at all, or (b)
syncw is not enough and sync is needed, since syncw is only a
store-before-store ordering barrier.

- Insert SYNC_REL before ll/sc in mutex_exit and mutex_spin_exit.
This is currently redundant with the SYNC already there, but
SYNC_REL more clearly identifies the necessary semantics in case we
want to define it differently on different systems, and having a
sync in the middle of an ll/sc is a bit weird and possibly not a
good idea, so I intend to (carefully) remove the redundant SYNC in
a later change.

- Change BDSYNC to BDSYNC_PLUNGER at the end of mutex_exit. This has
no semantic change right now -- it's syncw on Octeon, sync on
non-Octeon MP, nop on UP -- but we can relax it later to nop on
non-Cavium MP.

- Leave LLSCSYNC in for now -- it is apparently there for a Cavium
erratum, but I'm not sure what the erratum is, exactly, and I have
no reference for it. I suspect these can be safely removed, but we
might have to double up some other syncw instructions -- Linux uses
it only in store-release sequences, not at the head of every ll/sc.

Add an abicalls version of asm mcount prologue. XXX not tested because
profiled programs fail to link, but fixes build. Thanks dholland@ for
help analysing this.

While here, rename _KERN_MCOUNT to _MIPS_ASM_MCOUNT - it's not kernel
specific.

Working kernel profiling for n32/n64:
- Different MCOUNT and _KERN_MCOUNT macros for n32/n64.
- Don't profile mipsXX_lwp_trampoline().
- Allow a few new instructions in the stub fixups.

Use t9 instead of $25 in the SETUP_GP64 macro to hopefully make things
a bit clearer. Same libc binary after.

branches: 1.62.2;
Add EXPORT_OBJECT - export definition of symbol of symbol type Object,
visible to ksyms(4) address search.

Provide assmebler versions of BITS(3) macros. These are only good for
32 bit masks

More SYNC centralisation

Use compiler defines to determine which LLSCSYNC, et al
to provide.

This should fix mips builds.

Centralise SYNC/BDSYNC in asm.h and introduce a new LLCSCSYNC and use it
before any ll/sc sequences.

Define LLSCSYNC as syncw; syncw for cnMIPS - issue two as early cnMIPS
has errat{um,a} that means the first can fail.

#define<tab>
Nuke trailing whitespace.

Mark the .ident section as mergable string section to avoid redundant
entries.

branches: 1.55.4; 1.55.10;
mark STATIC_NESTED_NOPROFILE() functions as functions.

branches: 1.54.6; 1.54.12; 1.54.14;
Switch from __ABICALLS__ to __mips_abicalls like upstream GCC does in
the generic MIPS target logic.

branches: 1.53.2;
switch mfc0_hazard to be superscalar nop, some mips3 are superscalar
and need this to do the right thing

Move MFC0_HAZARD definition to asm.h instead of defining it twice

Move the NOP_L macro into asm.h

Trailing whitespace

branches: 1.49.2;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

branches: 1.48.2;
Normal spelling is .asciz, so use that on MIPS too.

Drop undocumented and redundant 0 argument to .ent.

branches: 1.46.10; 1.46.24;
Don't redefine _C_LABEL.

branches: 1.45.2;
xxx_SUB macros should use a variant of subu, not add

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

branches: 1.43.2; 1.43.4;
Consistently use .gnu.warning with .pushsectio and .popsection on all
architectures instead of obsolete STABS frames for linker warnings.

implement ucas_* for mips.

branches: 1.41.2; 1.41.4;
Merge from matt-nb5-mips64
Merge mips-specific arch files.

branches: 1.40.20; 1.40.38;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.39.2; 1.39.10;
merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.38.2; 1.38.6; 1.38.8; 1.38.14;
Merge newlock2 to head.

branches: 1.37.18;
Add a STRONG_ALIAS macro

branches: 1.36.2;
merge ktrace-lwp.

branches: 1.35.16;
Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

branches: 1.34.2;
Add STATIC_LEAF and STATIC_XLEAF macros, ala the alpha port.

Remove an ELF-related comment that isn't needed any more.

branches: 1.32.2;
Oops, remove an #endif leftover from the previous change.

All MIPS ports have been ELF for a long time (most since they were
created); remove non-ELF assembly support.

Include <machine/cdefs.h> to select 32/64bit APIs.

branches: 1.29.4; 1.29.8;
For MIPS software masking option, when returning to user mode apply
the mask to all interrupts to catch changes in the mask state faster.
Does not affect platforms w/o this option enabled.

Correct _KERN_MCOUNT restoration of $t9.
From Ethan Solomita (ethan@geocast.com).

Fix a bug in how .S routines call _mcount to allocate stack before
use. By Ethan Solomita (ethan@geocast.com).

add nops after jals in PANIC and PRINTF. (these macros are often used in
code which has noreorder set, and they're not used with nops afterwards,
as is appropriate in that case, so put the nops in the macros.)

Add option to apply additional mask to the SR at run-time for MIPS3 platforms.
By default this is off, and only slightly changes the code to load SR when
a temp register is available. This can be used by the platform code to
handle slow to clear interrupts (our case) or to mask off any interrupt
any interrupt at run-time. This can be very useful for embedded platforms
that have less than desirable interrupt properties.

Add a WEAK_ALIAS() macro.

branches: 1.23.2;
Profiling fixes from Ethan Solomita <ethan@geocast.com>.

Merge Kernel MCOUNT and user MCOUNT.

The earlier code which was inserted to call _mcount in profiling
assembler routines is busted badly. This gets it working with PIC
code and should work with any arbitrary assembler routine.

branches: 1.22.2; 1.22.10;
Nuke register and remove trailling white space.

branches: 1.21.4;
do not include <machine/regdef.h>, but include <mips/regdef.h>,
requested by Matthias Drochner and Toru Nishimura.

- add _C_LABEL() to IMPORT(), to make this consistent with EXPORT().
- fix some oversight of previous my changes on defined(USE_AENT) or
!defined(__NO_LEADING_UNDERSCORES__) case.

- regdef.h is back, so use it.
- ALIAS() is not needed, use XLEAF() or XNESTED() instead
- use AENT() instead of .aent
- _END_LABEL() is not needed (and was wrong)
- define ALEAF(), NLEAF(), NON_LEAF(), NNON_LEAF() by
XLEAF(), LEAF_NONPROFILE(), NESTED(), NESTED_NONPROFILE()

sync to [nisimura-pmax-wscons] version
(only change: include register definitions from regdef.h)

Add VECTOR() and VECTOR_END() macros for declaring exception-vector
code. Fold in <xxx>End names used to copy exception code to vector
locations. Use in mips3 locore code.

Remove genpubassym.cf stuff. The macro _MIPS_BSD_API allows selection of a
64-bit clean compilation model.

* Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors

Implement WARN_REFERENCES().

branches: 1.13.10;
Don't emit ".set reorder ; .set noreorder" around mcount profiling
stubs if _LOCORE or _KERNEL are defined,. _LOCORE means we're
compiling locore. Locore assumes ".set noreorder" for the whole file.

Align to 8-byte boundary after ASMSTR(), for mips3.

PROF -> GPROF

backout previous kprintf change

printf -> kprintf

Rename from pmax/include/machAsmDefs.h to mips/include/asm.h.
Update the include-idempotency preprocessor token to match.

References to machAsmDefs in vendor (sprite, 4.4bsd) headers left unchanged,
for historical accuracy.

Support for alternate compilers and file formats

Make a new macro _C_LABEL(), which prepends an underscore to the argument unless
NO_UNDERSCORES is defined. Use it in the *LEAF() and END() macros.

Prepended underscores

new RCS ID format.

bsd 4.4-lite pmax port as ported to NetBSD

upgrade to bsd 4.4-lite code base. only mod is rcsids

branches: 1.1.1;
Initial revision

Nuke a.out support for MIPS.

branches: 1.5.112; 1.5.126;
Standardise on #ifdef _MIPS_<header>_H_ for multiple inclusion tests.

branches: 1.4.20;
Nuke register and remove trailling white space.

branches: 1.3.12;
RCSID Police.

KERNEL -> _KERNEL

4.4BSD binary format

mips: Use the inline macro version of bswap.

mips suffers from the same problem as sparc where bswap is slow
and using the GCC builtin does not make it better.

This change improves the speed of disk encryption by around 3 MiB/s
on an EdgeRouter 4.

PR port-sparc64/59789

branches: 1.5.28;
#define<tab>
Nuke trailing whitespace.

add generic copyrights so FreeBSD can use them.

branches: 1.3.146; 1.3.156;
Standardise on #ifdef _MIPS_<header>_H_ for multiple inclusion tests.

branches: 1.2.20;
Include <sys/bswap.h> for function prototypes. i386, pc532 and vax
still include <machine/byte_swap.h> and define macros for some of
the bswap*() functions.

Move the bswap functions from libutil to libc (this bups the
minor of libc and the major of libutil). For little-endian architectures
merge the bnswap() assembly versions with nto* and hton* using symbols
aliasing. Use symbol renaming for the bswap function in this case to avoid
namespace pollution.
Declare bswap* in machine/bswap.h, not machine/endian.h. For little-endian
machines, common code for inline macros go in machine/byte_swap.h
Sync libkern with libc.
Adjust #include in kernel sources for machine/bswap.h.

Remove unused file.

branches: 1.10.14; 1.10.28;
Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

branches: 1.9.18; 1.9.22; 1.9.28; 1.9.30;
Remove clause 3 and 4 from TNF licenses

branches: 1.8.40; 1.8.42; 1.8.44;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

add a pair of new bus_dma(9) functions:
int _bus_dmatag_subregion(bus_dma_tag_t tag,
bus_addr_t min_addr,
bus_addr_t max_addr,
bus_dma_tag_t *newtag,
int flags)
void _bus_dmatag_destroy(bus_dma_tag_t tag)

that allow a (normally broken/limited) device to restrict the bus address
range it can talk to. this is used by bce(4) to limit DMA addresses to
1GB range, the maximum the chip can address.

all this is from Yorick Hardy <yhardy@uj.ac.za> with input from several
people on tech-kern.

XXX: bus_dma(9) needs an update still.

branches: 1.6.20;
merge yamt-uio_vmspace branch.

- use vmspace rather than proc or lwp where appropriate.
the latter is more natural to specify an address space.
(and less likely to be abused for random purposes.)
- fix a swdmover race.

branches: 1.5.2; 1.5.4; 1.5.6;
merge ktrace-lwp.

branches: 1.4.4;
Add a dm_maxsegsz public member to bus_dmamap_t. This allows a user of the API
to select the maximum segment size for each bus_dmamap_load (up to the maxsegsz
supplied to bus_dmamap_create). dm_maxsegsz is reset to the value supplied to
bus_dmamap_create when the dmamap is unloaded.

branches: 1.3.2; 1.3.10; 1.3.12;
Introduce BUS_DMA_NOCACHE, and bus_dmamem_map() of i386 supports it.

branches: 1.2.4; 1.2.10;
Oops, balance #ifdef/#endif _KERNEL.

Add generic MIPS bus_space and bus_dma headers; these are a straight
split of the algor <machine/bus.h>.

Ensure bus_dmatag_subregion is called with an inclusive max_addr
everywhere.

#define<tab>
Nuke trailing whitespace.

add missing BUS_DMA_PREFETCHABLE

branches: 1.3.16;
Use register_t for _ds_vaddr

branches: 1.2.2;
Add struct pmap_limits and pm_{min,max}addr from uvm/pmap/map.h and use it to
store avail_start, avail_end, virtual_start, and virtual_end.
Remove iospace and let emips just bump pmap_limits.virtual_start to get the
VA space it needs.
pmap_segtab.c is almost identical to uvm/pmap/pmap_segtab.c now. It won't
be long until we switch to the uvm/pmap one.

branches: 1.1.12; 1.1.30;
Add new files involved in the bus.h->bus_defs.h/bus_funcs.h split.

Add new files involved in the bus.h->bus_defs.h/bus_funcs.h split.

Switch MIPS and MIPS-ish architectures to new-style <sys/bus.h>. This
involves moving some inline bus_space(9) implementation into .c files.

Merge from matt-nb5-mips64
Merge mips-specific arch files.

branches: 1.4.18;
Remove clause 3 and 4 from TNF licenses

branches: 1.3.68; 1.3.70; 1.3.72;
Provide streaming bus_space methods that don't swap if bus is otherwise
swapped from host byte order.
Closes PR port-mips/31910
Reviewed by <izumi>, <matt>, and <simonb>

branches: 1.2.4; 1.2.10; 1.2.32; 1.2.44; 1.2.46; 1.2.48;
Oops, balance #ifdef/#endif _KERNEL.

Add generic MIPS bus_space and bus_dma headers; these are a straight
split of the algor <machine/bus.h>.

Add missing PRIuBUSSIZE to mips.

branches: 1.4.20;
#define<tab>
Nuke trailing whitespace.

remove last isolated islands using BUS_SPACE_BARRIER_SYNC and
BUS_SPACE_BARRIER_X_BEFORE_X - these were only ever defined for mips and ia64,
and never actually implemented even there

branches: 1.2.2;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

branches: 1.1.12; 1.1.30;
Add new files involved in the bus.h->bus_defs.h/bus_funcs.h split.

#define<tab>
Nuke trailing whitespace.

Add new files involved in the bus.h->bus_defs.h/bus_funcs.h split.

mips: Include opt_cputype.h before any of the flags it defines.

PR port-evbmips/59385: PGSHIFT is inconsistently defined on MIPS

branches: 1.16.26;
s/MODULE/_MODULE/

spotted by chuq@

#define<tab>
Nuke trailing whitespace.

Need to compile in cache alias support when MIPS3 or MIPS4

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Multiple inclusion protection

branches: 1.11.14; 1.11.32;
Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

branches: 1.9.96; 1.9.100; 1.9.106; 1.9.108;
merge ktrace-lwp.

Add a workaround to handle virtual alias which may cause data corruption
on R5000/Rm52xx machines:
- Add a new global variable mips_cache_virtual_alias in mips/cache.c,
which indicates that VIPT cache on the CPU could cause virtual alias
and software support is required to handle it. (i.e. no VCED/VCEI)
- Add several cache flush/invalidate ops around KSEG0 access which
might cause virtual alias if mips_cache_virtual_alias is true.
(note checking mips_sdcache_line_size isn't valid for R5000/Rm52xx
because only R4000/R4400 with L2 cache have VCED/VCEI)
- Remove a global variable mips_sdcache_forceinv, which is now superseded
by new mips_cache_virtual_alias.

While here, also change some R4000/R4400 cache ops:
- Don't override mips_cache_alias_mask and mips_cache_prefer_mask with
values based on MIPS3_MAX_PCACHE_SIZE for R4000/R4400 with L2 cache
because it's still worth to reduce VCED/VCEI.
- Flush dcache in pmap_zero_page(9) unconditionally on all MIPS_HAS_R4K_MMU
CPUs and remove cache flush code from cpu_lwp_fork() in vm_machdep.c.

Thanks to Markus W Kilbinger for testing patches on port-cobalt/port-mips.


XXX This fix is just a workaround because it doesn't handle all possible
XXX virtual aliases. As discussed on port-mips, maybe the real fix
XXX for virtual alias is to change MI UVM to adapt it to VIPT cache.
XXX (all VA mappings against the same PA must have the same VAC index etc.)

branches: 1.7.2;
Add a hint variable (mips_sdcache_forceinv, explicitly initialized to zero)
that tells pmap_zero_page() and pmap_copy_page() to unconditionally invalidate
pages for r5k-class CPUs with secondary cache.

This behavior must be explicitly enabled by setting mips_sdcache_forceinv to 1.

This is the last bit of a patch that has been kicked around since 2000 between
rafal@, tsutsui@, and myself.

branches: 1.6.2; 1.6.10; 1.6.12;
No need to protect headers with #ifdef _KERNEL if they're never installed
in /usr/include.

Add support for caches where the data cache is fully coherent, and
either requires flushing either only when the I cache ops are used
or not at all. Currently only used by MIPS32/MIPS64 cache code.

Make cache size/mask variables unsigned.

branches: 1.3.2;
Add mips_dcache_align and mips_dcache_align_mask variables that
contain information suitable for allowing other parts of the kernel
to determine if a memory region is aligned to the largest data cache
line size present in the system.

Add a mips_dcache_compute_align() function which must be called whenever
one of the data cache line size variables is changed, in order to
compute mips_dcache_align and mips_dcache_align_mask.

branches: 1.2.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.

branches: 1.1.2;
file cache.h was initially added on branch thorpej-mips-cache.

#define<tab>
Nuke trailing whitespace.

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

branches: 1.2.2; 1.2.24; 1.2.42;
Flush by increasing way, then increasing addr. flush L1 before L2 (even
though according to the specification it should be needed). Reset
mips_sdcache_size to 0 so we will configure it.

Add loongson2 specific cache ops

#define<tab>
Nuke trailing whitespace.

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

branches: 1.4.126; 1.4.152; 1.4.172;
No need to protect headers with #ifdef _KERNEL if they're never installed
in /usr/include.

New generic way-aware MIPS32/64 range-index cache functions with proper
handling for phyiscally-indexed caches where the way size is greater than
the page size.
These work fine with pass 1 SB1 cores, so g/c those workarounds.

Much thanks to Chris Demetriou for many suggestions and helping me get
my head around all this.

Include 2way cache ops for mips{32,64} CPUs.

branches: 1.1.4; 1.1.8;
Prototypes for MIPS32/64 cache ops.

#define<tab>
Nuke trailing whitespace.

Define Octeon Cavium cache layouts for various cnMIPS cores.

Fix tyop.

branches: 1.2.16; 1.2.20;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

branches: 1.1.2;
Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

branches: 1.3.96; 1.3.122; 1.3.142;
merge ktrace-lwp.

branches: 1.2.4;
cache_r10k.c rev. 1.1 is broken. Because,

1) R10k uses VA0 to select cache ways, but in rev. 1.1, VA14
is used instead.
2) R10k does not support HitWriteBack and should map HitWriteBack
to HitWriteBackInvalidate, but in rev. 1.1, HitWriteBack is not
handled properly.

So, cache_r10k.c rev. 1.1 was replaced by new implementation.

Add R10000 cache ops, written by KIYOHARA Takashi and posted on port-sgimips.
Enabled by options ENABLE_MIPS4_CACHE_R10K for now.

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

branches: 1.3.126; 1.3.152; 1.3.172;
No need to protect headers with #ifdef _KERNEL if they're never installed
in /usr/include.

branches: 1.2.2; 1.2.4;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.

branches: 1.1.2;
file cache_r3k.h was initially added on branch thorpej-mips-cache.

#define<tab>
Nuke trailing whitespace.

Appease gcc and asm

Fix RCSId

Use sdcache routines.
Remove old cache support.
Switch to new cache routines.

Trailing whitespace

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

branches: 1.11.96; 1.11.122; 1.11.142;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

branches: 1.10.18;
Add support for R5k secondary caches, from code Chris Sekiya sent me a long
time ago, with small tweaks by me. Since the R5k doesn't do VCE, the pmap
still needs to be whacked for R5kSC CPUs to work correctly, but this is a
start.

No need to protect headers with #ifdef _KERNEL if they're never installed
in /usr/include.

Add cache_r4k_op_8lines_{16,32} macros to perform cache ops on 8
consecutive lines.

Add 4way 16/32-byte-line cache op primitives.

add VR4131 cache-op bug workaround code.
we can't use Hit_WriteBack_Invalidate.

branches: 1.5.2;
Added Vr4131 support.

Add 32B/l L1 D/I-cache ops for newer ARC machines.

Add 128b/l L2 cache ops.

branches: 1.2.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.

branches: 1.1.2;
file cache_r4k.h was initially added on branch thorpej-mips-cache.

#define<tab>
Nuke trailing whitespace.

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

branches: 1.8.4; 1.8.6;
Restore file for playstation2 accidently overlooked in the big revitilazation

branches: 1.7.12;
Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

branches: 1.6.18; 1.6.22; 1.6.28; 1.6.30;
Remove clause 3 and 4 from TNF licenses

branches: 1.5.74; 1.5.76; 1.5.78;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

branches: 1.4.18;
No need to protect headers with #ifdef _KERNEL if they're never installed
in /usr/include.

branches: 1.3.2;
add #ifndef _LOCORE.

branches: 1.2.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.

branches: 1.1.2;
file cache_r5900.h was initially added on branch thorpej-mips-cache.

mips: Fix R5000SC cache page macro typo that broke boot.

A change in rev 1.5 to mips_r5k_round_page() and mips_r5k_trunc_page()
in cache_r5k.h (for PR/55139) had a fatal typo in the mask, so the
R5000SC cache flush code ended up operating on unintended addresses
and at least R5000SC Indy would no longer boot.
(not sure how my Qube 2700 worked at that time..)

Fix the macros to use the intended mask so that the secondary cache
flushes are done on the correct range again.

Sorry for the long breakage.

Analyzed and reported by Adrian Chadd on port-mips@.
https://mail-index.netbsd.org/port-mips/2025/12/thread1.html#001536

Should be pulled up to netbsd-9, netbsd-10, and netbsd-11.

branches: 1.6.20; 1.6.28;
#define<tab>
Nuke trailing whitespace.

Use proper "page" alignments for R5k Page Invalidate(S) op. PR/55139

According to NEC "User's Manual VR5000, VR1000 64-BIT MICROPROCESSOR
INSTRUCTION" (U12754EJ1V0UMJ1), R5000 Page Invalidate (S) op does
"a page invalidate by doing a burst of 128 line invalidates to
the secondary cache at the page specified by the effective address
generated by the CACHE instruction, which must be page aligned."

This description looks a bit confusing, but "page" used here
implies fixed 32 byte cacheline * 128 lines == 4096 bytes,
not our variable "PAGE_SIZE" used in VM paging ops. Note
the current default PAGE_SIZE for MIPS3 has been changed to 8192.

While here, also define and use proper macro for the "page" and CACHEOP
arg for the R5k Page_Invalidate_S op, as the manual also describes
the cache op field 10111 as "Page Invalidate" for the secondary cache.

No visible regression on Cobalt Qube 2700 (Rm5230) through
whole installation using netbsd-9 based Cobalt RestoreCD/USB.

branches: 1.4.22;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

branches: 1.3.96; 1.3.122; 1.3.142;
merge ktrace-lwp.

Add prototype for r5k_sdcache_wbinv_range_index()

branches: 1.1.2;
Add support for R5k secondary caches, from code Chris Sekiya sent me a long
time ago, with small tweaks by me. Since the R5k doesn't do VCE, the pmap
still needs to be whacked for R5kSC CPUs to work correctly, but this is a
start.

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

branches: 1.6.18; 1.6.44; 1.6.64;
Remove clause 3 and 4 from TNF licenses

branches: 1.5.74; 1.5.76; 1.5.78;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

branches: 1.4.18;
No need to protect headers with #ifdef _KERNEL if they're never installed
in /usr/include.

Clean up #ifdef checks a little.

branches: 1.2.2; 1.2.4;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.

branches: 1.1.2;
file cache_tx39.h was initially added on branch thorpej-mips-cache.

#define<tab>
Nuke trailing whitespace.

- elide parameter tags
- make argument size_t as appropriate
- add begin/end decls

branches: 1.9.12; 1.9.16;
Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.

branches: 1.8.8; 1.8.14;
Remove clause 3 and 4 from TNF licenses

branches: 1.7.74; 1.7.76; 1.7.78;
merge ktrace-lwp.

Don't use "int" to represent lengths; this is what size_t is for. This
does not change the ABI since we don't have 64 bit mips yet.

branches: 1.5.14;
ANSIfy.

branches: 1.4.4; 1.4.8;
Move prototypes for mips_user_cachectl() and mips_user_cacheflush()
to <mips/cachectl.h>.

branches: 1.3.18;
Prototype ANSI-safe gcc trampoline entrypoint.

Add sys_sysarch() calls for the standard mips userspace cache-control calls.

Declarations for standard MIPS-ABI cacheflush() and cachectl() calls,
as used by g++ trampoline code.

s/depreciated/deprecated/g

branches: 1.16.2; 1.16.4;
#define<tab>
Nuke trailing whitespace.

Make all __ALIGNBYTES macros return the same type (size_t)

branches: 1.14.6; 1.14.10;
Change CMSG_SPACE and CMSG_LEN to provide Integer Constant Expressions
again. This was changed in sys/socket.h r1.51 to work around fallout
from the IPv6 aux data migration. It broke the historic ABI on some
platforms. This commit restores compatibility for netbsd32 code on such
platforms and provides a template for future changes to the CMSG_*
alignment. Revert PCC/Clang workarounds in postfix and tmux.

branches: 1.13.12; 1.13.16;
Merge from matt-nb5-mips64
Merge mips-specific arch files.

branches: 1.12.60; 1.12.78;
Define _MIPS_BSD_API correctly according to GCC builting __mips_n64,
__mips_n32, and __mips_o64.

branches: 1.11.52; 1.11.66; 1.11.70;
Nuke register and remove trailling white space.

branches: 1.10.4;
Garbage-collect.

Remove genpubassym.cf stuff. The macro _MIPS_BSD_API allows selection of a
64-bit clean compilation model.

* Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors

Bug fixes and cleanup from Chris Demetriou <cgd@pa.dec.com>:
- fix _C_LABEL so that it actually works.
- make __RENAME use _C_LABEL.
- fix __RENAME so that it expects an unquoted argument.
- fix __indr_reference and __warn_references so that they
supply their own final semicolon.
- define __warn_references to nothing if not GNU C (required
by the way it's used).

The __warn_references semicolon change has to be made
so that __warn_references can be defined into nothing.
(A ; all by itself isn't a great idea.) The __indr_reference
change was made for consistency.

Implement __RENAME() in <machine/cdefs.h>

branches: 1.5.8;
Add hooks for definiing kernel RCSId and copyright symbols,
via asm(".section"), for compatibility with Alpha tc and ioasic drivers.

Assumes ELF and binutils-2.8 toolchain.

Change mips __warn_references() macro to use the ELF warning features
in binutils 2.6 and (patched) gcc 2.7.2. Only works with gcc in ANSI C
mode, for now.

Use Alpha cdefs.h

Changed name of __weak_reference() to __indr_reference(). They really
are indirect references, and I want to add a real __weak_reference()
macro to <machine/cdefs.h> soon.

This file, which will be included by <sys/cdefs.h>, will contain macros
such as __warn_references() and __weak_reference() which are actually
machine dependant. This will make it easier for ports that are being
bootstraped with ELF and ECOFF based toolchains.

This change also introduces a new macro, _C_LABEL(x). _C_LABEL expands
its argument, an identifier, to a character string of the identifier
name as it is represented in an object file.

For most ports, _C_LABEL(x) will expand to "_x", for ELF based ports
_C_LABEL(x) will expand to "x".

- Nuke old leftover; round four. This file has little usefuls, and
target MIPS ports are expected to have 'machine/conf.h' if necessary.

lint: Create mips/include/conf.h with prototypes for {mem device.
Add 'struct proc *p' 4th arg to mmopen(), mmclose().
Delete unused variable.

USE __BIT() for CPUF_* flags. NFCI.

fix few typos in comments.

Improved the performance of kernel profiling on MULTIPROCESSOR, and possible to get profiling data for each CPU.

In the current implementation, locks are acquired at the entrance of the mcount
internal function, so the higher the number of cores, the more lock conflict
occurs, making profiling performance in a MULTIPROCESSOR environment unusable
and slow. Profiling buffers has been changed to be reserved for each CPU,
improving profiling performance in MP by several to several dozen times.

- Eliminated cpu_simple_lock in mcount internal function, using per-CPU buffers.
- Add ci_gmon member to struct cpu_info of each MP arch.
- Add kern.profiling.percpu node in sysctl tree.
- Add new -c <cpuid> option to kgmon(8) to specify the cpuid, like openbsd.
For compatibility, if the -c option is not specified, the entire system can be
operated as before, and the -p option will get the total profiling data for
all CPUs.

Include #include <mips/frame.h> to get lwp_trapframe() definition.
Needed for dtrace.

branches: 1.131.2; 1.131.4;
port crash(8) to mips. (most of the kernel side.)

- expose parts of _KERNEL to _KMEMUSER as well
- hide more things for _KERNEL
- avoid DB_MACHINE_COMMANDS in crash(8)
- XXX add mips_label_t for !_KERNEL and use it in the pcb to
avoid conflicting with the ddb/crash one
- enable dumppcb

some changes to make stack trace fail instead of SEGV and
the userland changes to crash itself not part of this change.

Don't kcpuset_clone every pmap_tlb_shootdown_bystanders. Instead allocate
a kcpuset_t per cpu_info and use that.

#define<tab>
Nuke trailing whitespace.

Fix false sharing problems with cpu_info. Identified with tprof(8).
This was a very nice win in my tests on a 48 CPU box.

- Reorganise cpu_data slightly according to usage.
- Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc).
- On x86, put some items in their own cache lines according to usage, like
the IPI bitmask and ci_want_resched.

mi_userret(): take care of calling preempt(), set spc_curpriority directly,
and remove MD code that does the same.

interrupt has two 'r's

fix another typo while I'm here (flsah)

- Cleanup for dynamic sysctl:
- Remove unused *_NAMES macros for sysctl.
- Remove unused *_MAXID for sysctls.
- Move CTL_MACHDEP sysctl definitions for m68k into m68k/include/cpu.h and
use them on all m68k machines.

branches: 1.124.2;
Adjust ci on the second iteration.

Now a MULTIPROCESSOR+LOCKDEBUG ERLITE reaches userland again

branches: 1.123.2;
Don't attempt to dereference cpu_infos if ncpus == 0.
Instead use the already initialized cpu_info_store.

(Also, now we assume all ncpus have cpu_infos initialized. seems to work.)

fixes PR port-mips/52940: ERLITE multiprocessor hangs early

CPU_INFO_FOREACH() must always iterate at least the boot cpu.
document this in sys/cpu.h and fix the arm and mips versions
to check ncpu is non zero before using it as an iterator max.

this should fix the new assert in init_main.c.

branches: 1.121.8;
Pre-allocate some kcpuset_ts so that we don't try and allocate in the
wrong context.

move sysctl-related #defines out of #ifdef _KERNEL so userland can see them
now pixman builds again on loongson

branches: 1.119.2;
Remove commented #include

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Define (but not use) separate kernel and user pagetables.
Move to the new names.

Transition from __cpuset_t to kcpuset_t *. This brings the local pmap one
step closer to uvm/pmap, its eventual replacement. Tested on ERLITE MP kernel.

assembly no longer include <machine/cpu.h>. Instead MIPS_CURLWP is gotten
from regdef.h and everything else from assym.h. <mips/mips_param.h> no
longer include <machine/cpu.h>

Reuse the ci_next to hold the nmi exception stack.

Fix CPU_INFO_FOREACH which had the MULTIPROCESSOR/!MULTIPROCESSOR definitions
reversed.

Rework cavium support in preparation for MULTIPROCESSOR support

Use the lwp_getcpu() inline for curcpu().

Don't define MIPS1/MIPS32/MIPS32R2 if ABI is N32 or N64.

branches: 1.109.6;
fix unused

use __unused instead of __USE and void cast to mark iterator variable unused
where needed (from phone)

branches: 1.107.6;
add sysctl machdep.loongson-mmi to indicate wether Loongson Multimedia
Instructions are supported
mostly for pixman

branches: 1.106.2; 1.106.12;
support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory and
DMA buffers with cacheing disabled but things like write combining, relaxed
ordering etc. allowed when the CPU supports it
so far enabled only on Loongson, should work on R1xk and probably newer CPUs

Add support for the MIPS DSP ASE (as a second PCU).

Add CPU_MIPS_LOONGSON2 flag (rather defining a CPU_ARCH_MIPS3_LOONGSON2).
This is much less intrusive and disruptive.

Add

uint32_t kfetch_32(volatile uint32_t *, uint32_t);

which fetches a 32-bit value from a provided addess or returns
an user supplied value on error.

Extend PCU:
- Add pcu_ops_t::pcu_state_release() operation for PCU_RELEASE case.
- Add pcu_switchpoint() to perform release operation on context switch.
- Sprinkle const, misc. Also, sync MIPS with changes.

Per discussions with matt@.

- MIPS CPU (COP0) watchpoint support moved from db_machdep.h to cpu.h
- CPU watchpoints are per-cpu; add ci_cpuwatch_count, ci_watchpoint_tab[]
to struct cpuinfo

Fix LKM/MODULAR case.

Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

Add support for the Extensible MIPS ("eMIPS") platform. The
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the
Giano system simulator.

eMIPS is a platform developed at Microsoft Research for researching
reconfigurable computing. eMIPS allows dynamic loading and scheduling
of application-specific circuits for the purpose of accelerating
computations based on the current workload.

NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research
by Alessandro Forin and Neil Pittman. Microsoft Corporation has
donated full copyright to The NetBSD Foundation.

Platform support for eMIPS is the first part of Microsoft's
contribution. The second part includes the hardware accelerator
framework and will be proposed on tech-kern soon.

branches: 1.96.2; 1.96.4;
PROC_PC() should have been changed to LWP_PC().

branches: 1.95.4;
rename pridtab{}::cpu_name to cpu_displayname.

should fix a build error reported by he@.

Merge from matt-nb5-mips64
Merge mips-specific arch files.

- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.

Remove uarea swap-out functionality:

- Addresses the issue described in PR/38828.
- Some simplification in threading and sleepq subsystems.
- Eliminates pmap_collect() and, as a side note, allows pmap optimisations.
- Eliminates XS_CTL_DATA_ONSTACK in scsipi code.
- Avoids few scans on LWP list and thus potentially long holds of proc_lock.
- Cuts ~1.5k lines of code. Reduces amd64 kernel size by ~4k.
- Removes __SWAP_BROKEN cases.

Tested on x86, mips, acorn32 (thanks <mpumford>) and partly tested on
acorn26 (thanks to <bjh21>).

Discussed on <tech-kern>, reviewed by <ad>.

branches: 1.90.16;
Remove all initialization of obsolete ci_divisor_recip in
mips struct cpu_info and related macroes.
The member was prepared for a hack in MD microtime(9) implementation
but it has been superseded by MI timecounter(9).

branches: 1.89.2; 1.89.4; 1.89.6;
Remove CTL_MACHDEP_NAMES, it's not used anywhere.

Ok by martin@.

branches: 1.88.2; 1.88.6;
Fix typo in macro name and comments.

branches: 1.87.4;
Define the various MIPS* CPU macros also for _STANDALONE in addition
to for _LKM, so that we don't #error out in that case.

This fixes the build for sgimips boot programs, which wants to use
libkern, which now includes the atomic stuff, which for the mips ports
ends up including this file.

"simonb said OK"

branches: 1.86.2;
Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

branches: 1.85.2;
Merge from vmlocking: add CPU_INFO_ITERATOR.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.83.2; 1.83.6;
Add ci_cpuid where it's missing.

branches: 1.82.2; 1.82.4; 1.82.8;
merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.81.4; 1.81.6; 1.81.12;
Fix a tyop.

branches: 1.80.2;
Fix typo from newlock2 merge, allowing MIPS64 to build again.

Remove spllowersoftclock() and CLKF_BASEPRI(), and always dispatch callouts
via a soft interrupt. In the near future, softclock will be run from process
context.

Merge newlock2 to head.

branches: 1.77.8;
include/cpu.h: make sure MIPS3_PLUS properly defined even if _LOCORE is defined
mips/fp.S: include <mips/cpu.h> for #ifdef MIPS3_PLUS

Closes PR port-mips/27298.

branches: 1.76.4; 1.76.6; 1.76.8; 1.76.10; 1.76.12;
bare asm -> __asm

merge ktrace-lwp.

Make MIPS3_PG_SHIFT a variable and initialize it accordingly
in mips_vector_init() if options MIPS3_4100 is specified
so that kernels which have options MIPS3_4100 also work
on other MIPS3 CPUs.

XXX: now should we rename options MIPS3_4100 to options ENABLE_MIPS_R4100,
XXX: or just make MIPS3_PG_SHIFT always a variable?

branches: 1.73.10; 1.73.12; 1.73.18;
move some per-cpu data definitions to MI place so that they can be modified
without touching all ports. discussed on tech-kern@.

Rearrange process exit path to avoid need to free resources from different
process context ('reaper').

From within the exiting process context:
* deactivate pmap and free vmspace while we can still block
* introduce MD cpu_lwp_free() - this cleans all MD-specific context (such
as FPU state), and is the last potentially blocking operation;
all of cpu_wait(), and most of cpu_exit(), is now folded into cpu_lwp_free()
* process is now immediatelly marked as zombie and made available for pickup
by parent; the remaining last lwp continues the exit as fully detached
* MI (rather than MD) code bumps uvmexp.swtch, cpu_exit() is now same
for both 'process' and 'lwp' exit

uvm_lwp_exit() is modified to never block; the u-area memory is now
always just linked to the list of available u-areas. Introduce (blocking)
uvm_uarea_drain(), which is called to release the excessive u-area memory;
this is called by parent within wait4(), or by pagedaemon on memory shortage.
uvm_uarea_free() is now private function within uvm_glue.c.

MD process/lwp exit code now always calls lwp_exit2() immediatelly after
switching away from the exiting lwp.

g/c now unneeded routines and variables, including the reaper kernel thread

Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

branches: 1.70.2;
Merge the nathanw_sa branch.

Add support for caches where the data cache is fully coherent, and
either requires flushing either only when the I cache ops are used
or not at all. Currently only used by MIPS32/MIPS64 cache code.

Move the curpcb and segbase extern decls to cpu.h to better group together
what will need to change for SMP.
Hide 'struct cpu_info' and some macros in #ifdef _KERNEL/#endif.

++CPU_MAXID for CPU_LLSC.

Add sysctl variable to represent native CPU support for LL/SC instructions.

Typo

3 ports are now using the reciprocal count divisor code now, move it
to <mips/cpu.h>, and add MIPS_SET_CI_RECIPRICAL and MIPS_COUNT_TO_MHZ
macros to use it.

Add two new cpu capability flags: CPU_MIPS_USE_WAIT for CPUs that use a
"wait" instruction based cpu_idle(), and CPU_MIPS_NO_WAIT for specific
CPUs that don't use this (applicable to mips32/64 mainly).

branches: 1.62.2;
Add a "CPU_MIPS_DOUBLE_COUNT" flag for CPUs where the cp0 count register
ticks over at half the CPU clock speed, and set this flag for the known
CPUs with this behaviour. Better names for this flag gratefully accepted!

Also adjust comment about known R4000/R4400 revisions.

Add prototype for badaddr64().

Define all CPU types if _LKM is defined; fixes problems building LKM's
as noted by FUKAUMI Naoki on port-mips.

Add a field for the reciprocal of the divisor delay for use by microtime.

Add support for MIPS32 and MIPS64 architectures:
- Clean up (somewhat) mips1 vs mips3+ configuration.
XXX: this is still quite messy.
- Add cpu frequency info to struct cpu_info.
- ANSIfy.

branches: 1.57.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.

branches: 1.56.2;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.

Oops, <sys/sched.h> isn't asm safe, move inside an "#ifndef LOCORE" block.

May as well include <mips/cpuregs.h> in <mips/cpu.h> once rather than
in every MIPS port's <machine/cpu.h>.

Centralise struct cpu_info declaration and related info to <mips/cpu.h>.

branches: 1.52.2;
Don't need to prototype child_return() here, it's in <sys/proc.h>.

Fix various misspellings of compatible/compatibility.

branches: 1.50.2;
Make the astpending flag per-process.

- Make ast() loop around astpending; it's possible for a new
AST to be posted when delivering signals, or after a process
is preempted.
- Move all signal posting to ast(). userret() is now a one-liner.

Mmm, dependency problems. Add a cast to make PROC_PC() actually
work.

Modeled after mycroft's changes to the Alpha port, add PROC_PC() to
get profiling out of userret(), and move the preemption check to ast().

always have to declare cpu_arch and the related constants (since setting
it isn't conditionalized). (d'oh!)

tweak cpu_arch. Eliminate all direct checks of it (making them
use the macro CPUISMIPS3 -- which is badly misnamed), and set it
from #defines named CPU_ARCH_N (where N is 1..5, 32, 64).

Make need_resched() take a "struct cpu_info *" argument. This
causes gives a primitive form of processor affinity. Its use in
roundrobin() still needs some work.

Add comment that overriding the sysctl defines in machine/cpu.h
breaks userland binary compatiabiltiy between mips ports. Move
check down so common values are always defined here.

Only define machdep sysctls if CPU_MAXID is not defined by machine/cpu.h.
This lets mips ports have additional machdep sysctl. Define CPUISMIPS3
for MIPS1+MIPS2 as cpu_arch >= 3 to support mips4. Add cpu_intr()
prototype so this is defined in one place.

branches: 1.41.2;
savefpregs() and loadfpregs() are defined in mips_machdep.c

branches: 1.40.2;
First sweep at scheduler state cleanup. Collect MI scheduler
state into global and per-CPU scheduler state:

- Global state: sched_qs (run queues), sched_whichqs (bitmap
of non-empty run queues), sched_slpque (sleep queues).
NOTE: These may collectively move into a struct schedstate
at some point in the future.

- Per-CPU state, struct schedstate_percpu: spc_runtime
(time process on this CPU started running), spc_flags
(replaces struct proc's p_schedflags), and
spc_curpriority (usrpri of processes on this CPU).

- Every platform must now supply a struct cpu_info and
a curcpu() macro. Simplify existing cpu_info declarations
where appropriate.

- All references to per-CPU scheduler state now made through
curcpu(). NOTE: this will likely be adjusted in the future
after further changes to struct proc are made.

Tested on i386 and Alpha. Changes are mostly mechanical, but apologies
in advance if it doesn't compile on a particular platform.

remove following symbols which became unnecessary in recent cpu_intr() change:
mips_hardware_intr
MIPS3_INTERNAL_TIMER_INTERRUPT
mips3_intr_cycle_count
mips3_timer_delta

Introduce cpu_intr() whose body is now provided by target ports in
their own ways. Ugly fixup #define in machine/intr.h have gone.
mips_hardware_intr global variable patch work has gone.

Move fpcurproc declaration to <mips/cpu.h>.

Revert previous.

Move sysctl definitions from arch/mips to arch/foo.

Garbage collect MIPS_SR_INT_ENAB/MIPS_SR_INT_ENA_CUR definitions.

Use the badaddr() prototype in mips/include/cpu.h by including
<machine/cpu.h> in mips/include/mips_param.h. Remove duplicate
badaddr() prototypes from some pmax header files.

branches: 1.32.2;
Define cpu_number() as discussed on tech-smp.

* convert to using MI allocsys(). most ports were using an MD allocsys(),
although a couple still used the old pre-4.4-lite (?) mechanism.
* use format_bytes() to format the various printf()s that print out memory sizes

- Move MachSetPID(1) call to pmap_bootstrap() adajacent to kernel pmap
initialization code.
- Abandon mips_init_proc0() and do the 4 lines straightly in MD mach_init().
- Restore a block of code accidentally lost in prevous commit.
- Change the term 'tlbpid' to a MIPS3 nomenclature 'asid'.
- Hide PTE size exposures by symbolic names in locore.S

branches: 1.29.4;
Add CPU_BOOTED_KERNEL to CTL_MACHDEP definition.

* Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors

Changes to support fork_kthread():
- cpu_set_kpc() now takes void *arg third argument, passed to the
entry point.
- cpu_fork() allows parent to be non-curproc iff parent is proc0.
When forking non-curproc, assume its state has already been saved.
- Adjust various pieces of machine-dependent code to account of all of this.

Add `struct proc;' to keep egcs warnings happy in userland.
XXX why are kernel prototypes visible here at all?

branches: 1.25.2;
Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.

* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.

Prototype allocsys(), mips_init_msgbuf(), and mips_init_proc0().

Prototype dumpsys() and savectx().

* Change Sprite MACH_xxx prefix to MIPS_xxx.

* Use standard mips terminology (xxx_KSEG0, xxx_KSEG1) instead of the
(more meaningful) Sprite names (xxx_CACHED, xxx_UNCACHED).

More mips1/mips3 changes to cpuregs.h and psl.h:
* cpuregs.h:
Delete unused VMMACH_ names (e.g., duplicates of PTE bits in pte.h).
Change remaining VMMACH_xxx names to MIPS1_xxx or MIPS3_xx.
Fold remaining compile-time definitions into a single #ifdef MIPS3.

* Use MIPS1_ names in locore_r2000.S, mips3_ names in locore_r4000.S

* Garbage-collect MachHitFlushDCache()

* psl.h:
use MIPS1_, MIPS3_ symbolic names for Cause register bits.
change _R3K to MIPS1_, _R4K to MIPS3. Conditionalize for mips1 only,
mips3 only, or when both are defined, use runtime CPUISMIPS3 test.

Changes for configuring both MIPS1 and MIPS3, from a merge of
similar design and code by Jason Thorpe and Jonathan Stone.

NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.

mips/include/cpu.h:
Add CPUISMIPS3 for run-time tests of what CPU architecture level
we're running on.

mips/include/locore.h:
Add declarations of locore cache-size variables for ref/def toolchain.

mips/include/mips1_pte.h:
mips1 TLB bit definitions.

mips/include/mips3_pte.h:
mips3 TLB bit definitions.

mips/include/pte.h:
define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
that expand to CPU constants if only one CPU arch is configured,
or to inline functions if both MIPS1 and MIPS3 are configured.

mips/mips/locore_r2000.S:
Use MIPS1_PG_xxx constants inside mips1-specific code.

mips/mips/locore_r4000.S:
Use MIPS3_PG_xxx constants inside mips3-specific code.

mips/mips/locore.S:
Use MIPS1_PG_xxx constants inside mips3-specific code.
Use MIPS1_PG_xxx constants inside mips1-specific code.
(Needs more work!)

mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
Use MIPS3_PG_xxx constants inside mips3-specific functions,
and MIPS1_PG_XXX inside mips1-specific code.
Otherwise, use mips_pg_XXX_bit() macros where they apply,
and use "if (CPUISMIPS3) { ... } else {... }" where they don't.

mips/mips/mips_machdep.c:
Import Michael Hitch's fixes from the pmax locore-init code
into mips_vector_init().

pmax/pmax/machdep.c:
Use generic mips_vector_init() locore vector-init function.

Garbage-collect redundant declarations:
mips/include/locore.h:
Add prototypes for HitFlushDCache() functions. Moe cpu_prid definition here.
mips/include/cpu.h:
remove cpu_prid definition.
pmax/pmax/machdep.c:
remove local protoypes of HitFlushDCache() functions.
mips/mips/vm_machdep.c, mips/mips/vm_machdep.c::
remove local protoypes of HitFlushDCache() functions.

Yet more merging:
* Move declaration of locore communcation variables (CPU family,
cache sizes, etc) to mips/include/locore.h. Delete from
pmax/include/cpu.h and older versions from pica/include/cpu.h.

* Move definitions of CLKF_BASEPRI, CLKF_USERMODE to mips/include/cpu.
* Delete duplicate definitions in pica/include/cpu.h, pmax/include/cpu.h.

Garbage-collect #include <machine/machConst.h>.

From Toru Nishimura: _FORKBRAINDAMAGE is gone, user process entered through
proc_trampoline().

fix case typo: CLKF_BASEPRI_R4k to _R4K

Factor out r3000 versus r4000 differences (CLKF_USERMODE() and CLKF_BASEPRI()),
provide r3k and r4k versions of each, and move to sys/arch/mips/include.

Note in comments where each mips-based port should provide
definitions in its own cpu.h after including this file.

Add additional mips CPU and FPU ids from Pica port:
IDT r3081 family, r4600, MIPS-IV architecture, others.

remove unused cpu_exec() definitions. moved "broken swap" markers, for
ports that still need it, to types.h.

define BROKEN_SWAP and/or cpu_swapout as appropriate.

- added sunos_machdep.c for sun3, atari, amiga and mac68k.
- changed machdep.c and trap.c to use struct emul.
- remove ep_setup references.
- added struct emul to all emulations.

KERNEL -> _KERNEL

new RCS ID format.

fix a few integration bugs, add vmfault debugging, more ultrix stuff

bsd 4.4-lite pmax port as ported to NetBSD

upgrade to bsd 4.4-lite code base. only mod is rcsids

intrframe -> clockframe

some pmax updating (Terry Friedrichsen is helping on this now).

update from rick, tarfile of Oct 11 10:46

branches: 1.1.1;
Initial revision

#define<tab>
Nuke trailing whitespace.

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

branches: 1.4.14; 1.4.32;
Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

branches: 1.3.90; 1.3.94; 1.3.100; 1.3.102;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.

branches: 1.2.2; 1.2.4; 1.2.6;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

Replace machine/rnd.h with more appropriate name to share it
with cycle counter based microtime in kern/kern_microtime.c.

- Update 'cpuregs.h' and decline 'cpuarch.h'.

* Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors

branches: 1.1.2;
file cpuarch.h was initially added on branch nisimura-pmax-wscons.

Use the architecture documented name ULR for the RDHWR user local
register.

Add some comments for the RDHWR register numbers.

Only need one #define for MIPS_HWR_CPUNUM.

fix typos, mainly in words minimum and maximum, but also few others.

s/definitons/definitions/

Update the FPU register names and bit definitions to something somewhat
modern (MIPS32/MIPS64) and convert to __BIT/__BITS.

branches: 1.110.4; 1.110.6;
Handle gas/gcc generating a break/trap 6 for integer overflow and
break/trap 7 for integer divide by zero and setting the SIGFPE
si_code of FPE_INTOVF or FPE_INTDIV respectively. The break/trap
6/7 seems to have existed since the early days of MIPS but not
well documented anywhere.

Fixes ATF lib/libc/gen/t_siginfo::sigfpe_int .

branches: 1.109.2;
Remove bogus duplicate MIPS_COP_0_CONTEXT definition, it's not a MIPS32/64
specific reg and we already define MIPS_COP_0_TLB_CONTEXT elsewhere.

Add a few more perfcnt CP0 registers.

Add two cnMIPS III COP0 register names.

Add definitions for the CP0 WatchLo/WatchHi registers.

#define<tab>
Nuke trailing whitespace.

Add CP0 Config Registers 6 and 7.

Remove mostly duplicate MIPS spec CP0 regs from octeon_corereg.h, move
the Cavium specific CP0 regs to <mips/cpuregs.h> as done for other core
specific regs.

Expose the width of the MIPS_EBASE_CPUNUM bitfield for asm code.

Add an extra bitfield in MIPS_COP_0_EBASE.

Remove a magic number.

Add mipsNN_cp0_rdhwr_cpunum() which returns the current CPU number
read from the CPUNum hardware register on MIPS{32,64}R2.

Add CX73xx and CXF75xx Cavium Octeon PRIDs.

Add PRID definition for newer SiByte SB1 cores (rev 0x11).
Add a constant for SiByte/BCRM cacheable coherent TLB cache attribute.

Trailing whitespace

branches: 1.95.8;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Add a few MIPS32 R3 bits

Add MIPS 1074K

Define COP0 register that use select value in <mips/cpuregs.h>
Use those new definitions

Rework cavium support in preparation for MULTIPROCESSOR support

Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.

branches: 1.89.2;
deal with Ingenic XBurst CPUs

branches: 1.88.12;
Add Broadcom BCM3302 CPU to the table.

support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory and
DMA buffers with cacheing disabled but things like write combining, relaxed
ordering etc. allowed when the CPU supports it
so far enabled only on Loongson, should work on R1xk and probably newer CPUs

loongson2f support:
- Add some loongson2 definitions to cpuregs.h, from OpenBSD
- Make sure that the at register is useable before every jump register
instruction (exept when register is k0 or k1) because -mfix-loongson2f-btb
needs the at register for its workaround
- add code to mips_fixup.c to handle the instructions added by
-mfix-loongson2f-btb
- Add a ls2-specific tlb miss handler: it doesn't have separate handler
for the xtlbmiss exeption.
- Fixes for some #ifdef MIPS3_LOONGSON2 assembly code (using the wrong
register)

Add Loongson2 DIAG register definitions (partial)

Add define for loongson2 DIAG register

Fix some comments.

Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.

Change MIPS_CP0FL_CONFIG*
Add MIPS_CP0FL_HWRENA and USERLOCAL

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

Add support for the Extensible MIPS ("eMIPS") platform. The
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the
Giano system simulator.

eMIPS is a platform developed at Microsoft Research for researching
reconfigurable computing. eMIPS allows dynamic loading and scheduling
of application-specific circuits for the purpose of accelerating
computations based on the current workload.

NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research
by Alessandro Forin and Neil Pittman. Microsoft Corporation has
donated full copyright to The NetBSD Foundation.

Platform support for eMIPS is the first part of Microsoft's
contribution. The second part includes the hardware accelerator
framework and will be proposed on tech-kern soon.

branches: 1.78.2; 1.78.4; 1.78.6;
Spell "exception" properly.

branches: 1.77.2;
Merge from matt-nb5-mips64
Merge mips-specific arch files.

LOONGSON2 is a MIPS III

Add Loongson2 chip ids

branches: 1.74.10; 1.74.28;
Add PrID's for MIPS's 24K, 24KE, 34K and 74K cores.

From Alexander Voropay in mail to port-mips@.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Recognise the R2000A cpu as found in some pmaxen.

From Dennis Grevenstein on port-pmax@.

branches: 1.71.6; 1.71.12; 1.71.20; 1.71.22; 1.71.30; 1.71.32; 1.71.34;
Don't cast pointers using unsigned and/or int. Use intptr_t or uintptr_t
as appropriate.

Fix typo in MIPS3_SR_EIE.
From Anders Gavare.

branches: 1.69.4; 1.69.6; 1.69.8; 1.69.12;
Add basic support for Alchemy Au1550 processor (CPU and devices).
Patch contributed by Garrett D'Amore in PR port-evbmips/32030.

merge ktrace-lwp.

Remove unused and incorrect MIPS_KSEG2_TO_PHYS() and MIPS_PHYS_TO_KSEG2()
macro.

Check MIPS3_CONFIG_CS and adjust csizebase at runtime on MIPS_R4100 CPUs,
and remove "XXXCDC: THIS MIPS3_4100 SPECIAL CASE SHOULD GO AWAY" part
from cpuregs.h. Tested on gxemul.

BTW, cache.c doesn't have MIPS_RC32364 config which was added
in mips_machdep.c rev 1.101?

branches: 1.65.14; 1.65.16;
Add some more MTI CPU ids.

- Add MIPS_KSEG2_TO_PHYS() and MIPS_PHYS_TO_KSEG2() macro.
- Add definitions of the MIPS4 config register.

From Christopher SEKIYA.

Add another R4000 CPU revision ID. From Christopher SEKIYA.

Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

branches: 1.61.2;
Change MIPS3_SR_FR_32 to MIPS3_SR_FR. Both the old R4000 manual and the
current MIPS64 manuals don't use the "32" in the bit name.

Remove definitions and usage of MIPS_COP_0_STATUS_REG and
MIPS_COP_0_CAUSE_REG - use MIPS_COP_0_STATUS and MIPS_COP_0_CAUSE
instead.

Add the MIPS3_CONFIG_SE (name taken from Rm52xx manual) bit, which is the
external cache enable bit -- this allows software to enable or disable the
(external) L2 cache on the R5k and Rm527x and the (external) L3 cache on
the Rm7k. If the (external) cache is disabled, treat it as if there were
no cache for the purposes of the cache setup code.

Also, update sgimips code to use the new name.

Define COP0_HAZARD_FPUENABLE as four nops.
Include <mips/sb1regs.h> if MIPS64_SB1 is defined.

Add two PRiD values.
- 0x55 for NEC Vr5500. ISA might be MIPS64.
- 0x38 for Toshiba TX79. This has thirty-two 128bit GPRs while
maintaining 32bit only virtual address space. Any of pointer related
registers have 32bit.

Add the Toshiba TX4927 CPU.

Add support for detecting Alchemy Semiconductor CPUs. Alchemy use the
processor ID field to donote the CPU core revision and the company
options field do donate the SOC chip type, so we need to add an extra
field to the "pridtab" structure to identify these CPUs.