fix various typos in comments, documentation and messages.

Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.6.4;
Fix an obvious typo. Patch from seebs in PR port-powerpc/33107.

branches: 1.5.20; 1.5.22;
merge ktrace-lwp.

branches: 1.4.16;
Use %r<n> for register names.

Switch ibm4xx over to using the more flexible powerpc bus_space/bus_dma code.

branches: 1.2.2;
Merge the IBM 4xx into the common powerpc/locore_subr.S, and
eliminate all the duplicated context switch related code in
the IBM 4xx port.

branches: 1.1.2; 1.1.4; 1.1.6;
Split off common 4xx locore code so it can be re-used by other 4xx ports.

Make ibm4xx kernels compiled by clang.

As clang cannot correctly assemble m[ft]pid:
- for asm sources, use m[ft]spr from/to SPR_PID
- for C sources, use M[FT]PID macros (see include/ibm4xx/spr.h)
This is ugly...

No binary changes for GCC-compiled kernels.

Fix comment.

ibm4xx does not use powerpc/powerpc/trap_subr.S, but
powerpc/ibm4xx/trap_subr.S.

Implement workaround for IBM405 Errata 77 (aka CPU_210), where
interrupted stwcx. may errantly write data to memory:

https://elinux.org/images/1/1d/Ppc405gp-errata.pdf

This is because stwcx. is split into two pieces in the pipeline.

We need to
(1) insert dcbt before every stwcx. instruction, as well as
(2) insert sync before every rfi/rfci instruction.

It is unclear which processors are affected, but according to Linux,
all 405-based cores up until 405GPR and 405EP are affected:

https://github.com/torvalds/linux/blob/master/arch/powerpc/platforms/40x/Kconfig#L140

For kernel, this workaround can be restricted to affected processors.
However, for kernel modules and userland, we have to enable it for all
32bit powerpc archs in order to share common binaries as before.

Proposed on port-powerpc:

http://mail-index.netbsd.org/port-powerpc/2020/02/21/msg003583.html

branches: 1.7.56; 1.7.60;
+ Load TLB-miss-address from SRR0, if ITMISS.
+ Remove a white space.

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.5.100; 1.5.104; 1.5.106;
merge ktrace-lwp.

Use %r<n> for register names.

branches: 1.3.2;
Add support for the IBM 403GCX cpu. Enabled with "options PPC_IBM403".

- different set of device control registers.
- non-standard access to the time base.
- 16 byte cache lines.

Approved by: Eduardo Horvath <eeh@netbsd.org>

Clean up some white space niggles.

branches: 1.1.2; 1.1.8; 1.1.16;
Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.

Remove MD codes from arch/powerpc/ibm4xx.

branches: 1.1.2; 1.1.4; 1.1.6; 1.1.10;
Add device_register machine-independent-glue.

Use <sys/foo.h> instead of <machine/foo.h> if such a file exists.
Don't assume <sys/cpu.h> includes <powerpc/subarch/cpu*.h>. Include it
explicitly.

branches: 1.3.98;
Remove the devprop API and switch everthing over to the new proplib. Add
a new device_properties() accessor for device_t that returns the device's
property dictionary.

branches: 1.2.4; 1.2.6; 1.2.8; 1.2.10; 1.2.12;
merge ktrace-lwp.

branches: 1.1.2; 1.1.10; 1.1.12; 1.1.14;
Add openbios-board related modules.
- openbios.c
getting board data memory image from openbios.
setting all board data to board properties database.
- board_prop.c
initialize board properties database.
(set/get board properties [macros in ibm4xx/cpu.h])

Minor style fixes to asm codes. No binary changes.

For Explora 451, call calc_delayconst() before pckbc_cnattach(), which
depends on delay() and DELAY().

Unfortunately, proplib(9) API is not available for MD codes, that are
called before consinit() (since pool(9) is not initialized yet).

Therefore, hard-code CPU frequency to calc_delayconst() in case
"processor-frequency" is not initialized.

Invoke hardclock() and statclock() in the interrupt context.

Otherwise, entropy_enter() is used instead of entropy_enter_intr() in
statclock(), which results in KASSERT() failure.

Simplify and correct stale comment; nticks-th hardclock() had no longer
been special since rev 1.24:

http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/powerpc/ibm4xx/clock.c#rev1.24

No functional changes intended.

branches: 1.29.2;
Include missing opt_ppcarch.h.

For struct timecounter, use C99 initializers.
Compile tested. No functional changes intended.

Reenable interrupt before was call pic_do_pending_int() by splx(), or KASSERT().

branches: 1.26.2; 1.26.6;
Change IBM4xx to use the common powerpc PIC framework.
Consolidate most ibm4xx initppc function into ibm4xx_init
and Make all IBM4xx use it.
Change explora to use initppc instead of bootstrap.

Use <sys/foo.h> instead of <machine/foo.h> if such a file exists.
Don't assume <sys/cpu.h> includes <powerpc/subarch/cpu*.h>. Include it
explicitly.

branches: 1.24.4;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.23.2;
Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits. Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

branches: 1.22.2;
Adapt to spr.h breakup.

branches: 1.21.10; 1.21.30; 1.21.34;
Bump uvmexp.intrs when we get a clock or statclock interrupt.

Mask is unsigned, add missing u.

Finish conversion of ppc and evbppc to timecounter.
Tested by simonb@ on WALNUT.

branches: 1.18.28; 1.18.34; 1.18.42;
Make sure we mask statclock timer on ibm4xx systems. This avoids
pthread "related" panics like:

panic: remrunqueue: bit 18 not set
Stopped in pid 479.3 (exsprite) at netbsd:cpu_Debugger+0x10: lwz
r
0, r1, 0x14
db> bt
0x869abe00: at panic+0x1b4
0x869abe50: at remrunqueue+0x80
0x869abe60: at mi_switch+0x114
0x869abea0: at sa_unblock_userret+0x4e8
0x869abee0: at syscall_plain+0x224
0x869abf40: user SC trap #93 by 0x41949810: srr1=0xc030
r1=0x445fff40 cr=0x40000002 xer=0 ctr=0x41aae208 esr=0 pid=0x36

While there, cleanup IPL_ definitions somewhat and fix interrupt mask
calculation per spl(9).

OK by matt@

branches: 1.17.4; 1.17.6;
Bring ibm4xx interrupt code up to date:

- generic soft interrupts (ie. use powerpc/softintr.c)
- interrupt event counters (using the ones from powerpc/cpu.h:cpu_info
where appropriate)
- cleanup ibm4xx_intr.h, move implementation details to intr.c

Convert all affected evbppc platforms.

OK by simonb@, some points discussed with matt@

branches: 1.16.4;
Remove the devprop API and switch everthing over to the new proplib. Add
a new device_properties() accessor for device_t that returns the device's
property dictionary.

branches: 1.15.2;
Use the SI capitalization for "Hz", "kHz", and "MHz" in comments and strings.
Add a space between numbers and Hz unit.

branches: 1.14.4; 1.14.6; 1.14.8; 1.14.10;
bare asm -> __asm

In decr_intr(), update lasttb only when clock interrupt is not masked.
(sync with macppc/macppc/clock.c: rev.1.11 -> 1.12)

branches: 1.12.2; 1.12.8;
Appease the -Wshadow and -Wcast-qual gods.

A more accurate microtime() implementation. Avoids precision
errors when the clock frequency doesn't divide nicely in to 10^9.

branches: 1.10.4;
Apply suggested changes from PR port-powerpc/24830 arch/powerpc/ibm4xx:
Bad register constraints in copyin(), copyout(), copyinstr(), copyoutstr(),
and delay().

__KERNEL_RCSID()

branches: 1.8.2;
Add support for the IBM 403GCX cpu. Enabled with "options PPC_IBM403".

- different set of device control registers.
- non-standard access to the time base.
- 16 byte cache lines.

Approved by: Eduardo Horvath <eeh@netbsd.org>

Don't need <machine/walnut.h> here.

Don't frob cpu-specific DCR registers in common code.

move more inlines to cpu.h: mftb(), mftbl() and mfpvr().
(the mftb() in pmap.c only wanted the lower 32 bits, so that's now mftbl()).

Sprinkle a small amount of KNF.

Clean up some white space niggles.

branches: 1.2.4; 1.2.6; 1.2.10;
Use properties instead of board_info.

This should be pretty standard.

Minor style fixes to asm codes. No binary changes.

copy{in,out}str: As a tiny optimization, drop redundant mtpid.

No regression for ATF on 405. 403 seems to work fine.

copy{in,out}str: Consistently use tmp as scratch register. NFC.

copy{in,out}str: "insn[TAB]operands;" for inline asm codes.

copy{in,out}str: Style sync with copy{in,out}. No binary changes.

copy{in,out}{,str}: Drop needless dcbst.

Data cache is purely physical for 40[53] with 16KB pages, and therefore
no need to flush cache before context switch.

This significantly improves copy{in,out} against small data; for example,
bytebench on DHT becomes:

-Pipe Throughput 12440.0 8826.1 7.1
+Pipe Throughput 12440.0 18364.8 14.8

No performance/ATF regression observed on 405. 403 boots successfully
into multiuser mode, and builds some packages.

copy{in,out}str: Add cr0 and ctr to list of clobbered registers.

copy{in,out}str: Consistently use uaddr instead of udaddr.
Note that we use kaddr, not kdaddr, for kernel data address.

copy{in,out}str: Tidy up inline asm's:
- Use %[foo], %[bar], ... instead of %0, %1, ...
- One instruction per line.
- Paragraph grouped instructions.
- Fix wrong comments.
No binary changes.

Make ibm4xx kernels compiled by clang.

As clang cannot correctly assemble m[ft]pid:
- for asm sources, use m[ft]spr from/to SPR_PID
- for C sources, use M[FT]PID macros (see include/ibm4xx/spr.h)
This is ugly...

No binary changes for GCC-compiled kernels.

Try to sanitize usage of isync and sync instructions.

According to reference manuals of 4xx, isync is "context synchronization",
which satisfies both 1 and 2:

1. instructions preceding it complete in the context that existed before it
2. instructions following it complete in the context that exists after it

Whereas sync (== msync for 440) is "execution synchronization", which
satisfies just 1, not 2. At the same time, sync guarantees "storage
synchronization", by which any previous storage references completes
before any subsequent instructions begin to execute.

Tested on 405 over months.

Cosmetic changes. No binary changes.

Use dcbst instead of dcbf to flush cache; the former does not invalidate
the cache line, which should be used immediately in most cases.

copy{in,out}str: Correctly return ENAMETOOLONG if source is not
NUL-terminated.

copy{in,out}str: sync style with booke.

- early return in case of len == 0
- *done = 0 on fault

branches: 1.9.60; 1.9.64;
fix copy{in,out}{,str}() to return the error returned by uvm_fault().
fixes PR 41813.

branches: 1.8.78; 1.8.98; 1.8.100;
bare asm -> __asm

merge ktrace-lwp.

branches: 1.6.12;
Apply suggested changes from PR port-powerpc/24830 arch/powerpc/ibm4xx:
Bad register constraints in copyin(), copyout(), copyinstr(), copyoutstr(),
and delay().

Remove some numeric asm labels that aren't used.

__KERNEL_RCSID()

branches: 1.3.2;
Perform a rototill of the powerpc code. Mandate use of SPRG0 to store
a pointer to current cpu's cpu_info structure. Use cpu_info for
intstk,intr_depth,still_stk,idle_pcb,curpcb,curlwp,etal even on
non-MULTIPROCESSOR machines. Add common macros GET_CPUINFO and
INIT_CPUINFO to get and initialize the cpu_info struct on startup. Make
ibm4xx use the standard <powerpc/frame.h>. Use IFRAME_xx in ibm4xx
trap_subr.S instead of explicit magic offsets. Move INTSTK and SPILLSTK
to std.<platform>. Change faultbuf to a struct instead of an array.

On MPC6XX cpus, stop using the vector page for temporary space and use
reserved space in cpu_info.

Clean up some white space niggles.

branches: 1.1.2; 1.1.8; 1.1.16;
Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.

Minor style fixes to asm codes. No binary changes.

copy{in,out}str: As a tiny optimization, drop redundant mtpid.

No regression for ATF on 405. 403 seems to work fine.

copy{in,out}str: Consistently use tmp as scratch register. NFC.

copy{in,out}str: "insn[TAB]operands;" for inline asm codes.

copy{in,out}str: Style sync with copy{in,out}. No binary changes.

copy{in,out}{,str}: Drop needless dcbst.

Data cache is purely physical for 40[53] with 16KB pages, and therefore
no need to flush cache before context switch.

This significantly improves copy{in,out} against small data; for example,
bytebench on DHT becomes:

-Pipe Throughput 12440.0 8826.1 7.1
+Pipe Throughput 12440.0 18364.8 14.8

No performance/ATF regression observed on 405. 403 boots successfully
into multiuser mode, and builds some packages.

copy{in,out}str: Add cr0 and ctr to list of clobbered registers.

copy{in,out}str: Consistently use uaddr instead of udaddr.
Note that we use kaddr, not kdaddr, for kernel data address.

copy{in,out}str: Tidy up inline asm's:
- Use %[foo], %[bar], ... instead of %0, %1, ...
- One instruction per line.
- Paragraph grouped instructions.
- Fix wrong comments.
No binary changes.

Make ibm4xx kernels compiled by clang.

As clang cannot correctly assemble m[ft]pid:
- for asm sources, use m[ft]spr from/to SPR_PID
- for C sources, use M[FT]PID macros (see include/ibm4xx/spr.h)
This is ugly...

No binary changes for GCC-compiled kernels.

Try to sanitize usage of isync and sync instructions.

According to reference manuals of 4xx, isync is "context synchronization",
which satisfies both 1 and 2:

1. instructions preceding it complete in the context that existed before it
2. instructions following it complete in the context that exists after it

Whereas sync (== msync for 440) is "execution synchronization", which
satisfies just 1, not 2. At the same time, sync guarantees "storage
synchronization", by which any previous storage references completes
before any subsequent instructions begin to execute.

Tested on 405 over months.

Cosmetic changes. No binary changes.

Use dcbst instead of dcbf to flush cache; the former does not invalidate
the cache line, which should be used immediately in most cases.

copy{in,out}str: Correctly return ENAMETOOLONG if source is not
NUL-terminated.

copy{in,out}str: sync style with booke.

- early return in case of len == 0
- *done = 0 on fault

branches: 1.9.60; 1.9.64;
fix copy{in,out}{,str}() to return the error returned by uvm_fault().
fixes PR 41813.

branches: 1.8.78; 1.8.98; 1.8.100;
bare asm -> __asm

merge ktrace-lwp.

branches: 1.6.12;
Apply suggested changes from PR port-powerpc/24830 arch/powerpc/ibm4xx:
Bad register constraints in copyin(), copyout(), copyinstr(), copyoutstr(),
and delay().

Remove some numeric asm labels that aren't used.

__KERNEL_RCSID()

branches: 1.3.2;
Perform a rototill of the powerpc code. Mandate use of SPRG0 to store
a pointer to current cpu's cpu_info structure. Use cpu_info for
intstk,intr_depth,still_stk,idle_pcb,curpcb,curlwp,etal even on
non-MULTIPROCESSOR machines. Add common macros GET_CPUINFO and
INIT_CPUINFO to get and initialize the cpu_info struct on startup. Make
ibm4xx use the standard <powerpc/frame.h>. Use IFRAME_xx in ibm4xx
trap_subr.S instead of explicit magic offsets. Move INTSTK and SPILLSTK
to std.<platform>. Change faultbuf to a struct instead of an array.

On MPC6XX cpus, stop using the vector page for temporary space and use
reserved space in cpu_info.

Clean up some white space niggles.

branches: 1.1.2; 1.1.8; 1.1.16;
Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.

Minor style fixes to asm codes. No binary changes.

Fix nearly 20 year old type - cache sizes are 2048 bytes, not 2848 bytes.

According to "PPC405GP Embedded Processor User’s Manual",
405GP has 16KB instruction cache, not 8KB.

branches: 1.36.2;
Show PVR as 8-digit hex.

Add 403 family processors other than 403GCX.

branches: 1.34.4;
Cosmetic change. No binary changes.

branches: 1.33.30; 1.33.34;
use cpu_{g,s}etmodel

branches: 1.32.2; 1.32.12; 1.32.16;
Reap the ci_ev_soft* evcnts since every variant implements __HAVE_FAST_SOFTINTS

Constify cputab.

Use <sys/foo.h> instead of <machine/foo.h> if such a file exists.
Don't assume <sys/cpu.h> includes <powerpc/subarch/cpu*.h>. Include it
explicitly.

struct device * -> device_t, struct cfdata * -> cfdata_t
CFATTACH_DECL(*, sizeof(struct device), -> CFATTACH_DECL_NEW(&, 0

branches: 1.28.2; 1.28.6;
Support PowerPC 405EX/EXr.
1. Add some new source and header files.
(MAL(split) and RGMII(new) relations for EMAC)
2. Create dcr4xx.h. Its moved from dcr405gp.h. Also remove dcr405xx.h.
3. intr.c supports MULTIUIC with virtual-irq. likes to oea.
support 32-virq/128-hwirq.
4. multiple emac support.
5. WALNUT and VIRTEX_* includes arch/powerpc/conf/files.ibm4xx.
6. WALNUT pci uses arch/powerpc/ibm4xx/pci/.

branches: 1.27.2; 1.27.4;
Ansify function definitions w/o arguments. Generated with sed.

branches: 1.26.18; 1.26.26; 1.26.32;
Set curlwp for the boot CPU before entering main().

branches: 1.25.12; 1.25.30; 1.25.32; 1.25.36; 1.25.38;
* add PVR values for Xilinx 405 cores
* don't try to decode vendor-specific PVR, print raw value instead.
* panic() if we see cache wasn't probed, we'd crash later anyway.
* rework the way PVR gets translated to core name.
* while there, normalize printf format ("%s: ...", device_xname(self), ...).

OK by matt@

Bring ibm4xx interrupt code up to date:

- generic soft interrupts (ie. use powerpc/softintr.c)
- interrupt event counters (using the ones from powerpc/cpu.h:cpu_info
where appropriate)
- cleanup ibm4xx_intr.h, move implementation details to intr.c

Convert all affected evbppc platforms.

OK by simonb@, some points discussed with matt@

branches: 1.23.4;
Remove the devprop API and switch everthing over to the new proplib. Add
a new device_properties() accessor for device_t that returns the device's
property dictionary.

branches: 1.22.4; 1.22.6; 1.22.8; 1.22.10; 1.22.12;
bare asm -> __asm

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.19.2;
Appease -Wshadow and -Wcast-qual

Uppercase CPU, plural is CPUs.

Add global cpu_model variable.

__KERNEL_RCSID()

branches: 1.15.2;
Sprinkle some TABs to line up the columns in the cputab models array.

Add support IBM 405GPr

Use PAGE_SIZE rather than NBPG.

Add support for the IBM 403GCX cpu. Enabled with "options PPC_IBM403".

- different set of device control registers.
- non-standard access to the time base.
- 16 byte cache lines.

Approved by: Eduardo Horvath <eeh@netbsd.org>

Perform a rototill of the powerpc code. Mandate use of SPRG0 to store
a pointer to current cpu's cpu_info structure. Use cpu_info for
intstk,intr_depth,still_stk,idle_pcb,curpcb,curlwp,etal even on
non-MULTIPROCESSOR machines. Add common macros GET_CPUINFO and
INIT_CPUINFO to get and initialize the cpu_info struct on startup. Make
ibm4xx use the standard <powerpc/frame.h>. Use IFRAME_xx in ibm4xx
trap_subr.S instead of explicit magic offsets. Move INTSTK and SPILLSTK
to std.<platform>. Change faultbuf to a struct instead of an array.

On MPC6XX cpus, stop using the vector page for temporary space and use
reserved space in cpu_info.

Use CFATTACH_DECL().

Declare all cfattach structures const.

Rather than referencing the cfdriver directly in the cfdata entries,
instead use a string naming the driver. The cfdriver is then looked
up in a list which is built at run-time.

Add "ecc at plb" device.
Add an "irq" locator to the plb device.
This gets rid of the original hack where ecc support was wedged into
the cpu driver.

Show the IRQ we attach the ECC handler to.

Install the ECC error interrupt handler at the level specified by
a "4xx-ecc-irq" property.
If the property isn't defined, assume the hardware has no ECC support.
This should, ideally, be a config file option.

Reorganise the IBM 4xx bus layout, using terminology from the IBM
documentation:
- Remove "mainbus" altogether.
- The new root is "plb" - the Processor Local Bus.
- Attached to this is the "opb" - the On-chip Peripheral Bus, to which
all the on-chip devices are attached (except the cpu and pci host
bridge).
- Port-specific code can pass an array of 'struct plb_dev' to
config_rootfound() to attach extra devices to the plb. The walnut
port attaches a "pbus" (Peripheral Bus) in here for the RTC and
pc keyboard controller to attach to.
There is still much 405GP specific code; the next round of changes will
generalise this to enable easier support for other 4xx CPUs.

Clean up some white space niggles.

branches: 1.2.2; 1.2.6; 1.2.8;
Use properties instead of board_info.

Add cache_info to cpu_info which provides details about D$ and I$
sizes and line sizes. This is needed for cache flusing, clearing
memory, and several other operations. This information is accessible
from userland through a new CPU_CACHEINFO sysctl.

Retire ipkdb entirely. The option was removed from the config files
yesterday.

ok kamil christos

branches: 1.23.52; 1.23.54;
Don't include *pmap.h in assembly files. Get the needed definitions
from "assym.h".

Make struct cpu_info the same size if building MODULAR
kernels or compiling a module.

Make a common genassym.cf (powerpc/genassym.cf) and then
only put specific stuff in foo/genassym.cf

Add things needed for __HAVE_FAST_SOFTINTRS

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.18.4;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.17.2;
fix copy{in,out}{,str}() to return the error returned by uvm_fault().
fixes PR 41813.

branches: 1.16.2; 1.16.4;
Rename L_ADDR to L_PCB and amend some comments accordingly.

branches: 1.15.4; 1.15.26;
Add MTX_* and RW_* definitions

branches: 1.14.12; 1.14.16;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.13.10;
Fix for yamt-idlelwp merge.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.11.26; 1.11.30; 1.11.32; 1.11.38;
merge ktrace-lwp.

branches: 1.10.8;
Split the hw-dependent powermanglement into its own function and make
Idle call that. Add a ci_idlespin function pointer to cpu_info.
Update INIT_CPUINFO to initialize it to a naked 'blr' instruction.
In oea/cpu_subr.c, add cpu_idlespin and make ci_idlespin point to it.

branches: 1.9.8;
Need offset of ci_curpm in struct cpu_info on 4xx as well.

Move SFRAMELEN to frame.h and use it in vm_machdep.c. In setfunc, setup
callframe linkages correctly. Restore use of ldptr to locore_subr.S
[pthreads and gdb no longer crash/hang the system]

Cleanup/rework cpu_switch*, switch_exit, Idle routine. Remove pcb_psl
since it was write-only. When setting up a process, make sure the fake
callframes are properly linked together.

Only lower SPL when in Idle loop. Raise spl to previous level (which would
be IPL_SCHED) when exiting Idle loop. Never lower SPL anyplace else.

Nuke ci_curpm and curpm. Nuke pcb_pmreal. Those were use for spill stacks
and those no longer exist. for few uses that need CURPM, use CURPCB/PCB_PM

catch up with changes elsewhere.

Add SFRAME_USER_SR (even though the 4XX doesn't have one).

Add each register in trapframe, switchframe, and faultbuf.

SZ_BOARD_CFG_DATA is not used anywhere, remove it.

branches: 1.1.2;
Re-arrange things in evbppc & powerpc to support OEA-based eval boards
in evbppc. OEA-based board(s) to be added later.

Use <sys/foo.h> instead of <machine/foo.h> if such a file exists.
Don't assume <sys/cpu.h> includes <powerpc/subarch/cpu*.h>. Include it
explicitly.

branches: 1.5.110;
merge ktrace-lwp.

Arrange some machine-dependent code.
- ibm40x_machdep.c: ibm40x specific
. ibm40x_memsize_init
. mem_regions
. other functions are moved to machdep.c or ibm4xx_machdep.c.
- ibm4xx_machdep.c: ibm4xx specific
. ibm4xx_init (moved from ibm40x_machdep.c)
. ibm4xx_install_extint (moved from ibm40x_machdep.c)
. ibm4xx_cpu_startup (moved from ibm40x_machdep.c:ibm4xx_startup)
. ibm4xx_dumpsys

Remove openbios dependent code from ibm4xx/ibm40x dependent module.

branches: 1.2.4; 1.2.8; 1.2.10;
Replace the traditional buffer memory management -- based on fixed per buffer
virtual memory reservation and a private pool of memory pages -- by a scheme
based on memory pools.

This allows better utilization of memory because buffers can now be allocated
with a granularity finer than the system's native page size (useful for
filesystems with e.g. 1k or 2k fragment sizes). It also avoids fragmentation
of virtual to physical memory mappings (due to the former fixed virtual
address reservation) resulting in better utilization of MMU resources on some
platforms. Finally, the scheme is more flexible by allowing run-time decisions
on the amount of memory to be used for buffers.

On the other hand, the effectiveness of the LRU queue for buffer recycling
may be somewhat reduced compared to the traditional method since, due to the
nature of the pool based memory allocation, the actual least recently used
buffer may release its memory to a pool different from the one needed by a
newly allocated buffer. However, this effect will kick in only if the
system is under memory pressure.

Add IBM40x specific machdep functions.

Delete this file because filename includes uppercase letters.

Copy IBM4xxGPx specific autoconf code from evbppc/walnut/autoconf.c.

Set com(4) frequency in ibm4xx_device_register() in order to dedup codes.

Centralize cpu_rootconf().

branches: 1.15.66; 1.15.68;
Use <sys/foo.h> instead of <machine/foo.h> if such a file exists.
Don't assume <sys/cpu.h> includes <powerpc/subarch/cpu*.h>. Include it
explicitly.

struct device * -> device_t
struct cfdata * -> cfdata_t
split device/softc (CFATTACH_DECL_NEW)
use device_accessors and device_private
constify

branches: 1.13.6;
Support PowerPC 405EX/EXr.
1. Add some new source and header files.
(MAL(split) and RGMII(new) relations for EMAC)
2. Create dcr4xx.h. Its moved from dcr405gp.h. Also remove dcr405xx.h.
3. intr.c supports MULTIUIC with virtual-irq. likes to oea.
support 32-virq/128-hwirq.
4. multiple emac support.
5. WALNUT and VIRTEX_* includes arch/powerpc/conf/files.ibm4xx.
6. WALNUT pci uses arch/powerpc/ibm4xx/pci/.

branches: 1.12.2; 1.12.4;
Unify the name of the device property to hold a MAC address - there was
no clear majority for either "mac-addr" vs. "mac-address", but a quick
gallup poll among developers selected the latter.

branches: 1.11.46;
TRUE -> true, FALSE -> false

branches: 1.10.14;
Remove the devprop API and switch everthing over to the new proplib. Add
a new device_properties() accessor for device_t that returns the device's
property dictionary.

Use opb_instance instead of dv->dv_unit when checking if we should set
the mac-addr property.

branches: 1.8.2; 1.8.4; 1.8.6;
Fix fallout from obviously untested device_is_a() rototill.

Use device_is_a()

Use device_parent().

Add an "instance" member to opb_attach_args and use it when fetching
the mac-address property from board_info. port-powerpc/32862

- Don't expose dev_propdb directly -- provide devprop_*() wrappers instead.
- Rework the ARMADILLO / epe device properties interaction so that it actually
associates the MAC address property with the epe device instance.

branches: 1.3.2; 1.3.4; 1.3.6;
merge ktrace-lwp.

branches: 1.2.2; 1.2.10; 1.2.12;
Remove openbios dependent code from ibm4xx/ibm40x dependent module.

branches: 1.1.2;
Add device_register function for all ibm4xx machine.

Convert all cnpollc callers to using true/false for consistency.

Move the at-shutdown call to resettodr() from cpu_reboot() to kern_reboot().

It's a small step, but it's a step.

Minor style fixes to asm codes. No binary changes.

Use ``for (;;)'' for infinite loop, as required by style.
No binary changes.

Centralize cpu_reboot().

branches: 1.35.2;
For booke and ibm4xx, switch to software-based single-stepping for PT_STEP
ptrace(2) command from broken hardware-based implementation.

As described in proposal on port-powerpc@,

http://mail-index.netbsd.org/port-powerpc/2021/02/26/msg003597.html

hardware debug facilities of booke and 4xx use critical interrupts, that
are difficult to handle for this purpose; they are not automatically masked
when entering kernel mode via system call trap or hardware interrupt.
See my proposal above for more details.

Now, hardware debug facilities are exclusively usable by kernel itself.
They are much more functional than PSL_SE MSR bit of oea, and should be
useful to, e.g., support byte-granular watchpoint for DDB in the future.

white space --> tab

Sort headers. No functional changes intended.

branches: 1.32.2;
Set cpu_psluserset, cpu_pslusermod, cpu_pslusermask for MODULAR.

Drop unused opt_compat_netbsd.h include.

Style and cosmetic changes. No binary changes intended.

uvm_availmem(): give it a boolean argument to specify whether a recent
cached value will do, or if the very latest total must be fetched. It can
be called thousands of times a second and fetching the totals impacts not
only the calling LWP but other CPUs doing unrelated activity in the VM
system.

Rename uvm_free() -> uvm_availmem().

uvmexp.free -> uvm_free()

Retire ipkdb entirely. The option was removed from the config files
yesterday.

ok kamil christos

branches: 1.25.14; 1.25.16;
Assert that the size of a trap handler does not exceed its room.

XXX
The debug exception is critical for ibm4xx. Since rev 1.24, we use the critical
trap hundler for it. Sorry for the wrong commit log for rev 1.24.

No need to have same trap handlers in trap_subr.S.
No functional changes.

We cannot have DDB and IPKDB at the same time.

switch all ports to use uvm_init.c:uvm_md_init()

uvm_setpagesize() is now subsumed within this funciton.

Fix typo: s/IPKBD/IPKDB/

Fix comments. No functional changes.

Fix build without DDB.

branches: 1.18.6; 1.18.24; 1.18.28;
Remove white-spaces.
Indents.

branches: 1.17.2; 1.17.6;
Change IBM4xx to use the common powerpc PIC framework.
Consolidate most ibm4xx initppc function into ibm4xx_init
and Make all IBM4xx use it.
Change explora to use initppc instead of bootstrap.

Use <sys/foo.h> instead of <machine/foo.h> if such a file exists.
Don't assume <sys/cpu.h> includes <powerpc/subarch/cpu*.h>. Include it
explicitly.

branches: 1.15.4;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.14.2;
Add a #include <machine/pcb.h>

branches: 1.13.2;
Adapt to spr.h breakup.

branches: 1.12.2;
- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

Kill proc0paddr. Use lwp0.l_addr instead.

Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.

Add a flags argument to pmap_kenter_pa(9).
Patch showed on tech-kern@ http://mail-index.netbsd.org/tech-kern/2009/11/04/msg006434.html
No objections.

branches: 1.8.18;
Replce exec_map with a pool. Proposed on tech-kern@, reviewed by chs@.

branches: 1.7.40; 1.7.44; 1.7.46; 1.7.48;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

TRUE -> true, FALSE -> false

branches: 1.5.26;
bare asm -> __asm

merge ktrace-lwp.

branches: 1.3.2; 1.3.4; 1.3.6;
Move the MI printing of `copyright' to the MD cpu_startup() code
where the printing of `version' is already performed.
This has the benefit of allowing the copyright to be available
via dmesg(8) on platforms which need the `msgbuf' to be setup
in cpu_startup() before printed output is remembered.

merge yamt-km branch.
- don't use managed mappings/backing objects for wired memory allocations.
save some resources like pv_entry. also fix (most of) PR/27030.
- simplify kernel memory management API.
- simplify pmap bootstrap of some ports.
- some related cleanups.

branches: 1.1.2; 1.1.4;
Arrange some machine-dependent code.
- ibm40x_machdep.c: ibm40x specific
. ibm40x_memsize_init
. mem_regions
. other functions are moved to machdep.c or ibm4xx_machdep.c.
- ibm4xx_machdep.c: ibm4xx specific
. ibm4xx_init (moved from ibm40x_machdep.c)
. ibm4xx_install_extint (moved from ibm40x_machdep.c)
. ibm4xx_cpu_startup (moved from ibm40x_machdep.c:ibm4xx_startup)
. ibm4xx_dumpsys

Move cpu_configure to evbppc/*.c.
(Remove ibm4xxgpx_autoconf.c)
I'm sorry for my wrong thinking.

branches: 1.5.4; 1.5.6; 1.5.8; 1.5.12;
bare asm -> __asm

merge ktrace-lwp.

branches: 1.3.10;
Remove device_register, cpu_rootconf functions.
These functions are moved to ibm4xx/autoconf.c.

Centralize the declaration of booted_device and booted_partition.

branches: 1.1.4; 1.1.6;
Copy IBM4xxGPx specific autoconf code from evbppc/walnut/autoconf.c.

Change IBM4xx to use the common powerpc PIC framework.
Consolidate most ibm4xx initppc function into ibm4xx_init
and Make all IBM4xx use it.
Change explora to use initppc instead of bootstrap.

Use <sys/foo.h> instead of <machine/foo.h> if such a file exists.
Don't assume <sys/cpu.h> includes <powerpc/subarch/cpu*.h>. Include it
explicitly.

branches: 1.24.6;
Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits. Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

Support PowerPC 405EX/EXr.
1. Add some new source and header files.
(MAL(split) and RGMII(new) relations for EMAC)
2. Create dcr4xx.h. Its moved from dcr405gp.h. Also remove dcr405xx.h.
3. intr.c supports MULTIUIC with virtual-irq. likes to oea.
support 32-virq/128-hwirq.
4. multiple emac support.
5. WALNUT and VIRTEX_* includes arch/powerpc/conf/files.ibm4xx.
6. WALNUT pci uses arch/powerpc/ibm4xx/pci/.

branches: 1.22.2;
Adapt to spr.h breakup.

branches: 1.21.4;
Account ci->ci_idepth on calling handlers in ext_intr() as well as
powerpc/pic/intr.c:pic_handle_intr(). Closes PR port-evbppc/40288.

Should be pulled up to netbsd-5.

branches: 1.20.6; 1.20.10; 1.20.18; 1.20.20;
Merge vmlocking2 to head.

branches: 1.19.2; 1.19.6;
Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

branches: 1.18.2;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.17.4; 1.17.6;
Handle IST_LEVEL interrupts better. Disable interrupt while it is
processed and enable afterwards. Up to now IST_LEVEL interrupts always
fired again during processing leaving unnecessary pending interrupts.

Tested on EXPLORA451.

Ok: Simon Burge <simonb@netbsd.org>

branches: 1.16.6; 1.16.14; 1.16.16; 1.16.18;
Make these compile again.

Welcome to evbppc/virtex -- port to Xilinx Virtex series FPGA's with embedded
ibm405d5 core.

OK by Simon Burge

Make sure we mask statclock timer on ibm4xx systems. This avoids
pthread "related" panics like:

panic: remrunqueue: bit 18 not set
Stopped in pid 479.3 (exsprite) at netbsd:cpu_Debugger+0x10: lwz
r
0, r1, 0x14
db> bt
0x869abe00: at panic+0x1b4
0x869abe50: at remrunqueue+0x80
0x869abe60: at mi_switch+0x114
0x869abea0: at sa_unblock_userret+0x4e8
0x869abee0: at syscall_plain+0x224
0x869abf40: user SC trap #93 by 0x41949810: srr1=0xc030
r1=0x445fff40 cr=0x40000002 xer=0 ctr=0x41aae208 esr=0 pid=0x36

While there, cleanup IPL_ definitions somewhat and fix interrupt mask
calculation per spl(9).

OK by matt@

branches: 1.13.4; 1.13.6;
Fix recent ibm4xx/intr.c rework:

- Recalculate masks _after_ new interrupt handler is enqueued, otherwise
the very last one won't ever be enabled (from hannken@)

- We can't use splhigh() to protect intr_calculatemasks() since it would
use soon-to-be-invalid mask. Instead, fiddle PSL_EE directly as we do
in other places.

Reviewed and tested (evbppc/explora) by hannken@

Bring ibm4xx interrupt code up to date:

- generic soft interrupts (ie. use powerpc/softintr.c)
- interrupt event counters (using the ones from powerpc/cpu.h:cpu_info
where appropriate)
- cleanup ibm4xx_intr.h, move implementation details to intr.c

Convert all affected evbppc platforms.

OK by simonb@, some points discussed with matt@

branches: 1.11.2;
Merge multiple definitions of cntlzw() ("count leading zeros")
instruction-wrapper to <powerpc/cpu.h>.

OK by briggs@

branches: 1.10.4; 1.10.8; 1.10.14;
bare asm -> __asm

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.7.2;
Appease -Wcast-qual

__KERNEL_RCSID()

branches: 1.5.2;
Rename IPL_IMP -> IPL_VM.

Add support for the IBM 403GCX cpu. Enabled with "options PPC_IBM403".

- different set of device control registers.
- non-standard access to the time base.
- 16 byte cache lines.

Approved by: Eduardo Horvath <eeh@netbsd.org>

Clean up some white space niggles.

branches: 1.2.2;
Remove redundant declarations.

branches: 1.1.2; 1.1.6;
Generalized IBM UIC driver.

Remove MD codes from arch/powerpc/ibm4xx.

branches: 1.2.2; 1.2.4; 1.2.8;
Add consinit() and md_consinit funcptr to ibm4xx/machdep.c.
Rename consinit() to obs405_consinit() at evbppc/obs405/consinit.c.

Set md_consinit to obs405_consinit() at initppc().
Consinit fuction calls a function stored at md_consinit pointer.

Add ibm4xx family common module.
- machine-dependent global variables
- cpu_startup glue
- softnet/softserial (copy from ibm40x_machdep.c)

Reorganise the IBM 4xx bus layout, using terminology from the IBM
documentation:
- Remove "mainbus" altogether.
- The new root is "plb" - the Processor Local Bus.
- Attached to this is the "opb" - the On-chip Peripheral Bus, to which
all the on-chip devices are attached (except the cpu and pci host
bridge).
- Port-specific code can pass an array of 'struct plb_dev' to
config_rootfound() to attach extra devices to the plb. The walnut
port attaches a "pbus" (Peripheral Bus) in here for the RTC and
pc keyboard controller to attach to.
There is still much 405GP specific code; the next round of changes will
generalise this to enable easier support for other 4xx CPUs.

Clean up some white space niggles.

branches: 1.1.2; 1.1.6; 1.1.8;
Generic mainbus driver.

Fix hard freeze in pic_handle_intr() for PPC_IBM403.

Not clearly documented in reference manual, but DCR_EXISR register is
not updated immediately after some bits are cleared by mtdcr, no matter
whether sync (= eieio) and/or isync are issued.

Therefore, we have to manage our own status mask in the interrupt handler.
This is what we did in obsoleted powerpc/ibm4xx/intr.c.

With this change, my Explora 451 works just fine with serial console!
Fix for framebuffer console will be committed soon.

Switch to intr_establish_xname().

branches: 1.7.2;
Include missing opt_ppcarch.h and opt_uic.h.

Style and cosmetic changes. No binary changes intended.

Remove unused macros.

branches: 1.4.30; 1.4.34;
Fix IPL for cascading pic to HIGH.

branches: 1.3.6; 1.3.10;
Use kmem instead of malloc. Remove unneeded <sys/malloc.h> includes.

Fix the mistake in level and type.

branches: 1.1.2; 1.1.4; 1.1.8;
Change IBM4xx to use the common powerpc PIC framework.
Consolidate most ibm4xx initppc function into ibm4xx_init
and Make all IBM4xx use it.
Change explora to use initppc instead of bootstrap.

s/againt/against/ in comment.

ppc4xx_tlb_enter: One more style sync. No binary changes.

Use hi and lo instead of th and tl for TLBHI and TLBLO, respectively,
as done for other functions in pmap.c.

Use %[foo], %[bar], ... instead of %0, %1, ... for asm codes.
Unify variable names if possible. No binary changes.

Minor style fixes to asm codes. No binary changes.

Make ibm4xx kernels compiled by clang.

As clang cannot correctly assemble m[ft]pid:
- for asm sources, use m[ft]spr from/to SPR_PID
- for C sources, use M[FT]PID macros (see include/ibm4xx/spr.h)
This is ugly...

No binary changes for GCC-compiled kernels.

pte_enter() and pmap_enter_pv(): return zero for success, and
non-zero value for failure, as normally expected.

Now, ctx_flush() never fails. So, make this function void.

pmap_enter_pv(): At the moment, this function is always called with
pmap_initialized. So, convert test for this condition to KASSERT.

pmap_enter_pv(): No need to initialize npv to NULL.

No functional changes intended.

pmap_testout(): Use pmap_{protect,remove}() for va to (va + PAGE_SIZE),
instead of (va + 1).

No functional changes for the current implementation. Also, this affects
only when the function is manually called from DDB on DEBUG kernel.

if (cond) panic() or Debugger() in #ifdef DIAGNOSTIC ---> KASSERT(!cond)

There is no regression observed during a full ATF run.

Style. No binary changes.

Also, remove old #if-0'ed code block copied from oea (and therefore
will never be enabled).

Use uvm_km_alloc(9) with UVM_KMF_NOWAIT flag in pte_enter(), in order not to
sleep in pmap_enter(9) and pmap_kenter_pa(9), which can result in dead lock.

In most cases, pmap_enter(9) is used with PMAP_CANFAIL flag. In this case,
if pte_enter() fails due to uvm_km_alloc(9), we can safely return ENOMEM.
UVM layer will take care of it.

uvm_km_alloc(9) fails for pmap_enter(9) without PMAP_CANFAIL or for
pmap_kenter_pa(9), we have no choice but to panic there.

However, my testbeds for 403 and 405 survive more than a week at least
without hitting this panic.

Style fixes:

- Add "static inline" to pte_enter(), to match with its declaration.
- Remove parentheses from return.
- Use NULL instead of 0 for pointer initialization.

No binary changes.

G/C misleading <evbppc/tlb.h>. Use <powerpc/ibm4xx/tlb.h> directly.

branches: 1.95.2; 1.95.4;
Tiny cosmetic fix for previous. No functional changes.

Real fix for pmap_procwr(), attempted in revs 1.85 and 1.87:
http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/powerpc/ibm4xx/pmap.c#rev1.85
http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/powerpc/ibm4xx/pmap.c#rev1.87

ibm4xx has VIPT icache and operations in pmap_procwr() should be done with
DMMU enabled (write back dcache into memory and invalidate icache).

When p == curproc, this is trivial. However, p != curproc needs a special
care; we cannot rely upon TLB miss handler in user context. Therefore,
extract pa and operate against it.

Note that va below VM_MIN_KERNEL_ADDRESS (== 2GB at the moment) is reserved
for direct mapping.

Tested by gdb with WIP software single stepping for ibm4xx.

Introduce PMAP_TLBDEBUG option for ibm4xx: clear only TLBHI[V] bit when
TLB entry is invalidated, instead of clearing entire TLBHI register.

pmap_kenter_pa: Remove comment which says ``Have to remove any existing
mapping first.'' Contrary to this comment, pmap_kremove(9) has never
been called there since rev 1.1, and we don't for other ports also.

Introduce PV_VA() macro to extract va from pv->pv_va by clearing
PV_WIRED flag, and use it where appropriate.

There should be no functional changes. Only for safety in future.

Include missing opt_ddb.h.

Remove evcnt(9) counter for tlbhit; there's no way to observe TLB hits
from kernel, and it just counted intersection b/w tlbmiss and tlbenter.

Try to sanitize usage of isync and sync instructions.

According to reference manuals of 4xx, isync is "context synchronization",
which satisfies both 1 and 2:

1. instructions preceding it complete in the context that existed before it
2. instructions following it complete in the context that exists after it

Whereas sync (== msync for 440) is "execution synchronization", which
satisfies just 1, not 2. At the same time, sync guarantees "storage
synchronization", by which any previous storage references completes
before any subsequent instructions begin to execute.

Tested on 405 over months.

Oops, commit log was missing. It should be:

Revert rev 1.85:
http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/powerpc/ibm4xx/pmap.c#rev1.85

Not clearly documented in reference manual, but the previous code seems
correct; the operations must be carried out with DMMU disabled. Otherwise,
WIP software single step for userland does not work correctly (stalled
indefinitely at pmap_procwr()).

XXX
pullup to netbsd-9

*** empty log message ***

Fix pmap_procwr().

While we need to turn off IMMU, DMMU should be kept on. Otherwise,
dcbst (and also icbi probably, though not documented clearly both
for 405 and 403) should not work correctly.

Retire tlbpid_t (u_short):

- PID (ctx, ASID) is 8-bit length, not half word.
- For struct pmap, no need to use integer types smaller than word as
pm_ctx because of alignment.
- For ppc4xx_tlb_enter(), we need word-length storage for pid (and msr).

XXX
Better to rewrite pmap module with more suggestive integer types rather
than char, int, long, and so on.

pmap_procwr(): use dcbst instead of dcbf as a tiny optimization.

ppc4xx_tlb_enter(): invalidate entry after clearing MSR for sure.

Misc non-critical fixes.

- __asm --> __asm volatile for sure
- turn DEBUG code in __asm into DIAGNOSTIC code in C
- style

In ppc4xx_tlb_find_victim(), mark kernel stack page TLBF_REF instead of
TLBF_USED. This should be originally intended behavior of this code
segment, because

- TLBF_USED is already checked just before, so marking this page
TLBF_USED is no-op.
- TLBF_REF flag exempts that page from being flushed from TLB in next
scan, when kernel stack may be still there with high probability.

Clear ti_ctx when flushing a TLB entry for clarity.

Fix off-by-one error for ctx (ASID).

Note that NUM_CTX = 256 = 0 stands for disabling protection by ASID.

Fix NULL dereference; "pap" argument of pmap_extract(9) can be NULL.

branches: 1.76.16; 1.76.20; 1.76.22;
Conform API use of uvm_hotplug(9) to documented behaviour:

When testing for an invalid uvm_physseg_t,
compare with UVM_PHYSSEG_TYPE_INVALID which is implementation agnostic.

introduce evbppc pmap to the uvm_hotplug(9) API

Should fix build.

"Make NetBSD great again!"

Introduce uvm_hotplug(9) to the kernel.

Many thanks, in no particular order to:

TNF, for funding the project.

Chuck Silvers - for multiple API reviews and feedback.
Nick Hudson - for testing on multiple architectures and bugfix patches.
Everyone who helped with boot testing.

KeK (http://www.kek.org.in) for hosting the primary developers.

switch all ports to use uvm_init.c:uvm_md_init()

uvm_setpagesize() is now subsumed within this funciton.

branches: 1.72.6; 1.72.24; 1.72.28;
extending vmem(9) to be able to allocated resources for it's own needs.
simplifying uvm_map handling (no special kernel entries anymore no relocking)
make malloc(9) a thin wrapper around kmem(9)
(with private interface for interrupt safety reasons)

releng@ acknowledged

Move spl from ppc4xx_tlb_enter() to pmap_enter(). Don't call splx() on
I/DTLBMISS.

branches: 1.70.2; 1.70.6;
Modify mapiodev to take a third argument indicating whether the space
should be prefetchable (true) or not (false).

Switch to using dcache_wbinv_page

Get rid of extern inline.
Cleanup includes.
Rearrange pv_entry so that are pointers are first.

Use <sys/foo.h> instead of <machine/foo.h> if such a file exists.
Don't assume <sys/cpu.h> includes <powerpc/subarch/cpu*.h>. Include it
explicitly.

branches: 1.66.2;
Use EVCNT_ATTACH_STATIC

branches: 1.65.2; 1.65.4;
Retire struct user, remove sys/user.h inclusions. Note sys/user.h header
as obsolete. Remove USER_TO_UAREA/UAREA_TO_USER macros.

Various #include fixes and review by matt@.

Use more VM_PHYSMEM_*() accessors. No functional changes.

Merge from uebayasi-xip:

Teach TLB miss handler (pmap_tlbmiss()) to map "Expansion ROM" area as
PA == VA. Now we don't need to reserve a TLB entry for it.

branches: 1.62.2;
Adapt to spr.h breakup.

s/cpu_fork/cpu_lwp_fork/ in comment

branches: 1.60.2;
Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.

Add a flags argument to pmap_kenter_pa(9).
Patch showed on tech-kern@ http://mail-index.netbsd.org/tech-kern/2009/11/04/msg006434.html
No objections.

Remove uarea swap-out functionality:

- Addresses the issue described in PR/38828.
- Some simplification in threading and sleepq subsystems.
- Eliminates pmap_collect() and, as a side note, allows pmap optimisations.
- Eliminates XS_CTL_DATA_ONSTACK in scsipi code.
- Avoids few scans on LWP list and thus potentially long holds of proc_lock.
- Cuts ~1.5k lines of code. Reduces amd64 kernel size by ~4k.
- Removes __SWAP_BROKEN cases.

Tested on x86, mips, acorn32 (thanks <mpumford>) and partly tested on
acorn26 (thanks to <bjh21>).

Discussed on <tech-kern>, reviewed by <ad>.

Add a real API for testing if a page is a managed page, and adjust callers
to stop relying on vm_physseg_find() for this purpose.

Remove all declarations of physmem from sys/arch. Add an include of
<sys/systm.h> to the one file that did not already contain it.
This now means that physmem can be changed by updating systm.h and uvm_page.c
(excluding fixing printfs)

Follow up the changed prototype of pmap_enter(), flag from int to u_int.

Ansify function definitions w/o arguments. Generated with sed.

Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.

branches: 1.52.2;
Make kernel_pmap_ptr a const. Requested by steve_martin.

Make pmap_kernel() a MI macro for struct pmap *kernel_pmap_ptr,
which is now the "API" provided by the pmap module. pmap_kernel()
remains as the syntactic sugar.

Bonus cosmetics round: move all the pmap_t pointer typedefs into
uvm_pmap.h.

Thanks to Greg Oster for providing cpu muscle for doing test builds.

branches: 1.50.16; 1.50.20; 1.50.26; 1.50.28; 1.50.40;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.49.6;
Use PR_NOWAIT in in pmap_enter_pv() and take care of PMAP_CANFAIL. Built
after powerpc/oea/pmap.c. Now a LOCKDEBUG kernel runs on EXPLORA451.

Ok: Simon Burge <simonb@netbsd.org>

branches: 1.48.8; 1.48.10; 1.48.12;
Pass an ipl argument to pool_init/POOL_INIT to be used when initializing
the pool's lock.

branches: 1.47.2;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

TRUE -> true, FALSE -> false

Replace the Mach-derived boolean_t type with the C99 bool type. A
future commit will replace use of TRUE and FALSE with true and false.

branches: 1.44.4;
Instead of mapping whole RAM with reserved TLB entries, map just enough
to ensure trap code will work (that is 0 upto ${endkernel}) and leave the
rest to pmap_tlbmiss(). Mapping whole physmem into the kernel wired way
too many TLB entries, see

http://mail-index.netbsd.org/port-powerpc/2006/10/27/0000.html

for performance analysis. While there, be a bit more descriptive in
pmap_tlbmiss() comment and use macro instead of numeric constant.

OK by Simon Burge

* convert ibm4xx-based evbppc from reserved-TLB entry allocation to recently
introduced ppc4xx_tlb_reserve() API.

branches: 1.42.2; 1.42.4;
* ppc4xx_tlb_reserve(): allocate "reserved" TLB entries dynamically
* ppc4xx_tlb_mapiodev(): resolve pa to va from reserved TLB entries

OK by matt@

XXX we'll keep TLB_NRESERVED defined until we fix explora to use new API

Remove unused ppc4xx_tlb_unpin() function.

Remove some unused variables.

branches: 1.39.4; 1.39.8; 1.39.16;
bare asm -> __asm

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.36.2;
Appease the -Wshadow and -Wcast-qual gods.

pmap_testout: fix too many arguments for pmap_kenter_pa.
from Shoichi Miyake. PR/29914.

merge yamt-km branch.
- don't use managed mappings/backing objects for wired memory allocations.
save some resources like pv_entry. also fix (most of) PR/27030.
- simplify kernel memory management API.
- simplify pmap bootstrap of some ports.
- some related cleanups.

fix two bugs with wiring:
(1) in pmap_enter_pv(), we would always mark the header entry wired, even if
the new entry wasn't put there. noticed by Juergen Hannken-Illjes.
(2) in pmap_unwire(), we would never examine the header entry.
noticed by me.

while I'm here, move the counter increment in the pmap_enter() path to be
next to the corresponding PV_WIRE() call so it's more obvious they match.

KNF: put "if (...)" and following statement on separate lines.

Fix a typo in a printf string.

branches: 1.30.2;
implement pmap_wired_count(). fix some places we would forget to splx().
move the parts of pte.h that were used into pmap.c (since they were really
pmap-internal details) and delete ibm4xx/pte.h. other misc cleanup.

branches: 1.29.4;
Remove some debug printf()s.
Reorder an evcnt_attach_static().

Use uvm_km_zalloc(...) instead of uvm_km_alloc1(...,1).

Need Data Relocate in the MSR for the dcbf in pmap_procwr().
From Matt Thomas.

add support for non-executable mappings (where the hardware allows this)
and make the stack and heap non-executable by default. the changes
fall into two basic catagories:

- pmap and trap-handler changes. these are all MD:
= alpha: we already track per-page execute permission with the (software)
PG_EXEC bit, so just have the trap handler pay attention to it.
= i386: use a new GDT segment for %cs for processes that have no
executable mappings above a certain threshold (currently the
bottom of the stack). track per-page execute permission with
the last unused PTE bit.
= powerpc/ibm4xx: just use the hardware exec bit.
= powerpc/oea: we already track per-page exec bits, but the hardware only
implements non-exec mappings at the segment level. so track the
number of executable mappings in each segment and turn on the no-exec
segment bit iff the count is 0. adjust the trap handler to deal.
= sparc (sun4m): fix our use of the hardware protection bits.
fix the trap handler to recognize text faults.
= sparc64: split the existing unified TSB into data and instruction TSBs,
and only load TTEs into the appropriate TSB(s) for the permissions.
fix the trap handler to check for execute permission.
= not yet implemented: amd64, hppa, sh5

- changes in all the emulations that put a signal trampoline on the stack.
instead, we now put the trampoline into a uvm_aobj and map that into
the process separately.

originally from openbsd, adapted for netbsd by me.

Nuke ci_curpm and curpm. Nuke pcb_pmreal. Those were use for spill stacks
and those no longer exist. for few uses that need CURPM, use CURPCB/PCB_PM

Remove an unused variable.

__KERNEL_RCSID()

Fix resident page accounting for the kernel pmap.

branches: 1.21.2;
Back out the following chagne:
http://mail-index.netbsd.org/source-changes/2003/05/08/0068.html

There were some side-effects that I didn't anticipate, and fixing them
is proving to be more difficult than I thought, do just eject for now.
Maybe one day we can look at this again.

Fixes PR kern/21517.

Simplify the way the bounds of the managed kernel virtual address
space is advertised to UVM by making virtual_avail and virtual_end
first-class exported variables by UVM. Machine-dependent code is
responsible for initializing them before main() is called. Anything
that steals KVA must adjust these variables accordingly.

This reduces the number of instances of this info from 3 to 1, and
simplifies the pmap(9) interface by removing the pmap_virtual_space()
function call, and removing two arguments from pmap_steal_memory().

This also eliminates some kludges such as having to burn kernel_map
entries on space used by the kernel and stolen KVA.

This also eliminates use of VM_{MIN,MAX}_KERNEL_ADDRESS from MI code,
this giving MD code greater flexibility over the bounds of the managed
kernel virtual address space if a given port's specific platforms can
vary in this regard (this is especially true of the evb* ports).

Use PAGE_SIZE rather than NBPG.

Add support for the IBM 403GCX cpu. Enabled with "options PPC_IBM403".

- different set of device control registers.
- non-standard access to the time base.
- 16 byte cache lines.

Approved by: Eduardo Horvath <eeh@netbsd.org>

Merge the nathanw_sa branch.

writable, not writeable.

Make this compile without DDB.

Use EVCNT_TYPE_TRAP.

remove trailing \n in panic(). approved perry.

Clean up some white space niggles.

branches: 1.11.2;
Follow the post-UBC semantics of resetting ref/mod collection inside of
pmap_clear_{reference,modify}().

pmap improvements:

Remove the cache flush routines that have been moved to cpu.c

Make sure we clear out the unused PA bits in the TTE which causes breakage
on some MMU models.

Pool deals fairly well with physical memory shortage, but it doesn't
deal with shortages of the VM maps where the backing pages are mapped
(usually kmem_map). Try to deal with this:

* Group all information about the backend allocator for a pool in a
separate structure. The pool references this structure, rather than
the individual fields.
* Change the pool_init() API accordingly, and adjust all callers.
* Link all pools using the same backend allocator on a list.
* The backend allocator is responsible for waiting for physical memory
to become available, but will still fail if it cannot callocate KVA
space for the pages. If this happens, carefully drain all pools using
the same backend allocator, so that some KVA space can be freed.
* Change pool_reclaim() to indicate if it actually succeeded in freeing
some pages, and use that information to make draining easier and more
efficient.
* Get rid of PR_URGENT. There was only one use of it, and it could be
dealt with by the caller.

From art@openbsd.org.

Rename NOCACHE -> PPC_4XX_NOCACHE to avoid conflict with the namei
flag of the same name.

From Frank van der Linden <fvdl@wasabisystems.com>.

Reset the unused RPN bits in a TLBLO to 0, as specified by the PPC401B3
user's manual, page 8-40.

From Frank van der Linden <fvdl@wasabisystems.com>.

In pmap_enter(), sync the instruction cache if VM_PROT_EXECUTE. Fixes
problems when executing programs where text is copied to a page without
a dma sync (like NFS data bcopy'd to a buffer cache page).

From discussion with Jason Thorpe and Eduardo Horvath.

branches: 1.5.2; 1.5.4;
Implement pmap_growkernel().

Update pmap_update to now take the updated pmap as an argument.
This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.

Currently this is a no-op on most platforms, so they should see no difference.

Reviewed by Jason.

branches: 1.3.2;
Replace memcpy's of obviously overlapping regions with memmove.
Noted by Izumi Tsutsui.

bcopy -> memcpy, bzero -> memset, bcmp -> memcmp.
Reviewed by Matt Thomas, ok'd by Tsubai Masanari.

branches: 1.1.2;
Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.

branches: 1.1.2;
file pmap.c.work was initially added on branch uebayasi-xip.

Arrange to update cached LWP credentials in userret() rather than during
syscall/trap entry, eliminating a test+branch on every syscall/trap.

This wasn't possible in the 3.99.x timeframe when l->l_cred came about
because there wasn't a reliable/timely way to force an ONPROC LWP running on
a remote CPU into the kernel (which is just about the only new thing in
this scheme).

Minor style fixes to asm codes. No binary changes.

copy{in,out}{,str}: Drop needless dcbst.

Data cache is purely physical for 40[53] with 16KB pages, and therefore
no need to flush cache before context switch.

This significantly improves copy{in,out} against small data; for example,
bytebench on DHT becomes:

-Pipe Throughput 12440.0 8826.1 7.1
+Pipe Throughput 12440.0 18364.8 14.8

No performance/ATF regression observed on 405. 403 boots successfully
into multiuser mode, and builds some packages.

Work around clang 13.0.0 bug; copy{in,out}() are miscompiled with -O[12],
by which /sbin/init cannot be executed.

Make ibm4xx kernels compiled by clang.

As clang cannot correctly assemble m[ft]pid:
- for asm sources, use m[ft]spr from/to SPR_PID
- for C sources, use M[FT]PID macros (see include/ibm4xx/spr.h)
This is ugly...

No binary changes for GCC-compiled kernels.

copy{in,out}(): Minor clean up:
- No need to supply count (== 0).
- %r0 can be used as %[ctx] and %[len].

copyin(): Remove one more needless mtpid. No regression for full ATF.

copyin(): Fix comment. No binary changes.

copy{in,out}(): Tiny optimizations for __asm codes.
No regressions for full ATF run.

- Use {l,st}swx instead of loop for remaining bytes.
- Drop needless "mtpid %[x]; isync;".

copy{in,out}(): Add missing clobber registers to __asm codes.

copy{in,out}(): Add missing ``if (count == 0) goto done;''.

copy{in,out}(): Consistently use %[tmp] as scratch register. NFC.

copyin(): Fix copy-paste in comment. No binary changes.

copy{in,out}(): Cosmetic changes to __asm codes. No binary changes.

- Editor-friendly indentation.
- One insn per line.
- Group insns with logical blocks.

s/udaddr/uaddr/g for consistency; we use kaddr for kernel data address.
No binary changes.

For IBM_PPC403, emulate unaligned memory access for userland process.

For booke and ibm4xx, switch to software-based single-stepping for PT_STEP
ptrace(2) command from broken hardware-based implementation.

As described in proposal on port-powerpc@,

http://mail-index.netbsd.org/port-powerpc/2021/02/26/msg003597.html

hardware debug facilities of booke and 4xx use critical interrupts, that
are difficult to handle for this purpose; they are not automatically masked
when entering kernel mode via system call trap or hardware interrupt.
See my proposal above for more details.

Now, hardware debug facilities are exclusively usable by kernel itself.
They are much more functional than PSL_SE MSR bit of oea, and should be
useful to, e.g., support byte-granular watchpoint for DDB in the future.

branches: 1.85.2;
For booke and ibm4xx, emulate m[ft]msr in user mode, in the same
manner as oea.

Now, user process can decide by itself whether floating-point
exception triggers SIGFPE or not via fenv(3).

Treat trap instruction from userland correctly in EXC_PGM handler;
raise SIGTRAP with TRAP_BRKPT instead of SIGILL.

- Drop unused opt_altivec.h.
- Include missing opt_ppcarch.h.

Style and cosmetic changes. No binary changes intended.

Try to sanitize usage of isync and sync instructions.

According to reference manuals of 4xx, isync is "context synchronization",
which satisfies both 1 and 2:

1. instructions preceding it complete in the context that existed before it
2. instructions following it complete in the context that exists after it

Whereas sync (== msync for 440) is "execution synchronization", which
satisfies just 1, not 2. At the same time, sync guarantees "storage
synchronization", by which any previous storage references completes
before any subsequent instructions begin to execute.

Tested on 405 over months.

Return correct signo and si_code to userland when page fault.
Taken from powerpc/trap.c. Found by tests in lib/libc/sys.

Return error code from uvm layer on fault, instead of hard-coded 1.
Found by some tests in tests/lib/libc/sys.

Do not try to recovery from data page fault in interrupt context;
catch up belatedly with powerpc/trap.c rev 1.49 and etc.:

http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/powerpc/powerpc/trap.c#rev1.49

Tiny improvements to copyin() and copyout():

- Use lwz/stw instead of 4-byte lswi/stswi for 405 and later, which
support unaligned word load/store by hardware. In many cases, both
source and destination are aligned on word boundaries.

- Use dcbst instead of dcbf to flush cache. The former does not
invalidate the cache line. Copied data should be used soon after.

Cosmetic changes for assembler codes. No binary changes.

Comment out badaddr() and badaddr_read() on ibm4xx for now.

They are not used nor exposed externally in any header file; these
functions may have never been tested so far.

Enable them again when necessary.

Note that badaddr() for oea is used by macppc port, where it is
declared as an external function.

Oops, sort header again. My bad...

Convert mi_userret(9) into powerpc-specific userret().

This is necessary in order to support RAS.

There are some sanity checks in userret() as well.

Sort more headers...

Sort headers.

branches: 1.70.4; 1.70.6;
Detangle some of the PowerPC CPU configuration spaghetti.

branches: 1.69.16;
Remove wrong comment which was copy-and-pasted from somewhere.

Remove needless goto's. No functional changes.

branches: 1.67.2; 1.67.4;
src is too big these days to tolerate superfluous apostrophes. It's
"its", people!

Get rid of MDLWP_USED{FPU,VEC}

branches: 1.65.2; 1.65.4;
Add support for PPC FP emulation to BookE.
Pass a ksiginfo_t to fpu_emulation so it can give more detailed
info on signals.

Remove COMPAT_SA / KERN_SA. Welcome to 6.99.3!
Approved by core@.

Remove white-spaces.

branches: 1.62.2; 1.62.6;
Switch to use new common cpu_ast routine.

Use <sys/foo.h> instead of <machine/foo.h> if such a file exists.
Don't assume <sys/cpu.h> includes <powerpc/subarch/cpu*.h>. Include it
explicitly.

Make startlwp and upcallret common instead of having 3 mostly identical copies.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.58.4;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.57.2;
Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits. Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

Remove lwp_uc_pool, replace it with kmem(9), plus add some consistency.
As discussed, a while ago, with ad@.

fix copy{in,out}{,str}() to return the error returned by uvm_fault().
fixes PR 41813.

branches: 1.54.2;
Adapt to spr.h breakup.

branches: 1.53.2;
Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.

Remove uarea swap-out functionality:

- Addresses the issue described in PR/38828.
- Some simplification in threading and sleepq subsystems.
- Eliminates pmap_collect() and, as a side note, allows pmap optimisations.
- Eliminates XS_CTL_DATA_ONSTACK in scsipi code.
- Avoids few scans on LWP list and thus potentially long holds of proc_lock.
- Cuts ~1.5k lines of code. Reduces amd64 kernel size by ~4k.
- Removes __SWAP_BROKEN cases.

Tested on x86, mips, acorn32 (thanks <mpumford>) and partly tested on
acorn26 (thanks to <bjh21>).

Discussed on <tech-kern>, reviewed by <ad>.

Change about 4500 of the K&R function definitions to ANSI ones.
There are still about 1600 left, but they have ',' or /* ... */
in the actual variable definitions - which my awk script doesn't handle.
There are also many that need () -> (void).
(The script does handle misordered arguments.)

Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.

branches: 1.49.2; 1.49.8; 1.49.16;
Merge wrstuden-revivesa into HEAD.

branches: 1.48.6; 1.48.10; 1.48.12; 1.48.16;
Merge vmlocking2 to head.

branches: 1.47.2; 1.47.6;
Use lswi/syswi instead of lwz/stw when doing loads/stores since we don't
know the alignment of data being copied. 403 cores have alignment
restrictions on lwz/stw that 405 cores don't have. lswi/syswi benchmark
at the same speed as lwz/stw on a 405 Walnut.

Fixes problems reported by Juergen Hannken-Illjes on the Explora.

Optimize copyin/copyout to transfer as many words as possible before doing
residual bytes. This improves small transfers. As a result, we can avoid
doing bigcopyin/bigcopyout until len>1024 instead of len>256.

Reviewed by: simonb.

(everybody run, Herb's in the kernel again).

branches: 1.45.2;
Don't set l_usrpri / spc_curpriority here. mi_userret() does it.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.43.8; 1.43.10; 1.43.12; 1.43.14;
Merge some of the less invasive changes from the vmlocking branch:

- kthread, callout, devsw API changes
- select()/poll() improvements
- miscellaneous MT safety improvements

Fix for yamt-idlelwp merge.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.40.2; 1.40.4; 1.40.10;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.39.2;
Make these compile again.

Merge newlock2 to head.

add support for O_DIRECT (I/O directly to application memory,
bypassing any kernel caching for file data).

branches: 1.36.4; 1.36.6;
Use the LWP cached credentials where sane.

- Hold a reference to the process credentials in each struct lwp.
- Update the reference on syscall and user trap if p_cred has changed.
- Collect accounting flags in the LWP, and collate on LWP exit.

include kauth.h for kauth_cred_geteuid.

integrate kauth.

branches: 1.32.2;
adapt to uvm_fault() interface cleanup: kill the useless 3rd argument

branches: 1.31.2;
Syscall debug tracing is handled by trace_enter() / trace_exit(). Change
trace_is_enabled() to return TRUE if SYSCALL_DEBUG is defined, and g/c
all of the SYSCALL_DEBUG handling from individual system call dispatch
routines.

Clean up fallout proc_is_traced_p() change:
- proc_is_traced_p() -> trace_is_enabled(), to match trace_enter() and
trace_exit().
- trace_is_enabled() becomes a real function.
- Remove unnecessary include files from various files that used to care
about KTRACE and SYSTRACE, but do no more.

branches: 1.29.4; 1.29.6; 1.29.8;
bare asm -> __asm

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.26.2;
Appease the -Wshadow and -Wcast-qual gods.

KNF: put "if (...)" and following statement on separate lines.

branches: 1.24.2;
White space nit.

branches: 1.23.4;
Apply suggested changes from PR port-powerpc/24830 arch/powerpc/ibm4xx:
Bad register constraints in copyin(), copyout(), copyinstr(), copyoutstr(),
and delay().

add kernel part of concurrency support for SA on MP systems
- move per VP data into struct sadata_vp referenced from l->l_savp
* VP id
* lock on VP data
* LWP on VP
* recently blocked LWP on VP
* queue of LWPs woken which ran on this VP before sleep
* faultaddr
* LWP cache for upcalls
* upcall queue
- add current concurrency and requested concurrency variables
- make process exit run LWP on all VPs
- make signal delivery consider all VPs
- make timer events consider all VPs
- add sa_newsavp to allocate new sadata_vp structure
- add sa_increaseconcurrency to prepare new VP
- make sys_sa_setconcurrency request new VP or wakeup idle VP
- make sa_yield lower current concurrency
- set sa_cpu = VP id in upcalls
- maintain cached LWPs per VP

deliver SIGSEGV/SEGV_ACCERR if code execution on stack is attempted,
tested by Juergen Hannken-Illjes
(there are more uninitialized ksi.ksi_code arguments)

Reduce code duplication by adding mi_userret() in sys/userret.h
containing signal posting, kernel-exit handling and sa_upcall processing.

XXX the pc532, sparc, sparc64 and vax ports should have their
XXX userret() code rearranged to use this.

* Shuffle some data structures so, and add a flags word to ksiginfo_t.
Right now the only flag is used to indicate if a ksiginfo_t is a
result of a trap. Add a predicate macro to test for this flag.
* Add initialization macros for ksiginfo_t's.
* Add accssor macro for ksi_trap. Expands to 0 if the ksiginfo_t was
not the result of a trap. This matches the sigcontext trapcode semantics.
* In kpsendsig(), use KSI_TRAP_P() to select the lwp that gets the signal.
Inspired by Matthias Drochner's fix to kpsendsig(), but correctly handles
the case of non-trap-generated signals that have a > 0 si_code.

This patch fixes a signal delivery problem with threaded programs noted by
Matthias Drochner on tech-kern.

As discussed on tech-kern. Reviewed and OK's by Christos.

Define ksi.

Add siginfo support for PowerPC.

add MD part of SA/pthread pagefault handling on powerpc

add support for non-executable mappings (where the hardware allows this)
and make the stack and heap non-executable by default. the changes
fall into two basic catagories:

- pmap and trap-handler changes. these are all MD:
= alpha: we already track per-page execute permission with the (software)
PG_EXEC bit, so just have the trap handler pay attention to it.
= i386: use a new GDT segment for %cs for processes that have no
executable mappings above a certain threshold (currently the
bottom of the stack). track per-page execute permission with
the last unused PTE bit.
= powerpc/ibm4xx: just use the hardware exec bit.
= powerpc/oea: we already track per-page exec bits, but the hardware only
implements non-exec mappings at the segment level. so track the
number of executable mappings in each segment and turn on the no-exec
segment bit iff the count is 0. adjust the trap handler to deal.
= sparc (sun4m): fix our use of the hardware protection bits.
fix the trap handler to recognize text faults.
= sparc64: split the existing unified TSB into data and instruction TSBs,
and only load TTEs into the appropriate TSB(s) for the permissions.
fix the trap handler to check for execute permission.
= not yet implemented: amd64, hppa, sh5

- changes in all the emulations that put a signal trampoline on the stack.
instead, we now put the trampoline into a uvm_aobj and map that into
the process separately.

originally from openbsd, adapted for netbsd by me.

__KERNEL_RCSID()

branches: 1.13.2;
Sprinkle some KNF.

Fix some printf formats.

Perform a rototill of the powerpc code. Mandate use of SPRG0 to store
a pointer to current cpu's cpu_info structure. Use cpu_info for
intstk,intr_depth,still_stk,idle_pcb,curpcb,curlwp,etal even on
non-MULTIPROCESSOR machines. Add common macros GET_CPUINFO and
INIT_CPUINFO to get and initialize the cpu_info struct on startup. Make
ibm4xx use the standard <powerpc/frame.h>. Use IFRAME_xx in ibm4xx
trap_subr.S instead of explicit magic offsets. Move INTSTK and SPILLSTK
to std.<platform>. Change faultbuf to a struct instead of an array.

On MPC6XX cpus, stop using the vector page for temporary space and use
reserved space in cpu_info.

Merge the nathanw_sa branch.

branches: 1.9.2;
Statements after labels.

use a completely separate trap handler for syscall traps.
this reduces syscall overhead by 10% to 20% depending on cpu type.

Clean up some white space niggles.

Peform a rototill over the powerpc-based ports.

Move the trap/vector initialization for MPC6xx ports to mpc6xx_machdep.c
Also move softnet, install_extintr, mapiodev, kvtop. Add common BAT
initialization code.

Add user Altivec support.

Fix calls to OF_call_method in macppc/macppc/machdep.c.

Use ci_fpuproc in cpu_info instead of separate fpuproc.

Add separate syscall.c and defined __HAVE_SYSCALL_INTERN.

apply the fix from the powerpc port. this is almost a copy of powerpc/trap.c
and needs to be refactored.

MD systrace gluons.

branches: 1.3.8;
allow writing to write-only mappings. fixes PR 3493.

branches: 1.2.6;
bcopy -> memcpy, bzero -> memset, bcmp -> memcmp.
Reviewed by Matt Thomas, ok'd by Tsubai Masanari.

branches: 1.1.2;
Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.

Make ibm4xx kernels compiled by clang.

As clang cannot correctly assemble m[ft]pid:
- for asm sources, use m[ft]spr from/to SPR_PID
- for C sources, use M[FT]PID macros (see include/ibm4xx/spr.h)
This is ugly...

No binary changes for GCC-compiled kernels.

Include required opt_*.h for sure.

Implement workaround for IBM405 Errata 77 (aka CPU_210), where
interrupted stwcx. may errantly write data to memory:

https://elinux.org/images/1/1d/Ppc405gp-errata.pdf

This is because stwcx. is split into two pieces in the pipeline.

We need to
(1) insert dcbt before every stwcx. instruction, as well as
(2) insert sync before every rfi/rfci instruction.

It is unclear which processors are affected, but according to Linux,
all 405-based cores up until 405GPR and 405EP are affected:

https://github.com/torvalds/linux/blob/master/arch/powerpc/platforms/40x/Kconfig#L140

For kernel, this workaround can be restricted to affected processors.
However, for kernel modules and userland, we have to enable it for all
32bit powerpc archs in order to share common binaries as before.

Proposed on port-powerpc:

http://mail-index.netbsd.org/port-powerpc/2020/02/21/msg003583.html

branches: 1.27.4;
Retire ipkdb entirely. The option was removed from the config files
yesterday.

ok kamil christos

branches: 1.26.14; 1.26.16;
PR port-powerpc/51367: kernel panic for powerpc/ibm4xx with "option DDB"

Stop using ddbstk/ipkdbstk to make nested traps possible, which avoids
kernel panics reported in the PR.

Suggested and approved by matt.

No need to have same trap handlers in trap_subr.S.
No functional changes.

branches: 1.24.14; 1.24.18;
Fix KASSERT(l == curlwp)ed in mi_switch(). Don't use INTSTK of cpu_info in
INTR_PROLOG when user-mode. Interrupted user context switches to newlwp, if
sched tick. This context must save to USPACE.
When use our INTSTK?

Set SRR1 to r31 in intr_exit. Not cpuinfo.

branches: 1.22.6;
Check PSL_PR instead of CI_IDEPTH in INTR_PROLOG.

Like intrleave_to_user:, intrleave_to_kernel: should also restore PID.
Moreover, disable transration.

Store r30 and r31 beforehand to restore.

Indent.
Remove white-spaces and unnecessary semi-collons.

branches: 1.18.2; 1.18.6;
Must need srr0 and srr1 in FRAME_SETUP and trapexit.
parentheses is good.
Remove no-need 'addi FRAME_TF'.

Fix broken stack. The r4 points cpu_info in ddb_trap. (not test)

- FRAME_SAVE_CALLEE() starts at r14 (not r13, which is curlwp) (from matt@)
- INTR_SAVE() must also save r13 (from matt@).
- fitint must pass clock frame, not trap frame
- fix comment in pitint and fitint to indicate passing clock frame, not intr frame

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.14.2;
Fix broken stack. The r1 is stack pointer. Not cpu_info pointer.

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.12.2;
Use regnames (%rX %crX), use m[ft]sprg[0-9]. No binary difference.

branches: 1.11.42; 1.11.46;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.10.30; 1.10.38; 1.10.48; 1.10.50; 1.10.52; 1.10.54;
merge ktrace-lwp.

branches: 1.9.16;
catch up with changes elsewhere.

Enhance db_trace to understand syscalls and print the syscall number
that the user requested. For example:

0xd5c56f40: SC trap #240 by 0x15668c60: srr1=0xd032
r1=0xffffe470 cr=0x44000045 xer=0 ctr=0xeff27ab8

branches: 1.7.2;
Perform a rototill of the powerpc code. Mandate use of SPRG0 to store
a pointer to current cpu's cpu_info structure. Use cpu_info for
intstk,intr_depth,still_stk,idle_pcb,curpcb,curlwp,etal even on
non-MULTIPROCESSOR machines. Add common macros GET_CPUINFO and
INIT_CPUINFO to get and initialize the cpu_info struct on startup. Make
ibm4xx use the standard <powerpc/frame.h>. Use IFRAME_xx in ibm4xx
trap_subr.S instead of explicit magic offsets. Move INTSTK and SPILLSTK
to std.<platform>. Change faultbuf to a struct instead of an array.

On MPC6XX cpus, stop using the vector page for temporary space and use
reserved space in cpu_info.

Merge the nathanw_sa branch.

use a completely separate trap handler for syscall traps.
this reduces syscall overhead by 10% to 20% depending on cpu type.

Clean up some white space niggles.

branches: 1.3.4;
Add a vector for machine check traps.

branches: 1.2.2; 1.2.8;
Globalise "trapexit" for new ddb tracing changes.

Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.

Reorganise the IBM 4xx bus layout, using terminology from the IBM
documentation:
- Remove "mainbus" altogether.
- The new root is "plb" - the Processor Local Bus.
- Attached to this is the "opb" - the On-chip Peripheral Bus, to which
all the on-chip devices are attached (except the cpu and pci host
bridge).
- Port-specific code can pass an array of 'struct plb_dev' to
config_rootfound() to attach extra devices to the plb. The walnut
port attaches a "pbus" (Peripheral Bus) in here for the RTC and
pc keyboard controller to attach to.
There is still much 405GP specific code; the next round of changes will
generalise this to enable easier support for other 4xx CPUs.

branches: 1.4.4;
Adapt to the new, separate mainbus.

Include libkern.h for strcmp() prototype.

branches: 1.2.2;
Don't return at the end of a void function.

branches: 1.1.2; 1.1.6;
Move on-chip 405GP devices to powerpc/ibm4xx/dev.