Create a new header lwp_private.h to contain _lwp_getprivate_fast,
_lwp_gettcb_fast, _lwp_settcb and remove them from mcontext.h, so that:
1. we don't need special hacks to hide them
2. we can include <lwp.h> where needed to get the necessary prototypes
without redefining them locally.

Undo previous lwp.h change.

Split __lwp_getprivate_fast and __lwp_*tcb from mcontext.h into a separate
lwp.h file.

branches: 1.42.36;
Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.

branches: 1.41.16; 1.41.18;
Add mips fenv.h (From FreeBSD)

branches: 1.40.4;
Rename sljitarch.h to sljit_machdep.h.

branches: 1.39.2;
Enable sljit and bpfjit on powerpc.

branches: 1.38.2; 1.38.12; 1.38.16;
Retire varargs.h support. Move machine/stdarg.h logic into MI
sys/stdarg.h and expect compiler to provide proper builtins, defaulting
to the GCC interface. lint still has a special fallback.
Reduce abuse of _BSD_VA_LIST_ by defining __va_list by default and
derive va_list as required by standards.

Readd powerpc/include/vmparam.h to the set lists
Export it to powerpc/include.h
Protect pmap.h and vmparam.h from getting an #error when included
from userland.
Export safe definitions of VM_MAXUSER_ADDRESS, VM_MIN_ADDRESS,
VM_MAX_ADDRESS when _RUMPKERNEL is defined.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.35.2; 1.35.4; 1.35.8;
Add missing <powerpc/FOO/spr.h> to a few files missed on the first pass.
Don't export <machine/spr.h> to userland, only <powerpc/spr.h>

branches: 1.34.48; 1.34.68;
Merge newlock2 to head.

branches: 1.33.20;
merge ktrace-lwp.

branches: 1.32.6;
Install spr.h

branches: 1.31.4; 1.31.6;
Factor out W{CHAR,INT}_{MAX,MIN} into their own header file.

Reorganize the way powerpc port install machine specific headers.
Use <powerpc/oea/bat.h> exclusively and remove <machine/bat.h> and
<powerpc/bat.h>. Remove unneeded <machine/cpufunc.h>. To insure
1:1 correspondence of <powerpc/FOO.h> to <machine/FOO.h> include
"../../powerpc/include/Makefile" in "arch/FOO/include/Makefile".
Incororpate <byte_swap.h> into <bswap.h> and then byte_swap.h

branches: 1.29.2;
Merge the nathanw_sa branch.

Remove KDIR=, since SYS_INCLUDE=symlinks and KDIR are not supported any more.

back previous off; don't install macho_machdep.h

Add COMPAT_MACH and EXEC_MACHO support on the PowerPC

Implement pmc(9) -- An interface to hardware performance monitoring
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.

install atomic.h.

branches: 1.23.2; 1.23.8; 1.23.16;
Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.

Include powerpc/mpc6xx/{bat.h,pte.h} if PPC_MPC6XX is defined.

Make the new pmap optional. Use the old (stable!) pmap by default.

Introduce a new & faster pmap for the MPC6xx (60x, 7xx, 7xxx) PPC CPUs.
Move MPC6xx dependent header files to powerpc/include/mpc6xx/

Inline bswap{16,32} when the argument is constant.

PPC machine type tags haven't been used for a while.

Add definitions of C99 integer format conversion macros.
XXX Fastest minimum-width integer types haven't been decided upon yet.

Add definitions of C99 specified-width integer type limits.
XXX Fastest minimum-width integer types haven't been decided upon yet.

Add definitions of C99 integer constant macros.
Tidy Makefiles up a little.

Add definitions of C99 minimum-width and greatest-width integer types.
XXX Fastest minimum-width integer types haven't been decided upon yet.

branches: 1.13.2;
Add pio.h to INCS.

powerpc HID registers definitions (only HID0 for now).

Add <machine/int_types.h>, which provides namespace-pure definitions
of exact-width integer types.

Require that each each MACHINE/MACHINE_ARCH supply a lock.h. This file
contains the values __SIMPLELOCK_LOCKED and __SIMPLELOCK_UNLOCKED, which
replace the old SIMPLELOCK_LOCKED and SIMPLELOCK_UNLOCKED. These files
are also required to supply inline functions __cpu_simple_lock(),
__cpu_simple_lock_try(), and __cpu_simple_unlock() if locking is to be
supported on that platform (i.e. if MULTIPROCESSOR is defined in the
_KERNEL case). Change these functions to take an int * (&alp->lock_data)
rather than the struct simplelock * itself.

These changes make it possible for userland to use the locking primitives
by including <machine/lock.h>.

Install "machineendian_machdep.h".

Rewrite stdarg/varargs.

Remove vmparam.h.

C99: Define a NAN macro in <math.h> which evaulates to a constant expression of
a single-precision quiet NaN; only to be defined on platforms that do support
this value.

Hardware Implementation Dependent registers for the PowerPC 601.

branches: 1.4.2; 1.4.8;
Add cpu.h.

branches: 1.3.4;
Add missing backslash.

Move the bswap functions from libutil to libc (this bups the
minor of libc and the major of libutil). For little-endian architectures
merge the bnswap() assembly versions with nto* and hton* using symbols
aliasing. Use symbol renaming for the bswap function in this case to avoid
namespace pollution.
Declare bswap* in machine/bswap.h, not machine/endian.h. For little-endian
machines, common code for inline macros go in machine/byte_swap.h
Sync libkern with libc.
Adjust #include in kernel sources for machine/bswap.h.

Rework the way kernel include files are installed. In the new method,
as with user-land programs, include files are installed by each directory
in the tree that has includes to install. (This allows more flexibility
as to what gets installed, makes 'partial installs' easier, and gives us
more options as to which machines' includes get installed at any given
time.) The old SYS_INCLUDES={symlinks,copies} behaviours are _both_
still supported, though at least one bug in the 'symlinks' case is
fixed by this change. Include files can't be build before installation,
so directories that have includes as targets (e.g. dev/pci) have to move
those targets into a different Makefile.

Put GCC/GAS specific options under ACTIVE_CC == "gcc".

branches: 1.2.12;
avoid linker warnings with the new binutils by not forcing rump modules
to be soft-float.

branches: 1.1.2;
Build LKMs with -msoft-float.

fix various typos in comments.

s/static inline/static __inline/g for consistency.

branches: 1.17.12;
allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.

branches: 1.16.6; 1.16.10; 1.16.14;
-extend the pcu(9) API by a function which saves all context on the
current CPU, and use it if a CPU is taken offline
-add a bool argument to pcu_discard which tells whether the internal
"LWP has used the coprocessor" flag should be set or reset. The flag
is reported by pcu_used_p(). If set, future accesses should use the
state stored in the PCB. If reset, it should be reset to default.
The former case is useful for setmcontext().
With that, it should not be necessary anymore to manage the "FPU used"
state by an additional MD variable.

approved by matt

branches: 1.15.4; 1.15.14; 1.15.18;
Fix cut/paste error.

Move powerpc to use pcu to manage FPU/AltiVec/SPE.

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.12.22; 1.12.26; 1.12.28;
Remove clause 3 and 4 from TNF licenses

branches: 1.11.16; 1.11.18; 1.11.20;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.10.30; 1.10.38; 1.10.48; 1.10.50; 1.10.52; 1.10.54;
merge ktrace-lwp.

branches: 1.9.12;
Add a SAVE/DISCARD flag to save_{fpu,vec}_lwp. Use it appropriately.
Nuke struct fpu and use struct fpreg instead (except for the names, they
were identical). On MP machines, this will avoid an unneeded IPI to save
the register contents that are about to discarded.

branches: 1.8.2;
Make sure to include opt_foo.h if a defflag option FOO is used.

Make AltiVec registers available via ptrace/procfs. Simplify AltiVec
processing. Add a "common" procfs_machdep.c for PowerPC platforms.
Even though it is supposed to be port specific, most (if not all)
PowerPC ports can just use the common one.

Merge the nathanw_sa branch.

Change _MACHINE_foo_H_ to _POWERPC_foo_H_

restructure the FPU and AltiVEC code so that it works for MP.

Make sure that pmap_zero_page and pmap_copy_page don't make calls or
reference while relocation is disabled since the stack will be inaccessible.
Add support for using AltiVec in pmap_zero_page and pmap_copy_page on
AltiVec capable processors.

Peform a rototill over the powerpc-based ports.

Move the trap/vector initialization for MPC6xx ports to mpc6xx_machdep.c
Also move softnet, install_extintr, mapiodev, kvtop. Add common BAT
initialization code.

Add user Altivec support.

Fix calls to OF_call_method in macppc/macppc/machdep.c.

Use ci_fpuproc in cpu_info instead of separate fpuproc.

Add separate syscall.c and defined __HAVE_SYSCALL_INTERN.

branches: 1.1.2; 1.1.6; 1.1.10; 1.1.18;
Add AltiVec VSCR definitions.

Switch all users (except ia64) of custom machine/ansi.h to common_ansi.h

Deduplicate the code among ports and poll definitions of types
directly from a compiler.

This fixes miscompilation of certain programs that instruct compilers
to generate code for different types. This bug has been detected with
-fshort-wchar in EFI firmware.

Proposed and discussed on a mailing list (twice).

Itanium uses custom !ELF fallback switch, temporarily leave it as it is.

branches: 1.30.18;
Make _BSD_CLOCK_T_ unsigned int so it's the same for IPL32 and LP64
environments. We don't really have a powerpc64 native userland
and the mips64 native userland is IPL32 so this shouldn't affect anything.

branches: 1.29.12; 1.29.28; 1.29.30;
Retire varargs.h support. Move machine/stdarg.h logic into MI
sys/stdarg.h and expect compiler to provide proper builtins, defaulting
to the GCC interface. lint still has a special fallback.
Reduce abuse of _BSD_VA_LIST_ by defining __va_list by default and
derive va_list as required by standards.

1. {wctype,wctrans,mbstate}_t: switch MD to MI like other
libc implementation (such as *BSD and glibc2).

2. don't typedef void * wc{type,trans}_t, suggested by soda@-san.
it may pass through compiler type check, it's harmful.
so i introduce dummy struct __tag_wc{type,trans}_t(iconv_t already does).

no ABI change was made.

branches: 1.27.4; 1.27.6;
merge christos-time_t

branches: 1.26.4;
Add stdargs support for pcc.

branches: 1.25.16; 1.25.18; 1.25.22; 1.25.24; 1.25.26;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

clean up some definitions around rune_t which are not needed anymore

branches: 1.23.8; 1.23.16; 1.23.22; 1.23.26; 1.23.28;
fix gcc -Werror -Wmissing-braces problem
mbstate_t(this is opaque object)'s initializer should be ``{ 0 }'',
so changed 1st field of union from character array to integer.

branches: 1.22.20; 1.22.22;
merge ktrace-lwp.

branches: 1.21.16;
Define va_list as __builtin_va_list for GCC 3.x. Change stdarg macros
appropriately. (this is committed from a system run a kernel and userland
built with these changes).

Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

branches: 1.19.2;
add some ISO C 1995 I18N functions and types:
btowc, wctrans, towctrans, wcscoll, wcsxfrm, wctype_t and wctrans_t.

Fix LP64 botch.

Revert my previous GCC 3.3-related changes; GCC 3.3 has been fixed
to handle our stdarg/varargs ABI for PowerPC.

Make these work with GCC 3.x.

Prepare for PPC64. Use register_t for mtmsr/mfmsr since the msr on PPC64
is 64bits wide. Define proper types for PPC64 if _LP64 is defined.

Re-correct previous. It's intentional.

Correct __va_list typedef for GCC 3.* to match the GCC 3.* definition.

Add gcc 3.x version.

branches: 1.11.4; 1.11.8; 1.11.16; 1.11.18;
replace 'long long' with int64_t to compile stand alone program with
compiler other than GCC.

make mbstate_t bigger (32 -> 128 bytes).
XXX if you have libc after citrus locale import, please recompile libc,
and your applications that use mbstate_t (rather rare). really sorry
for the mess.

populate _BSD_MBSTATE_T_. add warning regarding to rune_t.

G/c _BSD_INTPTR_T_ and _BSD_UINTPTR_T_.

branches: 1.7.2;
Rewrite stdarg/varargs.

branches: 1.6.12;
Add missing wint_t (currently unused).

Provide definitions for intptr_t and uintptr_t, signed resp. unsigned integral
types large enough to hold any pointer.

Add _BSD_SUSECONDS_T_ and _BSD_USECONDS_T_; do some space vs. tab formatting
cleanup

Update to varargs/stdarg implementation; conform to the SVR4 calling
convention.

Define _BSD_CLOCKID_T_ and _BSD_TIMER_T_

PowerPC port

Style and cosmetic changes. No binary changes intended.

Rename __LDPGSZ to AOUT_LDPGSZ, to accurately reflect what it is.

Changed the ifndef guard of this header file from _MACH_EXEC_H_ to
_POWERPC_AOUT_EXEC_H_. The former was conflicting with
<compat/mach/mach_exec.h>.

branches: 1.3.8;
De-lint. Reviewed by christos.

branches: 1.2.10;
Change r_type bit field size 5 to 6 and reduce unused bit(2 to 1).
Suggested by Mirian Crzig Lennox.

PowerPC port

PR 58960: fix misunderstanding in semantic and provide both the original
id string as well as _NETBSD_REVISIONID.
Do not rely on string concatenation in the inline assembler, use .ascii
and .asciz for individual string parts instead.

PR 58960: powerpc/asm.h: Respect NETBSD_REVISIONID.

branches: 1.54.2;
s/psuedo/pseudo/ in comments.

s/udpate/update/

Consistently use _LP64 instead of __LP64__, although both are defined for
powerpc64.

No binary changes intended.

It's __RCSID for an extra level of indirection on PPC

Mark the .ident section as mergable string section to avoid redundant
entries.

branches: 1.49.4;
Implement workaround for IBM405 Errata 77 (aka CPU_210), where
interrupted stwcx. may errantly write data to memory:

https://elinux.org/images/1/1d/Ppc405gp-errata.pdf

This is because stwcx. is split into two pieces in the pipeline.

We need to
(1) insert dcbt before every stwcx. instruction, as well as
(2) insert sync before every rfi/rfci instruction.

It is unclear which processors are affected, but according to Linux,
all 405-based cores up until 405GPR and 405EP are affected:

https://github.com/torvalds/linux/blob/master/arch/powerpc/platforms/40x/Kconfig#L140

For kernel, this workaround can be restricted to affected processors.
However, for kernel modules and userland, we have to enable it for all
32bit powerpc archs in order to share common binaries as before.

Proposed on port-powerpc:

http://mail-index.netbsd.org/port-powerpc/2020/02/21/msg003583.html

branches: 1.48.18; 1.48.22;
Name the offsets to the remaining fields in the ppc64
stack frame header. Add a stack frame alignment macro
to avoid hard-coding that.

branches: 1.47.2;
Fix cmpptr/cmpreq/etc to use right mnemonics

branches: 1.46.4;
Add _XENTRY which doesn't set the section to .text

Add cmp{ptr,long,reg}{,l}{,i}

Use ## for concatenation

Add P2SZREG to be usign with .p2align

Pass PICFLAGS down to cc-as-as and use __PIC__ to decide if it is small
vs big PIC mode. Retire -DPIC and -DBIGPIC.

branches: 1.41.2;
Support 16bits over stack size.

provide _ENTRY(x) because some code needs it.

branches: 1.39.2; 1.39.12;
- Indent ifdefs, comment endif and else cpp tags
- Add missing END macro for LP64
- Make whitespace consistent

In INIT_CPUINFO, make L_CPU to set the cpu_info (just to be safe).

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.36.2;
binutils is automagically doing securecrt so make sure plt calls are emitted
with the secureplt magic as well.

Some ports use %r0 as tmp2 to INIT_CPUINFO which has adverse effects so
never use tmp2 to hold an address.

branches: 1.34.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

Kill _NOREGNAMES. Everything should be using %rX now. If it doesn't it
soon will.

branches: 1.32.2;
Add PIC_GOTSETUP and PIC_TOCSETUP which replace the old methods to get the
GOT (via a bl) to the new REL16 based relocs. This is another step to
supporting secure plt.

Add END(sym)
Add __RCSID (to match cdefs.h)

Consistently use .gnu.warning with .pushsectio and .popsection on all
architectures instead of obsolete STABS frames for linker warnings.

branches: 1.29.2;
Put ASM RCSIDs into .ident

branches: 1.28.2;
Rename L_ADDR to L_PCB and amend some comments accordingly.

Kill proc0paddr. Use lwp0.l_addr instead.

branches: 1.26.4; 1.26.26;
Add clrr{ptr,long,reg}i, l{ptr,long,reg}arx, st{ptr,long,reg}cx macros

branches: 1.25.12; 1.25.16;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.24.10;
merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.23.10; 1.23.14; 1.23.16; 1.23.22;
wrap as(1)-only elements in #ifdef _LOCORE

Add stmd and lmd macros.

more refinements for ppc64 PIC/PLT/TOC issues

Add ppc64 ENTRY() macro that defines the descriptor and the dot symbol.

branches: 1.19.2; 1.19.6; 1.19.14;
Add a STRONG_ALIAS macro

branches: 1.18.2;
merge ktrace-lwp.

branches: 1.17.8;
Use lis@h/ori@l instead of lis@ha/addi@l since we may use r0 and addi
is one of those funny instructions that treats r0 == 0 when used as the
first arg.

Fixes problems on ibm4xx. Ok'd by matt@.

Split the hw-dependent powermanglement into its own function and make
Idle call that. Add a ci_idlespin function pointer to cpu_info.
Update INIT_CPUINFO to initialize it to a naked 'blr' instruction.
In oea/cpu_subr.c, add cpu_idlespin and make ci_idlespin point to it.

branches: 1.15.8;
Nuke ci_spillstk/CI_SPILLSTK. No longer needed.

Nuke stmreg/ldmreg. PPC64 doesn't have a lmd/stmd so make sure lmw/stmw
don't invoke valid instructions on PPC64.

Define SZREG {4,8} appropriately. Add pseudo-instructions (via #define)
to load/store int, long, pointer, register, multiple registers. This is so
assembly files can be support IPL32 and LP64 PowerPC implementations.

branches: 1.12.2;
Perform a rototill of the powerpc code. Mandate use of SPRG0 to store
a pointer to current cpu's cpu_info structure. Use cpu_info for
intstk,intr_depth,still_stk,idle_pcb,curpcb,curlwp,etal even on
non-MULTIPROCESSOR machines. Add common macros GET_CPUINFO and
INIT_CPUINFO to get and initialize the cpu_info struct on startup. Make
ibm4xx use the standard <powerpc/frame.h>. Use IFRAME_xx in ibm4xx
trap_subr.S instead of explicit magic offsets. Move INTSTK and SPILLSTK
to std.<platform>. Change faultbuf to a struct instead of an array.

On MPC6XX cpus, stop using the vector page for temporary space and use
reserved space in cpu_info.

Add a temporary bridge to use %foo regnames in kernel / standalone code.

Don't define register references if not KERNEL or STANDALONE.

Add ENTRY_NOPROFILE().

branches: 1.8.2; 1.8.8; 1.8.16; 1.8.18;
Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.

branches: 1.7.2;
Add a WEAK_ALIAS() macro.

branches: 1.6.8; 1.6.18;
First-cut of profiling support.
XXX userland only, for now.

Implement WARN_REFERENCES().

Add PIC definitions.

Update for Elf.

PROF -> GPROF

PowerPC port

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.4.100; 1.4.106; 1.4.110;
inline -> __inline

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

branches: 1.2.22;
No newlines in string constants.

branches: 1.1.2; 1.1.4; 1.1.6;
add some atomic operations.

Rewrite a big chunk of the pmap and locore code for powerpc to better
deal with the 64bit bridge mode. pmap changes by Matt Thomas, rest by myself.

Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel. This allows the pmap for bridge64 to
co-exist with the 32bit pmap.

Yank __HAVE_PMAP_PHYSSEG from all the oea code.

Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features. This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.

Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in. Some of it seemed incorrect, and my 7044 booted just fine
without it. It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.

In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].

With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu. However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE. Work remains to be done there to fix that.

branches: 1.5.18; 1.5.80; 1.5.86;
Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

branches: 1.4.8;
Include powerpc/mpc6xx/{bat.h,pte.h} if PPC_MPC6XX is defined.

Introduce a new & faster pmap for the MPC6xx (60x, 7xx, 7xxx) PPC CPUs.
Move MPC6xx dependent header files to powerpc/include/mpc6xx/

branches: 1.2.6;
- Comment the BAT bits.
- Add defintions for the PowerPC 601 BATs.
- Change the BATU()/BATL() macros to be a bit more flexible; allow size,
permissions, etc. to be specified.

branches: 1.1.28; 1.1.34;
PowerPC port

powerpc: Use GCC builtins for bswap.

This doubled disk encryption performance on an (emulated) G4. Further
improvements are possible if the GCC 2 version of the endian functions
is used, so we might want to consider doing that on more NetBSD ports.

PR port-sparc64/59789 bswap is slow

branches: 1.6.202;
This file only needs to #include sys/bswap.h

branches: 1.5.2;
merge ktrace-lwp.

branches: 1.4.16;
Reorganize the way powerpc port install machine specific headers.
Use <powerpc/oea/bat.h> exclusively and remove <machine/bat.h> and
<powerpc/bat.h>. Remove unneeded <machine/cpufunc.h>. To insure
1:1 correspondence of <powerpc/FOO.h> to <machine/FOO.h> include
"../../powerpc/include/Makefile" in "arch/FOO/include/Makefile".
Incororpate <byte_swap.h> into <bswap.h> and then byte_swap.h

branches: 1.3.8; 1.3.24;
Inline bswap{16,32} when the argument is constant.

branches: 1.2.14;
Include <sys/bswap.h> for function prototypes. i386, pc532 and vax
still include <machine/byte_swap.h> and define macros for some of
the bswap*() functions.

Move the bswap functions from libutil to libc (this bups the
minor of libc and the major of libutil). For little-endian architectures
merge the bnswap() assembly versions with nto* and hton* using symbols
aliasing. Use symbol renaming for the bswap function in this case to avoid
namespace pollution.
Declare bswap* in machine/bswap.h, not machine/endian.h. For little-endian
machines, common code for inline macros go in machine/byte_swap.h
Sync libkern with libc.
Adjust #include in kernel sources for machine/bswap.h.

Enable new-style <sys/bus.h> on several PowerPC ports supporting PCI
buses. Make non-inline implementations of bus_space(9) and bus_dma(9)
routines and move them to appropriate .c files.

This may leave amigappc in a bad state, sorry. Fortunately, it will be
easy to repair by imitating the bus.h -> bus_{defs,funcs}.h split in
some other PowerPC port.

For PPC_BOOKE, make BUS_DMA_COHERENT equal to BUS_DMA_NOCACHE. Now USB
works again. (which means USB uses of bus_dmamap_sync is broken).

branches: 1.20.20; 1.20.22; 1.20.26; 1.20.32;
Remove clause 3 and 4 from TNF licenses

branches: 1.19.6; 1.19.8; 1.19.10;
Use uintN_t in comments (since that's what are really using) instead of
u_intN_t

branches: 1.18.2;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.17.2; 1.17.10; 1.17.18; 1.17.20; 1.17.22; 1.17.24;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

add a pair of new bus_dma(9) functions:
int _bus_dmatag_subregion(bus_dma_tag_t tag,
bus_addr_t min_addr,
bus_addr_t max_addr,
bus_dma_tag_t *newtag,
int flags)
void _bus_dmatag_destroy(bus_dma_tag_t tag)

that allow a (normally broken/limited) device to restrict the bus address
range it can talk to. this is used by bce(4) to limit DMA addresses to
1GB range, the maximum the chip can address.

all this is from Yorick Hardy <yhardy@uj.ac.za> with input from several
people on tech-kern.

XXX: bus_dma(9) needs an update still.

branches: 1.15.26;
merge ktrace-lwp.

branches: 1.14.4;
Add a dm_maxsegsz public member to bus_dmamap_t. This allows a user of the API
to select the maximum segment size for each bus_dmamap_load (up to the maxsegsz
supplied to bus_dmamap_create). dm_maxsegsz is reset to the value supplied to
bus_dmamap_create when the dmamap is unloaded.

branches: 1.13.8; 1.13.10;
Need to set BUS_DMA_COHERENT to BUS_DMA_NOCACHE on IBM ppc4xx CPUs.

The "emac" interface now works properly again on my Walnut. Much
thanks to Steve Woodford for tracking this down.

Switch ibm4xx over to using the more flexible powerpc bus_space/bus_dma code.

branches: 1.11.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Oops, delete an accidentally committed local change.

Allow <machine/bus.h> to override the definition of BUS_DMA_COHERENT.
For example, machine-dependent code can make it equivalent to
BUS_DMA_NOCACHE if the hardware cannot reliably snoop the bus.

Switch/adapt to new bus space infrastructure.

Adapt to powerpc/bus.h changes.

Add preliminary support Marvell (Galileo) Discovery System Controllers.
This code was contributed by Allegro Networks.

Introduce BUS_DMA_NOCACHE, and bus_dmamem_map() of i386 supports it.

Add bus_space_vaddr().

branches: 1.3.8;
Provide basic bus_space_mmap(). Noted by self and in PR port-powerpc/14873.
This at least allows the compile to complete. There are still Issues with
vga_pci.c's assumptions about a PC-ish environment.

branches: 1.2.6;
Add BUS_DMA_READ and BUS_DMA_WRITE flags, that hint the back-end
at dmamap load time that the mapping will be used for a unidirectional
transfer of the specified direction.

branches: 1.1.2; 1.1.4;
Include a common bus.h and bus_dma.c that powerpc ports can use
if they so choose.

powerpc: Implement bus_space_barrier as eieio.

Style and cosmetic changes. No binary changes intended.

Provide PRIxBUSADDR, PRIxBUSSIZE, PRIuBUSSIZE, and PRIxBSH for all arches
to follow arm and (generic) mips.

Reviewed by christos.

branches: 1.2.30;
Use uintptr_t for bus_size_t, bus_addr_t, bus_space_handler_t since uint32_t
doesn't really work too 64-bit platforms.

branches: 1.1.2; 1.1.12; 1.1.16;
Per discussion at
<http://mail-index.netbsd.org/tech-kern/2010/04/02/msg007941.html>,
divide each machine's bus.h into bus_defs.h (constants & data types)
and bus_funcs.h (macro implementations of bus_space(9) routines and MD
prototypes).

Note that some bus_space(9) routines' implementation will move to .c
files from inline subroutines or macros in .h files.

I've only made the split for machine architectures where there is PCI.
All of the non-PCI-having architectures will require a similar split.

These #include files are not referenced by any (committed) Makefiles or
header files, yet. Changes to Makefiles, to <sys/bus.h>, and to some
more machine-dependent files will dribble in before I throw the switch.

powerpc: Implement bus_space_barrier as eieio.

Per discussion at
<http://mail-index.netbsd.org/tech-kern/2010/04/02/msg007941.html>,
divide each machine's bus.h into bus_defs.h (constants & data types)
and bus_funcs.h (macro implementations of bus_space(9) routines and MD
prototypes).

Note that some bus_space(9) routines' implementation will move to .c
files from inline subroutines or macros in .h files.

I've only made the split for machine architectures where there is PCI.
All of the non-PCI-having architectures will require a similar split.

These #include files are not referenced by any (committed) Makefiles or
header files, yet. Changes to Makefiles, to <sys/bus.h>, and to some
more machine-dependent files will dribble in before I throw the switch.

Reorganize the way powerpc port install machine specific headers.
Use <powerpc/oea/bat.h> exclusively and remove <machine/bat.h> and
<powerpc/bat.h>. Remove unneeded <machine/cpufunc.h>. To insure
1:1 correspondence of <powerpc/FOO.h> to <machine/FOO.h> include
"../../powerpc/include/Makefile" in "arch/FOO/include/Makefile".
Incororpate <byte_swap.h> into <bswap.h> and then byte_swap.h

branches: 1.1.2; 1.1.10; 1.1.26;
Inline bswap{16,32} when the argument is constant.

Add ALIGNBYTES32 for COMPAT_NETBSD32

branches: 1.9.2; 1.9.4;
Restore back to double alignment.

Change ALIGNBYTES to be AltiVec savvy

Change CMSG_SPACE and CMSG_LEN to provide Integer Constant Expressions
again. This was changed in sys/socket.h r1.51 to work around fallout
from the IPv6 aux data migration. It broke the historic ABI on some
platforms. This commit restores compatibility for netbsd32 code on such
platforms and provides a template for future changes to the CMSG_*
alignment. Revert PCC/Clang workarounds in postfix and tmux.

branches: 1.6.146; 1.6.150;
Change _MACHINE_foo_H_ to _POWERPC_foo_H_

branches: 1.5.26;
Garbage-collect.

Bug fixes and cleanup from Chris Demetriou <cgd@pa.dec.com>:
- fix _C_LABEL so that it actually works.
- make __RENAME use _C_LABEL.
- fix __RENAME so that it expects an unquoted argument.
- fix __indr_reference and __warn_references so that they
supply their own final semicolon.
- define __warn_references to nothing if not GNU C (required
by the way it's used).

The __warn_references semicolon change has to be made
so that __warn_references can be defined into nothing.
(A ; all by itself isn't a great idea.) The __indr_reference
change was made for consistency.

Implement __RENAME() in <machine/cdefs.h>

branches: 1.2.8;
Update for Elf.

PowerPC port

add a "struct trapframe;" forward decl before a prototype that wants
a pointer to it. GCC 14 didn't like this.

Trailing whitespace

remove workaround for old clang - it's not needed anymore and caused problems
elsewhere

Export CPU capability of unaligned memory access to userland
as machdep.no_unaligned sysctl(7) variable.

This will be used for ld.so.conf in order to provide strictly-
aligned versions of libc routines.

Introduce PPC_NO_UNALIGNED flag to indicate that CPU cannot handle
unaligned memory access, and emulation should be provided to userland.

In order to prevent _mcount() from being recursively called when built with COPTS=-O0,
sprinkle `__always_inline' to make _mcount() be generated as a single function.

Improved the performance of kernel profiling on MULTIPROCESSOR, and possible to get profiling data for each CPU.

In the current implementation, locks are acquired at the entrance of the mcount
internal function, so the higher the number of cores, the more lock conflict
occurs, making profiling performance in a MULTIPROCESSOR environment unusable
and slow. Profiling buffers has been changed to be reserved for each CPU,
improving profiling performance in MP by several to several dozen times.

- Eliminated cpu_simple_lock in mcount internal function, using per-CPU buffers.
- Add ci_gmon member to struct cpu_info of each MP arch.
- Add kern.profiling.percpu node in sysctl tree.
- Add new -c <cpuid> option to kgmon(8) to specify the cpuid, like openbsd.
For compatibility, if the -c option is not specified, the entire system can be
operated as before, and the -p option will get the total profiling data for
all CPUs.

For LP64, remove members of struct cpu_info that exist just for
compatible with booke or ibm4xx. Even if MODULAR || _MODULE,
these members are useless for powerpc64.

Add a provision for a per-cpu battable. Each CPU starts with the global
one, but this allows CPUs to temporarily switch to an alternate battable
if needed.

Pull out constant definitions inside struct declaration.

Enable CTASSERT(9) for CPUSAVE_SIZE.

branches: 1.115.2;
Factor out emulation code for m[ft]msr in user mode from oea, and
adjust it for systems without FPU.

Now, it can be used from booke and ibm4xx in order to support fenv(3).

Part of PR port-powerpc/55425
openssl fails on FPU emulation for powerpc

Provide machdep.fpu_present sysctl variable like other ports.

Userland can get informed that FPU is absent and emulated in software
(and calculation results may not be correct in bit-to-bit precision).

This variable should be useful even if we could fix FPU emulation;
it is much faster to skip FPU arithmetic in general, rather than
relying upon emulation by kernel via illegal instruction handler.

Use (CI_SAVEMAX*CPUSAVE_LEN) as CPUSAVE_SIZE for MODULAR || _MODULE,
since it exceeds 128 (256 for now).

XXX
We should use CTASSERT here, but it conflicts with genassym...

Drop unused opt_lockdebug.h.

apply __HIDE_DELAY so zfs and friends at least compile

Fix false sharing problems with cpu_info. Identified with tprof(8).
This was a very nice win in my tests on a 48 CPU box.

- Reorganise cpu_data slightly according to usage.
- Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc).
- On x86, put some items in their own cache lines according to usage, like
the IPI bitmask and ci_want_resched.

cpu_need_resched():

- Remove all code that should be MI, leaving the bare minimum under arch/.
- Make the required actions very explicit.
- Pass in LWP pointer for convenience.
- When a trap is required on another CPU, have the IPI set it locally.
- Expunge cpu_did_resched().

- Cleanup for dynamic sysctl:
- Remove unused *_NAMES macros for sysctl.
- Remove unused *_MAXID for sysctls.
- Move CTL_MACHDEP sysctl definitions for m68k into m68k/include/cpu.h and
use them on all m68k machines.

Retire ipkdb entirely. The option was removed from the config files
yesterday.

ok kamil christos

branches: 1.106.2;
copy HID1 from the boot CPU to secondary CPUs as well on 64bit CPUs
now the 2nd CPU on my G5s runs at full speed

save & restore HID4 and HID5, zero SPR_HIOR on 970

first step towards G5 SMP:
- only save/restore BATs on CPUs that have them
- treat HID0 as 64bit on 64bit CPUs

branches: 1.103.2;
apply the same change for powerpc as mrg did for arm and mips:

CPU_INFO_FOREACH() must always iterate at least the boot cpu.
document this in sys/cpu.h and fix the arm and mips versions
to check ncpu is non zero before using it as an iterator max.

this should fix the new assert in init_main.c.

branches: 1.102.8;
Added MSI/MSI-X and interrupt_distribute(9) support for powerpc.

branches: 1.101.2;
ddb MP support

branches: 1.100.6;
use cpu_{g,s}etmodel

support ppc601
from scole_mail, ok matt@

resort the sys/cpu.h way for unused cii iterator in !MULTIPROCESSOR case.

kcpuset_t changes for the pmap and removal of __cpuset_t

branches: 1.96.4; 1.96.6;
we can read the timebase register as a 64bit chunk when _ARCH_PPC64 is defined,
not necessarily LP64

Make the 85xx get closer to spinning up the secondary CPUs.
Don't assume TLB1[0] has the mapping for VA/PA 0.
Make sure the TLB1 entries that map physical memory have the M (memory
coherent) bit set.

Support Cache Protocol 'MEI' with MULTIPROCESSOR.

branches: 1.93.2;
Fix -fno-common fallout.

More cleanup. Use a union (pmap_segtab) and a typedef (pmap_segtab_t). Add
more functionality from the mips pmap and try to make it more common to ease
the transition for mips in the future.

Don't use global asm for __clang__

Add CPU_EXECPROT sysctl so that atf can enable exec permission tests for
PPC Booke.

branches: 1.89.2;
Remove white-spaces.

branches: 1.88.2; 1.88.6;
Modify mapiodev to take a third argument indicating whether the space
should be prefetchable (true) or not (false).

Cleanup hatch names.
Add cpuset_info.

Add a common cpu_ast(l, ci) routine.
Add a ci_pmap_asid_cur for BOOKE debugging.

Reap the ci_ev_soft* evcnts since every variant implements __HAVE_FAST_SOFTINTS

Make struct cpu_info the same size if building MODULAR
kernels or compiling a module.

Make more module friendly (part 1).
Don't export frame.h and psl.h to all of the kernel.
add lwp_pc and clkf accessor functions.
whitespace cleanup.

struct device * -> device_t

Move booke_fixup_stubs() to fixup.c and rename it to cpu_fixup_stubs().
This makes it easier for other PPC variants to use it.

Take the fast softint support in e500_intr.c and make generic so that it can
be used to provide fast softint for other interrupt implementations.

Add __HAVE_CPU_UAREA_ROUTINES support so that uareas will be direct-mapped.
(This avoids the nasty tlb recursion problem on ibm4xx as well on mpc85xx).

Use mfsprg0 instead of mfsprg r,0

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.76.2;
add access functions for the Instruction Cache Throttling Control register
found in 750 and newer CPUs

Fix CLKF_INTR
Add debug evcnt.

branches: 1.74.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.73.2;
All ports have to expose 'struct cpu_info' when _KMEMUSER is defined.
We will just expose cpu_info.ci_data for the moment, which is needed for
vmstat(1) to compile. Doing so with the whole cpu_info structure is
problematic, because of imask_t.

Include sys/device_if.h instead of sys/device.h. machine/cpu.h is
one of the lower-most definitions. Relying on the huge sys/device.h
is not a good idea.

Support sysctl machdep.cpu_speed for 7447A and 7448 based Macs. On those
machines the CPU's DFS (Dynamic Frequency Switching) feature is used instead
of a GPIO to control the speed.
Two new functions in powerpc/oea/cpu_subr.c were introduced to support
reading and writing of DFS: cpu_get_dfs() and cpu_set_dfs(). Also works
for multiple CPUs, but not before interrupts are enabled.

Support 64-bit imask for powerpc/pic.

Support PowerPC 405EX/EXr.
1. Add some new source and header files.
(MAL(split) and RGMII(new) relations for EMAC)
2. Create dcr4xx.h. Its moved from dcr405gp.h. Also remove dcr405xx.h.
3. intr.c supports MULTIUIC with virtual-irq. likes to oea.
support 32-virq/128-hwirq.
4. multiple emac support.
5. WALNUT and VIRTEX_* includes arch/powerpc/conf/files.ibm4xx.
6. WALNUT pci uses arch/powerpc/ibm4xx/pci/.

branches: 1.68.2;
Add BookE modifications to cpu_info

branches: 1.67.2;
Provide cpu_lwp_free* stubs in vax and powerpc.
Reported by <he>.

Remove uarea swap-out functionality:

- Addresses the issue described in PR/38828.
- Some simplification in threading and sleepq subsystems.
- Eliminates pmap_collect() and, as a side note, allows pmap optimisations.
- Eliminates XS_CTL_DATA_ONSTACK in scsipi code.
- Avoids few scans on LWP list and thus potentially long holds of proc_lock.
- Cuts ~1.5k lines of code. Reduces amd64 kernel size by ~4k.
- Removes __SWAP_BROKEN cases.

Tested on x86, mips, acorn32 (thanks <mpumford>) and partly tested on
acorn26 (thanks to <bjh21>).

Discussed on <tech-kern>, reviewed by <ad>.

branches: 1.65.22;
add dummy argument to cpu_did_resched() so kern_synch.c is happy again

branches: 1.64.2; 1.64.4;
SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.

Remove CTL_MACHDEP_NAMES, it's not used anywhere.

Ok by martin@.

branches: 1.62.2; 1.62.6;
Replace as much of the hardcoded CACHELINESIZE with
curcpu()->ci_ci.dcache_line_size as I can. With this change, an ofppc kernel
compiled with both PPC_OEA and PPC_OEA64_BRIDGE defined, boots.

Rewrite a big chunk of the pmap and locore code for powerpc to better
deal with the 64bit bridge mode. pmap changes by Matt Thomas, rest by myself.

Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel. This allows the pmap for bridge64 to
co-exist with the 32bit pmap.

Yank __HAVE_PMAP_PHYSSEG from all the oea code.

Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features. This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.

Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in. Some of it seemed incorrect, and my 7044 booted just fine
without it. It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.

In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].

With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu. However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE. Work remains to be done there to fix that.

Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

branches: 1.59.2;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.58.8; 1.58.10; 1.58.12; 1.58.14;
- add booted_device and booted_kernel sysctl nodes to let userland know
about runtime environment.

Fix for yamt-idlelwp merge.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.55.2; 1.55.4; 1.55.10;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.54.2;
Remove spllowersoftclock() and CLKF_BASEPRI(), and always dispatch callouts
via a soft interrupt. In the near future, softclock will be run from process
context.

Merge newlock2 to head.

branches: 1.52.2;
Add unmapiodev.

1st cut of Powermac G5 support (uses bridge mode).

Bring ibm4xx interrupt code up to date:

- generic soft interrupts (ie. use powerpc/softintr.c)
- interrupt event counters (using the ones from powerpc/cpu.h:cpu_info
where appropriate)
- cleanup ibm4xx_intr.h, move implementation details to intr.c

Convert all affected evbppc platforms.

OK by simonb@, some points discussed with matt@

branches: 1.49.2;
Merge multiple definitions of cntlzw() ("count leading zeros")
instruction-wrapper to <powerpc/cpu.h>.

OK by briggs@

Remove duplicate definitions of mfdcr()/mtdcr() in favor of a single one
in cpu.h

OK Matt Thomas

branches: 1.47.2; 1.47.8;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.

branches: 1.46.2; 1.46.4; 1.46.6;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.44.6;
Keep track of the CPU's current speed (in kHz) in the cpu info structure,
if we can get it. May want to expand this in the future to include min
and max speeds for systems where we can adjust the speed.

branches: 1.43.2;
Split the hw-dependent powermanglement into its own function and make
Idle call that. Add a ci_idlespin function pointer to cpu_info.
Update INIT_CPUINFO to initialize it to a naked 'blr' instruction.
In oea/cpu_subr.c, add cpu_idlespin and make ci_idlespin point to it.

branches: 1.42.4;
move some per-cpu data definitions to MI place so that they can be modified
without touching all ports. discussed on tech-kern@.

Mark cr0 as clobbered in mfrtc().

Don't waste space on likely unused sysmon structure.
Instead malloc them as needed.

Rearrange process exit path to avoid need to free resources from different
process context ('reaper').

From within the exiting process context:
* deactivate pmap and free vmspace while we can still block
* introduce MD cpu_lwp_free() - this cleans all MD-specific context (such
as FPU state), and is the last potentially blocking operation;
all of cpu_wait(), and most of cpu_exit(), is now folded into cpu_lwp_free()
* process is now immediatelly marked as zombie and made available for pickup
by parent; the remaining last lwp continues the exit as fully detached
* MI (rather than MD) code bumps uvmexp.swtch, cpu_exit() is now same
for both 'process' and 'lwp' exit

uvm_lwp_exit() is modified to never block; the u-area memory is now
always just linked to the list of available u-areas. Introduce (blocking)
uvm_uarea_drain(), which is called to release the excessive u-area memory;
this is called by parent within wait4(), or by pagedaemon on memory shortage.
uvm_uarea_free() is now private function within uvm_glue.c.

MD process/lwp exit code now always calls lwp_exit2() immediatelly after
switching away from the exiting lwp.

g/c now unneeded routines and variables, including the reaper kernel thread

Restore ci_curpm since it re-enables 603 to working state.

Move CLKF_BASEPRI to machine specific <intr.h> file since it depends on
the encoding of the spl for the port.

Not all PPC ports (e.g. macppc) equate IPL_NONE with 0.

Nuke ci_curpm and curpm. Nuke pcb_pmreal. Those were use for spill stacks
and those no longer exist. for few uses that need CURPM, use CURPCB/PCB_PM

Nuke ci_spillstk/CI_SPILLSTK. No longer needed.

Make that OEA based kernels can properly deal with kernel ISI faults. Now
that LKMs are supported, it is possible for a LKM page to be "outspilled"
resulting in a possible ISI fault. Try to spill the page back in.

Add symbolic offsets for what's in cpu save locations.
Add a PPC64 variant of mftb

Switch ibm4xx over to using the more flexible powerpc bus_space/bus_dma code.

branches: 1.30.2;
Use __asm & __volatile to make lint(1) happy.

Add support for the IBM 403GCX cpu. Enabled with "options PPC_IBM403".

- different set of device control registers.
- non-standard access to the time base.
- 16 byte cache lines.

Approved by: Eduardo Horvath <eeh@netbsd.org>

Add some missing volatiles.

Only include kernel headers if _KERNEL is defined.

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

Perform a rototill of the powerpc code. Mandate use of SPRG0 to store
a pointer to current cpu's cpu_info structure. Use cpu_info for
intstk,intr_depth,still_stk,idle_pcb,curpcb,curlwp,etal even on
non-MULTIPROCESSOR machines. Add common macros GET_CPUINFO and
INIT_CPUINFO to get and initialize the cpu_info struct on startup. Make
ibm4xx use the standard <powerpc/frame.h>. Use IFRAME_xx in ibm4xx
trap_subr.S instead of explicit magic offsets. Move INTSTK and SPILLSTK
to std.<platform>. Change faultbuf to a struct instead of an array.

On MPC6XX cpus, stop using the vector page for temporary space and use
reserved space in cpu_info.

Add mfrtcl() and mfrtc(), similar to mftbl() and mftb().

Merge the nathanw_sa branch.

No newlines in string constants.

In mftb(), make sure we say we are clobbering cr0.

Prepare for PPC64. Use register_t for mtmsr/mfmsr since the msr on PPC64
is 64bits wide. Define proper types for PPC64 if _LP64 is defined.

move more inlines to cpu.h: mftb(), mftbl() and mfpvr().
(the mftb() in pmap.c only wanted the lower 32 bits, so that's now mftbl()).

define CPU_INFO iterators so that the CPU-states sysctl works for MP.

Add machdep.powerpc sysctl. Change the default value of powersave to -1
(< 0 mean no powersave available). Enable powersave by default for
750/7400/7410 but leave if off for 7450/7455.

Peform a rototill over the powerpc-based ports.

Move the trap/vector initialization for MPC6xx ports to mpc6xx_machdep.c
Also move softnet, install_extintr, mapiodev, kvtop. Add common BAT
initialization code.

Add user Altivec support.

Fix calls to OF_call_method in macppc/macppc/machdep.c.

Use ci_fpuproc in cpu_info instead of separate fpuproc.

Add separate syscall.c and defined __HAVE_SYSCALL_INTERN.

branches: 1.15.2;
Use size_t in prototype (so this will be LP64 clean for PPC64 someday).
Calculate len separately for icache & dcache in case each has different
cacheline widths. Make the code for both loops the same except for the
dcbst/icbi. Deal with sizes >=2GB properly (like that'll happen but ...)

Add cache_info to cpu_info which provides details about D$ and I$
sizes and line sizes. This is needed for cache flusing, clearing
memory, and several other operations. This information is accessible
from userland through a new CPU_CACHEINFO sysctl.

Move #include <dev/sysmon/sysmonvar.h> inside #ifdef _KERNEL.

Add sysmon data structures to struct cpu_info.

fix macppc MULTIPROCESSOR compilation.

branches: 1.10.6;
__syncicache needs to be exports to userspace as well as the kernel.

Make all powerpc ports use a common Makefile.powerpc (except walnut)
Enforce -Wmissing-prototypes -Wstrict-prototypes for all ppc ports.
Split out macppc cpu support and make common to mpc6xx ports. Make
other mpc6xx ports use it. Add evcnts for mpc6xx traps.

branches: 1.8.2;
Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.

Introduce a new & faster pmap for the MPC6xx (60x, 7xx, 7xxx) PPC CPUs.
Move MPC6xx dependent header files to powerpc/include/mpc6xx/

branches: 1.6.2; 1.6.16;
Add missing CPU_MAXID definition.

Modify syncicache on PowerPC from an inline to a real function.
Support different cache line sizes with the same object code in userland.
While here, move the function to implementation name space.

Rename NetBSD/powerpc to NetBSD/ofppc.
New sys/arch/powerpc with PowerPC-generic stuff.

asm -> __asm__, volatile -> __volatile

branches: 1.2.8;
Definitions for machine_vec interface, from Wolfgang Solfrank.

PowerPC port

Include missing opt_ppcarch.h.

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.7.2; 1.7.4;
Adapt to spr.h breakup.

branches: 1.6.10; 1.6.30; 1.6.34;
Ifdef out all the MPC601 code with PPC_OEA601. Now only arches that have the
possibility of running on an MPC601, are infected with all the extra code
and nops that it added.

Also, fix compilation that I broke with the pmap code, by adding
oeacpufeat to the locores of various ppc arches. Noted by mlelstv.

branches: 1.5.2;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.4.24; 1.4.32; 1.4.42; 1.4.44; 1.4.46; 1.4.48;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.

branches: 1.3.2; 1.3.4; 1.3.6;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

branches: 1.2.18;
Add support for the IBM 403GCX cpu. Enabled with "options PPC_IBM403".

- different set of device control registers.
- non-standard access to the time base.
- 16 byte cache lines.

Approved by: Eduardo Horvath <eeh@netbsd.org>

Replace machine/rnd.h with more appropriate name to share it
with cycle counter based microtime in kern/kern_microtime.c.

kcpuset_t changes for the pmap and removal of __cpuset_t

branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8; 1.1.10; 1.1.20; 1.1.24; 1.1.32;
Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

Remove Darwin, MACH and Mach-O support.

branches: 1.10.22; 1.10.28;
Remove clause 3 and 4 from TNF licenses

branches: 1.9.74; 1.9.76; 1.9.78;
merge ktrace-lwp.

move ppc commpage stuff here.

typo

MacOS X.3 introduces a new sigreturn for PowerPC, with a usercontext
versionning argument. For now we only implement the X.2 flavor.

In MacOS X.3, the kernel maps tw opages of memory in every user process.
This areas is called the comm pages. It is used to provide fast access to
several data and functions.

The comm pages are mapped starting at 0xffff800 (address chosed so that
absolute branch can be used, so it can be accessed even when dynamic linking
is not ready). NetBSD has the user stack here, so we need to provide a
Darwin-specific stack setup routine which sets the top of the stack at
0xbfff0000.

This implementation is not complete but it does enough to get MacOS X.3
starting again (static binaries run, dynamic binaries still have an issue).
in the comm pages functions, we only implement bcopy, pthread_self and
memcpy.

TODO:
- clean up the powerpc specific code from MD parts
- for now we map only one page to avoid a crash, we want two pages.
- write all the comm functions.

Implement mach_thread_get_state.
While we are here, try to tag machine dependent functions in header files.
also transformed darwin_ppc_*_state into mach_ppc_*_state, as this is
what they really are (COMPAT_DARWIN is on the top of COMPAT_MACH, not the
other way around)

forgotten commit for KERN_PROCARGS sysctl in COMPAT_DARWIN

branches: 1.2.2; 1.2.8;
A working fork/vfork implementation. Darwin fork differs from our fork by
two ways:
- the child gets its pid as retval[0] (userland stub will turn it into a 0),
retval[1] is 1 and it is 0 in the parent.
- in the child, the fork syscall is successful, hence we must skip the next
instruction.

Add signal delivery for the PowerPC. Everything is implemented except siginfo.
The stack layout is observed from stack dumps on Darwin, so it should be
very accurate.

Use ifdef _KERNEL_OPT instead of ifdef _KERNEL before including
"opt_ppcarch.h".

Switch DDB for powerpc/booke into SOFTWARE_SSTEP.

SR_SINGLESTEP aka PSL_SE bit in MSR is only available for oea, and HW
debug facilities for booke are significantly different from oea.

branches: 1.28.2;
Style and cosmetic changes. No binary changes intended.

Do not mask out LK bit (bit 31) from M_BCTR, which distinguishes
bcctr and bcctrl.

Fix build failure for ibm4xx kernels with GCC8.

XXX
pullup to netbsd-9, -8, and -7

branches: 1.26.4; 1.26.8;
Cleanup and clarify the ELFSIZE mess:

We now have 2 variables automatically set in elf_machdep.h:

ARCH_ELFSIZE: the size for userland binaries
KERN_ELFSIZE: the size for the kernel binaries

DB_ELFSIZE has been deleted and KERN_ELFSIZE should have always the
same values DB_ELFSIZE used to have.

In sys/exec_elf.h, if ELFSIZE is not set, it is set to KERN_ELFSIZE
for the kernel and ARCH_ELFSIZE for userland. These defaults should
eliminate the need for most manual ELFSIZE setting.

ddb MP support

branches: 1.24.12; 1.24.30;
Update KDB_NUMREGS to match what gdb6 is using for PPC.
Patch taken from PR/43196

branches: 1.23.2;
Introduce DDB_EXPR_FMT and replace the logic around DB_EXPR_T_IS_QUAD.

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.21.4; 1.21.6;
New machine commands for PPC OEA:
bat: prints the BAT registers and translations
mmu: prints MMU registers (sdr1, sr0..15)

Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.

branches: 1.19.66; 1.19.74; 1.19.80; 1.19.88;
integrate kauth.

closes kern/32359

branches: 1.17.18; 1.17.32; 1.17.34; 1.17.36; 1.17.38; 1.17.40;
Add a BKPT_ADDR() macro which gives MD code a chance to munge a
breakpoint address before it's used. Currently a no-op on all but sh5.

This is useful on sh5, for example, to mask off the instruction
type encoding in the bottom two address bits, and makes it possible
to do "db> break $rXX" instead of manually munging the address.

Make lint happy by not assigning to casted lvalue.

MPC601 support bits:
* install 601-specific DSI and RUNMODETRC trap handlers
* save/restore MQ in trapframe, add MQ hooks to DDB
* extend battable to 512 entries to hold the 601's 8M translations
* instead of adding I/O to BAT starvation, set up segment registers
for Memory-Forced I/O Controller Interface Access
* sync after tlbie

Use Software Single Stepping for now when PPC_IBM4xx is defined. The
existing hardware assisted method doesn't work on this cpu.

Also correct the "I_B" constant in db_machine.h.

Eliminate commons.

add support for kgdb over zs

fix single stepping and continuing from breakpoints in ddb

branches: 1.10.2; 1.10.8;
Build for kgdb as well as for ddb (mutually exclusive).

Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.

branches: 1.8.2;
uvm/uvm_inherit.h was removed.

<vm/vm_param.h> -> <uvm/uvm_param.h>

remove/move more mach vm header files:

<vm/pglist.h> -> <uvm/uvm_pglist.h>
<vm/vm_inherit.h> -> <uvm/uvm_inherit.h>
<vm/vm_kern.h> -> into <uvm/uvm_extern.h>
<vm/vm_object.h> -> nothing
<vm/vm_pager.h> -> into <uvm/uvm_pager.h>

also includes a bunch of <vm/vm_page.h> include removals (due to redudancy
with <vm/vm.h>), and a scattering of other similar headers.

<vm/vm_prot.h> becomes <uvm/uvm_prot.h>

branches: 1.4.12; 1.4.22;
vm_offset_t --> [pv]addr_t

Change db_expr_t from int to long like other ports.

Fix layout of powerpc_saved_state.

Import DDB from OpenBSD/powerpc.

Rename NetBSD/powerpc to NetBSD/ofppc.
New sys/arch/powerpc with PowerPC-generic stuff.

Change MBR partition type for NetBSD to 0xa9, like the i386 port.
Provide compatibility via COMPAT_386BSD_MBRPART.

Don't define two partition types for NetBSD - just use the standard 0xa5.
(Eww, DOS MBR)

PowerPC port

powerpc/elf_machdep.h: Use psABI spellings and group symbols into psABI/local groups.

The prior spellings have been kept around for backward compatibility.

Permit this file to be used alongside <sys/elfdefinitions.h>.

PR lib/59564

Fix typo in the definition of #ha() in a comment.

branches: 1.15.4;
handle ppc64

Cleanup and clarify the ELFSIZE mess:

We now have 2 variables automatically set in elf_machdep.h:

ARCH_ELFSIZE: the size for userland binaries
KERN_ELFSIZE: the size for the kernel binaries

DB_ELFSIZE has been deleted and KERN_ELFSIZE should have always the
same values DB_ELFSIZE used to have.

In sys/exec_elf.h, if ELFSIZE is not set, it is set to KERN_ELFSIZE
for the kernel and ARCH_ELFSIZE for userland. These defaults should
eliminate the need for most manual ELFSIZE setting.

Add IRELATIVE support for ARM, X86 and PowerPC.

branches: 1.12.6;
Don't define ARCH_ELFSIZE if it's already defined.

Add PowerPC64 DTs

More comments.
rest of powerpc64 relocs

branches: 1.9.8; 1.9.18; 1.9.22;
Add some more reloc types as well as DT_PPC_GOT

branches: 1.8.4;
Add TLS relocation definitions.

branches: 1.7.56;
PR toolchain/35105: Don't include reloc.h, instead provide R_PPC_* defines
and make R_TYPE() use them. This is more consistent with other ports, too.

Suggested by Manuel Bouyer, ok'd by Matt Thomas.

branches: 1.6.4; 1.6.6;
add new split personality for ELF64

branches: 1.5.32; 1.5.46; 1.5.50; 1.5.58;
Add support for dumping ELF-cormat core files.

branches: 1.4.8; 1.4.12;
Move dl* function definitions to libc on ELF.
Based on the patch supplied by Takuya Shiozaki <tshiozak@astec.co.jp>.
See http://mail-index.netbsd.org/tech-userlevel/2000/02/23/0000.html.

Update to match new SVR4-style definition names in <sys/exec_elf.h>.

branches: 1.2.10; 1.2.12; 1.2.14;
Add PIC definitions.

Machine-dependent definitions for Elf on NetBSD/powerpc.

In the `MY THAT'S GROSS' department...
Eliminate the recursive include of machine/endian.h from sys/endian.h.

Foolish consistency. Mainly, always use underscores and sys/endian.h.

branches: 1.7.2;
Include <sys/endian.h> after defining whether where are little- or
big-endian. i386, pc532 and vax still include <machine/byte_swap.h>
and define macros for the {n,h}to{h,n}*() functions. mips also
defines some endian-independent assembly-code aliases for unaligned
memory accesses.

Mark [hn]to[nh][ls]() with __const__, so they are subject to CSE.

Move the bswap functions from libutil to libc (this bups the
minor of libc and the major of libutil). For little-endian architectures
merge the bnswap() assembly versions with nto* and hton* using symbols
aliasing. Use symbol renaming for the bswap function in this case to avoid
namespace pollution.
Declare bswap* in machine/bswap.h, not machine/endian.h. For little-endian
machines, common code for inline macros go in machine/byte_swap.h
Sync libkern with libc.
Adjust #include in kernel sources for machine/bswap.h.

(Always) (practice) (safe) (macro expansion).

branches: 1.3.4;
Add byte-swapping functions (bswap16, bswap32, bswap64) to libkern.
Only assembly version for i386 bswap16 and bswap32 for now (bswap64 uses
bswap32). Contribution of assembly versions of these are welcome.
Add byte-swapping of ext2fs metadata for big-endian systems.
Tested on i386 and sparc.

branches: 1.2.10;
use in_addr_t and in_port_t

PowerPC port

branches: 1.1.6;
In the `MY THAT'S GROSS' department...
Eliminate the recursive include of machine/endian.h from sys/endian.h.

moved to aout_machdep.h (via repository copy)

PowerPC port

Sprinkle <sys/featuretest.h> where _*_SOURCE macros are consulted.

Otherwise, the feature tests might come out wrong. For example,
header files that check for _NETBSD_SOURCE won't get the default when
no other _*_SOURCE macros are defined; header files that check for
_POSIX_C_SOURCE might miss _XOPEN_SOURCE, which is supposed to imply
a corresponding _POSIX_C_SOURCE.

PR lib/58752: various header files test _*_SOURCE macros but don't
include sys/featuretest.h

branches: 1.7.10;
fesetexceptflag(): Set FE_ALL_INVALID instead of FE_ALL_EXCEPT for
FE_INVALID. Taken from FreeBSD:

https://cgit.freebsd.org/src/commit/lib/msun/powerpc/fenv.h?id=e7bd4f846f0c9185aebfd3d116bb78ab137280fa

> [POWERPC] msun: fix incorrect flag in fesetexceptflag
> Fix incorrect mask being used when FE_INVALID bit is wanted by user.
> The problem was noticed thanks to msun fenv tests.
>
> Reviewed by: jhibbits, luporl
> Sponsored by: Eldorado Research Institute (eldorado.org.br)
> Differential Revision: https://reviews.freebsd.org/D27201

No regression for full ATF on both real and emulated FPU.

XXX
Import some tests from FreeBSD's lib/msun/tests.

do the ignore builtin dance for gcc-8

branches: 1.5.2;
s/static inline/static __inline/g for consistency.

branches: 1.4.2; 1.4.4;
Fixed feholdexcept() by copying the actual contents of FPSCR to the fenv_t
instead of a double precision floating point representation of it.

branches: 1.3.6;
provide a common softfloat fenv implemenation and use it for softfloat builds.
restore ABI compatibility with previous releases for ieeefp.h on sh3.
add namespace.h protection for all the fenv interfaces.
use MKSOFTFLOAT on sh3 instead of assuming softfloat.
standardize on comparing MKSOFTFLOAT with "no".
remove the arm-specific softfloat fenv code (which also had several bugs).
fix logic errors in the arm hardfloat feraiseexcept() and feupdateenv().

update the FE0/FE1 MSR bits as needed when changing the exception mask.

branches: 1.1.2; 1.1.4; 1.1.6;
Add fenv.h for powerpc (from FreeBSD)

Rename <sys/float_ieee.h> to <sys/float_ieee754.h>, following libc's
convention for these.

PR/3012: Greg A. Woods: Write all float.h files [except the vax of course]
in terms of float_ieee.h

branches: 1.4.8;
Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.

branches: 1.3.26;
Minor changes to make all the float.h files match.

Prototype __flt_rounds() consistently.

branches: 1.1.14;
PowerPC port

Expose fpu_get_fault_code() even if !PPC_HAVE_FPU, and
adjust it to systems without FPU.

Drop unused opt_multiprocessor.h includes.

Style and cosmetic changes. No binary changes intended.

s/static inline/static __inline/g for consistency.

branches: 1.21.12;
allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.

branches: 1.20.6; 1.20.10; 1.20.14;
-extend the pcu(9) API by a function which saves all context on the
current CPU, and use it if a CPU is taken offline
-add a bool argument to pcu_discard which tells whether the internal
"LWP has used the coprocessor" flag should be set or reset. The flag
is reported by pcu_used_p(). If set, future accesses should use the
state stored in the PCB. If reset, it should be reset to default.
The former case is useful for setmcontext().
With that, it should not be necessary anymore to manage the "FPU used"
state by an additional MD variable.

approved by matt

branches: 1.19.4; 1.19.14; 1.19.18;
Remove unnecessary Tab.

Move powerpc to use pcu to manage FPU/AltiVec/SPE.

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.16.42; 1.16.46; 1.16.48;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.15.14; 1.15.22; 1.15.32; 1.15.34; 1.15.36; 1.15.38;
1st cut of Powermac G5 support (uses bridge mode).

branches: 1.14.4; 1.14.8;
merge ktrace-lwp.

branches: 1.13.12;
Add a SAVE/DISCARD flag to save_{fpu,vec}_lwp. Use it appropriately.
Nuke struct fpu and use struct fpreg instead (except for the names, they
were identical). On MP machines, this will avoid an unneeded IPI to save
the register contents that are about to discarded.

Add int get_fpu_fault_code(void).

branches: 1.11.2;
Make sure to include opt_foo.h if a defflag option FOO is used.

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

Merge the nathanw_sa branch.

Change _MACHINE_foo_H_ to _POWERPC_foo_H_

restructure the FPU and AltiVEC code so that it works for MP.

make usable in LKM context (use #if defined(_KERNEL_OPT))

branches: 1.5.8;
fix macppc MULTIPROCESSOR compilation.

branches: 1.4.2; 1.4.8;
Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.

branches: 1.3.2;
Build with -Wall -Wetc.

Fix "FPCSR" to "FPSCR". ("Floating Point Status and Control Register")

branches: 1.1.28; 1.1.34;
PowerPC port

Style and cosmetic changes. No binary changes intended.

LKM was gone. _KERNEL is always defined for module.

expose __register32_t for frame.h

branches: 1.26.6;
Add trapframe32 for COMPAT_NETBSD32

branches: 1.25.2; 1.25.4;
Fix a problem where the kernel could randomly reset due to a watchdog event.
When an exception happens, the srr0 (exception PC) was being saved in the
normal location of the current callframe. This was fine except when the
routine was in its prologue after it had saved LR but had not yet updated the
stack pointer or when the routine was in its epilogue after it has restored
the stack pointer but not yet loaded the LR. In either case this would cause
the LR to be corrupted (either running the routine forever or by branching
to itself forever). Now we save and restore the contents of that memory
location so the corruption can't happen.

Remove COMPAT_SA / KERN_SA. Welcome to 6.99.3!
Approved by core@.

branches: 1.23.2; 1.23.6; 1.23.8;
Pad out trapframe for OEA so that trapframe has identical sizes for all
PPC variants.

branches: 1.22.4;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.21.4; 1.21.6;
- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

branches: 1.20.16;
Bring back saframe. Noted by Robert Swindells.

branches: 1.19.44; 1.19.48; 1.19.54;
Merge newlock2 to head.

branches: 1.18.20;
merge ktrace-lwp.

branches: 1.17.16;
Move SFRAMELEN to frame.h and use it in vm_machdep.c. In setfunc, setup
callframe linkages correctly. Restore use of ldptr to locore_subr.S
[pthreads and gdb no longer crash/hang the system]

Cleanup/rework cpu_switch*, switch_exit, Idle routine. Remove pcb_psl
since it was write-only. When setting up a process, make sure the fake
callframes are properly linked together.

Only lower SPL when in Idle loop. Raise spl to previous level (which would
be IPL_SCHED) when exiting Idle loop. Never lower SPL anyplace else.

Change switchframe to use register_t (anything that uses stmX/lmX needs
to be defined as register_t).

branches: 1.14.2;
Don't use trapframe in sigcontext. Instead define a new structure
utrapframe that fixed in size (and the same size as the trapframe
in NetBSD 1.5). This preserves binary compatibility for those programs
that dealt looked at sigcontexts.

Perform a rototill of the powerpc code. Mandate use of SPRG0 to store
a pointer to current cpu's cpu_info structure. Use cpu_info for
intstk,intr_depth,still_stk,idle_pcb,curpcb,curlwp,etal even on
non-MULTIPROCESSOR machines. Add common macros GET_CPUINFO and
INIT_CPUINFO to get and initialize the cpu_info struct on startup. Make
ibm4xx use the standard <powerpc/frame.h>. Use IFRAME_xx in ibm4xx
trap_subr.S instead of explicit magic offsets. Move INTSTK and SPILLSTK
to std.<platform>. Change faultbuf to a struct instead of an array.

On MPC6XX cpus, stop using the vector page for temporary space and use
reserved space in cpu_info.

MPC601 support bits:
* install 601-specific DSI and RUNMODETRC trap handlers
* save/restore MQ in trapframe, add MQ hooks to DDB
* extend battable to 512 entries to hold the 601's 8M translations
* instead of adding I/O to BAT starvation, set up segment registers
for Memory-Forced I/O Controller Interface Access
* sync after tlbie

Use CALLFRAMELEN instead of 16.

Add trapframe32 (for compat_netbsd32).
Add CALLFRAMELEN. (so we can remove many of the hard coded "16" or "15"
in the powerpc code).

Merge the nathanw_sa branch.

Change _MACHINE_foo_H_ to _POWERPC_foo_H_

rename the intr_depth field of struct intrframe to avoid a name conflict
in MULTIPROCESSOR builds.

Make sure that pmap_zero_page and pmap_copy_page don't make calls or
reference while relocation is disabled since the stack will be inaccessible.
Add support for using AltiVec in pmap_zero_page and pmap_copy_page on
AltiVec capable processors.

Peform a rototill over the powerpc-based ports.

Move the trap/vector initialization for MPC6xx ports to mpc6xx_machdep.c
Also move softnet, install_extintr, mapiodev, kvtop. Add common BAT
initialization code.

Add user Altivec support.

Fix calls to OF_call_method in macppc/macppc/machdep.c.

Use ci_fpuproc in cpu_info instead of separate fpuproc.

Add separate syscall.c and defined __HAVE_SYSCALL_INTERN.

branches: 1.4.2;
Convert the spill stack frame to use symbolic offset names; inspired by
a conversation with Matt Thomas.

Use a common genassym.cf for all the PPC_MPC6XX ports. Add a makeoptions to
std.foo to indicate the directory to get genassym.cf from. Add an intrframe
to <powerpc/frame.h> and make trap_subr.S use symbolic offsets into it.

branches: 1.2.22; 1.2.26;
Fix void * arithmetic.

PowerPC port

Introduce a new & faster pmap for the MPC6xx (60x, 7xx, 7xxx) PPC CPUs.
Move MPC6xx dependent header files to powerpc/include/mpc6xx/

branches: 1.1.2;
powerpc HID registers definitions (only HID0 for now).

Introduce a new & faster pmap for the MPC6xx (60x, 7xx, 7xxx) PPC CPUs.
Move MPC6xx dependent header files to powerpc/include/mpc6xx/

branches: 1.1.2; 1.1.8;
Hardware Implementation Dependent registers for the PowerPC 601.

powerpc/ieee.h: Protect from multiple includes

Fix build failure triggered by import of libm long-double functions.

Support copysignl on PowerPC.

branches: 1.5.122; 1.5.140;
merge ktrace-lwp.

Push back the descriptions of NaN formats, and descriptions of the
distinction between signalling NaNs and quiet NaNs back into the
machine-dependent headers; treat the implementation of __nanf in the
same spirit.

IEEE 754 leaves the distinction between signalling NaNs and quiet NANs
to the implementation, and unlike our headers used to suggest they're
not identical in the interpretation of the fraction's MSb; in due
course, make those of hppa, mips, sh3, and sh5 reflect reality.

branches: 1.3.8; 1.3.14;
Use <sys/ieee754.h> where applicable.

Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

branches: 1.1.62;
PowerPC port

provide a common softfloat fenv implemenation and use it for softfloat builds.
restore ABI compatibility with previous releases for ieeefp.h on sh3.
add namespace.h protection for all the fenv interfaces.
use MKSOFTFLOAT on sh3 instead of assuming softfloat.
standardize on comparing MKSOFTFLOAT with "no".
remove the arm-specific softfloat fenv code (which also had several bugs).
fix logic errors in the arm hardfloat feraiseexcept() and feupdateenv().

the FP_* exception constants need to be different from the new FE_* constants
to preserve the ABI, so shift them as needed when using them.

branches: 1.5.2; 1.5.4;
move fenv inside ifdef

remove dup definitions from fenv.h

branches: 1.3.38; 1.3.58;
Update <machine/ieeefp.h> to use the C99 FE_* definitions instead of the
NetBSD defined ones. Redefine the NetBSD ones in terms of the C99 ones.
Step 1 to having <fenv.h>

branches: 1.2.138; 1.2.142; 1.2.144; 1.2.148;
reorder the fp_rnd constants to match the values used by the
powerpc fpu

branches: 1.1.18;
Definitions for IEEE floating point for NetBSD/powerpc.

Move FTYPE_* definitions from instr.h to fpu_emu.h.

They are not defined by architecture, and used only for FPU emulation.

Add routines to fix unaligned memory access for userland process.

Mainly intended for 403, which cannot handle unaligned memory access
at all (not only ones across page boundaries like 601).

For more details, see comments in fix_unaligned.c.

Fix insn field definitions for MD and MDS formats.

No one uses these yet.

Factor out emulation code for m[ft]msr in user mode from oea, and
adjust it for systems without FPU.

Now, it can be used from booke and ibm4xx in order to support fenv(3).

have fpsetmask() change the FE0/FE1 MSR bits to precise mode if any
FP exceptions are enabled. fix the kernel emulation of mfmsr and mtmsr
to use the correct opcodes for these instructions. ignore PSL_FE
(the FP enable bit) in the MSR that a user program tries to set,
since it will naturally be set for FP-using processes but
we can't let the user process manage that bit.

branches: 1.7.4; 1.7.8; 1.7.12;
Add OPC31_OR

branches: 1.6.14; 1.6.28;
When an OEA kernel is configured for multiple MMU types, use the new
powerpc fixup mechanism to bind the kernel to a particular MMU. This
avoids an indirect call for every pmap call.