branches: 1.1.2; 1.1.6; 1.1.8;
Add initial versions of these for BookE.

Change booke_intr.h to intr.h since <powerpc/booke/intr.h> will be unique
enough.

branches: 1.1.2; 1.1.4;
Add initial versions of these for BookE.

Include missing opt_multiprocessor.h.

Detangle some of the PowerPC CPU configuration spaghetti.

branches: 1.19.2;
s/static inline/static __inline/g for consistency.

branches: 1.18.16;
This needs to define PRIxPTE too.

branches: 1.17.14;
move common tlb stuff to uvm

branches: 1.16.2;
Add a machine splhist command to give (a incomplete) spl history.
(only the most recent are going to be accurate).

splraise(6) from 0 at 549214603
splraise(7) from 6 at 549214643 (+40)
splx(6) from 7 at 549214691 (+48)
splx(0) from 6 at 549214730 (+39)

Export dump_trapframe.

Add command line processing from uboot
bootm $loadaddr [opts] [device]
where opts is -[advqs] and device is the boot device.
cpu_rootconf will now wait a bit for devices to appear until the boot device
appears.

Fix -fno-common fallout.

branches: 1.12.2;
Modify mapiodev to take a third argument indicating whether the space
should be prefetchable (true) or not (false).

Declare cpu_hatch_data

Switch to using the common <common/pmap/tlb/tlb.h>

Explicitly include <powerpc/psl.h>

Move booke_fixup_stubs() to fixup.c and rename it to cpu_fixup_stubs().
This makes it easier for other PPC variants to use it.

Take the fast softint support in e500_intr.c and make generic so that it can
be used to provide fast softint for other interrupt implementations.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.5.2; 1.5.4;
add begging of single step support. Since BookE doesn't support PSL_SE, if
userret find PSL_SE set in SRR1, it will call booke_sstep to setup the
debug registers.

Add little endian bus_space_tags.
Note highest memory in cpu_softc.

Allow code to allow inclusive/exclusive locators for subdevices.
(uses on mpc85xx to match on SVRs or not match on SVRs).

branches: 1.2.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4;
file cpuvar.h was initially added on branch matt-nb5-pq3.

fix various typos in comment, documentation and log messages.

Added SPI register definitions.

Preliminary support for P1023.

branches: 1.14.2; 1.14.16;
Add ESDHC DCR definitions

Add P1025 support to the PCI truth tables.
P1025 only has two PCIe ports, not 3.

The ETSEC on the P1025 has been moved/split so the MDIO stayed in the same
place but each ETSEC has been split into two virtual halves (G0 and G1) and
each one has a new different base address.
For some reason, tsec1 connects to phy 2 and tsec2 connects to phy 1.
Adjust config file to match

Add support for the Freescale TWR-P1025 evaluation board and the P1025/P1016
QorIQ processors. XXX tsec isn't working yet on the TWR-P1025.

branches: 1.10.2;
Add some more DDR register definitions

Add LSOR register

Correct definitions of USB_SNOOP registers. Add USB_CONTROL register.

branches: 1.7.2;
Add Boot Page PTR Register definitions.

Add LBC FCM defintions (for NAND).

Fix various nits related to P2020 support.

branches: 1.4.2;
Add USB_SNOOP1/2 related definitions

Add some P2020 / MPC856x definitions.

branches: 1.2.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4;
file e500reg.h was initially added on branch matt-nb5-pq3.

Style and cosmetic changes. No binary changes intended.

e500_cpunode_submatch() should be declared regardless of _KERNEL_OPT.

Make the 85xx get closer to spinning up the secondary CPUs.
Don't assume TLB1[0] has the mapping for VA/PA 0.
Make sure the TLB1 entries that map physical memory have the M (memory
coherent) bit set.

branches: 1.6.2;
Fix -fno-common fallout.

Add e500_tlb_minimize prototype.

branches: 1.4.2; 1.4.6; 1.4.8;
Add some e500 MP prototypes.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.2.4; 1.2.6;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4;
file e500var.h was initially added on branch matt-nb5-pq3.

s/UCP/UDP/ in comments.

branches: 1.11.2;
s/Transmi /Transmit / in comments.

fix various typos in comments.

fix various typos in comments, messages and documentation.

Added some register definitions for multi-queue.

fix offset value of RBASEn.

Added Interrupt coalescing support.

branches: 1.5.2; 1.5.16;
The ETSEC on the P1025 has been moved/split so the MDIO stayed in the same
place but each ETSEC has been split into two virtual halves (G0 and G1) and
each one has a new different base address.
For some reason, tsec1 connects to phy 2 and tsec2 connects to phy 1.
Adjust config file to match

Preserve some MACCFG2 bits

branches: 1.3.2; 1.3.6; 1.3.8;
Fix ATTR register definitions

branches: 1.2.4; 1.2.6;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4;
file etsecreg.h was initially added on branch matt-nb5-pq3.

PR port-powerpc/56922

__HAVE_FAST_SOFTINTS is broken for powerpc.
Disable it temporarily also for booke.

cpu_need_resched():

- Remove all code that should be MI, leaving the bare minimum under arch/.
- Make the required actions very explicit.
- Pass in LWP pointer for convenience.
- When a trap is required on another CPU, have the IPI set it locally.
- Expunge cpu_did_resched().

branches: 1.11.2;
s/static inline/static __inline/g for consistency.

branches: 1.10.14;
Added MSI/MSI-X and interrupt_distribute(9) support for powerpc.

branches: 1.9.2;
ddb MP support

branches: 1.8.4;
Implement MI IPI interface with cross-call support.

branches: 1.7.2;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

branches: 1.6.2; 1.6.12; 1.6.16;
forward declare cpu_info and trapframe.

Add IST_PULSE and intr_typename (converts IST_* to a name).

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.3.2;
Add IPI/cpu_send_ipi to intrsw.

branches: 1.2.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8; 1.1.10;
Change booke_intr.h to intr.h since <powerpc/booke/intr.h> will be unique
enough.

branches: 1.2.2;
Add prototypes for lbc_* routines.

branches: 1.1.2; 1.1.6;
Move obio softc definitions to a header so it can use by children of obio.

Preliminary support for P1023.

branches: 1.6.2; 1.6.16;
Add support for the Freescale TWR-P1025 evaluation board and the P1025/P1016
QorIQ processors. XXX tsec isn't working yet on the TWR-P1025.

branches: 1.5.2;
MPC8544 don't any onchip irqs of 20/21

Fix P20x0_ONCHIPBITMAP to reflect latest P2020RM.

Add MPC8555/41, MPC8568/67, and P2020 variations.

branches: 1.2.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8; 1.1.10;
OpenPIC register defintions used by e500 booke.

#define<space> -> #define<tab> for consistency

Support __HAVE_PMAP_PV_TRACK in sys/uvm/pmap based pmaps (aka common pmap)

branches: 1.23.2;
Provide a pmap_segtab_deactivate for symmetry with pmap_segtab_activate
and use it in pmap_deactivate

Call pmap_md_xtab_{,de}activate from pmap_segtab_{,de}activate to be used
for PMAP_HWPAGEWALKER and any caches ops that might be required.

Provide empty (for now) pmap_md_xtab_{,de}activate functions on the
platforms that use sys/uvm/pmap

Style and cosmetic changes. No binary changes intended.

Simplify #ifdefs

If we're going to consult the MULTIPROCESSOR option, we should pull in
"opt_multiprocessor.h".

With DEBUG defined, it's possible to execute a TLB-vs-segmap consistency
check from a (soft) interrupt handler. But if a platform does not otherwise
require the pmap_tlb_miss_lock, then where will be a brief window of
inconsistency that, while harmless, will still fire an assertion in the
consistency check.

Fix this with the following changes:
1- Refactor the pmap_tlb_miss_lock into MI code and rename it from
pmap_tlb_miss_lock_{enter,exit}() to pmap_tlb_miss_lock_{enter,exit}().
MD code can still define the "md" hooks as necessary, and if so, will
override the common implementation.
2- Provde a pmap_bootstrap_common() function to perform common pmap bootstrap
operations, namely initializing the pmap_tlb_miss_lock if it's needed.
If MD code overrides the implementation, it's responsible for initializing
its own lock.
3- Call pmap_bootstrap_common() from the mips, powerpc booke, and riscv
pmap_bootstrap() routines. (This required adding one for riscv.)
4- Switch powerpc booke to the common pmap_tlb_miss_lock.
5- Enable pmap_tlb_miss_lock if DEBUG is defined, even if it's not otherwise
required.

PR port-mips/55062 (Failed assertion in pmap_md_tlb_check_entry())

branches: 1.18.2;
s/static inline/static __inline/g for consistency.

branches: 1.17.14;
Tell mpc85xx about uvm_hotplug(9)

Should fix the evbppc build breakage.

branches: 1.16.2;
Adapt to common pmap changes.

Avoid race condition between PTE update and TLB miss walk.

branches: 1.14.6;
Add PMAP_TLB_FLUSH_ASID_ON_RESET define

Merge riastradh-drm2 to HEAD.

kcpuset_t changes for the pmap and removal of __cpuset_t

branches: 1.11.2; 1.11.8;
move common tlb stuff to uvm

branches: 1.10.2;
Use pmap_segtab_t

Add vsize_t to pmap_md_{un,}map_poolpage.
Add pmap_kvptefill prototype.
Slightly change pmap_bootstrap prototype.

branches: 1.8.2; 1.8.6; 1.8.8;
Modify mapiodev to take a third argument indicating whether the space
should be prefetchable (true) or not (false).

Move some MD parts back to the booke pmap.c. Cleanup initialization a bit.

PowerPC now exports a common view of cpu.h, vmparam.h and pmap.h
when building a MODULAR kernel or compiling _MODULE.
It should be noted that MODULAR or _MODULE export a view of the kernel
as being MULTIPROCESSOR (even if isn't).
The shared pmap TLB uses mdpg in places where it used mdpg to avoid
deadly embrance inclusion problems.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.4.2; 1.4.4;
Use _PMAP_PRIVATE to control the inclusion of <powerpc/booke/cpuvar.h>.
This prevents most of the MI files from depending on it.

BookE needs PMAP_NEEDS_PROCWR (for ptrace breakpoints)

branches: 1.2.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4;
file pmap.h was initially added on branch matt-nb5-pq3.

Remove pte_zero_p and simply check against 0.

s/static inline/static __inline/g for consistency.

branches: 1.9.4;
Provide a pte_set

Adapt to common pmap changes.

Add PRIxPTE and pte_value(pt_entry_t) for printing the value of a PTE.
Add pte_zero_p(pt_entry_t) to check that a PTE has been zeroed.

branches: 1.6.12; 1.6.30;
Modify mapiodev to take a third argument indicating whether the space
should be prefetchable (true) or not (false).

Redo how the pte_*wire* inlines work. Now pmap.c makes no assuming about
what type pt_entry_t. It can now be a scalar or a union/struct.

Switch to using the common <common/pmap/tlb/tlb.h>

PowerPC now exports a common view of cpu.h, vmparam.h and pmap.h
when building a MODULAR kernel or compiling _MODULE.
It should be noted that MODULAR or _MODULE export a view of the kernel
as being MULTIPROCESSOR (even if isn't).
The shared pmap TLB uses mdpg in places where it used mdpg to avoid
deadly embrance inclusion problems.

branches: 1.2.4;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8; 1.1.10;
Add initial versions of these for BookE.

s/seach/search/

Fix various typos in comments. Also add missing NetBSD RCS Id in some of these files.

Added MMUv2 define.

Added P1023/P1017.

branches: 1.11.2; 1.11.16;
Fix some copy&paste bugs.

Add some more PVRs and SVRs

Add support for the Freescale TWR-P1025 evaluation board and the P1025/P1016
QorIQ processors. XXX tsec isn't working yet on the TWR-P1025.

Add some e500mc/e5500 machines.

branches: 1.7.2;
Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.6.2;
Add some P10xx SVRs

Add MPC8533 SVR. Fix DBCR0 IAC bits

Add more MPC85xx SVRs.
Fix/add debug register definitions.

branches: 1.3.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.2.2; 1.2.4; 1.2.6;
Fix some TCR definitions.

branches: 1.1.2; 1.1.4;
Add initial versions of these for BookE.

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8; 1.1.10;
Add initial versions of these for BookE.

Add missing double p and d for stopped and overriden accordingly.
Fix few more typos along the way, mainly in copy-pasted comments.

Sync MAXfoo params with oea:

MAXTSIZ: 512MB -> 128MB
MAXDSIZ: 3.25GB -> 1GB

There should be no particular reasons for having different values.

PR port-powerpc/56107

Decrease MAXSSIZ from ~256MB to 32MB (same as oea).

This fixes tests in /usr/tests/usr.bin/make, that run with "ulimit -v 200000",
fail with "Cannot map anonymous memory".

Although I'm not fully convinced whether this limit is reasonable or not,
old MAXSSIZ of ~256MB is too much anyway.

branches: 1.7.52;
move common tlb stuff to uvm

branches: 1.6.2;
Allow the use of the full 4GB address space.

branches: 1.5.2;
PowerPC now exports a common view of cpu.h, vmparam.h and pmap.h
when building a MODULAR kernel or compiling _MODULE.
It should be noted that MODULAR or _MODULE export a view of the kernel
as being MULTIPROCESSOR (even if isn't).
The shared pmap TLB uses mdpg in places where it used mdpg to avoid
deadly embrance inclusion problems.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.3.4;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.2.2; 1.2.4;
Remove incomplete, never worked dynamic run-time memory registration
(uvm_page_physload(9)). This functionality will be re-added later.

branches: 1.1.2; 1.1.4; 1.1.6;
Add initial versions of these for BookE.