Split <powerpc/spr.h> into a common <powerpc/spr.h> and <powerpc/XXX/spr.h>
where XXX is ibm4xx or oea.

branches: 1.1.108; 1.1.128; 1.1.132;
Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

Include missing opt_ppcarch.h.

Style and cosmetic changes. No binary changes intended.

make sure struct bat is aligned to 8 bytes as we shift them 3 bits.

fixes PReP lossage as reported on port-powerpc and port-prep.
thanks to makoto@ki.nu and kiyohara@netbsd.

branches: 1.17.6; 1.17.20;
make BATs >256MB work, now macppc works again on 745x CPUs as well
ok riz

When making BATU, use (BAT_XBL|BAT_BL) for the extended bat lengths.

Enable XBSEN and HIGHBAT for OEA 7455 and related CPUs.
The BAT entries now have a resolution of 8MB. (Adjacent entries are merged
up to a total of 2GB per entry).

branches: 1.14.2; 1.14.6;
Include <powerpc/psl.h>

branches: 1.13.10;
protect C constructs from assembler source inclusion.

branches: 1.12.22;
Remove clause 3 and 4 from TNF licenses

branches: 1.11.2; 1.11.4;
Add BAT_VA2IDX to abstract out the va to index calculation.

Add BAT_WIMG and some XBL aware BAT_BL_{512,1G,2G,4G} macros.

branches: 1.9.2; 1.9.6;
Rewrite a big chunk of the pmap and locore code for powerpc to better
deal with the 64bit bridge mode. pmap changes by Matt Thomas, rest by myself.

Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel. This allows the pmap for bridge64 to
co-exist with the 32bit pmap.

Yank __HAVE_PMAP_PHYSSEG from all the oea code.

Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features. This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.

Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in. Some of it seemed incorrect, and my 7044 booted just fine
without it. It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.

In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].

With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu. However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE. Work remains to be done there to fix that.

branches: 1.8.34; 1.8.40;
1st cut of Powermac G5 support (uses bridge mode).

branches: 1.7.4; 1.7.8;
merge ktrace-lwp.

branches: 1.6.8;
Add extended BAT block size definitions.

branches: 1.5.2; 1.5.10;
Add _LOCORE protection.

Add oea_iobat_remove(paddr_t).

Make _LP64 friendly.

Make things a bit more LP64 friendly.

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

Split cpu_model_init() into cpu_features_probe() and cpu_features_enable()
so that early bootstrap can do those two steps independently, if needed.

Continue to provide a cpu_model_init() wrapper for now.

branches: 1.5.14;
provide a wrapper for mapiodev() - if we have BATs just use the paddr, if
we don't then actually map it

branches: 1.4.86;
Remove clause 3 and 4 from TNF licenses

branches: 1.3.2; 1.3.4; 1.3.6;
Add a XBSEN flag for large BATs

branches: 1.2.2; 1.2.4; 1.2.8;
Add multiple inclusion protection.
add oeacpufeat.

branches: 1.1.2;
Rewrite a big chunk of the pmap and locore code for powerpc to better
deal with the 64bit bridge mode. pmap changes by Matt Thomas, rest by myself.

Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel. This allows the pmap for bridge64 to
co-exist with the 32bit pmap.

Yank __HAVE_PMAP_PHYSSEG from all the oea code.

Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features. This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.

Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in. Some of it seemed incorrect, and my 7044 booted just fine
without it. It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.

In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].

With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu. However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE. Work remains to be done there to fix that.

powerpc/hid: fix snprintb format for HID0_970_BITMASK_U

fix comments: HID0 ICFI/DCFI are "flash invalidate", not "flush invalidate"

branches: 1.13.20;
Include missing opt_ppcarch.h.

add a few pp970-specific bits

add bits & masks for ppc970 HID0

branches: 1.10.6;
Define HID1_{SYNCBE,ABE} for the 7450

branches: 1.9.32; 1.9.42; 1.9.48;
Better call it HID0_BTCD, as in prep, mvmeppc and rs6000 locore.

Added HID0[BTAC] bit for the 604.

branches: 1.7.74; 1.7.76; 1.7.78; 1.7.80;
merge ktrace-lwp.

Add some HID1 definitions and HID0_XBSEN for 7455+ processors.

Correct BHTCLR/XAEN definitions.

branches: 1.4.2;
enable powersave mode on 7450 and family.
also, the HID0_DOZE bit in this context doesn't mean "doze",
it's actually "enable extra BATs". add an alias for this bit
and use it as appropriate.

Uppercase CPU, plural is CPUs.

branches: 1.2.2;
Add 7450 LRSTK and FOLD bits.

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

Remove clause 3 and 4 from TNF licenses

branches: 1.1.104; 1.1.106; 1.1.108;
Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

powerpc: oea: For OEA64_BRIDGE, 1:1 map up to 3GiB memory

As done for OEA. Note that kva over 3GiB is reserved.

Provide PMAP_MAP_POOLPAGE for OEA64_BRIDGE at the same time, by
which direct-mapped memory is utilized in order to work around
starvation of 512MiB kernel virtual space.

PR kern/57621

Trailing whitespace.

branches: 1.37.4;
Try to fix PV tracking support.

* For oea (with real PV tracking support):

Define __HAVE_PMAP_PV_TRACK. Otherwise, pmap_pv_init() is not called by
uvm_init().

* For booke and ibm4xx (without PV tracking support):

For MODULAR kernel and modules, define __HAVE_PMAP_PV_TRACK together with
PMAP_PV_TRACK_ONLY_STUBS, so that modules can be shared with oea.

Note that PMAP_PV_TRACK_ONLY_STUBS can be used even for oea,
as a compile-time option to strip real PV tracking support.

powerpc: Implement pv-tracking for unmanaged pages.

Needed for drm.

Re-factor the code in pmap_extract() that checks the 601 I/O segment
table and the BAT tables into separate functions that can be called
from outside of the pmap module.

Complete the pmap symbol renaming shenanigans for pmap_bootstrap[12]().

Split pmap_bootstrap() into 2 functions:
- pmap_bootstrap1(), which sets up the low-level pmap data structures.
- pmap_bootstrap2(), which actually programs the MMU hardware based on
pmap_bootstrap1()'s work.

pmap_bootstrap() is still provided as a wrapper around the two, but this
provides flexibility to platforms that might need to do additional work
between these two phases.

branches: 1.32.2;
Include missing opt_modular.h so that struct vm_page_md is compatible to
that for booke.

LKM was gone.

pmap_remove_all(): Return a boolean value to indicate the behaviour. If
true, all mappings have been removed, the pmap is totally cleared out, and
UVM can then avoid doing the work to call pmap_remove() for each map entry.
If false, either nothing has been done, or some helpful arch-specific voodoo
has taken place.

branches: 1.29.2;
s/static inline/static __inline/g for consistency.

branches: 1.28.28;
Add pmap_ste_spill

branches: 1.27.2; 1.27.4;
Fix -fno-common fallout.

branches: 1.26.2;
Modify *ASSERTMSG() so they are now used as variadic macros. The main goal
is to provide routines that do as KASSERT(9) says: append a message
to the panic format string when the assertion triggers, with optional
arguments.

Fix call sites to reflect the new definition.

Discussed on tech-kern@. See
http://mail-index.netbsd.org/tech-kern/2011/09/07/msg011427.html

Modify mapiodev to take a third argument indicating whether the space
should be prefetchable (true) or not (false).

PowerPC now exports a common view of cpu.h, vmparam.h and pmap.h
when building a MODULAR kernel or compiling _MODULE.
It should be noted that MODULAR or _MODULE export a view of the kernel
as being MULTIPROCESSOR (even if isn't).
The shared pmap TLB uses mdpg in places where it used mdpg to avoid
deadly embrance inclusion problems.

Add #error for unknown PPC variant
Now that oea calls cpu_fixup_stubs, we don't need pmap_fixup_stubs.

branches: 1.22.2;
implement pmap_mmap_flags() and teach PowerPC's bus_space_mmap() to actually
use BUS_SPACE_MAP_PREFETCHABLE which, now that /dev/pci* knows how to use it,
helps improve X performance

When an OEA kernel is configured for multiple MMU types, use the new
powerpc fixup mechanism to bind the kernel to a particular MMU. This
avoids an indirect call for every pmap call.

branches: 1.20.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.19.2;
Move struct vm_page_md definition from vmparam.h to pmap.h, because
it's used only by pmap. vmparam.h has definitions for wider
audience.

All GENERIC kernels build tested, except ia64.

powerpc/include/booke/vmparam.h has one too, but it has no pmap.h,
so it's left as is.

branches: 1.18.4;
Add a flags argument to pmap_kenter_pa(9).
Patch showed on tech-kern@ http://mail-index.netbsd.org/tech-kern/2009/11/04/msg006434.html
No objections.

Remove uarea swap-out functionality:

- Addresses the issue described in PR/38828.
- Some simplification in threading and sleepq subsystems.
- Eliminates pmap_collect() and, as a side note, allows pmap optimisations.
- Eliminates XS_CTL_DATA_ONSTACK in scsipi code.
- Avoids few scans on LWP list and thus potentially long holds of proc_lock.
- Cuts ~1.5k lines of code. Reduces amd64 kernel size by ~4k.
- Removes __SWAP_BROKEN cases.

Tested on x86, mips, acorn32 (thanks <mpumford>) and partly tested on
acorn26 (thanks to <bjh21>).

Discussed on <tech-kern>, reviewed by <ad>.

change pmap flags argument from int to u_int.
discussed with christos@ on source-changes-d@

branches: 1.15.2;
Wrap #include "opt_ppcarch.h" in #ifdef _KERNEL_OPT, to allow
lib/librump to build for evbppc.

Make pmap_kernel() a MI macro for struct pmap *kernel_pmap_ptr,
which is now the "API" provided by the pmap module. pmap_kernel()
remains as the syntactic sugar.

Bonus cosmetics round: move all the pmap_t pointer typedefs into
uvm_pmap.h.

Thanks to Greg Oster for providing cpu muscle for doing test builds.

branches: 1.13.6; 1.13.10; 1.13.16; 1.13.18; 1.13.30;
Cleanup/simplify #if/#endif

Rewrite a big chunk of the pmap and locore code for powerpc to better
deal with the 64bit bridge mode. pmap changes by Matt Thomas, rest by myself.

Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel. This allows the pmap for bridge64 to
co-exist with the 32bit pmap.

Yank __HAVE_PMAP_PHYSSEG from all the oea code.

Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features. This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.

Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in. Some of it seemed incorrect, and my 7044 booted just fine
without it. It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.

In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].

With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu. However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE. Work remains to be done there to fix that.

When compiling in bridge mode, add a prototype for pmap_setup_segment0_map()

branches: 1.10.22; 1.10.28; 1.10.34;
Replace the Mach-derived boolean_t type with the C99 bool type. A
future commit will replace use of TRUE and FALSE with true and false.

branches: 1.9.10;
1st cut of Powermac G5 support (uses bridge mode).

branches: 1.8.4; 1.8.8;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.6.16;
More PPC64 changes. (latent for now).

add support for non-executable mappings (where the hardware allows this)
and make the stack and heap non-executable by default. the changes
fall into two basic catagories:

- pmap and trap-handler changes. these are all MD:
= alpha: we already track per-page execute permission with the (software)
PG_EXEC bit, so just have the trap handler pay attention to it.
= i386: use a new GDT segment for %cs for processes that have no
executable mappings above a certain threshold (currently the
bottom of the stack). track per-page execute permission with
the last unused PTE bit.
= powerpc/ibm4xx: just use the hardware exec bit.
= powerpc/oea: we already track per-page exec bits, but the hardware only
implements non-exec mappings at the segment level. so track the
number of executable mappings in each segment and turn on the no-exec
segment bit iff the count is 0. adjust the trap handler to deal.
= sparc (sun4m): fix our use of the hardware protection bits.
fix the trap handler to recognize text faults.
= sparc64: split the existing unified TSB into data and instruction TSBs,
and only load TTEs into the appropriate TSB(s) for the permissions.
fix the trap handler to check for execute permission.
= not yet implemented: amd64, hppa, sh5

- changes in all the emulations that put a signal trampoline on the stack.
instead, we now put the trampoline into a uvm_aobj and map that into
the process separately.

originally from openbsd, adapted for netbsd by me.

branches: 1.4.2;
Add POOL_VTOPHYS. Change vtophys to return -1 if pmap_extract fails.
(callers of vtophys should always supply a valid VA so that
pmap_extract should never fail).

Make lint happy.

Make things a bit more LP64 friendly.

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

Fix comments. No binary changes.

Rewrite a big chunk of the pmap and locore code for powerpc to better
deal with the 64bit bridge mode. pmap changes by Matt Thomas, rest by myself.

Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel. This allows the pmap for bridge64 to
co-exist with the 32bit pmap.

Yank __HAVE_PMAP_PHYSSEG from all the oea code.

Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features. This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.

Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in. Some of it seemed incorrect, and my 7044 booted just fine
without it. It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.

In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].

With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu. However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE. Work remains to be done there to fix that.

branches: 1.8.34; 1.8.40;
1st cut of Powermac G5 support (uses bridge mode).

branches: 1.7.4; 1.7.8;
Fix typo inside PPC_OEA64

merge ktrace-lwp.

branches: 1.5.16;
More PPC64 changes. (latent for now).

Add PowerPC64 definitions

add support for non-executable mappings (where the hardware allows this)
and make the stack and heap non-executable by default. the changes
fall into two basic catagories:

- pmap and trap-handler changes. these are all MD:
= alpha: we already track per-page execute permission with the (software)
PG_EXEC bit, so just have the trap handler pay attention to it.
= i386: use a new GDT segment for %cs for processes that have no
executable mappings above a certain threshold (currently the
bottom of the stack). track per-page execute permission with
the last unused PTE bit.
= powerpc/ibm4xx: just use the hardware exec bit.
= powerpc/oea: we already track per-page exec bits, but the hardware only
implements non-exec mappings at the segment level. so track the
number of executable mappings in each segment and turn on the no-exec
segment bit iff the count is 0. adjust the trap handler to deal.
= sparc (sun4m): fix our use of the hardware protection bits.
fix the trap handler to recognize text faults.
= sparc64: split the existing unified TSB into data and instruction TSBs,
and only load TTEs into the appropriate TSB(s) for the permissions.
fix the trap handler to check for execute permission.
= not yet implemented: amd64, hppa, sh5

- changes in all the emulations that put a signal trampoline on the stack.
instead, we now put the trampoline into a uvm_aobj and map that into
the process separately.

originally from openbsd, adapted for netbsd by me.

branches: 1.2.2;
Make things a bit more LP64 friendly.

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

Include missing opt_ppcarch.h.

add functions to access SCOM registers on 970 CPUs

add Hardware Interrupt Offset Register found on 970

branches: 1.4.2;
add a few pp970-specific bits

add instruction cache throttling SPR found on 750

branches: 1.2.6; 1.2.24;
Enable XBSEN and HIGHBAT for OEA 7455 and related CPUs.
The BAT entries now have a resolution of 8MB. (Adjacent entries are merged
up to a total of 2GB per entry).

branches: 1.1.2; 1.1.6; 1.1.8; 1.1.16; 1.1.20;
Split <powerpc/spr.h> into a common <powerpc/spr.h> and <powerpc/XXX/spr.h>
where XXX is ibm4xx or oea.

Rather than putting it on the caller, just let oea_iobat_add() decide
whether to call mpc601_ioseg_add().

branches: 1.5.100;
Remove clause 3 and 4 from TNF licenses

branches: 1.4.34; 1.4.36; 1.4.38;
Make the SR601_VALID_P check less draconic wrt valid io segregs. There
are perfectly valid iosegregs for which the old test would fail.

branches: 1.3.26; 1.3.30; 1.3.32;
merge ktrace-lwp.

branches: 1.2.12;
Add some BAT-style predicate macros.

branches: 1.1.2; 1.1.6;
Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

bump MAXTSIZ
now clang runs again

Add missing double p and d for stopped and overriden accordingly.
Fix few more typos along the way, mainly in copy-pasted comments.

Adjust TABs. No functional changes.

branches: 1.20.18;
Raise the maximum text size value to 128MB, this allows binaries such as clang which
currently has a text area of around 96MB to execute successfully on macppc.

ok macallan

branches: 1.19.6;
G/C VM_MAX_KERNEL_BUF

branches: 1.18.6; 1.18.10; 1.18.14;
Make this 64-bit aware.

branches: 1.17.2; 1.17.12; 1.17.16;
PowerPC now exports a common view of cpu.h, vmparam.h and pmap.h
when building a MODULAR kernel or compiling _MODULE.
It should be noted that MODULAR or _MODULE export a view of the kernel
as being MULTIPROCESSOR (even if isn't).
The shared pmap TLB uses mdpg in places where it used mdpg to avoid
deadly embrance inclusion problems.

branches: 1.16.6;
Move struct vm_page_md definition from vmparam.h to pmap.h, because
it's used only by pmap. vmparam.h has definitions for wider
audience.

All GENERIC kernels build tested, except ia64.

powerpc/include/booke/vmparam.h has one too, but it has no pmap.h,
so it's left as is.

Remove incomplete, never worked dynamic run-time memory registration
(uvm_page_physload(9)). This functionality will be re-added later.

branches: 1.14.2; 1.14.4;
Remove SHMMAXPGS from all kernel configs. Dynamically compute the
initial limit as 1/4 of the physical memory. Ensure the limit is at
least 1024 pages, the old default on most platforms.

branches: 1.13.8; 1.13.14;
Remove clause 3 and 4 from TNF licenses

branches: 1.12.6; 1.12.8; 1.12.10;
Rewrite a big chunk of the pmap and locore code for powerpc to better
deal with the 64bit bridge mode. pmap changes by Matt Thomas, rest by myself.

Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel. This allows the pmap for bridge64 to
co-exist with the 32bit pmap.

Yank __HAVE_PMAP_PHYSSEG from all the oea code.

Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features. This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.

Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in. Some of it seemed incorrect, and my 7044 booted just fine
without it. It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.

In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].

With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu. However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE. Work remains to be done there to fix that.

bump the default data size to 256MB (i.e. double it) because compiling
gcc during a standard native system build doesn't pass with 128MB.

branches: 1.10.28; 1.10.34; 1.10.42;
Define a PHYSMAP_VSID for mapping pa==va.

branches: 1.9.4; 1.9.6;
1st cut of Powermac G5 support (uses bridge mode).

branches: 1.8.10; 1.8.22; 1.8.26;
Now that countless UVM bugs have been fixed, enable "topdown" memory
allocation by default.

More PPC64 changes. (latent for now).

branches: 1.6.2;
Make PAGE_SIZE, PAGE_SHIFT, and PAGE_MASK compile-time constants for
PowerPC processors.

#include opt_uvm.h in machine/vmparam.h (for those ports offering the
topdown option) so that including it directly before including
uvm/uvm_param.h (or uvm/uvm_extern.h which includes uvm/uvm_param.h)
and attempting to use topdown won't result in a compiler error.

Problem noted in private email.

Add TOPDOWN VM support.

Allow KERNEL_SR/KERNEL2_SR to be overriden (I run a kernel with
the mapped space at 0x8000000-0x9fffffff).

Make LP64 friendly.

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).