don't do anything in vec_restore_from_mcontext() if no altivec.

fixes a crash seen on netbsd-10 in PR#58283.

XXX: pullup-10.

branches: 1.34.4;
- In vec_restore_from_mcontext() and vec_save_to_mcontext(), allows the
mcontext argument to be NULL.
- In sendsig_sigcontext(), don't set PSL_VEC in the saved MSR; we can't
actually round-trip the AltiVec registers. At least get them saved
into the PCB by calling vec_save_to_mcontext() (with a NULL mcontext
argument).
- In compat_16_sys___sigreturn14(), call vec_restore_from_mcontext()
with a NULL mcontext argument, which will force any subsequent use
of AltiVec to re-load the AltiVec registers from the PCB.

This isn't ideal, but it's the best we can do with the limited capability
of sigcontext.

Fixes PR port-powerpc/56471.

Drop unused opt_multiprocessor.h includes.

Style and cosmetic changes. No binary changes intended.

allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.

branches: 1.30.2; 1.30.4;
Don't reload if just re-enabling

branches: 1.29.2; 1.29.4;
pcu(9):
- Remove PCU_KERNEL (hi matt!) and significantly simplify the code.
This experimental feature was tried on ARM did not meet the expectations.
It may be revived one day, but it should be done in a much simpler way.
- Add a message structure for xcall function, pass the LWP ower and thus
optimise a race condition: if LWP is discarding its state on a remote CPU,
but another LWP already did it - do not cause an unecessary re-faulting.
- Reduce the variety of flags for PCU operations (only PCU_VALID and
PCU_REENABLE are used now), pass them only to the pcu_state_load().
- Rename pcu_used_p() to pcu_valid_p(); hopefully it is less confusing.
- pcu_save_all_on_cpu: SPL ought to be used here.
- Update and improve the pcu(9) man page; it needs wizd(8) though.

branches: 1.28.2;
Get rid of MDLWP_USED{FPU,VEC}

-extend the pcu(9) API by a function which saves all context on the
current CPU, and use it if a CPU is taken offline
-add a bool argument to pcu_discard which tells whether the internal
"LWP has used the coprocessor" flag should be set or reset. The flag
is reported by pcu_used_p(). If set, future accesses should use the
state stored in the PCB. If reset, it should be reset to default.
The former case is useful for setmcontext().
With that, it should not be necessary anymore to manage the "FPU used"
state by an additional MD variable.

approved by matt

branches: 1.26.2;
Update to new pcu_state_{load,state,release} definitions

branches: 1.25.2; 1.25.8; 1.25.12;
zero PCU area when loading used area.

branches: 1.24.2;
Set PSL_VEC in the right place.

Make sure to enable the vector unit in the PSL when returning to userland.

Move powerpc to use pcu to manage FPU/AltiVec/SPE.

Powerpc send_ipi use ci_cpuid, not cpu_index

Clear ownership bit after saving contents to PCB.

branches: 1.19.2;
Fix some fallout from building the macppc GENERIC.MP.

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.17.2;
Retire struct user, remove sys/user.h inclusions. Note sys/user.h header
as obsolete. Remove USER_TO_UAREA/UAREA_TO_USER macros.

Various #include fixes and review by matt@.

branches: 1.16.2;
Adapt to spr.h breakup.

branches: 1.15.2;
Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.

branches: 1.14.4; 1.14.6; 1.14.26;
SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.

branches: 1.13.16;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.12.6; 1.12.14; 1.12.22; 1.12.24; 1.12.26; 1.12.28;
Merge newlock2 to head.

branches: 1.11.20;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.9.2;
Rewrite the inner loop of vcopypage() and vzeropage() to be entirely
in inline asm and include turning the DMMU off and back on. This
prevents the compiler (especially gcc -O0) from inserting accesses to
locations in virtual address space when such accesses would fail.

Don't clear PCB_FPU/PCB_ALTIVEC when releasing the FPU/AltiVec unit. Add
new flags to indicate whether the PCB currently owns the FPU/AltiVec unit.

branches: 1.7.4; 1.7.6;
Add a SAVE/DISCARD flag to save_{fpu,vec}_lwp. Use it appropriately.
Nuke struct fpu and use struct fpreg instead (except for the names, they
were identical). On MP machines, this will avoid an unneeded IPI to save
the register contents that are about to discarded.

Revamp how user MSR/SRR1 are dealt with.
Add a PSL_USEROK_P(psl) macro which valids the bits (replaces the use of
PSL_USERSTATIC).
Add a PSL_USERSRR1 mask which is used to mask out status bits in the upper
half of SRR1.
Make sure PSL_VEC is set appropriately in userret(). PSL_VEC is in the same
region as SSR1 status bits so it's not preserved on exceptions. Thus we
need to make to set it.
When returning a MSR/SRR1 to userland, always clear the status bits.
Add emulation of the mfpvr, mtmsr, and mfmsr instructions.

__KERNEL_RCSID()

branches: 1.4.2;
Make sure to include opt_foo.h if a defflag option FOO is used.

Use PAGE_SIZE rather than NBPG.

Make AltiVec registers available via ptrace/procfs. Simplify AltiVec
processing. Add a "common" procfs_machdep.c for PowerPC platforms.
Even though it is supposed to be port specific, most (if not all)
PowerPC ports can just use the common one.

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

Style and cosmetic changes. No binary changes intended.

branches: 1.2.4; 1.2.8;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2;
file altivec_subr.S was initially added on branch matt-nb5-pq3.

Drop unused opt_ppcparam.h.

Style and cosmetic changes. No binary changes intended.

branches: 1.1.2;
add clock speed control for 970MP CPUs

powerpc: Identify Broadway CPU.

Use hex to report Broadway revision and ignore TAU as it does not exist
on this processor.

Use console_debbuger() or DDB guards for Debugger() and db_stack_trace_print().

Should allow to build these files without DDB enabled option.

branches: 1.109.2;
powerpc: oea: Decode IBM750CL L2 cache information.

branches: 1.108.16;
Fix copy-paste.

branches: 1.107.2;
Split cpu_model_init() into cpu_features_probe() and cpu_features_enable()
so that early bootstrap can do those two steps independently, if needed.

Continue to provide a cpu_model_init() wrapper for now.

Declare oeacpufeat once, in powerpc/oea/cpu_subr.c, rather than in
N different locore.S files.

Add a provision for a per-cpu battable. Each CPU starts with the global
one, but this allows CPUs to temporarily switch to an alternate battable
if needed.

branches: 1.104.2;
Include missing opt_ppcarch.h.

Style and cosmetic changes. No binary changes intended.

register the IPI before spinning up CPUs, and make sure to do it exactly once
with this, and previous commits, G5s with four CPUs work
tested by Romain Dolbeau

don't enable NAP mode on 7450 CPUs - my Quicksilver has two of those and we
hang hard shortly after boot with NAP enabled, even on UP kernels

first step to address PR54331:
poll h->hatch_running for a bit instead of blindly relying on a fixed timeout
for secondary CPUs to wake up and get ready

needs more testing, possibly pullup

- add or adjust fallthru comments

Only execute dssall when the CPU has the Altivec instruction set extension.

branches: 1.97.2;
Fix fmttab value for L2CR_L2PE (parity enabled) so that we don't print
self-contradictory "no parity parity enabled".

when switching CPU speed using DFS, only use xcalls on MULTIPROCESSOR kernels

add clock speed control for 970MP CPUs

copy HID1 from the boot CPU to secondary CPUs as well on 64bit CPUs
now the 2nd CPU on my G5s runs at full speed

save & restore HID4 and HID5, zero SPR_HIOR on 970

fix build for 32bit non-bridge SMP kernels

first step towards G5 SMP:
- only save/restore BATs on CPUs that have them
- treat HID0 as 64bit on 64bit CPUs

branches: 1.90.2;
avoid 32 bit only code in 64 bit mode.

use mtspr64() in bridge mode

fix ofppc/pegasosII (and maybe others).

don't assume PPC_OEA64_BRIDGE means we have a 64 bit cpu (code
for 64 bit in bridge and normal 32 bit can co-exist due to
fixups the early boot code does has, and ofppc builds GENERIC
this way):
- fix mtmsr()/mfmsr() to use the right method based upon the
actually cpu booted on.
- fix cpu_setup() to have 32 bit and 64 bit hid0 variables
and operate on the right one based upon the current cpu.
restore a minor optimisation of not writing hid0 if it
didn't change.

in set_timebase() check if OF_finddevice("/cpus/@0") failed
and returned -1 before using it for OF_getprop().

fix a few typos in comments

use 7450 HID0 bitmask on 7447A and 7448 as well

inline HAVE_64BIT_HID0 and remove macro definition.

Fixes llvm INSTALL kernel build, which failed with:
error: macro expansion producing 'defined' has undefined behavior

remove accidential debug printf()

deal with ppc970's HID0

branches: 1.82.6;
use cpu_{g,s}etmodel

remove various set-but-unused variables.

- remove set but unused variables
- move some variables inside their relevant use #ifdef

Fix c&p bug.

Disable XBSEN for the 7450.

Make sure ABE/SYNCBE are enabled in HID1 for the 7450 CPUs
Enable XBSEN for the 7450.

branches: 1.76.2;
Support Cache Protocol 'MEI' with MULTIPROCESSOR.

Fix broken cpu_hatch_stack.
And define macro HATCH_STACK_SIZE.

Remove white-spaces. And remove unused 'extern void tlbia()'.

branches: 1.73.6;
Use kmem instead of malloc. Remove unneeded <sys/malloc.h> includes.

Enable XBSEN and HIGHBAT for OEA 7455 and related CPUs.
The BAT entries now have a resolution of 8MB. (Adjacent entries are merged
up to a total of 2GB per entry).

Insert some missing aprint_naive().

branches: 1.70.2; 1.70.6;
Cleanup hatch names.
Add cpuset_info.

Reap the ci_ev_soft* evcnts since every variant implements __HAVE_FAST_SOFTINTS

Initialize sensor state before registering.

<arch/powerpc/... -> <powerpc/...

struct device * -> device_t
struct cfdata * -> cfdata_t
split device/softc (CFATTACH_DECL_NEW)
use device_accessors and device_private
constify

Make sure to set curlwp (aka r13) in cpu_hatch

Use mtsprg0 instead of mtsprg 0,r

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.62.2;
Add support for the IBM750GX (from Bob Lee).

branches: 1.61.2;
Fix some fallout from building the macppc GENERIC.MP.

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.59.2;
Machine dependent code is considered as part of UVM. Include
internal API header.

Only read from HID1 when a G3 CPU was detected in cpu_get_dfs(), otherwise
the access might cause a PGM trap.

Use nap mode on 750-ish CPUs

Support sysctl machdep.cpu_speed for 7447A and 7448 based Macs. On those
machines the CPU's DFS (Dynamic Frequency Switching) feature is used instead
of a GPIO to control the speed.
Two new functions in powerpc/oea/cpu_subr.c were introduced to support
reading and writing of DFS: cpu_get_dfs() and cpu_set_dfs(). Also works
for multiple CPUs, but not before interrupts are enabled.

branches: 1.55.2;
Adapt to spr.h breakup.

branches: 1.54.2;
Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.

Ansify function definitions w/o arguments. Generated with sed.

Change about 4500 of the K&R function definitions to ANSI ones.
There are still about 1600 left, but they have ',' or /* ... */
in the actual variable definitions - which my awk script doesn't handle.
There are also many that need () -> (void).
(The script does handle misordered arguments.)

branches: 1.51.2;
replace bitmask_snprintf(9) with snprintb(3)

branches: 1.50.2; 1.50.14;
Some fixes to the TAU support code:
- set the ADC time according to clock speed, not some magic number
- move some mtspr()s which we really only need to do once
- make our envsys_data_t static, this should fix PR 39411

in cpu_hatch(), set PIR when the current value is not what we need
rather than only when it's zero.

properly 'probe' the MPC7400's L1 caches - before we'd fall through to
setting both to PAGE_SIZE

branches: 1.47.4;
add IBM970MP (used in the last model of powermac G5).

branches: 1.46.2; 1.46.4; 1.46.6;
SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.

Detect HIGHBAT/XBSEN/HIGHSPRG to MPC74[45]x where x > 1
Enable above as appropriate.

branches: 1.44.2; 1.44.6;
Some powerpc cleanup. Remove unneeded/bad usage of extern oeacpufeat.
Convert asm code to use %r register format. Done by comparison to
disassembled output, double checked with diff of dissasembled output
before and after, and test booted on my 7044.

Replace as much of the hardcoded CACHELINESIZE with
curcpu()->ci_ci.dcache_line_size as I can. With this change, an ofppc kernel
compiled with both PPC_OEA and PPC_OEA64_BRIDGE defined, boots.

Rewrite a big chunk of the pmap and locore code for powerpc to better
deal with the 64bit bridge mode. pmap changes by Matt Thomas, rest by myself.

Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel. This allows the pmap for bridge64 to
co-exist with the 32bit pmap.

Yank __HAVE_PMAP_PHYSSEG from all the oea code.

Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features. This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.

Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in. Some of it seemed incorrect, and my 7044 booted just fine
without it. It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.

In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].

With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu. However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE. Work remains to be done there to fix that.

Add support to ofppc for the IBM 7044-270 machine. This is a POWER3-II
based machine. Currently the kernel to run on this machine is
incompatible with the standard GENERIC kernel, so for now, we have a
separate GENERIC_B64. Eventually, I hope to combine the two.

Please note, this is a port of 32bit ofppc, not a powerpc64 port.

Thanks to Matt Thomas and Kevin Bowling for helping to make this port
possible.

Summary of changes:

Change ofwpci to use the ofmethod config for configuring the PCI bus,
rather than indirect configuration.
Move the wiring of the interrupt controllers from at the start of the
boot, into the configuration of the first PCI bus.
Rewrite the map_isa_ioregs() hack to work on a machine without BATs
Fix a ton of bugs in the genofw_find_pics routine, and in the map_space code.
Split the pic_openpic into openpic_common and pic_openpic.
Create a new pic_distopenpic driver, for the distributed openpic found on
some newer IBM machines.
Fix a bad panic in pmap_extract on 64bit bridge mode

On the 745x cpu, you have to invalidate cache slightly differently than
you do on the other cpus. Add an if statement that takes this into account.

'never try to fix more than one thing at once, especially if one is a crash'
backout bogus G4 CPU revision 'fix'

Remove a superfluous /* FALLTHROUGH */
Also switch back to waiting for L2CR_L2IP in cpu_enable_l2cr() - now my 2nd
G4 spins up again.

Fix a logic botch when setting up L3 cache - don't attempt to do so on CPUs
that can't have L3 cache. While there also fix revision reporting for MPC7400
so what we report matches MacOS X.

Lots and lots of fixes to the cpu identification code, and dealing with
L2 and L3 cache initialization. Mostly to get the L2 enabled on the
pegasos, but since I had the manual, I fixed a few other things I saw
while I was there.

branches: 1.35.6;
Initialize sensor's state
on behalf of xtraeme

Extend the envsys2 API (one more time, sorry) as defined in:

http://mail-index.netbsd.org/tech-kern/2007/11/09/0001.html

sysmon_envsys_create() and sysmon_envsys_destroy() were added to
create/destroy sysmon_envsys objects (and its TAILQ/LIST for sensors/events).

sysmon_envsys_sensor_attach() and sysmon_envsys_sensor_detach() were
added to attach/detach sensors to a specified sysmon_envsys device.

The events framework is now per device and configurable via the
ENVSYS_SETDICTIONARY ioctl or /etc/envsys.conf and envstat(8).

Update all users and documentation to reflect these changes.

branches: 1.33.2;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.32.8; 1.32.10; 1.32.12; 1.32.14;
Imported envsys 2, a brief description of the new features:
(Part 2: drivers)

* Support for detachable sensors.
* Cleaned up the API for simplicity and efficiency.
* Ability to send capacity/critical/warning events to powerd(8).
* Adapted all the code to the new locking order.
* Compatibility with the old envsys API: the ENVSYS_GTREINFO
and ENVSYS_GTREDATA ioctl(2)s are supported.
* Added support for a 'dictionary based communication channel' between
sysmon_power(9) and powerd(8), that means there is no 32 bytes event
size restriction anymore.
* Binary compatibility with old envstat(8) and powerd(8) via COMPAT_40.
* All drivers with the n^2 gtredata bug were fixed, PR kern/36226.

Tested by:

blymn: smsc(4).
bouyer: ipmi(4), mfi(4).
kefren: ug(4).
njoly: viaenv(4), adt7463.c.
riz: owtemp(4).
xtraeme: acpiacad(4), acpibat(4), acpitz(4), aiboost(4), it(4), lm(4).

Recognize the Freescale G2 cores: initialize cache line size, and doze mode
While there, fix the way the major version of a PowerPC processor is computed

- add MPC8245 to cpuname table.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.28.4; 1.28.8; 1.28.10; 1.28.16;
Make these files compile with -Wextra -Wno-unused.

branches: 1.27.4; 1.27.6;
1st cut of Powermac G5 support (uses bridge mode).

branches: 1.26.4; 1.26.8;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.24.2;
Fix shadowing and cast qualification warnings.

Keep track of the CPU's current speed (in kHz) in the cpu info structure,
if we can get it. May want to expand this in the future to include min
and max speeds for systems where we can adjust the speed.

branches: 1.22.2;
Add more support for MPC7447A/MPC7448.

Add entry for MPC7447A

Split the hw-dependent powermanglement into its own function and make
Idle call that. Add a ci_idlespin function pointer to cpu_info.
Update INIT_CPUINFO to initialize it to a naked 'blr' instruction.
In oea/cpu_subr.c, add cpu_idlespin and make ci_idlespin point to it.

branches: 1.19.2;
enable powersave mode on 7450 and family.
also, the HID0_DOZE bit in this context doesn't mean "doze",
it's actually "enable extra BATs". add an alias for this bit
and use it as appropriate.

Allow MSR[POW] off for power saving on 604-era CPUs. From Tim Kelly.
XXX -- needs benchmarking

Don't attempt to probe the cache with l2cr on 604ev. From Tim Kelly.

Add MPC7400 to the list of CPUs for which we try to measure the speed.
Noticed missing by Tim Kelly.

Minor (old) patch from me to correct CPU ID of 604e vs. 604ev.
Tested by Tim Kelly.
Also patched from Tim to
- Delay longer for second CPU spinup.
- Only attempt to print CPU speed and cache configuration on certain
CPU types.

On OEA, turn PSL_USER* into runtime values appropriate for the CPU model
we're executing on; besides dealing with the bits not implemented in the
601's MSR it also removes the silent failure behaviour when passing
PSL_VEC set on a CPU not implementing it.

Also, fix those masks for the 4xx again.

PR/24741: Aymeric Vincent: Variable sme_flags isn't initialized to zero

Don't waste space on likely unused sysmon structure.
Instead malloc them as needed.

Add support for MPC74[45]7

Make that OEA based kernels can properly deal with kernel ISI faults. Now
that LKMs are supported, it is possible for a LKM page to be "outspilled"
resulting in a possible ISI fault. Try to spill the page back in.

__KERNEL_RCSID()

branches: 1.8.2;
Re-read L2CR after enabling the L2 cache to avoid returning without
printing the cache details.

Rework l2cr/l3cr enabling/printing code. Make printing table driven.

Use PAGE_SIZE rather than NBPG.

Make sure to turn on the speed knobs in HID0 on the 745x.

s;backside;; and report L2CR_L2DO & L2CR_L2IO

Use aprint_normal. Print 2MB L2 sizes with 7410.

Added L3CR_CONFIG for support of 745x G4 L3 cache configuration.

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

Add a provision for a per-cpu battable. Each CPU starts with the global
one, but this allows CPUs to temporarily switch to an alternate battable
if needed.

branches: 1.28.2;
Style and cosmetic changes. No binary changes intended.

Retire ipkdb entirely. The option was removed from the config files
yesterday.

ok kamil christos

branches: 1.26.46; 1.26.48;
Enable XBSEN and HIGHBAT for OEA 7455 and related CPUs.
The BAT entries now have a resolution of 8MB. (Adjacent entries are merged
up to a total of 2GB per entry).

branches: 1.25.2; 1.25.6;
Don't include *pmap.h in assembly files. Get the needed definitions
from "assym.h".

Make struct cpu_info the same size if building MODULAR
kernels or compiling a module.

Make a common genassym.cf (powerpc/genassym.cf) and then
only put specific stuff in foo/genassym.cf

Add IPL_HIGH and IPL_SCHED so locore.S can use them.

ifdef / define / endif can't be the first thing. So move that block down.

Make __HAVE_FAST_SOFTINTS appear in assym.h so all oeas don't need to include
<powerpc/intr.h>
XXX <powerpc/intr.h> should be <powerpc/oea/intr.h>

enable FAST_SOFTINTR support for all ports that use powerpc/pic/
This has been successfully tested on macppc
TODO:
- ibm4xx needs to be adapted
- SMP doesn't work yet, 2nd CPU crashes when trying to leave the idle loop

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.17.4;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.16.2;
fix copy{in,out}{,str}() to return the error returned by uvm_fault().
fixes PR 41813.

branches: 1.15.2; 1.15.4;
Rename L_ADDR to L_PCB and amend some comments accordingly.

branches: 1.14.4; 1.14.26;
Add MTX_* and RW_* definitions

branches: 1.13.2; 1.13.6;
Rewrite a big chunk of the pmap and locore code for powerpc to better
deal with the 64bit bridge mode. pmap changes by Matt Thomas, rest by myself.

Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel. This allows the pmap for bridge64 to
co-exist with the 32bit pmap.

Yank __HAVE_PMAP_PHYSSEG from all the oea code.

Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features. This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.

Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in. Some of it seemed incorrect, and my 7044 booted just fine
without it. It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.

In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].

With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu. However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE. Work remains to be done there to fix that.

branches: 1.12.2;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.11.10;
Fix for yamt-idlelwp merge.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.9.26; 1.9.30; 1.9.32; 1.9.38;
merge ktrace-lwp.

branches: 1.8.8;
Split the hw-dependent powermanglement into its own function and make
Idle call that. Add a ci_idlespin function pointer to cpu_info.
Update INIT_CPUINFO to initialize it to a naked 'blr' instruction.
In oea/cpu_subr.c, add cpu_idlespin and make ci_idlespin point to it.

branches: 1.7.8;
Restore ci_curpm since it re-enables 603 to working state.

Move SFRAMELEN to frame.h and use it in vm_machdep.c. In setfunc, setup
callframe linkages correctly. Restore use of ldptr to locore_subr.S
[pthreads and gdb no longer crash/hang the system]

Cleanup/rework cpu_switch*, switch_exit, Idle routine. Remove pcb_psl
since it was write-only. When setting up a process, make sure the fake
callframes are properly linked together.

Only lower SPL when in Idle loop. Raise spl to previous level (which would
be IPL_SCHED) when exiting Idle loop. Never lower SPL anyplace else.

Nuke ci_curpm and curpm. Nuke pcb_pmreal. Those were use for spill stacks
and those no longer exist. for few uses that need CURPM, use CURPCB/PCB_PM

Nuke ci_spillstk/CI_SPILLSTK. No longer needed.

Add CPUSAVE_* and each register in the saveframe and faultbuf.

branches: 1.1.2;
Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

Ansify function definitions w/o arguments. Generated with sed.

branches: 1.2.2; 1.2.4; 1.2.8; 1.2.26; 1.2.34; 1.2.40;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.1.2; 1.1.6; 1.1.8; 1.1.10;
file kgdb_glue.c was initially added on branch ppcoea-renovation.

powerpc: oea: Fix prefetchable mappings

Prefetchable mappings need PMAP_NOCACHE to get write-combine semantics.

branches: 1.84.4;
fix typos in comments.

s/specificed/specified/ in comment.

Rather than putting it on the caller, just let oea_iobat_add() decide
whether to call mpc601_ioseg_add().

branches: 1.81.2;
Drop unused opt_compat_netbsd.h include.

Style and cosmetic changes. No binary changes intended.

uvm_availmem(): give it a boolean argument to specify whether a recent
cached value will do, or if the very latest total must be fetched. It can
be called thousands of times a second and fetching the totals impacts not
only the calling LWP but other CPUs doing unrelated activity in the VM
system.

Rename uvm_free() -> uvm_availmem().

uvmexp.free -> uvm_free()

- add or adjust fallthru comments

Retire ipkdb entirely. The option was removed from the config files
yesterday.

ok kamil christos

branches: 1.74.2; 1.74.4;
introduce a inline function to set a value to zero while
hiding this fact from GCC. this allows the PPC code that
writes to address zero to actually work rather than cause
GCC to emit an explicit "trap" instruction, which in early
boot means hang on my pegasosII. use this in oae_init()
for both rfid->rfi and also setting the jump-to-zero trap.

found with a lot of debugging, but GCC 6's new warning
-Wnull-dereference found it when i was informed of its
existence. unfortunately, there are dozens of other
violations in our kernel today so simply enabling that
option for everything is not a good idea, but is a goal.

allocate cpuset structures needed by MP DDB.

Don't preserve PSL_FP/PSL_VEC in cpu_setmcontext.

branches: 1.71.4; 1.71.6;
use cpu_{g,s}etmodel

support ppc601
from scole_mail, ok matt@

Use more appropriate type.

- remove set but unused variables
- move some variables inside their relevant use #ifdef

convert rfid to rfi in exception handlers.

Move the pmap_setup to the start oea_init (no non-OFW ports can use it).
If PPC_OEA64_BRIDGE is defined, add code so that when OEACPU_64_BRIDGE is not
present, it replaces the rfid with rfi and mfmsr/rldicl/mtmsrd sequence
with NOPs. This allows plain OEA kernels to work. (tested on PMPPC with
PPC_OEA64_BRIDGE option added).

When trying to write into page 0, use volatile to force the compiler to
actually create this access.

branches: 1.64.2; 1.64.4;
Allow use of large (>256MB) bats for iobats. If XBSEN isn't present, they
will be "downsized" into multiple 256MB bats. Tested by riz.

branches: 1.63.2;
fix crash during early startup - we can't call OpenFirmware between zapping
the BATs and complete setting them up again
ok releng

Use kmem instead of malloc. Remove unneeded <sys/malloc.h> includes.

Enable XBSEN and HIGHBAT for OEA 7455 and related CPUs.
The BAT entries now have a resolution of 8MB. (Adjacent entries are merged
up to a total of 2GB per entry).

branches: 1.60.2; 1.60.6;
Retire varargs.h support. Move machine/stdarg.h logic into MI
sys/stdarg.h and expect compiler to provide proper builtins, defaulting
to the GCC interface. lint still has a special fallback.
Reduce abuse of _BSD_VA_LIST_ by defining __va_list by default and
derive va_list as required by standards.

Modify mapiodev to take a third argument indicating whether the space
should be prefetchable (true) or not (false).

Cleanup includes. (<net/netisr.h> is handled by softints, not MD anymore,
so this can be nuked).

Call cpu_fixup_stubs at the end of oea_machdep

branches: 1.56.4;
Fix some fallout from building the macppc GENERIC.MP.

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.54.2;
Retire struct user, remove sys/user.h inclusions. Note sys/user.h header
as obsolete. Remove USER_TO_UAREA/UAREA_TO_USER macros.

Various #include fixes and review by matt@.

branches: 1.53.2;
Adapt to spr.h breakup.

Remove separate mb_map. The nmbclusters is computed at boot time based
on the amount of physical memory and limited by NMBCLUSTERS if present.
Architectures without direct mapping also limit it based on the kmem_map
size, which is used as backing store. On i386 and ARM, the maximum KVA
used for mbuf clusters is limited to 64MB by default.

The old default limits and limits based on GATEWAY have been removed.
key_registered_sb_max is hard-wired to a value derived from 2048
clusters.

branches: 1.51.2;
- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

Kill proc0paddr. Use lwp0.l_addr instead.

Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.

Add a flags argument to pmap_kenter_pa(9).
Patch showed on tech-kern@ http://mail-index.netbsd.org/tech-kern/2009/11/04/msg006434.html
No objections.

MSGBUFADDR creates a msgbuf at a fixed address, usually defined by the port's
config file.
The use of MSGBUGADDR was already prepared in powerpc/oea/pmap.c years ago,
but was never used and missing powerpc/oea/oea_machdep.c. The option will
be used by port amigappc.

branches: 1.46.18;
Replce exec_map with a pool. Proposed on tech-kern@, reviewed by chs@.

branches: 1.45.2;
Make oea_init() support systems with high-vector configurations (i.e exception
vectors at 0xfff00000), and trap_subr.S allows the kernel to be in a memory
region which is not reachable by absolute branch instructions (ba and bla).

High-vector support can be enabled by option PPC_HIGH_VEC, and long-branches
to the kernel are enabled by the option DISTANT_KERNEL.

branches: 1.44.6; 1.44.8; 1.44.10; 1.44.12;
Some powerpc cleanup. Remove unneeded/bad usage of extern oeacpufeat.
Convert asm code to use %r register format. Done by comparison to
disassembled output, double checked with diff of dissasembled output
before and after, and test booted on my 7044.

Code to disable BAT use on cpu's that either don't have BAT's, or don't
gain any benefit from them. This nets a small speedup on the POWER3, and
is probably needed for POWER5, which might not emulate BATs like the 3 does.
Also, thanks to Matt Thomas, who suggested re-using alitrap rather than
writing a new dsinobattrap that would have looked remarkably identical
when finished.

Cleanup a few 601 ifdefs.

Some minor cleanup in the PPC_OEA601 code, and a fix for bridge-mode
cpus, which apparently still need the non-601 code to zap various
instructions into nops.

Ifdef out all the MPC601 code with PPC_OEA601. Now only arches that have the
possibility of running on an MPC601, are infected with all the extra code
and nops that it added.

Also, fix compilation that I broke with the pmap code, by adding
oeacpufeat to the locores of various ppc arches. Noted by mlelstv.

Apparently BRIDGE mode allows BAT registers, so re-enable that code.
Change the pegasos PCI_NETBSD_CONFIGURE arguments around to wire up mem
space into the correct area, and move the io regs a little to make it
work properly. Just avoid the secondary PCI entirely.
Change the list of things that we fiddle with in pci_conf_hook. Map mem
on the fwohci, avoid display cards, avoid IO on the auvia.
Change some printf's to aprint_*
Yank a call to genppc_pci_indirect_make_tag and change it to the
bus-independant pci call instead. (in pci_conf_hook)

Make this compile when compiling in bridge mode w/o ALTIVEC

branches: 1.37.6;
Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

branches: 1.36.2;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.35.8; 1.35.10; 1.35.12; 1.35.14;
Generic soft interrupts are mandatory.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.33.2; 1.33.4; 1.33.10;
make this compile again

Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

TRUE -> true, FALSE -> false

branches: 1.30.2;
Merge newlock2 to head.

Remove debug printf

branches: 1.28.2; 1.28.4;
* move the "cheating" conditional into unmapiodev() implementation
itself (instead of memio_unmap()), as it differs between OEA and
ibm4xx.

OK by matt@

Add unmapiodev(vaddr_t, vsize_t) (to be used by bus_space_unmap)

1st cut of Powermac G5 support (uses bridge mode).

undef memset before calling it with a destination address of 0.
GCC4.1 complains about this when using the builtin, so force
this to call the real function normally.

branches: 1.24.4; 1.24.6; 1.24.8; 1.24.14;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.22.2;
Fix variable shadowing warnings by renaming the innermost variables.

Move the MI printing of `copyright' to the MD cpu_startup() code
where the printing of `version' is already performed.
This has the benefit of allowing the copyright to be available
via dmesg(8) on platforms which need the `msgbuf' to be setup
in cpu_startup() before printed output is remembered.

merge yamt-km branch.
- don't use managed mappings/backing objects for wired memory allocations.
save some resources like pv_entry. also fix (most of) PR/27030.
- simplify kernel memory management API.
- simplify pmap bootstrap of some ports.
- some related cleanups.

branches: 1.19.4; 1.19.6;
On OEA, turn PSL_USER* into runtime values appropriate for the CPU model
we're executing on; besides dealing with the bits not implemented in the
601's MSR it also removes the silent failure behaviour when passing
PSL_VEC set on a CPU not implementing it.

Also, fix those masks for the 4xx again.

On MPC601s, rewrite any (unimplemented) tlbsync instruction as a sync.

Get rid of the silly CPU601 hooks and move BAT register restoration and
obliteration to RESTORE_{KERN,USER}_SRS, respectively; have oea_init()
patch these sequences to be skipped on non-MPC601s. The code sequence
matching heuristic isn't as pretty as the one for VRSAVE and MQ but works
well enough with the current structure of the trap code, and can be easily
updated when necessary.

Remove softintr__init call.

branches: 1.15.2;
Add latent generic soft interrupt initialization.

Typo typo.

Replace the traditional buffer memory management -- based on fixed per buffer
virtual memory reservation and a private pool of memory pages -- by a scheme
based on memory pools.

This allows better utilization of memory because buffers can now be allocated
with a granularity finer than the system's native page size (useful for
filesystems with e.g. 1k or 2k fragment sizes). It also avoids fragmentation
of virtual to physical memory mappings (due to the former fixed virtual
address reservation) resulting in better utilization of MMU resources on some
platforms. Finally, the scheme is more flexible by allowing run-time decisions
on the amount of memory to be used for buffers.

On the other hand, the effectiveness of the LRU queue for buffer recycling
may be somewhat reduced compared to the traditional method since, due to the
nature of the pool based memory allocation, the actual least recently used
buffer may release its memory to a pool different from the one needed by a
newly allocated buffer. However, this effect will kick in only if the
system is under memory pressure.

Restore ci_curpm since it re-enables 603 to working state.

Nuke ci_curpm and curpm. Nuke pcb_pmreal. Those were use for spill stacks
and those no longer exist. for few uses that need CURPM, use CURPCB/PCB_PM

Nuke ci_spillstk/CI_SPILLSTK. No longer needed.

__KERNEL_RCSID()

branches: 1.8.2;
Use PAGE_SIZE rather than NBPG.

Allow oea_batinit to be called with either the MMU on or off.
(don't reset the BATs if the MMU is off).

Add LINTSTUBs and make oea_init() agree with them.

Make AltiVec registers available via ptrace/procfs. Simplify AltiVec
processing. Add a "common" procfs_machdep.c for PowerPC platforms.
Even though it is supposed to be port specific, most (if not all)
PowerPC ports can just use the common one.

Don't try to reserve DEAD zone unless the kernel address space encompasses it.

Add oea_iobat_remove(paddr_t).

Make things a bit more LP64 friendly.

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

in order to check for NWSDISPLAY we need to #include "wsdisplay.h"...

No longer need to copy "local-mac-address" and "shared-pins" into
the properties dictionary; they can be queried from the device tree
directly now.

Give each PowerPC OFW platform its own device_register(), which calls
into the common ofw_device_register(). ofppc's is a simple wrapper.

macppc's, on the other hand, takes care of looking up environmental
sensor descriptive information in the OFW device tree and adds those
properties directly to the sensor device property dictionaries. This
single implementation will replace the duplicated code that's scattered
across multiple macppc i2c controller drivers.

add ifdef NWSDISPLAY > 0 around rascons_* functions usage,
otherwise implementation is not available, which breaks macppc MAMBO config.

potentially better solution to provide empty implementation, comments welcome.

if we have the ROM font, make it available to wsdisplay
needs testing on non-macppc

Add a hack for qemu/macppc. OF_finddevice calls will crash depending on
the boot loader and kernel being used. This patch allows using
-prom-env qemu_boot_hack=y to disable the lookup.

branches: 1.23.4;
don't bother reading ofw properties for platinumfb

parse G5 device paths

branches: 1.21.2; 1.21.4;
detect if we netboot and set booted_device accordingly

branches: 1.20.22;
when looking for SCSI disks in canonicalize_bootpath() also match 'disk@'
since that's what at least some Adaptec firmware uses

branches: 1.19.2;
move console_node and console_instance to ofw_consinit.c where they're
actually used

some macppc boxes have onboard devices where parts or the whole PCI interrupt
register is hardwired to zero - fix this up here

branches: 1.17.2;
Do not call setroot() from MD code and from MI code, which has
unwanted sideeffects in the RB_ASKNAME case. This fixes PR/46732.

No longer wrap MD cpu_rootconf(), as hp300 port stores reboot information
as a side effect. Instead call MI rootconf() from MD code which makes
rootconf() now a wrapper to setroot().

Adjust several MD routines to set the global booted_device,booted_partition
variables instead of passing partial information to setroot().

Make cpu_rootconf(9) describe the calling order.

copy properties for valkyriefb as well

branches: 1.15.2; 1.15.6; 1.15.8;
Retire varargs.h support. Move machine/stdarg.h logic into MI
sys/stdarg.h and expect compiler to provide proper builtins, defaulting
to the GCC interface. lint still has a special fallback.
Reduce abuse of _BSD_VA_LIST_ by defining __va_list by default and
derive va_list as required by standards.

#include <sys/bus.h> instead of <machine/bus.h>.

struct device * -> device_t
struct cfdata * -> cfdata_t
split device/softc (CFATTACH_DECL_NEW)
use device_accessors and device_private
constify

branches: 1.12.6;
Support MV64361 on PegasosII by gt(4).
+ Support gtpci@gt instead of pegasospci more smartly.
+ Support Gigabit Ethernet by mvgbe@gt.

branches: 1.11.2; 1.11.4;
pass some OF properties as device properties for network devices
namely local-mac-address and shared-pins needed by gem

Ansify function definitions w/o arguments. Generated with sed.

Change about 4500 of the K&R function definitions to ANSI ones.
There are still about 1600 left, but they have ',' or /* ... */
in the actual variable definitions - which my awk script doesn't handle.
There are also many that need () -> (void).
(The script does handle misordered arguments.)

branches: 1.8.2; 1.8.8;
recognize ATY,DDparent as display device so the rest of the code can find
the nodes for each individual display

branches: 1.7.6; 1.7.10; 1.7.12; 1.7.16;
several changes to make boot device work for disks, at least
on my pegasos:

- don't chop off the 2nd part of the OFW address, it makes it
match pcib (ISA bridge - dev 12 fn 0) instead of viaide (dev 12
fn 1).
- now that it's available, provide an "addr2" that has the
second address present.
- for pci devices match against device and function, not just
function.
- remove the special case and actually broken check in the
"pciide" section, and use the now generic "addr2" and check
against the drive and channel number if provided.
- support "viaide" and "slide" in here, as well as "pciide".
(is there a good way to say "any ide adapter"?)

probe as console devices which have a "class-code" property corresponding to
PCI_CLASS_DISPLAY, and not just those which have a "display" device_type.
In the case where each head is a subnode of the graphics card, it's the heads
which have a "display" device_type.

Maybe only testing "class-code" would make sense if this property is defined
on any openfirmware based PowerPC platform.

branches: 1.5.2;
At least under certain (mis)configurations (e.g. on the "Pegasos" board)
the VT8231-IDE's native mode only works with irq 14/15, and cannot be
programmed to use a single native PCI irq alone. So we install an interrupt
handler for each channel, as in compatibility mode.
This behaviour has to be activated by the "use-compat-native-irq" property,
otherwise the driver works as before.

branches: 1.4.2; 1.4.4; 1.4.8;
repeat after me: I will not test OF nodes for validity by checking for >0
since node numbers may well have 0x80000000 set

Apply a set of patches from Frank Wille to make the genfb attachment work
better on ofppc. In doing so, we also move a few functions around in
macppc and the generic ofw powerpc stuff to allow better sharing of code.
Also, introduce a model_init function.

move ofb_cons.c from macppc/dev to powerpc/oea and rename it to rascons.
This gets rid of some naming confusion, and makes it OFW-MI rather than
macppc specific.

branches: 1.2.2; 1.2.4; 1.2.6; 1.2.8;
Convert macppc to shared ofw_autoconf.c. Compile tested only.

Create a new ofw_autoconf.c based almost entirely on the one from macppc.

convert more seriously early output to ofprint
regular console output needs more of the kernel in working order now, and this
stuff happ0ens long before the banner

move ofprint() to powerpc/ofw_machdep.c and make it official
now that console output uses locks it needs more of the kernel to function, so
for now use direct OF calls for earliest debug output

PR port-macppc/56091: on G5 macs we currently can not easily make
early serial console work, so keep the OF based "failsafe" console
but note that we would like to switch over.
Once zs attaches, use the new device mapping and do a belated init
of the zs console globals, and then switch over to real zs based
serial console.

Separate probing for the console device and initializing it, so that
ofwoea_initppc() can have more control over which of those steps are
performed during initialization. Probing happens before setting up
the exception vectors, initializing happens after.

Fix the previously differently.

Avoid an unused variable warning for the not-building-macppc case.

Revert unintended change.

Shuffle around a couple of things that aren't particularly OEA-specific:

- Early bootstrap console initialization moves to ofw_machdep.c, and
is called a bit earlier, from ofw_bootstrap().

- Decoding the "translations" property from /chosen/mmu is specified
in the general OpenFirmware PowerPC bindings, and is not specific to
any particular PowerPC flavor. It's now decoded a bit earlier in
ofw_bootstrap().

The *interpretation* of the mode field of a translation is, however,
implementation-specific, so that remains in ofwoea_machdep.c.

branches: 1.19.2;
Style and cosmetic changes. No binary changes intended.

When boot up with auto-boot? == true, some systems do not provide stdout
if the normal output is screen.

Open screen explicitly as stdout in this case, both for ofwboot and kernel,
which fixes problems with auto-boot? == true for Mac mini G4:

- messages from ofwboot do not appear
- kernel freeze during early boot stage

Taken from OpenBSD:
http://cvsweb.openbsd.org/cgi-bin/cvsweb/src/sys/arch/macppc/macppc/ofw_machdep.c#rev1.3
http://cvsweb.openbsd.org/cgi-bin/cvsweb/src/sys/arch/macppc/stand/Locore.c#rev1.3

XXX
pullup to netbsd-9 and -8

branches: 1.17.10; 1.17.18; 1.17.22; 1.17.28;
Add missing va_end, from David Binderman in PR 50798.

branches: 1.16.10;
move console_node and console_instance to ofw_consinit.c where they're
actually used

fix compile problems (for POWERMAC_G5).

Adapt to the changed signature of pckbc_cnattach().

branches: 1.13.2; 1.13.12;
Retire varargs.h support. Move machine/stdarg.h logic into MI
sys/stdarg.h and expect compiler to provide proper builtins, defaulting
to the GCC interface. lint still has a special fallback.
Reduce abuse of _BSD_VA_LIST_ by defining __va_list by default and
derive va_list as required by standards.

#include <sys/bus.h> instead of <machine/bus.h>.

prop/proplib.h is indirectly used here, include it.

XXX What is the conclusion about direct vs. indirect #include from headers?

branches: 1.10.2;
Fix isa(4) support for ofw.
ofw not initialized bus_space for isa(4).
It tested on ofppc(PegasosII).

Remove white-spaces.

branches: 1.8.14;
If we have to guess wether the console keyboard is USB or ADB check if the
PMU actually has ADB support.

branches: 1.7.2; 1.7.6;
Remove clause 3 and 4 from TNF licenses

branches: 1.6.14; 1.6.16; 1.6.18;
Apply a set of patches from Frank Wille to make the genfb attachment work
better on ofppc. In doing so, we also move a few functions around in
macppc and the generic ofw powerpc stuff to allow better sharing of code.
Also, introduce a model_init function.

move ofb_cons.c from macppc/dev to powerpc/oea and rename it to rascons.
This gets rid of some naming confusion, and makes it OFW-MI rather than
macppc specific.

unbork the initial console for macppc
ofb_cnattach() has nothing to do with ofb (anymore) - it's simply a dumb
rasops console we use until a real wsdisplay driver attaches, therefore
it needs to be #if NWSDISPLAY > 0, not NOFB > 0
Should probably be renamed to avoid future confusion.

branches: 1.4.2; 1.4.4;
Lots of small changes for ofppc:

Remove the ofb driver. I'm not interested in trying to make this work.
It should be replaced with the genfb driver, which I have added,
commented out because that driver needs work before it will function on
ofppc. (it's too panic-happy, and ofppc needs a working autoconf.c)

Change the way we do isa_inb/outb. The new way is a slightly nastier
hack, but won't run afoul of the other isa drivers as much.

Fix ofw_consinit.c to remove the dependency on ofb.

Get rid of the ofppc use of the ofbus completely, for the last time.

Write a complete OF boot console into ofw_consinit.c and rewire a bunch
of the ifdef logic in that file to use it when appropriate on both macppc
and ofppc. Get rid of the attempt to wire up the serial console early,
as that is extremely difficult on ofppc. Yank all the console code out
of ofppc/machdep.c. (This is a boot console only, not a full blown
console like ofcons.c)

Delete all the ofbus references out of the config files, and pull in
dev/ofw/openfirmio.c and dev/ofw/ofw_subr.c directly rather than pulling
in files.ofw. It might be worth going back and adding a files.ofw-nobus
to that directory to allow pulling in the openfirmware driver without
pulling in the whole ofbus mess.

Change rtas driver to connect directly to mainbus, like the PCI bus nodes do.

branches: 1.2.2; 1.2.4;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.1.2; 1.1.6; 1.1.8; 1.1.10;
file ofw_consinit.c was initially added on branch ppcoea-renovation.

fix multiplei repetitive typos in comments, messages and documentation. mainly because copy paste code big amount of files are affected.

rascons_init_rasops(): Initialize color palette only for macppc.
Fix build failure for ofppc.

It turned out that using some Open Firmware routines causes the system
freeze after calling OF_quiesce().

This is why setting color palette crash the system for some Power Mac G5
models, like PowerMac11,2.

Therefore, stop using color-palette and backlight callbacks for genfb(4)
in this case.

Also, postpone OF_quiesce() after rascons_init_rasops(), and initialize
color palette there if OF is going to be quiesced and color depth is 8.

Now, color palette for wscons is initialized correctly for PowerMac11,2.

Fix boot failure for PowerMac11,2 when ``auto-boot?'' is true.

For some machines like PowerMac11,2, Open Firmware does not correctly
initialize console-related variables, like font-adr and line#, when
``auto-boot?'' is true; -1 is returned instead of correct values.

Fall back to wsfont embedded in kernel in this case. Also, do not use
line# if it is negative.

make the ROM font usable on G5s:
- copy the font data into a buffer instead of just pointing at the ROM
- don't blindly assume the font's width
- don't try to center output ourselves - rasops_init() will do it for us
- provide a hook to add the ROM font to wsfont when we're ready

Rename min/max -> uimin/uimax for better honesty.

These functions are defined on unsigned int. The generic name
min/max should not silently truncate to 32 bits on 64-bit systems.
This is purely a name change -- no functional change intended.

HOWEVER! Some subsystems have

#define min(a, b) ((a) < (b) ? (a) : (b))
#define max(a, b) ((a) > (b) ? (a) : (b))

even though our standard name for that is MIN/MAX. Although these
may invite multiple evaluation bugs, these do _not_ cause integer
truncation.

To avoid `fixing' these cases, I first changed the name in libkern,
and then compile-tested every file where min/max occurred in order to
confirm that it failed -- and thus confirm that nothing shadowed
min/max -- before changing it.

I have left a handful of bootloaders that are too annoying to
compile-test, and some dead code:

cobalt ews4800mips hp300 hppa ia64 luna68k vax
acorn32/if_ie.c (not included in any kernels)
macppc/if_gm.c (superseded by gem(4))

It should be easy to fix the fallout once identified -- this way of
doing things fails safe, and the goal here, after all, is to _avoid_
silent integer truncations, not introduce them.

Maybe one day we can reintroduce min/max as type-generic things that
never silently truncate. But we should avoid doing that for a while,
so that existing code has a chance to be detected by the compiler for
conversion to uimin/uimax without changing the semantics until we can
properly audit it all. (Who knows, maybe in some cases integer
truncation is actually intended!)

branches: 1.12.2; 1.12.4;
add a comment to explain why we defer wsdisplay_preattach() in bridge mode

defer scribbling into video memory until after re-enabling the MMU if
we're in bridge mode.
With this NetBSD boots on PCI-X G5s

Remove OFB_ENABLE_CACHE
from <macallan>
"it is outdated, genfb and friends don't need or use it, and it makes no sense
on accelerated drivers either. It tries to BAT-map the framebuffer cacheable,
which works on most macs but makes a few models lock up. Genfb doesn't have that
problem and is faster too."

branches: 1.9.28;
for some reason we can't use the ROM font on G5, so disable it with
options OFWOEA_WSCONS_NO_ROM_FONT
from Phileas Fogg

branches: 1.8.6;
Use kmem instead of malloc. Remove unneeded <sys/malloc.h> includes.

Enable XBSEN and HIGHBAT for OEA 7455 and related CPUs.
The BAT entries now have a resolution of 8MB. (Adjacent entries are merged
up to a total of 2GB per entry).

branches: 1.6.2; 1.6.6;
#include <sys/bus.h> instead of <machine/bus.h>.

set RI_NO_AUTO when initializing the early console - we're so early that
kmem_alloc() can't be used and we don't really need box drawing characters
for the OF font anyway

branches: 1.4.2;
Remove white-spaces.

branches: 1.3.2;
Ansify function definitions w/o arguments. Generated with sed.

branches: 1.2.4; 1.2.12; 1.2.18; 1.2.26;
Removed the check for device_type==display in rascons_cnattach(). It is not
required, because this function will be called for display-consoles only,
and it allows SmartFirmware to attach a rascons console.
Approved by garbled.

branches: 1.1.2; 1.1.4; 1.1.8; 1.1.10; 1.1.18; 1.1.20; 1.1.24;
Apply a set of patches from Frank Wille to make the genfb attachment work
better on ofppc. In doing so, we also move a few functions around in
macppc and the generic ofw powerpc stuff to allow better sharing of code.
Also, introduce a model_init function.

move ofb_cons.c from macppc/dev to powerpc/oea and rename it to rascons.
This gets rid of some naming confusion, and makes it OFW-MI rather than
macppc specific.

make the ROM font usable on G5s:
- copy the font data into a buffer instead of just pointing at the ROM
- don't blindly assume the font's width
- don't try to center output ourselves - rasops_init() will do it for us
- provide a hook to add the ROM font to wsfont when we're ready

branches: 1.2.4;
defer scribbling into video memory until after re-enabling the MMU if
we're in bridge mode.
With this NetBSD boots on PCI-X G5s

branches: 1.1.2; 1.1.4; 1.1.8; 1.1.10; 1.1.18;
Apply a set of patches from Frank Wille to make the genfb attachment work
better on ofppc. In doing so, we also move a few functions around in
macppc and the generic ofw powerpc stuff to allow better sharing of code.
Also, introduce a model_init function.

move ofb_cons.c from macppc/dev to powerpc/oea and rename it to rascons.
This gets rid of some naming confusion, and makes it OFW-MI rather than
macppc specific.

Minor re-ordering of a few things, and issue an isync barrier at all
critical MMU on/off transitions.

- Fix a comment.
- rename ofwsrsave to clsrsave; we're saving / restoring the client's
(i.e. kernel's) SRs there, not the firmware's.

Don't save the firmware's copy of SPRG[0-3], and don't fiddle with
SPRG[0-3] in the firmware trampoline. Section 7.1 of the OpenFirmware
PowerPC CPU bindings says that firmware "client interface shall not modify"
when in virtual-mode, and "client interface shall preserve" in real-mode.

This is important because in vritual-mode, DSI exceptions will land in
the kernel's DSI exception handler, and that handler depends on the
kernel's SPRG0 value (it contains the pointer to the cpu_info for that
CPU).

Additionally, in the firmware trampoline, point curcpu at an empty
ofw_battable. This ensures that the DSI exception handler won't
load a BAT register with a kernel block translation that clobbers
a segment translation owned by the firmware. Eventually, this ofw_battable
might contain some of the larger translations owned by the firmware.

ofwreal_incharge does not need to be global.

Put back accidental removal of "ofwreal_incharge".

Add an ofw_bootstrap() function, called during early bootstrap from
ofwinit() to perform additional early initialization in C code. Use
this to get the memory config while we're still running in the OpenFirmware
client environment, rather than waiting until we've started fiddling with
the system state.

- Tidy up some comments.
- Use correct stack frame linkage everywhere so that if something goes
wrong, we can get a meaningful back trace.
- Use an additional layer of indirection so that, when we're very
early in bootstrap, we can just call OpenFirmware directly, rather
than using our trampoline that saves/restores kernel state.
- Carve out a space for ofwinit() to call into C code to do additional
initialization. (This is not done yet.)

- Don't change to the OFW stack in C code; instead, switch to the OFW
stack in the openfirmware() wrapper itself. Inspired by a similar
change in OpenBSD designed to appease clang.
- The OF_*() entry firmware interfaces use several global resources;
protect those global resources with a __cpu_simple_lock_t.
- Make ofbcopy() static -- it's no longer referenced outside openfirm.c

branches: 1.12.2;
Include missing opt_ppcarch.h.

bump OF_buf(fer) since we may put extra parameters in there

branches: 1.10.54;
move clearing PSL_IP in ofwmsr back where it was - if we do it too early my
PowerBook 3400c hangs on startup.

Save/restore all sprgs when calling OFW.
Move all-zero variables from .data to .bss
Use .lcomm for local variables.
Cleanup a bit of assembly.
Clear PSL_IP in the saved ofmsr (was previously done in ofwoea_machdep.c)

branches: 1.8.36;
SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.

branches: 1.7.6;
Some powerpc cleanup. Remove unneeded/bad usage of extern oeacpufeat.
Convert asm code to use %r register format. Done by comparison to
disassembled output, double checked with diff of dissasembled output
before and after, and test booted on my 7044.

Pull another instance of bridge mode avoiding the BATs.
Fix FIRMWORKSBUGS. The #else on one of the ifdefs for it made it so that
it would never work on a machine that didn't need it. This caused IBM
machines to be unable to talk to OFW if the option was enabled. Replace
the #else with a branch and call it good.

branches: 1.5.2;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.4.10;
in the FIRMWORKSBUGS case, and if PSL_DR/PSL_IR are set, don't do the
job of saving and restoring registers twice: let ofwreal cope with everything.

This was the last bit needed to get a stock NetBSD/ofppc kernel booting
on the Efika. This will have to be adapted to the ppcoea-renovation branch.

branches: 1.3.14; 1.3.16; 1.3.22;
1st cut of Powermac G5 support (uses bridge mode).

branches: 1.2.18; 1.2.32; 1.2.36;
Use register 8, not 0, when construct OF_buffer address.

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

- initialize bootpath
- if we don't get anything useful from args, check /chosen
now my G5 finds its boot device even when netbooting a kernel directly

add ifdef NWSDISPLAY > 0 around rascons_* functions usage,
otherwise implementation is not available, which breaks macppc MAMBO config.

potentially better solution to provide empty implementation, comments welcome.

s/preceed/preced/ in comment.

clarify comment in previous
( this is a hack, should go away when the root cause is fixed etc. )
no functional change

avoid mapping 0xfffff000 - my beige G3 DSIs on it
with this my the machine boots again
tested on a variety of G4 and G5 models with no problems

branches: 1.59.2;
Separate probing for the console device and initializing it, so that
ofwoea_initppc() can have more control over which of those steps are
performed during initialization. Probing happens before setting up
the exception vectors, initializing happens after.

Split set_timebase() into get_timebase_frequency() and init_decrementer().
Call get_timebase_frequency() much earlier.

Move ofppc-specific CPU spinup code to ofppc/machdep.c

Un-do a bunch of misguided code sharing. It's not really shared if it's
full of platform-specific #ifdefs:
- ofwoea_batinit() is gone; just do what's needed early in macppc / ofppc
initppc() functions.
- Get a bunch of Mac-specific stuff out of ofwoea_initppc().

In ofwoea_initppc(), call oea_init() after getting the bootpath, etc.
Also, add a comment explaining why it's actually necessary to clear
PSL_IP after installing the kernel's exception vectors.

Don't save the firmware's copy of SPRG[0-3], and don't fiddle with
SPRG[0-3] in the firmware trampoline. Section 7.1 of the OpenFirmware
PowerPC CPU bindings says that firmware "client interface shall not modify"
when in virtual-mode, and "client interface shall preserve" in real-mode.

This is important because in vritual-mode, DSI exceptions will land in
the kernel's DSI exception handler, and that handler depends on the
kernel's SPRG0 value (it contains the pointer to the cpu_info for that
CPU).

Additionally, in the firmware trampoline, point curcpu at an empty
ofw_battable. This ensures that the DSI exception handler won't
load a BAT register with a kernel block translation that clobbers
a segment translation owned by the firmware. Eventually, this ofw_battable
might contain some of the larger translations owned by the firmware.

Update some #ifdef PMAC_G5 for previous change that I missed before.

Shuffle around a couple of things that aren't particularly OEA-specific:

- Early bootstrap console initialization moves to ofw_machdep.c, and
is called a bit earlier, from ofw_bootstrap().

- Decoding the "translations" property from /chosen/mmu is specified
in the general OpenFirmware PowerPC bindings, and is not specific to
any particular PowerPC flavor. It's now decoded a bit earlier in
ofw_bootstrap().

The *interpretation* of the mode field of a translation is, however,
implementation-specific, so that remains in ofwoea_machdep.c.

Add some comments to help visually track the nested #ifdef blocks in
ofwoea_batinit().

branches: 1.50.2;
It turned out that using some Open Firmware routines causes the system
freeze after calling OF_quiesce().

This is why setting color palette crash the system for some Power Mac G5
models, like PowerMac11,2.

Therefore, stop using color-palette and backlight callbacks for genfb(4)
in this case.

Also, postpone OF_quiesce() after rascons_init_rasops(), and initialize
color palette there if OF is going to be quiesced and color depth is 8.

Now, color palette for wscons is initialized correctly for PowerMac11,2.

- Drop unused opt_compat_netbsd.h.
- Include missing opt_multiprocessor.h.

Style and cosmetic changes. No binary changes intended.

do what FreeBSD does and OF_quiesce() only on PowerMac11,2 and 12,1

switch PowerMac7,* CPUs to full speed via OF
if we do this later we hang

branches: 1.45.6;
Retire ipkdb entirely. The option was removed from the config files
yesterday.

ok kamil christos

branches: 1.44.2; 1.44.4;
get bootpath from OF if we don't get it as an argument

defer scribbling into video memory until after re-enabling the MMU if
we're in bridge mode.
With this NetBSD boots on PCI-X G5s

fix ofppc/pegasosII (and maybe others).

don't assume PPC_OEA64_BRIDGE means we have a 64 bit cpu (code
for 64 bit in bridge and normal 32 bit can co-exist due to
fixups the early boot code does has, and ofppc builds GENERIC
this way):
- fix mtmsr()/mfmsr() to use the right method based upon the
actually cpu booted on.
- fix cpu_setup() to have 32 bit and 64 bit hid0 variables
and operate on the right one based upon the current cpu.
restore a minor optimisation of not writing hid0 if it
didn't change.

in set_timebase() check if OF_finddevice("/cpus/@0") failed
and returned -1 before using it for OF_getprop().

add quick path for timebase-frequency detection
deal with differences in /u4 reg property encoding vs. /uni-n, so this works
on my G5 now

flesh out RANGE_TYPE_MACIO

switch all ports to use uvm_init.c:uvm_md_init()

uvm_setpagesize() is now subsumed within this funciton.

branches: 1.38.6; 1.38.10;
sprintf -> snprintf

support ppc601
from scole_mail, ok matt@

Use uintptr_t instead of int.

- remove set but unused variables
- move some variables inside their relevant use #ifdef

Move the pmap_setup to the start oea_init (no non-OFW ports can use it).
If PPC_OEA64_BRIDGE is defined, add code so that when OEACPU_64_BRIDGE is not
present, it replaces the rfid with rfi and mfmsr/rldicl/mtmsrd sequence
with NOPs. This allows plain OEA kernels to work. (tested on PMPPC with
PPC_OEA64_BRIDGE option added).

branches: 1.33.2;
more G5 stuff:
- call OF_quiesce()
- properly map the message buffer

make PPC_OEA64_BRIDGE mode work
from Phileas Fogg

Support Cache Protocol 'MEI' with MULTIPROCESSOR.

branches: 1.30.2;
OF_finddevice returns -1 on error, not an arbitrary negative number. Make
conditional explicit so that model_name gets a chance to be initialized when
the handle for the device is actually negative (which appears to be the case
in my Mac Mini G4).

provide a BAT mapping for the PCI IO range on Grackle/Heathrow based macs
now drivers that need PCI IO access work again

Allow use of large (>256MB) bats for iobats. If XBSEN isn't present, they
will be "downsized" into multiple 256MB bats. Tested by riz.

branches: 1.27.2;
fix crash during early startup - we can't call OpenFirmware between zapping
the BATs and complete setting them up again
ok releng

branches: 1.26.2; 1.26.6;
Drop into ddb, when requested by ofwboot (-d option).

move clearing PSL_IP in ofwmsr back where it was - if we do it too early my
PowerBook 3400c hangs on startup.

Enable new-style <sys/bus.h> on several PowerPC ports supporting PCI
buses. Make non-inline implementations of bus_space(9) and bus_dma(9)
routines and move them to appropriate .c files.

This may leave amigappc in a bad state, sorry. Fortunately, it will be
easy to repair by imitating the bus.h -> bus_{defs,funcs}.h split in
some other PowerPC port.

Select pmap style before calling oea_init.

<arch/powerpc/... -> <powerpc/...

Save/restore all sprgs when calling OFW.
Move all-zero variables from .data to .bss
Use .lcomm for local variables.
Cleanup a bit of assembly.
Clear PSL_IP in the saved ofmsr (was previously done in ofwoea_machdep.c)

branches: 1.20.8;
Fix isa(4) support for ofw.
ofw not initialized bus_space for isa(4).
It tested on ofppc(PegasosII).

Remove white-spaces.

branches: 1.18.2;
Heed modeldata.ranges_offset while constructing the ranges bitmap.

Use "defopt MODULAR" in sys/conf/files, and #include "opt_modular.h"
in all kernel sources that use the MODULAR option.
Proposed in tech-kern on 18 Jan 2009.

branches: 1.16.4;
As discussed on tech-kern: mutex_init is too heavyweight for early bootstrap
phases, so move the initialization of the ksyms mutex back into main via
a function called ksyms_init. Rename the existing (but quite different)
ksyms_init* variations into ksyms_addsyms_elf() and ksyms_addsyms_explicit()
and adapt machdep code accordingly.

Remove LKMs and switch to the module framework, pass 1.

Proposed on tech-kern@.

branches: 1.14.6; 1.14.8;
Remove clause 3 and 4 from TNF licenses

branches: 1.13.2; 1.13.4;
SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.

branches: 1.12.6;
Some powerpc cleanup. Remove unneeded/bad usage of extern oeacpufeat.
Convert asm code to use %r register format. Done by comparison to
disassembled output, double checked with diff of dissasembled output
before and after, and test booted on my 7044.

Use model_init to clean up how we decide the ranges for
PCI_NETBSD_CONFIGURE. Add some code to hopefully better handle the
firepower and powerstackII, based on the OFW dumps from those machines.
Untested on those machines, but doesn't break anything on pegasos/7044.

Rewrite a big chunk of the pmap and locore code for powerpc to better
deal with the 64bit bridge mode. pmap changes by Matt Thomas, rest by myself.

Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel. This allows the pmap for bridge64 to
co-exist with the 32bit pmap.

Yank __HAVE_PMAP_PHYSSEG from all the oea code.

Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features. This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.

Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in. Some of it seemed incorrect, and my 7044 booted just fine
without it. It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.

In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].

With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu. However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE. Work remains to be done there to fix that.

Apparently BRIDGE mode allows BAT registers, so re-enable that code.
Change the pegasos PCI_NETBSD_CONFIGURE arguments around to wire up mem
space into the correct area, and move the io regs a little to make it
work properly. Just avoid the secondary PCI entirely.
Change the list of things that we fiddle with in pci_conf_hook. Map mem
on the fwohci, avoid display cards, avoid IO on the auvia.
Change some printf's to aprint_*
Yank a call to genppc_pci_indirect_make_tag and change it to the
bus-independant pci call instead. (in pci_conf_hook)

Add support to ofppc for the IBM 7044-270 machine. This is a POWER3-II
based machine. Currently the kernel to run on this machine is
incompatible with the standard GENERIC kernel, so for now, we have a
separate GENERIC_B64. Eventually, I hope to combine the two.

Please note, this is a port of 32bit ofppc, not a powerpc64 port.

Thanks to Matt Thomas and Kevin Bowling for helping to make this port
possible.

Summary of changes:

Change ofwpci to use the ofmethod config for configuring the PCI bus,
rather than indirect configuration.
Move the wiring of the interrupt controllers from at the start of the
boot, into the configuration of the first PCI bus.
Rewrite the map_isa_ioregs() hack to work on a machine without BATs
Fix a ton of bugs in the genofw_find_pics routine, and in the map_space code.
Split the pic_openpic into openpic_common and pic_openpic.
Create a new pic_distopenpic driver, for the distributed openpic found on
some newer IBM machines.
Fix a bad panic in pmap_extract on 64bit bridge mode

ofwoea_batinit should be a nop when PPC_OEA is not defined

branches: 1.6.6;
Apply a set of patches from Frank Wille to make the genfb attachment work
better on ofppc. In doing so, we also move a few functions around in
macppc and the generic ofw powerpc stuff to allow better sharing of code.
Also, introduce a model_init function.

move ofb_cons.c from macppc/dev to powerpc/oea and rename it to rascons.
This gets rid of some naming confusion, and makes it OFW-MI rather than
macppc specific.

Commit a fix for the _SR regions that are needed by ofppc. Because this
platform tends to just declare anything from 0x8 to 0xf as mem or io
regions willy-nilly, we need to avoid batmapping a few of those in order
to save space for USER_SR, KERNEL_SR and KERNEL2_SR. I picked values for
these three that are least-commonly used or used for non-vital things.

branches: 1.4.2; 1.4.4; 1.4.6;
Fix the ranges_bitmap function so it correctly finds the various ranges
on OFW, and passes them on to ofwoea_batmap correctly. With this fix,
ofppc now properly initializes all of it's batmappings.

Kept the macppc specific override of the bitmap, but surrounded it with
an #ifdef macppc. It would probably be worth testing macppc without this
ifdef to see if it works there as well.

Add a bunch of fixes and minor rewrites to ofppc to bring it closer to
working properly. This is still a work in progress, and all work so far
has been based on the PegasosII machne.

1) Rewrite how the ISA memory and IO space maps are found. More work
will still need to be done in this area.
2) Add a new OFW method of pci configuration. So far I can only get this
to work on the primary PCI bus on the Pegasos. Unsure if this is a
pegasos bug or a code bug.
3) Add the rtas device to ofppc, and add an "rtas_reboot" function to
rtas to allow me to reboot the PegasosII. The rtas driver works, and is
a great start but needs to be changed slightly to allow easier access to
the functions from outside the driver.
4) Fix a number of bugs that existed in the shared PCI code for ofw that
probably weren't tickled by macppc.

There is much much more left to do here, this is all still a work in
progress, but this commit will allow other people to play around with the
code if they want to.

branches: 1.2.2;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.1.2; 1.1.6; 1.1.8; 1.1.10;
file ofwoea_machdep.c was initially added on branch ppcoea-renovation.

Fix various typos, mainly in comments.

Fix various typos in comments.

branches: 1.121.2;
powerpc: oea: For OEA64_BRIDGE, 1:1 map up to 3GiB memory

As done for OEA. Note that kva over 3GiB is reserved.

Provide PMAP_MAP_POOLPAGE for OEA64_BRIDGE at the same time, by
which direct-mapped memory is utilized in order to work around
starvation of 512MiB kernel virtual space.

PR kern/57621

powerpc/oea: pmap_create: Use PR_ZERO and drop memset(9), NFC

Part of PR kern/57621

powerpc/oea: pmap: Fix mostly-pointless overhead of pmap_pvo_pool

(1) Drop __aligned(32) from struct pvo_entry; otherwise,
sizeof(struct pvo_entry) is round-up'ed to a multiple of 32.

(2) Do not set sizeof(struct pvo_entry) to `align` argument for
pool_init(9); it must be power of 2.

(3) Align pvo_entry to 32-byte boundary only if reasonably possible,
i.e., OEA without DIAGNOSTIC (--> POOL_REDZONE) for now.

Part of PR kern/57621

powerpc/oea: pmap: Rework pmap_pte_spill()

It was broken in many ways... Now, it gets working stable both for
OEA and OEA64_BRIDGE, as far as I can see.

Part of PR kern/57621

powerpc/oea: pmap: Drop unused argument for pmap_pvo_reclaim(), NFC

Part of PR kern/57621

fix triple s typos in comments.

powerpc/oea: pmap: Use pool_allocator_nointr() for pmap_pool

As done for (majority of) other pmap implementations.

pmap_pool_allocator() allocates memory below 256MB, but it is not
necessary for struct pmap.

Fix part of PR kern/57621, i.e., stall in pmap_create(9).

There should be another bugs that cause (MP?) kernel hangs
reported in the PR, in pmap or other MD components for powerpc
(PR port-powerpc/56922 should be one of the candidates).

XXX
pmap for powerpc/oea apparently needs some clean ups. But leave it
as is, and pull up this minimum fix to netbsd-10 at the moment.

branches: 1.114.4;
PR port-powerpc/56818

Fix inverted logic introduced in rev. 1.108, by which modified/referenced
bits of pages were never cleared appropriately.

Now, full ATF runs on macppc and sandpoint, with no regression observed.

sys: Use membar_release/acquire around reference drop.

This just goes through my recent reference count membar audit and
changes membar_exit to membar_release and membar_enter to
membar_acquire -- this should make everything cheaper on most CPUs
without hurting correctness, because membar_acquire is generally
cheaper than membar_enter.

sys: Membar audit around reference count releases.

If two threads are using an object that is freed when the reference
count goes to zero, we need to ensure that all memory operations
related to the object happen before freeing the object.

Using an atomic_dec_uint_nv(&refcnt) == 0 ensures that only one
thread takes responsibility for freeing, but it's not enough to
ensure that the other thread's memory operations happen before the
freeing.

Consider:

Thread A Thread B
obj->foo = 42; obj->baz = 73;
mumble(&obj->bar); grumble(&obj->quux);
/* membar_exit(); */ /* membar_exit(); */
atomic_dec -- not last atomic_dec -- last
/* membar_enter(); */
KASSERT(invariant(obj->foo,
obj->bar));
free_stuff(obj);

The memory barriers ensure that

obj->foo = 42;
mumble(&obj->bar);

in thread A happens before

KASSERT(invariant(obj->foo, obj->bar));
free_stuff(obj);

in thread B. Without them, this ordering is not guaranteed.

So in general it is necessary to do

membar_exit();
if (atomic_dec_uint_nv(&obj->refcnt) != 0)
return;
membar_enter();

to release a reference, for the `last one out hit the lights' style
of reference counting. (This is in contrast to the style where one
thread blocks new references and then waits under a lock for existing
ones to drain with a condvar -- no membar needed thanks to mutex(9).)

I searched for atomic_dec to find all these. Obviously we ought to
have a better abstraction for this because there's so much copypasta.
This is a stop-gap measure to fix actual bugs until we have that. It
would be nice if an abstraction could gracefully handle the different
styles of reference counting in use -- some years ago I drafted an
API for this, but making it cover everything got a little out of hand
(particularly with struct vnode::v_usecount) and I ended up setting
it aside to work on psref/localcount instead for better scalability.

I got bored of adding #ifdef __HAVE_ATOMIC_AS_MEMBAR everywhere, so I
only put it on things that look performance-critical on 5sec review.
We should really adopt membar_enter_preatomic/membar_exit_postatomic
or something (except they are applicable only to atomic r/m/w, not to
atomic_load/store_*, making the naming annoying) and get rid of all
the ifdefs.

Backout previous and fix the correct macro magic

pmap_pv_protect is not STATIC

powerpc: Sprinkle "memory" clobbers on eieio and nearby asm blocks.

Otherwise the compiler may reorder these around loads and stores,
which mostly defeats the purpose. `asm volatile' just ensures the
instruction isn't _deleted_; it may still move around.

powerpc: Implement pv-tracking for unmanaged pages.

Needed for drm.

there is no need to keep pvos for unmanaged mappings on a hidden p/v list,
since "unmanaged" means that we don't want to find such pvos on any p/v list.
instead, just don't put such pvos on any p/v list at all and remove
the two hidden p/v lists for unmanaged mappings. code mostly from martin,
to implement rin's suggestion of unifying the two hidden lists.

PR 55325: unify both pvo pools (for managed and unmanaged pages).
Analyzis by rin, fix suggested by chs.

branches: 1.105.4;
Fix paste-o in last.

Re-factor the code in pmap_extract() that checks the 601 I/O segment
table and the BAT tables into separate functions that can be called
from outside of the pmap module.

Tidy up initialization of the kernel SRs just a bit.

- In pmap_bootstrap1(), make sure to initialize pmap_kernel()->pm_vsid
with the kernel's base VSID.
- In va_to_vsid(), always compute the VSID from the base VSID in the
pmap and the effective segment ID (ESID), rather than extracting it
from the pmap's segment register value for that ESID. Not only does
this make the code the same between OEA and OEA64, but is also lets
us compute the correct VSID for that pmap/ESID even if the cached SR
for that ESID currently contains something else, such as an I/O segment
mapping (as might be the case on a 601).

With this change, we can temporarily toggle between an I/O segment and
and HTAB-mapped segment if needed (e.g. when calling OpenFirmware on
a 601-based system).

Complete the pmap symbol renaming shenanigans for pmap_bootstrap[12]().

Apply PMAPNAME() to pmap_bootstrap[12](); fix build for ofppc, which has
both pmap32 and pmap64bridge in a single kernel.

Split pmap_bootstrap() into 2 functions:
- pmap_bootstrap1(), which sets up the low-level pmap data structures.
- pmap_bootstrap2(), which actually programs the MMU hardware based on
pmap_bootstrap1()'s work.

pmap_bootstrap() is still provided as a wrapper around the two, but this
provides flexibility to platforms that might need to do additional work
between these two phases.

branches: 1.98.2;
Style and cosmetic changes. No binary changes intended.

Fix typo; PMAP_OEA64_BRIDGE not PMAP_OEA_BRIDGE.
Tested on Power Mac G5.

Stop returning while PMAP_LOCK() (= KERNEL_LOCK(1, NULL)) is held.

Kernel freeze with heavy load is significantly mitigated (fixed?),
in which I could not even enter DDB from console.

XXX
There is still inconsistency in usage of two PVO pools.
I will send-pr later.

XXX
pullup to netbsd-[987]

branches: 1.95.8;
apply the change from arch/x86/x86/pmap.c rev. 1.266 commitid vZRjvmxG7YTHLOfA:

In pmap_enter_ma(), only try to allocate pves if we might need them,
and even if that fails, only fail the operation if we later discover
that we really do need them. If we are replacing an existing mapping,
reuse the pv structure where possible.

This implements the requirement that pmap_enter(PMAP_CANFAIL) must not fail
when replacing an existing mapping with the first mapping of a new page,
which is an unintended consequence of the changes from the rmind-uvmplock
branch in 2011.

The problem arises when pmap_enter(PMAP_CANFAIL) is used to replace an existing
pmap mapping with a mapping of a different page (eg. to resolve a copy-on-write).
If that fails and leaves the old pmap entry in place, then UVM won't hold
the right locks when it eventually retries. This entanglement of the UVM and
pmap locking was done in rmind-uvmplock in order to improve performance,
but it also means that the UVM state and pmap state need to be kept in sync
more than they did before. It would be possible to handle this in the UVM code
instead of in the pmap code, but these pmap changes improve the handling of
low memory situations in general, and handling this in UVM would be clunky,
so this seemed like the better way to go.

This somewhat indirectly fixes PR 52706 on the remaining platforms where
this problem existed.

branches: 1.94.8;
"Make NetBSD great again!"

Introduce uvm_hotplug(9) to the kernel.

Many thanks, in no particular order to:

TNF, for funding the project.

Chuck Silvers - for multiple API reviews and feedback.
Nick Hudson - for testing on multiple architectures and bugfix patches.
Everyone who helped with boot testing.

KeK (http://www.kek.org.in) for hosting the primary developers.

branches: 1.93.2;
Add missing va_end; PR 50795 from David Binderman.

branches: 1.92.2; 1.92.4;
Update conditions on mfsrin definition to match use.

support ppc601
from scole_mail, ok matt@

gcc 4.8.1 wants:
- remove some set but unused variables
- move some variables inside their usage #ifdef's
- cast to (void) instead of using a dummy return variable

(there are more to come, but this one is now tested with gcc 4.5)

branches: 1.89.4;
make PPC_OEA64_BRIDGE mode work
from Phileas Fogg

Fix loop bug (Phileas Fogg)

Support Cache Protocol 'MEI' with MULTIPROCESSOR.

branches: 1.86.2;
Fix -fno-common fallout.

Use CPP __VA_ARGS__ for DPRINTF*

Use kmem instead of malloc. Remove unneeded <sys/malloc.h> includes.

Enable XBSEN and HIGHBAT for OEA 7455 and related CPUs.
The BAT entries now have a resolution of 8MB. (Adjacent entries are merged
up to a total of 2GB per entry).

branches: 1.82.2; 1.82.6;
Retire varargs.h support. Move machine/stdarg.h logic into MI
sys/stdarg.h and expect compiler to provide proper builtins, defaulting
to the GCC interface. lint still has a special fallback.
Reduce abuse of _BSD_VA_LIST_ by defining __va_list by default and
derive va_list as required by standards.

Modify mapiodev to take a third argument indicating whether the space
should be prefetchable (true) or not (false).

Use __builtin_clz instead of cntlzw

branches: 1.79.2;
A little PMAP_OEA64 pmap support.

Move powerpc_mmap_flags since pmap.c can get compiled multiple time resulting
in multiple defintions of powerpc_mmap_flags.

implement pmap_mmap_flags() and teach PowerPC's bus_space_mmap() to actually
use BUS_SPACE_MAP_PREFETCHABLE which, now that /dev/pci* knows how to use it,
helps improve X performance

When an OEA kernel is configured for multiple MMU types, use the new
powerpc fixup mechanism to bind the kernel to a particular MMU. This
avoids an indirect call for every pmap call.

branches: 1.75.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.74.2;
Put VM_PAGE_TO_MD() definition in one place. No functional changes.

Use more VM_PHYSMEM_*() accessors. No functional changes.

Use VM_PAGE_TO_MD() to locate struct vm_page_md. No functional
changes.

branches: 1.71.2;
Adapt to spr.h breakup.

s/cpu_fork/cpu_lwp_fork/ in comment

branches: 1.69.2;
Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.

Add a flags argument to pmap_kenter_pa(9).
Patch showed on tech-kern@ http://mail-index.netbsd.org/tech-kern/2009/11/04/msg006434.html
No objections.

Remove uarea swap-out functionality:

- Addresses the issue described in PR/38828.
- Some simplification in threading and sleepq subsystems.
- Eliminates pmap_collect() and, as a side note, allows pmap optimisations.
- Eliminates XS_CTL_DATA_ONSTACK in scsipi code.
- Avoids few scans on LWP list and thus potentially long holds of proc_lock.
- Cuts ~1.5k lines of code. Reduces amd64 kernel size by ~4k.
- Removes __SWAP_BROKEN cases.

Tested on x86, mips, acorn32 (thanks <mpumford>) and partly tested on
acorn26 (thanks to <bjh21>).

Discussed on <tech-kern>, reviewed by <ad>.

Remove all declarations of physmem from sys/arch. Add an include of
<sys/systm.h> to the one file that did not already contain it.
This now means that physmem can be changed by updating systm.h and uvm_page.c
(excluding fixing printfs)

change pmap flags argument from int to u_int.
discussed with christos@ on source-changes-d@

branches: 1.64.2;
Since oea pmap.c is #included many times, put kernel_pmap_ptr into
its own source module to avoid multiple initialized data definitions.

Make kernel_pmap_ptr a const. Requested by steve_martin.

Make pmap_kernel() a MI macro for struct pmap *kernel_pmap_ptr,
which is now the "API" provided by the pmap module. pmap_kernel()
remains as the syntactic sugar.

Bonus cosmetics round: move all the pmap_t pointer typedefs into
uvm_pmap.h.

Thanks to Greg Oster for providing cpu muscle for doing test builds.

branches: 1.61.12;
Typo in comment.

branches: 1.60.6; 1.60.8;
pmap_upvo_pool needs to use IPL_VM since it is used from
pmap_kenter_pa(), which can be called from interrupt context.

Remove clause 3 and 4 from TNF licenses

branches: 1.58.2; 1.58.4;
SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.

on MP systems, whenever we change a PTE, make to sync the data cache so that
other processors can see the change.

branches: 1.56.2; 1.56.6;
Fixed compilation with DEBUG option for PMAP_OEA64_BRIDGE.
Approved by garbled.

Ifdef out all the MPC601 code with PPC_OEA601. Now only arches that have the
possibility of running on an MPC601, are infected with all the extra code
and nops that it added.

Also, fix compilation that I broke with the pmap code, by adding
oeacpufeat to the locores of various ppc arches. Noted by mlelstv.

fix and cleanup debug printf formats

Rewrite a big chunk of the pmap and locore code for powerpc to better
deal with the 64bit bridge mode. pmap changes by Matt Thomas, rest by myself.

Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel. This allows the pmap for bridge64 to
co-exist with the 32bit pmap.

Yank __HAVE_PMAP_PHYSSEG from all the oea code.

Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features. This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.

Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in. Some of it seemed incorrect, and my 7044 booted just fine
without it. It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.

In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].

With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu. However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE. Work remains to be done there to fix that.

Add support to ofppc for the IBM 7044-270 machine. This is a POWER3-II
based machine. Currently the kernel to run on this machine is
incompatible with the standard GENERIC kernel, so for now, we have a
separate GENERIC_B64. Eventually, I hope to combine the two.

Please note, this is a port of 32bit ofppc, not a powerpc64 port.

Thanks to Matt Thomas and Kevin Bowling for helping to make this port
possible.

Summary of changes:

Change ofwpci to use the ofmethod config for configuring the PCI bus,
rather than indirect configuration.
Move the wiring of the interrupt controllers from at the start of the
boot, into the configuration of the first PCI bus.
Rewrite the map_isa_ioregs() hack to work on a machine without BATs
Fix a ton of bugs in the genofw_find_pics routine, and in the map_space code.
Split the pic_openpic into openpic_common and pic_openpic.
Create a new pic_distopenpic driver, for the distributed openpic found on
some newer IBM machines.
Fix a bad panic in pmap_extract on 64bit bridge mode

fix a bad cast when compiling in bridge mode

Merge vmlocking2 to head.

__FUNCTION__ -> __func__

branches: 1.48.18; 1.48.24; 1.48.26; 1.48.30;
Pass an ipl argument to pool_init/POOL_INIT to be used when initializing
the pool's lock.

branches: 1.47.2;
make this compile again

Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

TRUE -> true, FALSE -> false

Replace the Mach-derived boolean_t type with the C99 bool type. A
future commit will replace use of TRUE and FALSE with true and false.

branches: 1.43.4;
Make these files compile with -Wextra -Wno-unused.

When mapping the kernel, make to update its segment register to be valid.

At the end of pmap_bootstrap, if PMAP_NEED_MAPKERNEL, map the kernel into
the kernel's pmap (text will be rx, data will be rw).

branches: 1.40.2; 1.40.4;
Remove debug printf that got left in accidentally