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History log of /src/sys/arch/powerpc/pic
RevisionDateAuthorComments
 1.2 17-Oct-2007  garbled branches: 1.2.2; 1.2.4; 1.2.6; 1.2.8; 1.2.12;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.1 10-Oct-2007  garbled branches: 1.1.2;
file files.ipi was initially added on branch ppcoea-renovation.
 1.1.2.1 10-Oct-2007  garbled New ppcoea-MI IPI infrastructure. This is similar to the PIC
infrastructure, but simplified greatly.

Also, convert macppc (the only port currently using IPI's) over to this new
infrastructure. Still some minor work left to do here.
 1.2.12.2 06-Nov-2007  matt sync with HEAD
 1.2.12.1 17-Oct-2007  matt file files.ipi was added on branch matt-armv6 on 2007-11-06 23:20:51 +0000
 1.2.8.2 02-Nov-2007  joerg More diff reduce to HEAD due to botched up merging.
 1.2.8.1 17-Oct-2007  joerg file files.ipi was added on branch jmcneill-pm on 2007-11-02 13:34:44 +0000
 1.2.6.2 27-Oct-2007  yamt sync with head.
 1.2.6.1 17-Oct-2007  yamt file files.ipi was added on branch yamt-lazymbuf on 2007-10-27 11:27:58 +0000
 1.2.4.2 23-Oct-2007  ad Sync with head.
 1.2.4.1 17-Oct-2007  ad file files.ipi was added on branch vmlocking on 2007-10-23 20:36:15 +0000
 1.2.2.2 18-Oct-2007  yamt sync with head.
 1.2.2.1 17-Oct-2007  yamt file files.ipi was added on branch yamt-x86pmap on 2007-10-18 08:32:44 +0000
 1.7 17-Jun-2011  matt intr.h must not include cpu due to deadly embrace with SOFTINT_COUNT.
Cleanup intr.h so MD definitions can overload common definitions.
Rototill pic/intr.c. Virtual IRQs can now be reclaimed. separate virq
from hwirq from picirq. Redo intr mask calculations.
tested on pmppc and macppc (MP).
 1.6 16-Jun-2011  macallan enable FAST_SOFTINTR support for all ports that use powerpc/pic/
This has been successfully tested on macppc
TODO:
- ibm4xx needs to be adapted
- SMP doesn't work yet, 2nd CPU crashes when trying to leave the idle loop
 1.5 05-Jun-2011  matt Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.
 1.4 19-Aug-2009  nisimura branches: 1.4.4; 1.4.6; 1.4.10;
- Have pic_mpcsoc.c to adapt variations of Moto/Freescale OpenPIC
compliant interrupt controllers. Mostly the refrain of pic_openpic.c
and shall be useful for 85xx/86xx/QorIQ and Tundra product lines.
 1.3 17-Jan-2008  garbled branches: 1.3.10;
Add support to ofppc for the IBM 7044-270 machine. This is a POWER3-II
based machine. Currently the kernel to run on this machine is
incompatible with the standard GENERIC kernel, so for now, we have a
separate GENERIC_B64. Eventually, I hope to combine the two.

Please note, this is a port of 32bit ofppc, not a powerpc64 port.

Thanks to Matt Thomas and Kevin Bowling for helping to make this port
possible.

Summary of changes:

Change ofwpci to use the ofmethod config for configuring the PCI bus,
rather than indirect configuration.
Move the wiring of the interrupt controllers from at the start of the
boot, into the configuration of the first PCI bus.
Rewrite the map_isa_ioregs() hack to work on a machine without BATs
Fix a ton of bugs in the genofw_find_pics routine, and in the map_space code.
Split the pic_openpic into openpic_common and pic_openpic.
Create a new pic_distopenpic driver, for the distributed openpic found on
some newer IBM machines.
Fix a bad panic in pmap_extract on 64bit bridge mode
 1.2 17-Oct-2007  garbled branches: 1.2.2; 1.2.4; 1.2.6; 1.2.8; 1.2.14;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.1 02-May-2007  macallan branches: 1.1.2; 1.1.6; 1.1.8;
file files.pic was initially added on branch ppcoea-renovation.
 1.1.8.1 18-Oct-2007  yamt sync with head.
 1.1.6.1 02-Nov-2007  joerg More diff reduce to HEAD due to botched up merging.
 1.1.2.10 16-Oct-2007  macallan make interrupt distribution via OpenPIC optional
with options OPENPIC_DISTRIBUTE all CPUs will receive hardware interrupts,
otherwise only cpu0
 1.1.2.9 09-May-2007  garbled The i8259 and prepivr code had a bunch of functions that were duplicates
of one another. Break those out into i8259_common.c and share that file
between the two of them.
 1.1.2.8 04-May-2007  macallan sprinkle needs-flag
 1.1.2.7 04-May-2007  macallan add config voodoo to select support for various PICs using options PIC_*
 1.1.2.6 04-May-2007  garbled Add an i8259 pic. Compile tested only.
Add 8259 initialization code to prepivr. (Forgot to add this when I nuked
init_icu(), oddly enough, my machine didn't care, but I'm sure thats pure
luck.)
There is probably alot more sharing that can take place between these two
files, but I'm not sure how to accomplish it yet because of the PIC_XXX
options. That will be a TODO item.
 1.1.2.5 03-May-2007  garbled Move the functions down from openpic.c into pic_openpic.c, as there
really is no need to have them over there when all the interrupt routines
will be using pic_openpic.c
Change the openpic setup to set all the irqs except 0 to negative polarity.
Set the spurious vector reg to 0xff.
Emit a nice printf showing the version of the openpic, and getrid of the
maxint thing.
Add a global, primary_pic, so machines can elect any registered pic as
the primary interrupt controller.
Clean up a few nits in pic_prepivr to make it more similar to the openpic
one, add a prototype for the setup_prepivr function, etc etc.
 1.1.2.4 03-May-2007  nisimura - files.pic
allow to choose files as designated for Makefile.
- pic_openpic.c, pic_prepivr.c
remove #ifdef PIC_xxx constructs.
- pic_openpic.c
honour OPENPIC feature register NIRQ field for max. number of
available irqs. Valid for MPC107/MPC824x EPIC.
 1.1.2.3 03-May-2007  garbled Add pic_prepivr.c to this
 1.1.2.2 02-May-2007  macallan OpenPIC support
 1.1.2.1 02-May-2007  macallan first try on a generic interrupt handler.
Features:
- PIC details are hidden by struct pic_ops
- PICs can easily be cascaded
- support for soft interrupts
tested so far only on macppc with a PowerBook 3400c
 1.2.14.1 19-Jan-2008  bouyer Sync with HEAD
 1.2.8.3 23-Mar-2008  matt sync with HEAD
 1.2.8.2 06-Nov-2007  matt sync with HEAD
 1.2.8.1 17-Oct-2007  matt file files.pic was added on branch matt-armv6 on 2007-11-06 23:20:52 +0000
 1.2.6.1 18-Feb-2008  mjf Sync with HEAD.
 1.2.4.3 21-Jan-2008  yamt sync with head
 1.2.4.2 27-Oct-2007  yamt sync with head.
 1.2.4.1 17-Oct-2007  yamt file files.pic was added on branch yamt-lazymbuf on 2007-10-27 11:27:58 +0000
 1.2.2.2 23-Oct-2007  ad Sync with head.
 1.2.2.1 17-Oct-2007  ad file files.pic was added on branch vmlocking on 2007-10-23 20:36:16 +0000
 1.3.10.1 19-Aug-2009  yamt sync with head.
 1.4.10.1 23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.4.6.1 06-Jun-2011  jruoho Sync with HEAD.
 1.4.4.1 12-Jun-2011  rmind sync with head
 1.7 01-Feb-2012  matt Use kmem instead of malloc. Remove unneeded <sys/malloc.h> includes.
 1.6 20-Jun-2011  matt branches: 1.6.2; 1.6.6;
<arch/powerpc/... -> <powerpc/...
 1.5 18-Jun-2011  matt Use <sys/foo.h> instead of <machine/foo.h> if such a file exists.
Don't assume <sys/cpu.h> includes <powerpc/subarch/cpu*.h>. Include it
explicitly.
 1.4 28-Apr-2008  martin branches: 1.4.32;
Remove clause 3 and 4 from TNF licenses
 1.3 11-Dec-2007  garbled branches: 1.3.8; 1.3.10; 1.3.12;
Fix the endless stream of 7's problem on i8259-like interrupt controllers
once and for all. The i8259 does not like to be read in a loop, when an
interrupt comes in, it will return a valid value, however, if you keep
reading it until there are no outstanding interrupts, it will return 7
(which is the lpt interrupt). Change the pic handler to give an argument
to the get_irq functions of mode, which indicates if this is the first
time we are asking, or if we are just rechecking in a loop. Non-i8259
handlers can safely ignore this argument.

Tested to fix the stream of 7's problem on prep and ofppc. Got rid of
the nasty hack in ofppc with this too, and the prep machine seems to take
less interrupts now, which is a good thing.
 1.2 17-Oct-2007  garbled branches: 1.2.2; 1.2.4; 1.2.8; 1.2.10; 1.2.12; 1.2.14;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.1 09-May-2007  garbled branches: 1.1.2; 1.1.6; 1.1.8;
file i8259_common.c was initially added on branch ppcoea-renovation.
 1.1.8.1 18-Oct-2007  yamt sync with head.
 1.1.6.1 02-Nov-2007  joerg More diff reduce to HEAD due to botched up merging.
 1.1.2.2 10-Oct-2007  garbled Change pic_prepivr around a bit. Handle the default IRQ 7 from the 8259
better, and add a new motivr_get_irq(). The motorola machines require an
actual read from the 8259 for PCI irqs, so in that case, we read the
8259, and then read the IVR to ack the irq.

Move i8259_get_irq() to i8259_common.c for above.

Fix some minor typos in the chip id's for prep residual.

Fix ibmnws and prep to properly initialize the prep ivr depending on if
the machine is motorola, or IBM based.

Tested on a 7043 and an MTX604
 1.1.2.1 09-May-2007  garbled The i8259 and prepivr code had a bunch of functions that were duplicates
of one another. Break those out into i8259_common.c and share that file
between the two of them.
 1.2.14.1 13-Dec-2007  bouyer Sync with HEAD
 1.2.12.1 13-Dec-2007  yamt sync with head.
 1.2.10.1 26-Dec-2007  ad Sync with head.
 1.2.8.3 09-Jan-2008  matt sync with HEAD
 1.2.8.2 06-Nov-2007  matt sync with HEAD
 1.2.8.1 17-Oct-2007  matt file i8259_common.c was added on branch matt-armv6 on 2007-11-06 23:20:52 +0000
 1.2.4.3 21-Jan-2008  yamt sync with head
 1.2.4.2 27-Oct-2007  yamt sync with head.
 1.2.4.1 17-Oct-2007  yamt file i8259_common.c was added on branch yamt-lazymbuf on 2007-10-27 11:27:58 +0000
 1.2.2.2 23-Oct-2007  ad Sync with head.
 1.2.2.1 17-Oct-2007  ad file i8259_common.c was added on branch vmlocking on 2007-10-23 20:36:17 +0000
 1.3.12.1 16-May-2008  yamt sync with head.
 1.3.10.1 18-May-2008  yamt sync with head.
 1.3.8.1 02-Jun-2008  mjf Sync with HEAD.
 1.4.32.1 23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.6.6.1 18-Feb-2012  mrg merge to -current.
 1.6.2.1 17-Apr-2012  yamt sync with head
 1.38 05-Jul-2025  macallan add a function to find a PIC by its base address
 1.37 17-Feb-2025  jmcneill powerpc: Don't enable interrupts before calling cascaded intr handler.

Before calling a normal interrupt handler, the pic code adjusts cpl and
enables interrupts. Don't do this with interrupt sources that feed
cascaded pics as the resulting handler will do it anyway, and it can
result in multiple interrupts firing on the parent pic just to service
a single interrupt on the child.
 1.36 16-Feb-2025  jmcneill powerpc: Mask interrupts after returning from handler.

Now that we are explicitly masking interrupts on entry of pic_handle_intr,
we need to disable (instead of store) interrupts after calling
intr_deliver.
 1.35 15-Feb-2025  jmcneill powerpc: Fix ci_ipending corruption with cascaded pics

A cascaded pic will register pic_handle_intr as its interrupt handler,
but interrupt handlers are called with MSR[EE] = 1. This breaks
assumptions in pic callbacks and can result in eg. corrupt ci_ipending
due to a read/modify/write of the field with nested interrupts.

Fix this by always clearing MSR[EE] at the top of pic_handle_intr.
 1.34 16-Feb-2022  riastradh branches: 1.34.4; 1.34.10;
powerpc: Sprinkle "memory" clobbers on eieio and nearby asm blocks.

Otherwise the compiler may reorder these around loads and stores,
which mostly defeats the purpose. `asm volatile' just ensures the
instruction isn't _deleted_; it may still move around.
 1.33 23-Mar-2021  skrll KNF
 1.32 22-Mar-2021  rin Brush up previous, or make things more similar to x86:

- Prevent pic_name from appearing vmstat(1) twice.
- Restore "irq" in interrupt id fields of intrctl(8).

For these purposes,

- Add is_evname member to struct intr_source.
- Bump size of is_source to INTRIDBUF, and rename it to is_intrid for clarity.

Now, outputs from vmstat(1) and intrctl(8) are like:

----
$ vmstat -ev
...
openpic irq 39 3967 26 intr
...
$ intrctl list
interrupt id CPU0 device name(s)
...
openpic irq 39 3967* wdc1
...
----
 1.31 06-Mar-2021  rin branches: 1.31.2;
Include PIC name to interrupt source, instead of just "irq", so that
it appears in "interrupt id" field of intrctl(8).

Should be useful when multiple PICs are simultaneously available as in
405EX (where uic[12] are cascaded to uic0).
 1.30 02-Mar-2021  rin Turn imask into static.

XXX
Other macro etc. in powerpc/intr.h should also be moved into
powerpc/pic/intr.c, or protected by __INTR_PRIVATE.
 1.29 06-Jul-2020  rin branches: 1.29.2;
Include missing opt_ppcarch.h.
 1.28 06-Jul-2020  rin Style and cosmetic changes. No binary changes intended.
 1.27 20-Feb-2020  rin eieio is implemented as sync on 40x. Therefore, "sync; eieio" and
"eieio; sync" can be replaced by a single sync.
 1.26 03-Sep-2018  riastradh branches: 1.26.4; 1.26.6;
Rename min/max -> uimin/uimax for better honesty.

These functions are defined on unsigned int. The generic name
min/max should not silently truncate to 32 bits on 64-bit systems.
This is purely a name change -- no functional change intended.

HOWEVER! Some subsystems have

#define min(a, b) ((a) < (b) ? (a) : (b))
#define max(a, b) ((a) > (b) ? (a) : (b))

even though our standard name for that is MIN/MAX. Although these
may invite multiple evaluation bugs, these do _not_ cause integer
truncation.

To avoid `fixing' these cases, I first changed the name in libkern,
and then compile-tested every file where min/max occurred in order to
confirm that it failed -- and thus confirm that nothing shadowed
min/max -- before changing it.

I have left a handful of bootloaders that are too annoying to
compile-test, and some dead code:

cobalt ews4800mips hp300 hppa ia64 luna68k vax
acorn32/if_ie.c (not included in any kernels)
macppc/if_gm.c (superseded by gem(4))

It should be easy to fix the fallout once identified -- this way of
doing things fails safe, and the goal here, after all, is to _avoid_
silent integer truncations, not introduce them.

Maybe one day we can reintroduce min/max as type-generic things that
never silently truncate. But we should avoid doing that for a while,
so that existing code has a chance to be detected by the compiler for
conversion to uimin/uimax without changing the semantics until we can
properly audit it all. (Who knows, maybe in some cases integer
truncation is actually intended!)
 1.25 19-Oct-2016  nonaka branches: 1.25.14; 1.25.16;
Added MSI/MSI-X and interrupt_distribute(9) support for powerpc.
 1.24 26-May-2016  macallan branches: 1.24.2;
treat IPIs like regular interrupts at IPL_HIGH
should fix port-powerpc/44387
tested by chuq
 1.23 31-Aug-2012  macallan branches: 1.23.2; 1.23.16;
when calculating per-IPL virq masks, take into account that shared IRQs may
request different IPLs
fixes vr(4)-related problems seen on ofppc
 1.22 07-Jun-2012  macallan fix same thinko as in previous commit, in have_pending_intr_p()
 1.21 07-Jun-2012  macallan look at the right cpu_softints bits in pic_do_pending_int()
so we call the right softint handlers
 1.20 01-Feb-2012  matt branches: 1.20.2;
Use kmem instead of malloc. Remove unneeded <sys/malloc.h> includes.
 1.19 14-Jan-2012  phx Some PICs have the capability to define the interrupt's polarity (OpenPIC
for example). So the accepted interrupt types have been extended to:
- IST_EDGE_FALLING (which is the same as IST_EDGE)
- IST_EDGE_RISING (new)
- IST_LEVEL_LOW (is the same as IST_LEVEL)
- IST_LEVEL_HIGH (new)
Old code will continue to work without modification.
 1.18 27-Sep-2011  jym branches: 1.18.2; 1.18.6;
Modify *ASSERTMSG() so they are now used as variadic macros. The main goal
is to provide routines that do as KASSERT(9) says: append a message
to the panic format string when the assertion triggers, with optional
arguments.

Fix call sites to reflect the new definition.

Discussed on tech-kern@. See
http://mail-index.netbsd.org/tech-kern/2011/09/07/msg011427.html
 1.17 21-Jun-2011  rjs Make it compile when PIC_DEBUG is defined.
 1.16 20-Jun-2011  matt Cleanup includes. Explicitly include <powerpc/psl.h>
 1.15 17-Jun-2011  matt intr.h must not include cpu due to deadly embrace with SOFTINT_COUNT.
Cleanup intr.h so MD definitions can overload common definitions.
Rototill pic/intr.c. Virtual IRQs can now be reclaimed. separate virq
from hwirq from picirq. Redo intr mask calculations.
tested on pmppc and macppc (MP).
 1.14 17-Jun-2011  matt Change from level to ipl since we aren't dealing a mask anymore, just a
simple value.
Fix intr_calculatemasks to deal with ipl isn't a mask. Let establish
and disestablish determine the highest ipl for the interrut source being
modified. No reason to recompute that for every source when only one changes
at a time. Only change idepth while in the loop.
 1.13 16-Jun-2011  matt Make sure OEA ports without __HAVE_FAST_SOFTINTS still compile.
 1.12 16-Jun-2011  macallan enable FAST_SOFTINTR support for all ports that use powerpc/pic/
This has been successfully tested on macppc
TODO:
- ibm4xx needs to be adapted
- SMP doesn't work yet, 2nd CPU crashes when trying to leave the idle loop
 1.11 05-Jun-2011  matt Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.
 1.10 20-Dec-2010  matt branches: 1.10.2; 1.10.6;
Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits. Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.
 1.9 12-May-2010  macallan make this work again
 1.8 24-Apr-2010  kiyohara Support 64-bit imask for powerpc/pic.
 1.7 10-Mar-2010  kiyohara branches: 1.7.2;
Remove white-spaces.
 1.6 29-Apr-2008  martin branches: 1.6.20;
Convert to new 2 clause license
 1.5 08-Apr-2008  garbled branches: 1.5.2; 1.5.4;
SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.
 1.4 11-Dec-2007  garbled branches: 1.4.8;
Fix the endless stream of 7's problem on i8259-like interrupt controllers
once and for all. The i8259 does not like to be read in a loop, when an
interrupt comes in, it will return a valid value, however, if you keep
reading it until there are no outstanding interrupts, it will return 7
(which is the lpt interrupt). Change the pic handler to give an argument
to the get_irq functions of mode, which indicates if this is the first
time we are asking, or if we are just rechecking in a loop. Non-i8259
handlers can safely ignore this argument.

Tested to fix the stream of 7's problem on prep and ofppc. Got rid of
the nasty hack in ofppc with this too, and the prep machine seems to take
less interrupts now, which is a good thing.
 1.3 03-Dec-2007  ad branches: 1.3.2; 1.3.4; 1.3.6;
Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.
 1.2 17-Oct-2007  garbled branches: 1.2.2; 1.2.4; 1.2.6; 1.2.8;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.1 02-May-2007  macallan branches: 1.1.2; 1.1.6; 1.1.8;
file intr.c was initially added on branch ppcoea-renovation.
 1.1.8.1 18-Oct-2007  yamt sync with head.
 1.1.6.2 09-Dec-2007  jmcneill Sync with HEAD.
 1.1.6.1 02-Nov-2007  joerg More diff reduce to HEAD due to botched up merging.
 1.1.2.22 11-Oct-2007  macallan remove code that would restrict IRQs and softintrs to cpu0
 1.1.2.21 11-Oct-2007  macallan don't declare ipiops again
 1.1.2.20 10-Oct-2007  garbled New ppcoea-MI IPI infrastructure. This is similar to the PIC
infrastructure, but simplified greatly.

Also, convert macppc (the only port currently using IPI's) over to this new
infrastructure. Still some minor work left to do here.
 1.1.2.19 04-Oct-2007  macallan fix pasto - now we actually run IPIs on cpu0 again
 1.1.2.18 07-Sep-2007  macallan calculate interrupt maks after establishing the handler - otherwise the
last established IRQ handler would never be unblocked
 1.1.2.17 10-May-2007  garbled Change the biomask printf to aprint_normal.
 1.1.2.16 10-May-2007  garbled More cleanup:
1) Remove lcsplx, strayintr, and foosoft from all the converted ports.
None of this stuff is needed anymore.
2) because lcsplx is just "return spllower", just call spllower from
locore_subr.S instead.
3) Every port (except macppc) had a pretty similar cpu_configure(), so
take the common parts out and make a genppc_cpu_configure() in an attempt
to stop using imask[] outside of intr.c
 1.1.2.15 09-May-2007  matt Simplify intr_typename
 1.1.2.14 09-May-2007  macallan nuke #if(n)def __HAVE_GENERIC_SOFT_INTERRUPTS
 1.1.2.13 07-May-2007  garbled Rewrite how shared isa is done slightly. This will allow the individual
ports to override the shared functions if needed. Also, implement
isa_intr_alloc, which needed to be done inside pic/intr.c because it
needs access to structs which are static to the file.
 1.1.2.12 04-May-2007  nisimura follow up to the previous change for struct pic_ops, and make
pic_i8259.c compilable.
 1.1.2.11 04-May-2007  macallan adapt to picvar changes, call pic_establish_irq() with max priority in use on
the resp. IRQ
 1.1.2.10 03-May-2007  garbled Add splraise, splx, spllower and softintr here.
 1.1.2.9 03-May-2007  garbled Move the functions down from openpic.c into pic_openpic.c, as there
really is no need to have them over there when all the interrupt routines
will be using pic_openpic.c
Change the openpic setup to set all the irqs except 0 to negative polarity.
Set the spurious vector reg to 0xff.
Emit a nice printf showing the version of the openpic, and getrid of the
maxint thing.
Add a global, primary_pic, so machines can elect any registered pic as
the primary interrupt controller.
Clean up a few nits in pic_prepivr to make it more similar to the openpic
one, add a prototype for the setup_prepivr function, etc etc.
 1.1.2.8 03-May-2007  nisimura These two have no <machine/autoconf.h> dependency.
 1.1.2.7 03-May-2007  macallan add dummy establish_intr method
 1.1.2.6 03-May-2007  garbled Fix typo in pic_ack_irq
 1.1.2.5 03-May-2007  garbled Add some additional functions (pic_establish_irq) to enable use with an 8259
 1.1.2.4 03-May-2007  macallan remove pic_reenable_irq() from pic_handle_intr()
 1.1.2.3 03-May-2007  macallan fix some compiler warnings
 1.1.2.2 02-May-2007  macallan cosmetics:
- remove CPU number from pic_get_irq()
- add type parameter to enable/reenable
- add IRQ parameter to pic_ack_irq()
... and make intr.c compile again
 1.1.2.1 02-May-2007  macallan first try on a generic interrupt handler.
Features:
- PIC details are hidden by struct pic_ops
- PICs can easily be cascaded
- support for soft interrupts
tested so far only on macppc with a PowerBook 3400c
 1.2.8.3 09-Jan-2008  matt sync with HEAD
 1.2.8.2 06-Nov-2007  matt sync with HEAD
 1.2.8.1 17-Oct-2007  matt file intr.c was added on branch matt-armv6 on 2007-11-06 23:20:53 +0000
 1.2.6.2 27-Dec-2007  mjf Sync with HEAD.
 1.2.6.1 08-Dec-2007  mjf Sync with HEAD.
 1.2.4.4 21-Jan-2008  yamt sync with head
 1.2.4.3 07-Dec-2007  yamt sync with head
 1.2.4.2 27-Oct-2007  yamt sync with head.
 1.2.4.1 17-Oct-2007  yamt file intr.c was added on branch yamt-lazymbuf on 2007-10-27 11:27:59 +0000
 1.2.2.3 03-Dec-2007  ad Sync with HEAD.
 1.2.2.2 23-Oct-2007  ad Sync with head.
 1.2.2.1 17-Oct-2007  ad file intr.c was added on branch vmlocking on 2007-10-23 20:36:17 +0000
 1.3.6.1 13-Dec-2007  bouyer Sync with HEAD
 1.3.4.1 13-Dec-2007  yamt sync with head.
 1.3.2.1 26-Dec-2007  ad Sync with head.
 1.4.8.1 02-Jun-2008  mjf Sync with HEAD.
 1.5.4.2 11-Aug-2010  yamt sync with head.
 1.5.4.1 16-May-2008  yamt sync with head.
 1.5.2.1 18-May-2008  yamt sync with head.
 1.6.20.2 17-Aug-2010  uebayasi Sync with HEAD.
 1.6.20.1 30-Apr-2010  uebayasi Sync with HEAD.
 1.7.2.3 12-Jun-2011  rmind sync with head
 1.7.2.2 05-Mar-2011  rmind sync with head
 1.7.2.1 30-May-2010  rmind sync with head
 1.10.6.1 23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.10.2.1 06-Jun-2011  jruoho Sync with HEAD.
 1.18.6.1 18-Feb-2012  mrg merge to -current.
 1.18.2.2 30-Oct-2012  yamt sync with head
 1.18.2.1 17-Apr-2012  yamt sync with head
 1.20.2.2 03-Sep-2012  riz Pull up following revision(s) (requested by macallan in ticket #535):
sys/arch/powerpc/pic/intr.c: revision 1.23
when calculating per-IPL virq masks, take into account that shared =20
IRQs may
request different IPLs
fixes vr(4)-related problems seen on ofppc
 1.20.2.1 12-Jun-2012  riz branches: 1.20.2.1.2;
Pull up following revision(s) (requested by macallan in ticket #320):
sys/arch/powerpc/pic/intr.c: revision 1.21
sys/arch/powerpc/pic/intr.c: revision 1.22
look at the right cpu_softints bits in pic_do_pending_int()
so we call the right softint handlers
fix same thinko as in previous commit, in have_pending_intr_p()
 1.20.2.1.2.1 01-Nov-2012  matt sync with netbsd-6-0-RELEASE.
 1.23.16.2 05-Dec-2016  skrll Sync with HEAD
 1.23.16.1 29-May-2016  skrll Sync with HEAD
 1.23.2.1 03-Dec-2017  jdolecek update from HEAD
 1.24.2.1 04-Nov-2016  pgoyette Sync with HEAD
 1.25.16.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.25.16.1 10-Jun-2019  christos Sync with HEAD
 1.25.14.1 06-Sep-2018  pgoyette Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)
 1.26.6.1 29-Feb-2020  ad Sync with head.
 1.26.4.1 25-Feb-2020  martin Pull up following revision(s) (requested by rin in ticket #730):

sys/arch/powerpc/conf/files.powerpc: revision 1.93
sys/arch/powerpc/include/pio.h: revision 1.8
sys/arch/powerpc/pic/intr.c: revision 1.27
sys/arch/powerpc/powerpc/bus_dma.c: revision 1.50
sys/arch/powerpc/powerpc/pio_subr.S: revision 1.17

Add PPC_IBM440 flag as 440 is significantly different from 40x processors.
(It may be more easily supported by booke than by ibm4xx.)

-

eieio is implemented as sync on 40x. Therefore, "sync; eieio" and
"eieio; sync" can be replaced by a single sync.
 1.29.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.31.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.34.10.1 02-Aug-2025  perseant Sync with HEAD
 1.34.4.1 22-Feb-2025  martin Pull up following revision(s) (requested by jmcneill in ticket #1056):

sys/arch/powerpc/pic/intr.c: revision 1.35
sys/arch/powerpc/pic/intr.c: revision 1.36
sys/arch/powerpc/pic/intr.c: revision 1.37
sys/arch/powerpc/pic/picvar.h: revision 1.14

powerpc: Fix ci_ipending corruption with cascaded pics
A cascaded pic will register pic_handle_intr as its interrupt handler,
but interrupt handlers are called with MSR[EE] = 1. This breaks
assumptions in pic callbacks and can result in eg. corrupt ci_ipending
due to a read/modify/write of the field with nested interrupts.

Fix this by always clearing MSR[EE] at the top of pic_handle_intr.

powerpc: Mask interrupts after returning from handler.
Now that we are explicitly masking interrupts on entry of pic_handle_intr,
we need to disable (instead of store) interrupts after calling
intr_deliver.

powerpc: Don't enable interrupts before calling cascaded intr handler.
Before calling a normal interrupt handler, the pic code adjusts cpl and
enables interrupts. Don't do this with interrupt sources that feed
cascaded pics as the resulting handler will do it anyway, and it can
result in multiple interrupts firing on the parent pic just to service
a single interrupt on the child.
 1.16 06-Jul-2020  rin Drop unused opt_altivec.h, opt_interrupt.h, opt_ipi.h, and opt_pic.h.
 1.15 06-Jul-2020  rin Style and cosmetic changes. No binary changes intended.
 1.14 01-Dec-2019  ad Fix false sharing problems with cpu_info. Identified with tprof(8).
This was a very nice win in my tests on a 48 CPU box.

- Reorganise cpu_data slightly according to usage.
- Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc).
- On x86, put some items in their own cache lines according to usage, like
the IPI bitmask and ci_want_resched.
 1.13 24-Nov-2019  ad Add IPI_AST.
 1.12 23-Jan-2015  nonaka branches: 1.12.18;
ddb MP support
 1.11 19-May-2014  rmind branches: 1.11.4;
Implement MI IPI interface with cross-call support.
 1.10 20-Jun-2011  matt branches: 1.10.12; 1.10.26;
Cleanup includes. Explicitly include <powerpc/psl.h>
 1.9 05-Jun-2011  matt Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.
 1.8 02-May-2011  matt branches: 1.8.2;
Move powerpc to use pcu to manage FPU/AltiVec/SPE.
 1.7 18-Jan-2011  matt Fix some fallout from building the macppc GENERIC.MP.
 1.6 25-Jun-2010  rmind branches: 1.6.2;
Add missing sys/xcall.h inclusion, remove sys/malloc.h one.
 1.5 22-Jun-2010  rmind Implement high priority (XC_HIGHPRI) xcall(9) mechanism - a facility
to execute functions from software interrupt context, at SOFTINT_CLOCK.
Functions must be lightweight. Will be used for passive serialization.

OK ad@.
 1.4 28-Apr-2008  martin branches: 1.4.20; 1.4.22;
Remove clause 3 and 4 from TNF licenses
 1.3 08-Apr-2008  garbled branches: 1.3.2; 1.3.4;
SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.
 1.2 17-Oct-2007  garbled branches: 1.2.2; 1.2.4; 1.2.6; 1.2.8; 1.2.12; 1.2.26;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.1 10-Oct-2007  garbled branches: 1.1.2;
file ipi.c was initially added on branch ppcoea-renovation.
 1.1.2.1 10-Oct-2007  garbled New ppcoea-MI IPI infrastructure. This is similar to the PIC
infrastructure, but simplified greatly.

Also, convert macppc (the only port currently using IPI's) over to this new
infrastructure. Still some minor work left to do here.
 1.2.26.1 02-Jun-2008  mjf Sync with HEAD.
 1.2.12.2 06-Nov-2007  matt sync with HEAD
 1.2.12.1 17-Oct-2007  matt file ipi.c was added on branch matt-armv6 on 2007-11-06 23:20:54 +0000
 1.2.8.2 02-Nov-2007  joerg More diff reduce to HEAD due to botched up merging.
 1.2.8.1 17-Oct-2007  joerg file ipi.c was added on branch jmcneill-pm on 2007-11-02 13:34:46 +0000
 1.2.6.2 27-Oct-2007  yamt sync with head.
 1.2.6.1 17-Oct-2007  yamt file ipi.c was added on branch yamt-lazymbuf on 2007-10-27 11:27:59 +0000
 1.2.4.2 23-Oct-2007  ad Sync with head.
 1.2.4.1 17-Oct-2007  ad file ipi.c was added on branch vmlocking on 2007-10-23 20:36:18 +0000
 1.2.2.2 18-Oct-2007  yamt sync with head.
 1.2.2.1 17-Oct-2007  yamt file ipi.c was added on branch yamt-x86pmap on 2007-10-18 08:32:45 +0000
 1.3.4.2 11-Aug-2010  yamt sync with head.
 1.3.4.1 16-May-2008  yamt sync with head.
 1.3.2.1 18-May-2008  yamt sync with head.
 1.4.22.4 12-Jun-2011  rmind sync with head
 1.4.22.3 31-May-2011  rmind sync with head
 1.4.22.2 05-Mar-2011  rmind sync with head
 1.4.22.1 03-Jul-2010  rmind sync with head
 1.4.20.1 17-Aug-2010  uebayasi Sync with HEAD.
 1.6.2.1 06-Jun-2011  jruoho Sync with HEAD.
 1.8.2.1 23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.10.26.1 10-Aug-2014  tls Rebase.
 1.10.12.2 03-Dec-2017  jdolecek update from HEAD
 1.10.12.1 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.11.4.1 06-Apr-2015  skrll Sync with HEAD
 1.12.18.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.10 05-Mar-2021  rin Convert to intr_establish_xname().
 1.9 06-Jul-2020  rin branches: 1.9.2;
Style and cosmetic changes. No binary changes intended.
 1.8 26-May-2016  macallan treat IPIs like regular interrupts at IPL_HIGH
should fix port-powerpc/44387
tested by chuq
 1.7 01-Feb-2012  matt branches: 1.7.6; 1.7.24;
Use kmem instead of malloc. Remove unneeded <sys/malloc.h> includes.
 1.6 20-Jun-2011  matt branches: 1.6.2; 1.6.6;
<arch/powerpc/... -> <powerpc/...
 1.5 05-Jun-2011  matt Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.
 1.4 28-Apr-2008  martin branches: 1.4.22; 1.4.28; 1.4.32;
Remove clause 3 and 4 from TNF licenses
 1.3 08-Apr-2008  garbled branches: 1.3.2; 1.3.4;
SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.
 1.2 17-Oct-2007  garbled branches: 1.2.2; 1.2.4; 1.2.6; 1.2.8; 1.2.12; 1.2.26;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.1 10-Oct-2007  garbled branches: 1.1.2;
file ipi_openpic.c was initially added on branch ppcoea-renovation.
 1.1.2.2 10-Oct-2007  macallan - move IPI setup to ipi_openpic
- some cleanup
 1.1.2.1 10-Oct-2007  garbled New ppcoea-MI IPI infrastructure. This is similar to the PIC
infrastructure, but simplified greatly.

Also, convert macppc (the only port currently using IPI's) over to this new
infrastructure. Still some minor work left to do here.
 1.2.26.1 02-Jun-2008  mjf Sync with HEAD.
 1.2.12.2 06-Nov-2007  matt sync with HEAD
 1.2.12.1 17-Oct-2007  matt file ipi_openpic.c was added on branch matt-armv6 on 2007-11-06 23:20:54 +0000
 1.2.8.2 02-Nov-2007  joerg More diff reduce to HEAD due to botched up merging.
 1.2.8.1 17-Oct-2007  joerg file ipi_openpic.c was added on branch jmcneill-pm on 2007-11-02 13:34:46 +0000
 1.2.6.2 27-Oct-2007  yamt sync with head.
 1.2.6.1 17-Oct-2007  yamt file ipi_openpic.c was added on branch yamt-lazymbuf on 2007-10-27 11:27:59 +0000
 1.2.4.2 23-Oct-2007  ad Sync with head.
 1.2.4.1 17-Oct-2007  ad file ipi_openpic.c was added on branch vmlocking on 2007-10-23 20:36:19 +0000
 1.2.2.2 18-Oct-2007  yamt sync with head.
 1.2.2.1 17-Oct-2007  yamt file ipi_openpic.c was added on branch yamt-x86pmap on 2007-10-18 08:32:46 +0000
 1.3.4.1 16-May-2008  yamt sync with head.
 1.3.2.1 18-May-2008  yamt sync with head.
 1.4.32.1 23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.4.28.1 06-Jun-2011  jruoho Sync with HEAD.
 1.4.22.1 12-Jun-2011  rmind sync with head
 1.6.6.1 18-Feb-2012  mrg merge to -current.
 1.6.2.1 17-Apr-2012  yamt sync with head
 1.7.24.1 29-May-2016  skrll Sync with HEAD
 1.7.6.1 03-Dec-2017  jdolecek update from HEAD
 1.9.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.12 16-Apr-2020  rin Revert previous for now:
http://mail-index.netbsd.org/source-changes/2020/04/16/msg116278.html

The reasoning turned out to be wrong; __KERNEL_RCSID() in header files
does *not* overwrite RCSID in main source files. The real problem is that
it inserts its RCSID into *every* object files. However, it can be still
useful even if heavily duplicated.
 1.11 16-Apr-2020  rin Stop using __KERNEL_RCSID() in header files; it confuses ident(1) by
overwriting RCSID in main source files.

XXX
The first argument of __KERNEL_RCSID() is neglected for ELF. If we wish
to have RCSID of header files in kernel binary, we need something like
__FBSDID() macro in FreeBSD.
 1.10 24-Nov-2019  ad branches: 1.10.6;
Add IPI_AST.
 1.9 19-Apr-2018  christos branches: 1.9.2;
s/static inline/static __inline/g for consistency.
 1.8 23-Jan-2015  nonaka branches: 1.8.16;
ddb MP support
 1.7 19-May-2014  rmind branches: 1.7.4;
Implement MI IPI interface with cross-call support.
 1.6 13-Oct-2011  matt branches: 1.6.12; 1.6.26;
Don't declare cpu_send_ipi if BOOKE
 1.5 05-Jun-2011  matt Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.
 1.4 22-Jun-2010  rmind branches: 1.4.2; 1.4.6;
Implement high priority (XC_HIGHPRI) xcall(9) mechanism - a facility
to execute functions from software interrupt context, at SOFTINT_CLOCK.
Functions must be lightweight. Will be used for passive serialization.

OK ad@.
 1.3 28-Apr-2008  martin branches: 1.3.20; 1.3.22;
Remove clause 3 and 4 from TNF licenses
 1.2 17-Oct-2007  garbled branches: 1.2.2; 1.2.4; 1.2.6; 1.2.8; 1.2.12; 1.2.26; 1.2.28; 1.2.30;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.1 10-Oct-2007  garbled branches: 1.1.2;
file ipivar.h was initially added on branch ppcoea-renovation.
 1.1.2.2 11-Oct-2007  macallan convenience
 1.1.2.1 10-Oct-2007  garbled New ppcoea-MI IPI infrastructure. This is similar to the PIC
infrastructure, but simplified greatly.

Also, convert macppc (the only port currently using IPI's) over to this new
infrastructure. Still some minor work left to do here.
 1.2.30.2 11-Aug-2010  yamt sync with head.
 1.2.30.1 16-May-2008  yamt sync with head.
 1.2.28.1 18-May-2008  yamt sync with head.
 1.2.26.1 02-Jun-2008  mjf Sync with HEAD.
 1.2.12.2 06-Nov-2007  matt sync with HEAD
 1.2.12.1 17-Oct-2007  matt file ipivar.h was added on branch matt-armv6 on 2007-11-06 23:20:55 +0000
 1.2.8.2 02-Nov-2007  joerg More diff reduce to HEAD due to botched up merging.
 1.2.8.1 17-Oct-2007  joerg file ipivar.h was added on branch jmcneill-pm on 2007-11-02 13:34:47 +0000
 1.2.6.2 27-Oct-2007  yamt sync with head.
 1.2.6.1 17-Oct-2007  yamt file ipivar.h was added on branch yamt-lazymbuf on 2007-10-27 11:28:00 +0000
 1.2.4.2 23-Oct-2007  ad Sync with head.
 1.2.4.1 17-Oct-2007  ad file ipivar.h was added on branch vmlocking on 2007-10-23 20:36:20 +0000
 1.2.2.2 18-Oct-2007  yamt sync with head.
 1.2.2.1 17-Oct-2007  yamt file ipivar.h was added on branch yamt-x86pmap on 2007-10-18 08:32:46 +0000
 1.3.22.2 12-Jun-2011  rmind sync with head
 1.3.22.1 03-Jul-2010  rmind sync with head
 1.3.20.1 17-Aug-2010  uebayasi Sync with HEAD.
 1.4.6.1 23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.4.2.1 06-Jun-2011  jruoho Sync with HEAD.
 1.6.26.1 10-Aug-2014  tls Rebase.
 1.6.12.2 03-Dec-2017  jdolecek update from HEAD
 1.6.12.1 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.7.4.1 06-Apr-2015  skrll Sync with HEAD
 1.8.16.1 22-Apr-2018  pgoyette Sync with HEAD
 1.9.2.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.10.6.1 20-Apr-2020  bouyer Sync with HEAD
 1.9 06-Jul-2020  rin Drop unused opt_interrupt.h.
 1.8 06-Jul-2020  rin Style and cosmetic changes. No binary changes intended.
 1.7 19-Sep-2013  christos use ci_index.
 1.6 01-Feb-2012  matt branches: 1.6.6; 1.6.10;
Use kmem instead of malloc. Remove unneeded <sys/malloc.h> includes.
 1.5 20-Jun-2011  matt branches: 1.5.2; 1.5.6;
<arch/powerpc/... -> <powerpc/...
 1.4 05-Jun-2011  matt Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.
 1.3 29-Apr-2008  martin branches: 1.3.22; 1.3.28; 1.3.32;
Convert to new 2 clause license
 1.2 08-Apr-2008  garbled branches: 1.2.2; 1.2.4;
SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.
 1.1 17-Jan-2008  garbled branches: 1.1.2; 1.1.4; 1.1.6; 1.1.12; 1.1.14;
Add support to ofppc for the IBM 7044-270 machine. This is a POWER3-II
based machine. Currently the kernel to run on this machine is
incompatible with the standard GENERIC kernel, so for now, we have a
separate GENERIC_B64. Eventually, I hope to combine the two.

Please note, this is a port of 32bit ofppc, not a powerpc64 port.

Thanks to Matt Thomas and Kevin Bowling for helping to make this port
possible.

Summary of changes:

Change ofwpci to use the ofmethod config for configuring the PCI bus,
rather than indirect configuration.
Move the wiring of the interrupt controllers from at the start of the
boot, into the configuration of the first PCI bus.
Rewrite the map_isa_ioregs() hack to work on a machine without BATs
Fix a ton of bugs in the genofw_find_pics routine, and in the map_space code.
Split the pic_openpic into openpic_common and pic_openpic.
Create a new pic_distopenpic driver, for the distributed openpic found on
some newer IBM machines.
Fix a bad panic in pmap_extract on 64bit bridge mode
 1.1.14.2 23-Mar-2008  matt sync with HEAD
 1.1.14.1 17-Jan-2008  matt file openpic_common.c was added on branch matt-armv6 on 2008-03-23 02:04:18 +0000
 1.1.12.1 02-Jun-2008  mjf Sync with HEAD.
 1.1.6.2 18-Feb-2008  mjf Sync with HEAD.
 1.1.6.1 17-Jan-2008  mjf file openpic_common.c was added on branch mjf-devfs on 2008-02-18 21:04:58 +0000
 1.1.4.2 21-Jan-2008  yamt sync with head
 1.1.4.1 17-Jan-2008  yamt file openpic_common.c was added on branch yamt-lazymbuf on 2008-01-21 09:38:26 +0000
 1.1.2.2 19-Jan-2008  bouyer Sync with HEAD
 1.1.2.1 17-Jan-2008  bouyer file openpic_common.c was added on branch bouyer-xeni386 on 2008-01-19 12:14:42 +0000
 1.2.4.1 16-May-2008  yamt sync with head.
 1.2.2.1 18-May-2008  yamt sync with head.
 1.3.32.1 23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.3.28.1 06-Jun-2011  jruoho Sync with HEAD.
 1.3.22.1 12-Jun-2011  rmind sync with head
 1.5.6.1 18-Feb-2012  mrg merge to -current.
 1.5.2.2 22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.5.2.1 17-Apr-2012  yamt sync with head
 1.6.10.1 18-May-2014  rmind sync with head
 1.6.6.1 20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.14 23-Feb-2022  andvar fix various typos in comments, mainly immediatly/immediately/,
as well shared and recently fixed typos in OpenBSD code by Jonathan Grey.
 1.13 06-Jul-2020  rin Drop unused opt_interrupt.h.
 1.12 06-Jul-2020  rin Style and cosmetic changes. No binary changes intended.
 1.11 03-Sep-2018  riastradh Rename min/max -> uimin/uimax for better honesty.

These functions are defined on unsigned int. The generic name
min/max should not silently truncate to 32 bits on 64-bit systems.
This is purely a name change -- no functional change intended.

HOWEVER! Some subsystems have

#define min(a, b) ((a) < (b) ? (a) : (b))
#define max(a, b) ((a) > (b) ? (a) : (b))

even though our standard name for that is MIN/MAX. Although these
may invite multiple evaluation bugs, these do _not_ cause integer
truncation.

To avoid `fixing' these cases, I first changed the name in libkern,
and then compile-tested every file where min/max occurred in order to
confirm that it failed -- and thus confirm that nothing shadowed
min/max -- before changing it.

I have left a handful of bootloaders that are too annoying to
compile-test, and some dead code:

cobalt ews4800mips hp300 hppa ia64 luna68k vax
acorn32/if_ie.c (not included in any kernels)
macppc/if_gm.c (superseded by gem(4))

It should be easy to fix the fallout once identified -- this way of
doing things fails safe, and the goal here, after all, is to _avoid_
silent integer truncations, not introduce them.

Maybe one day we can reintroduce min/max as type-generic things that
never silently truncate. But we should avoid doing that for a while,
so that existing code has a chance to be detected by the compiler for
conversion to uimin/uimax without changing the semantics until we can
properly audit it all. (Who knows, maybe in some cases integer
truncation is actually intended!)
 1.10 01-Jun-2017  chs branches: 1.10.8; 1.10.10;
remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.
 1.9 01-Feb-2012  matt branches: 1.9.6; 1.9.24;
Use kmem instead of malloc. Remove unneeded <sys/malloc.h> includes.
 1.8 14-Jan-2012  phx Some PICs have the capability to define the interrupt's polarity (OpenPIC
for example). So the accepted interrupt types have been extended to:
- IST_EDGE_FALLING (which is the same as IST_EDGE)
- IST_EDGE_RISING (new)
- IST_LEVEL_LOW (is the same as IST_LEVEL)
- IST_LEVEL_HIGH (new)
Old code will continue to work without modification.
 1.7 02-Jul-2011  mrg branches: 1.7.2; 1.7.6;
avoid some uninitialised variable warnings from GCC 4.5. i'm pretty
sure they can't happen in practise, but i can see why GCC isn't sure.
 1.6 20-Jun-2011  matt <arch/powerpc/... -> <powerpc/...
 1.5 05-Jun-2011  matt Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.
 1.4 10-May-2008  martin branches: 1.4.20; 1.4.26; 1.4.30;
Backout previous: the license sweep touched these files in error, so
restore the old license.
 1.3 29-Apr-2008  martin branches: 1.3.2;
Convert to new 2 clause license
 1.2 08-Apr-2008  garbled SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.
 1.1 17-Jan-2008  garbled branches: 1.1.2; 1.1.4; 1.1.6; 1.1.12; 1.1.14;
Add support to ofppc for the IBM 7044-270 machine. This is a POWER3-II
based machine. Currently the kernel to run on this machine is
incompatible with the standard GENERIC kernel, so for now, we have a
separate GENERIC_B64. Eventually, I hope to combine the two.

Please note, this is a port of 32bit ofppc, not a powerpc64 port.

Thanks to Matt Thomas and Kevin Bowling for helping to make this port
possible.

Summary of changes:

Change ofwpci to use the ofmethod config for configuring the PCI bus,
rather than indirect configuration.
Move the wiring of the interrupt controllers from at the start of the
boot, into the configuration of the first PCI bus.
Rewrite the map_isa_ioregs() hack to work on a machine without BATs
Fix a ton of bugs in the genofw_find_pics routine, and in the map_space code.
Split the pic_openpic into openpic_common and pic_openpic.
Create a new pic_distopenpic driver, for the distributed openpic found on
some newer IBM machines.
Fix a bad panic in pmap_extract on 64bit bridge mode
 1.1.14.2 23-Mar-2008  matt sync with HEAD
 1.1.14.1 17-Jan-2008  matt file pic_distopenpic.c was added on branch matt-armv6 on 2008-03-23 02:04:18 +0000
 1.1.12.1 02-Jun-2008  mjf Sync with HEAD.
 1.1.6.2 18-Feb-2008  mjf Sync with HEAD.
 1.1.6.1 17-Jan-2008  mjf file pic_distopenpic.c was added on branch mjf-devfs on 2008-02-18 21:04:58 +0000
 1.1.4.2 21-Jan-2008  yamt sync with head
 1.1.4.1 17-Jan-2008  yamt file pic_distopenpic.c was added on branch yamt-lazymbuf on 2008-01-21 09:38:27 +0000
 1.1.2.2 19-Jan-2008  bouyer Sync with HEAD
 1.1.2.1 17-Jan-2008  bouyer file pic_distopenpic.c was added on branch bouyer-xeni386 on 2008-01-19 12:14:43 +0000
 1.3.2.1 23-Jun-2008  wrstuden Sync w/ -current. 34 merge conflicts to follow.
 1.4.30.1 23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.4.26.1 06-Jun-2011  jruoho Sync with HEAD.
 1.4.20.1 12-Jun-2011  rmind sync with head
 1.7.6.1 18-Feb-2012  mrg merge to -current.
 1.7.2.1 17-Apr-2012  yamt sync with head
 1.9.24.1 28-Aug-2017  skrll Sync with HEAD
 1.9.6.1 03-Dec-2017  jdolecek update from HEAD
 1.10.10.1 10-Jun-2019  christos Sync with HEAD
 1.10.8.1 06-Sep-2018  pgoyette Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)
 1.7 01-Jun-2017  chs remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.
 1.6 01-Feb-2012  matt branches: 1.6.6; 1.6.24;
Use kmem instead of malloc. Remove unneeded <sys/malloc.h> includes.
 1.5 20-Jun-2011  matt branches: 1.5.2; 1.5.6;
<arch/powerpc/... -> <powerpc/...
 1.4 18-Jun-2011  matt Use <sys/foo.h> instead of <machine/foo.h> if such a file exists.
Don't assume <sys/cpu.h> includes <powerpc/subarch/cpu*.h>. Include it
explicitly.
 1.3 28-Apr-2008  martin branches: 1.3.32;
Remove clause 3 and 4 from TNF licenses
 1.2 17-Oct-2007  garbled branches: 1.2.2; 1.2.4; 1.2.8; 1.2.22; 1.2.24; 1.2.26;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.1 04-May-2007  garbled branches: 1.1.2; 1.1.6; 1.1.8;
file pic_i8259.c was initially added on branch ppcoea-renovation.
 1.1.8.1 18-Oct-2007  yamt sync with head.
 1.1.6.1 02-Nov-2007  joerg More diff reduce to HEAD due to botched up merging.
 1.1.2.5 11-Oct-2007  macallan add NULL pic_finish_setup()
 1.1.2.4 10-Oct-2007  garbled Change pic_prepivr around a bit. Handle the default IRQ 7 from the 8259
better, and add a new motivr_get_irq(). The motorola machines require an
actual read from the 8259 for PCI irqs, so in that case, we read the
8259, and then read the IVR to ack the irq.

Move i8259_get_irq() to i8259_common.c for above.

Fix some minor typos in the chip id's for prep residual.

Fix ibmnws and prep to properly initialize the prep ivr depending on if
the machine is motorola, or IBM based.

Tested on a 7043 and an MTX604
 1.1.2.3 09-May-2007  garbled The i8259 and prepivr code had a bunch of functions that were duplicates
of one another. Break those out into i8259_common.c and share that file
between the two of them.
 1.1.2.2 04-May-2007  nisimura follow up to the previous change for struct pic_ops, and make
pic_i8259.c compilable.
 1.1.2.1 04-May-2007  garbled Add an i8259 pic. Compile tested only.
Add 8259 initialization code to prepivr. (Forgot to add this when I nuked
init_icu(), oddly enough, my machine didn't care, but I'm sure thats pure
luck.)
There is probably alot more sharing that can take place between these two
files, but I'm not sure how to accomplish it yet because of the PIC_XXX
options. That will be a TODO item.
 1.2.26.1 16-May-2008  yamt sync with head.
 1.2.24.1 18-May-2008  yamt sync with head.
 1.2.22.1 02-Jun-2008  mjf Sync with HEAD.
 1.2.8.2 06-Nov-2007  matt sync with HEAD
 1.2.8.1 17-Oct-2007  matt file pic_i8259.c was added on branch matt-armv6 on 2007-11-06 23:20:56 +0000
 1.2.4.2 27-Oct-2007  yamt sync with head.
 1.2.4.1 17-Oct-2007  yamt file pic_i8259.c was added on branch yamt-lazymbuf on 2007-10-27 11:28:00 +0000
 1.2.2.2 23-Oct-2007  ad Sync with head.
 1.2.2.1 17-Oct-2007  ad file pic_i8259.c was added on branch vmlocking on 2007-10-23 20:36:20 +0000
 1.3.32.1 23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.5.6.1 18-Feb-2012  mrg merge to -current.
 1.5.2.1 17-Apr-2012  yamt sync with head
 1.6.24.1 28-Aug-2017  skrll Sync with HEAD
 1.6.6.1 03-Dec-2017  jdolecek update from HEAD
 1.9 23-Feb-2022  andvar fix various typos in comments, mainly immediatly/immediately/,
as well shared and recently fixed typos in OpenBSD code by Jonathan Grey.
 1.8 06-Jul-2020  rin Style and cosmetic changes. No binary changes intended.
 1.7 03-Sep-2018  riastradh Rename min/max -> uimin/uimax for better honesty.

These functions are defined on unsigned int. The generic name
min/max should not silently truncate to 32 bits on 64-bit systems.
This is purely a name change -- no functional change intended.

HOWEVER! Some subsystems have

#define min(a, b) ((a) < (b) ? (a) : (b))
#define max(a, b) ((a) > (b) ? (a) : (b))

even though our standard name for that is MIN/MAX. Although these
may invite multiple evaluation bugs, these do _not_ cause integer
truncation.

To avoid `fixing' these cases, I first changed the name in libkern,
and then compile-tested every file where min/max occurred in order to
confirm that it failed -- and thus confirm that nothing shadowed
min/max -- before changing it.

I have left a handful of bootloaders that are too annoying to
compile-test, and some dead code:

cobalt ews4800mips hp300 hppa ia64 luna68k vax
acorn32/if_ie.c (not included in any kernels)
macppc/if_gm.c (superseded by gem(4))

It should be easy to fix the fallout once identified -- this way of
doing things fails safe, and the goal here, after all, is to _avoid_
silent integer truncations, not introduce them.

Maybe one day we can reintroduce min/max as type-generic things that
never silently truncate. But we should avoid doing that for a while,
so that existing code has a chance to be detected by the compiler for
conversion to uimin/uimax without changing the semantics until we can
properly audit it all. (Who knows, maybe in some cases integer
truncation is actually intended!)
 1.6 01-Jun-2017  chs branches: 1.6.8; 1.6.10;
remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.
 1.5 01-Feb-2012  matt branches: 1.5.6; 1.5.24;
Use kmem instead of malloc. Remove unneeded <sys/malloc.h> includes.
 1.4 01-Feb-2012  matt Use C89 function prototypes.
 1.3 14-Jan-2012  phx Some PICs have the capability to define the interrupt's polarity (OpenPIC
for example). So the accepted interrupt types have been extended to:
- IST_EDGE_FALLING (which is the same as IST_EDGE)
- IST_EDGE_RISING (new)
- IST_LEVEL_LOW (is the same as IST_LEVEL)
- IST_LEVEL_HIGH (new)
Old code will continue to work without modification.
 1.2 20-Jun-2011  matt branches: 1.2.2; 1.2.6;
<arch/powerpc/... -> <powerpc/...
 1.1 19-Aug-2009  nisimura branches: 1.1.2; 1.1.12;
- Have pic_mpcsoc.c to adapt variations of Moto/Freescale OpenPIC
compliant interrupt controllers. Mostly the refrain of pic_openpic.c
and shall be useful for 85xx/86xx/QorIQ and Tundra product lines.
 1.1.12.1 23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.1.2.2 19-Aug-2009  yamt sync with head.
 1.1.2.1 19-Aug-2009  yamt file pic_mpcsoc.c was added on branch yamt-nfs-mp on 2009-08-19 18:46:41 +0000
 1.2.6.1 18-Feb-2012  mrg merge to -current.
 1.2.2.1 17-Apr-2012  yamt sync with head
 1.5.24.1 28-Aug-2017  skrll Sync with HEAD
 1.5.6.1 03-Dec-2017  jdolecek update from HEAD
 1.6.10.1 10-Jun-2019  christos Sync with HEAD
 1.6.8.1 06-Sep-2018  pgoyette Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)
 1.20 23-Feb-2022  andvar fix various typos in comments, mainly immediatly/immediately/,
as well shared and recently fixed typos in OpenBSD code by Jonathan Grey.
 1.19 13-Jul-2020  rin Drop unused opt_interrupt.h include.
 1.18 12-Jul-2020  rin No need to test _KERNEL_OPT twice.
No binary changes.
 1.17 06-Jul-2020  rin Include missing opt_multiprocessor.h.
 1.16 06-Jul-2020  rin Style and cosmetic changes. No binary changes intended.
 1.15 03-Sep-2018  riastradh Rename min/max -> uimin/uimax for better honesty.

These functions are defined on unsigned int. The generic name
min/max should not silently truncate to 32 bits on 64-bit systems.
This is purely a name change -- no functional change intended.

HOWEVER! Some subsystems have

#define min(a, b) ((a) < (b) ? (a) : (b))
#define max(a, b) ((a) > (b) ? (a) : (b))

even though our standard name for that is MIN/MAX. Although these
may invite multiple evaluation bugs, these do _not_ cause integer
truncation.

To avoid `fixing' these cases, I first changed the name in libkern,
and then compile-tested every file where min/max occurred in order to
confirm that it failed -- and thus confirm that nothing shadowed
min/max -- before changing it.

I have left a handful of bootloaders that are too annoying to
compile-test, and some dead code:

cobalt ews4800mips hp300 hppa ia64 luna68k vax
acorn32/if_ie.c (not included in any kernels)
macppc/if_gm.c (superseded by gem(4))

It should be easy to fix the fallout once identified -- this way of
doing things fails safe, and the goal here, after all, is to _avoid_
silent integer truncations, not introduce them.

Maybe one day we can reintroduce min/max as type-generic things that
never silently truncate. But we should avoid doing that for a while,
so that existing code has a chance to be detected by the compiler for
conversion to uimin/uimax without changing the semantics until we can
properly audit it all. (Who knows, maybe in some cases integer
truncation is actually intended!)
 1.14 16-May-2018  macallan branches: 1.14.2;
special case IPIs so we don't mess with hardware IRQ sources
now SMP works on my PCI-X G5
 1.13 22-Mar-2018  macallan don't call mapiodev() - the caller should hand us a usable address
 1.12 02-Mar-2018  macallan branches: 1.12.2;
IRQ0 is perfectly legal to use on at least some macppc, so don't treat it
as an error or something special
with this svwsata works on my PCI-X G5
 1.11 01-Mar-2018  macallan use mapiodev() so this can work on G5s
 1.10 01-Jun-2017  chs remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.
 1.9 26-May-2016  macallan treat IPIs like regular interrupts at IPL_HIGH
should fix port-powerpc/44387
tested by chuq
 1.8 01-Feb-2012  matt branches: 1.8.6; 1.8.24;
Use kmem instead of malloc. Remove unneeded <sys/malloc.h> includes.
 1.7 14-Jan-2012  phx Some PICs have the capability to define the interrupt's polarity (OpenPIC
for example). So the accepted interrupt types have been extended to:
- IST_EDGE_FALLING (which is the same as IST_EDGE)
- IST_EDGE_RISING (new)
- IST_LEVEL_LOW (is the same as IST_LEVEL)
- IST_LEVEL_HIGH (new)
Old code will continue to work without modification.
 1.6 20-Jun-2011  matt branches: 1.6.2; 1.6.6;
<arch/powerpc/... -> <powerpc/...
 1.5 29-Apr-2008  martin branches: 1.5.32;
Convert to new 2 clause license
 1.4 17-Jan-2008  garbled branches: 1.4.6; 1.4.8; 1.4.10;
Add support to ofppc for the IBM 7044-270 machine. This is a POWER3-II
based machine. Currently the kernel to run on this machine is
incompatible with the standard GENERIC kernel, so for now, we have a
separate GENERIC_B64. Eventually, I hope to combine the two.

Please note, this is a port of 32bit ofppc, not a powerpc64 port.

Thanks to Matt Thomas and Kevin Bowling for helping to make this port
possible.

Summary of changes:

Change ofwpci to use the ofmethod config for configuring the PCI bus,
rather than indirect configuration.
Move the wiring of the interrupt controllers from at the start of the
boot, into the configuration of the first PCI bus.
Rewrite the map_isa_ioregs() hack to work on a machine without BATs
Fix a ton of bugs in the genofw_find_pics routine, and in the map_space code.
Split the pic_openpic into openpic_common and pic_openpic.
Create a new pic_distopenpic driver, for the distributed openpic found on
some newer IBM machines.
Fix a bad panic in pmap_extract on 64bit bridge mode
 1.3 11-Dec-2007  garbled Fix the endless stream of 7's problem on i8259-like interrupt controllers
once and for all. The i8259 does not like to be read in a loop, when an
interrupt comes in, it will return a valid value, however, if you keep
reading it until there are no outstanding interrupts, it will return 7
(which is the lpt interrupt). Change the pic handler to give an argument
to the get_irq functions of mode, which indicates if this is the first
time we are asking, or if we are just rechecking in a loop. Non-i8259
handlers can safely ignore this argument.

Tested to fix the stream of 7's problem on prep and ofppc. Got rid of
the nasty hack in ofppc with this too, and the prep machine seems to take
less interrupts now, which is a good thing.
 1.2 17-Oct-2007  garbled branches: 1.2.2; 1.2.4; 1.2.6; 1.2.8; 1.2.10; 1.2.12; 1.2.14;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.1 02-May-2007  macallan branches: 1.1.2; 1.1.6; 1.1.8;
file pic_openpic.c was initially added on branch ppcoea-renovation.
 1.1.8.1 18-Oct-2007  yamt sync with head.
 1.1.6.1 02-Nov-2007  joerg More diff reduce to HEAD due to botched up merging.
 1.1.2.12 16-Oct-2007  macallan make interrupt distribution via OpenPIC optional
with options OPENPIC_DISTRIBUTE all CPUs will receive hardware interrupts,
otherwise only cpu0
 1.1.2.11 11-Oct-2007  macallan implement pic_finish_setup() to send interrupts to all attached CPUs
 1.1.2.10 10-Oct-2007  macallan - move IPI setup to ipi_openpic
- some cleanup
 1.1.2.9 04-Oct-2007  macallan make openpic_set_priority non-static for now since cpu.c calls it on SMP
kernels. This should go away when the hatch code is rewritten.
 1.1.2.8 03-Jun-2007  nisimura - make setup_openpic() to have every SRC_VECTOR(irq) register a value
0x8000'0000 during initialization. opic_establish_irq() will assign
acutual usage values later on.
- note a comment describing that writing S1C bit for OPENPIC_CONFIG
register should bring the sane initial operation state. #if-0'ed out
this time since it remains unknown wether every OpenPIC compliant
controller behave in the same way.
- nuke struct openpic_ops which contains enable_mask for no use.
 1.1.2.7 04-May-2007  macallan nuke unused pic_ops methods, honour priority in pic_establish_irq()
 1.1.2.6 03-May-2007  garbled Move the functions down from openpic.c into pic_openpic.c, as there
really is no need to have them over there when all the interrupt routines
will be using pic_openpic.c
Change the openpic setup to set all the irqs except 0 to negative polarity.
Set the spurious vector reg to 0xff.
Emit a nice printf showing the version of the openpic, and getrid of the
maxint thing.
Add a global, primary_pic, so machines can elect any registered pic as
the primary interrupt controller.
Clean up a few nits in pic_prepivr to make it more similar to the openpic
one, add a prototype for the setup_prepivr function, etc etc.
 1.1.2.5 03-May-2007  nisimura These two have no <machine/autoconf.h> dependency.
 1.1.2.4 03-May-2007  nisimura - files.pic
allow to choose files as designated for Makefile.
- pic_openpic.c, pic_prepivr.c
remove #ifdef PIC_xxx constructs.
- pic_openpic.c
honour OPENPIC feature register NIRQ field for max. number of
available irqs. Valid for MPC107/MPC824x EPIC.
 1.1.2.3 03-May-2007  macallan fix typo
 1.1.2.2 03-May-2007  macallan adapt to changes picvar.h
 1.1.2.1 02-May-2007  macallan OpenPIC support
 1.2.14.2 19-Jan-2008  bouyer Sync with HEAD
 1.2.14.1 13-Dec-2007  bouyer Sync with HEAD
 1.2.12.1 13-Dec-2007  yamt sync with head.
 1.2.10.1 26-Dec-2007  ad Sync with head.
 1.2.8.4 23-Mar-2008  matt sync with HEAD
 1.2.8.3 09-Jan-2008  matt sync with HEAD
 1.2.8.2 06-Nov-2007  matt sync with HEAD
 1.2.8.1 17-Oct-2007  matt file pic_openpic.c was added on branch matt-armv6 on 2007-11-06 23:20:56 +0000
 1.2.6.1 18-Feb-2008  mjf Sync with HEAD.
 1.2.4.3 21-Jan-2008  yamt sync with head
 1.2.4.2 27-Oct-2007  yamt sync with head.
 1.2.4.1 17-Oct-2007  yamt file pic_openpic.c was added on branch yamt-lazymbuf on 2007-10-27 11:28:01 +0000
 1.2.2.2 23-Oct-2007  ad Sync with head.
 1.2.2.1 17-Oct-2007  ad file pic_openpic.c was added on branch vmlocking on 2007-10-23 20:36:21 +0000
 1.4.10.1 16-May-2008  yamt sync with head.
 1.4.8.1 18-May-2008  yamt sync with head.
 1.4.6.1 02-Jun-2008  mjf Sync with HEAD.
 1.5.32.1 23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.6.6.1 18-Feb-2012  mrg merge to -current.
 1.6.2.1 17-Apr-2012  yamt sync with head
 1.8.24.2 28-Aug-2017  skrll Sync with HEAD
 1.8.24.1 29-May-2016  skrll Sync with HEAD
 1.8.6.1 03-Dec-2017  jdolecek update from HEAD
 1.12.2.3 06-Sep-2018  pgoyette Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)
 1.12.2.2 21-May-2018  pgoyette Sync with HEAD
 1.12.2.1 30-Mar-2018  pgoyette Resolve conflicts between branch and HEAD
 1.14.2.1 10-Jun-2019  christos Sync with HEAD
 1.9 01-Jun-2017  chs remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.
 1.8 28-Jul-2012  matt branches: 1.8.2; 1.8.16;
Fix -fno-common fallout.
 1.7 01-Feb-2012  matt Use kmem instead of malloc. Remove unneeded <sys/malloc.h> includes.
 1.6 20-Jun-2011  matt branches: 1.6.2; 1.6.6;
<arch/powerpc/... -> <powerpc/...
 1.5 18-Jun-2011  matt Use <sys/foo.h> instead of <machine/foo.h> if such a file exists.
Don't assume <sys/cpu.h> includes <powerpc/subarch/cpu*.h>. Include it
explicitly.
 1.4 28-Apr-2008  martin branches: 1.4.32;
Remove clause 3 and 4 from TNF licenses
 1.3 11-Dec-2007  garbled branches: 1.3.8; 1.3.10; 1.3.12;
Fix the endless stream of 7's problem on i8259-like interrupt controllers
once and for all. The i8259 does not like to be read in a loop, when an
interrupt comes in, it will return a valid value, however, if you keep
reading it until there are no outstanding interrupts, it will return 7
(which is the lpt interrupt). Change the pic handler to give an argument
to the get_irq functions of mode, which indicates if this is the first
time we are asking, or if we are just rechecking in a loop. Non-i8259
handlers can safely ignore this argument.

Tested to fix the stream of 7's problem on prep and ofppc. Got rid of
the nasty hack in ofppc with this too, and the prep machine seems to take
less interrupts now, which is a good thing.
 1.2 17-Oct-2007  garbled branches: 1.2.2; 1.2.4; 1.2.8; 1.2.10; 1.2.12; 1.2.14;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.1 03-May-2007  garbled branches: 1.1.2; 1.1.6; 1.1.8;
file pic_prepivr.c was initially added on branch ppcoea-renovation.
 1.1.8.1 18-Oct-2007  yamt sync with head.
 1.1.6.1 02-Nov-2007  joerg More diff reduce to HEAD due to botched up merging.
 1.1.2.9 11-Oct-2007  macallan add NULL pic_finish_setup()
 1.1.2.8 10-Oct-2007  garbled Change pic_prepivr around a bit. Handle the default IRQ 7 from the 8259
better, and add a new motivr_get_irq(). The motorola machines require an
actual read from the 8259 for PCI irqs, so in that case, we read the
8259, and then read the IVR to ack the irq.

Move i8259_get_irq() to i8259_common.c for above.

Fix some minor typos in the chip id's for prep residual.

Fix ibmnws and prep to properly initialize the prep ivr depending on if
the machine is motorola, or IBM based.

Tested on a 7043 and an MTX604
 1.1.2.7 09-May-2007  garbled The i8259 and prepivr code had a bunch of functions that were duplicates
of one another. Break those out into i8259_common.c and share that file
between the two of them.
 1.1.2.6 07-May-2007  garbled add the third argument to prepivr_establish_irq()
 1.1.2.5 04-May-2007  nisimura follow up to the previous change for struct pic_ops, and make
pic_i8259.c compilable.
 1.1.2.4 04-May-2007  garbled Add an i8259 pic. Compile tested only.
Add 8259 initialization code to prepivr. (Forgot to add this when I nuked
init_icu(), oddly enough, my machine didn't care, but I'm sure thats pure
luck.)
There is probably alot more sharing that can take place between these two
files, but I'm not sure how to accomplish it yet because of the PIC_XXX
options. That will be a TODO item.
 1.1.2.3 03-May-2007  garbled Move the functions down from openpic.c into pic_openpic.c, as there
really is no need to have them over there when all the interrupt routines
will be using pic_openpic.c
Change the openpic setup to set all the irqs except 0 to negative polarity.
Set the spurious vector reg to 0xff.
Emit a nice printf showing the version of the openpic, and getrid of the
maxint thing.
Add a global, primary_pic, so machines can elect any registered pic as
the primary interrupt controller.
Clean up a few nits in pic_prepivr to make it more similar to the openpic
one, add a prototype for the setup_prepivr function, etc etc.
 1.1.2.2 03-May-2007  nisimura - files.pic
allow to choose files as designated for Makefile.
- pic_openpic.c, pic_prepivr.c
remove #ifdef PIC_xxx constructs.
- pic_openpic.c
honour OPENPIC feature register NIRQ field for max. number of
available irqs. Valid for MPC107/MPC824x EPIC.
 1.1.2.1 03-May-2007  garbled Add a generic prepIVR pic. used by ibmnws and prep.
 1.2.14.1 13-Dec-2007  bouyer Sync with HEAD
 1.2.12.1 13-Dec-2007  yamt sync with head.
 1.2.10.1 26-Dec-2007  ad Sync with head.
 1.2.8.3 09-Jan-2008  matt sync with HEAD
 1.2.8.2 06-Nov-2007  matt sync with HEAD
 1.2.8.1 17-Oct-2007  matt file pic_prepivr.c was added on branch matt-armv6 on 2007-11-06 23:20:57 +0000
 1.2.4.3 21-Jan-2008  yamt sync with head
 1.2.4.2 27-Oct-2007  yamt sync with head.
 1.2.4.1 17-Oct-2007  yamt file pic_prepivr.c was added on branch yamt-lazymbuf on 2007-10-27 11:28:01 +0000
 1.2.2.2 23-Oct-2007  ad Sync with head.
 1.2.2.1 17-Oct-2007  ad file pic_prepivr.c was added on branch vmlocking on 2007-10-23 20:36:22 +0000
 1.3.12.1 16-May-2008  yamt sync with head.
 1.3.10.1 18-May-2008  yamt sync with head.
 1.3.8.1 02-Jun-2008  mjf Sync with HEAD.
 1.4.32.1 23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.6.6.1 18-Feb-2012  mrg merge to -current.
 1.6.2.2 30-Oct-2012  yamt sync with head
 1.6.2.1 17-Apr-2012  yamt sync with head
 1.8.16.1 28-Aug-2017  skrll Sync with HEAD
 1.8.2.1 03-Dec-2017  jdolecek update from HEAD
 1.5 18-Jun-2011  matt Use <sys/foo.h> instead of <machine/foo.h> if such a file exists.
Don't assume <sys/cpu.h> includes <powerpc/subarch/cpu*.h>. Include it
explicitly.
 1.4 10-May-2008  martin branches: 1.4.30;
Backout previous: the license sweep touched these files in error, so
restore the old license.
 1.3 29-Apr-2008  martin branches: 1.3.2;
Convert to new 2 clause license
 1.2 17-Oct-2007  garbled branches: 1.2.2; 1.2.4; 1.2.8;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.1 11-May-2007  matt branches: 1.1.2; 1.1.6; 1.1.8;
file pic_soft.c was initially added on branch ppcoea-renovation.
 1.1.8.1 18-Oct-2007  yamt sync with head.
 1.1.6.1 02-Nov-2007  joerg More diff reduce to HEAD due to botched up merging.
 1.1.2.2 22-May-2007  matt Add IPL_SOFTI2C. Use common cas32.
 1.1.2.1 11-May-2007  matt Initial implementation of a "software interrupt" pic which is, of course,
completely in software without any backing hardware.
 1.2.8.2 06-Nov-2007  matt sync with HEAD
 1.2.8.1 17-Oct-2007  matt file pic_soft.c was added on branch matt-armv6 on 2007-11-06 23:20:58 +0000
 1.2.4.2 27-Oct-2007  yamt sync with head.
 1.2.4.1 17-Oct-2007  yamt file pic_soft.c was added on branch yamt-lazymbuf on 2007-10-27 11:28:02 +0000
 1.2.2.2 23-Oct-2007  ad Sync with head.
 1.2.2.1 17-Oct-2007  ad file pic_soft.c was added on branch vmlocking on 2007-10-23 20:36:23 +0000
 1.3.2.1 23-Jun-2008  wrstuden Sync w/ -current. 34 merge conflicts to follow.
 1.4.30.1 23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.2 17-Jun-2011  matt intr.h must not include cpu due to deadly embrace with SOFTINT_COUNT.
Cleanup intr.h so MD definitions can overload common definitions.
Rototill pic/intr.c. Virtual IRQs can now be reclaimed. separate virq
from hwirq from picirq. Redo intr mask calculations.
tested on pmppc and macppc (MP).
 1.1 16-Jun-2011  macallan enable FAST_SOFTINTR support for all ports that use powerpc/pic/
This has been successfully tested on macppc
TODO:
- ibm4xx needs to be adapted
- SMP doesn't work yet, 2nd CPU crashes when trying to leave the idle loop
 1.15 05-Jul-2025  macallan add a function to find a PIC by its base address
 1.14 17-Feb-2025  jmcneill powerpc: Don't enable interrupts before calling cascaded intr handler.

Before calling a normal interrupt handler, the pic code adjusts cpl and
enables interrupts. Don't do this with interrupt sources that feed
cascaded pics as the resulting handler will do it anyway, and it can
result in multiple interrupts firing on the parent pic just to service
a single interrupt on the child.
 1.13 22-Mar-2021  rin branches: 1.13.16; 1.13.22;
Brush up previous, or make things more similar to x86:

- Prevent pic_name from appearing vmstat(1) twice.
- Restore "irq" in interrupt id fields of intrctl(8).

For these purposes,

- Add is_evname member to struct intr_source.
- Bump size of is_source to INTRIDBUF, and rename it to is_intrid for clarity.

Now, outputs from vmstat(1) and intrctl(8) are like:

----
$ vmstat -ev
...
openpic irq 39 3967 26 intr
...
$ intrctl list
interrupt id CPU0 device name(s)
...
openpic irq 39 3967* wdc1
...
----
 1.12 16-Apr-2020  rin branches: 1.12.2; 1.12.4;
Revert previous for now:
http://mail-index.netbsd.org/source-changes/2020/04/16/msg116278.html

The reasoning turned out to be wrong; __KERNEL_RCSID() in header files
does *not* overwrite RCSID in main source files. The real problem is that
it inserts its RCSID into *every* object files. However, it can be still
useful even if heavily duplicated.
 1.11 16-Apr-2020  rin Stop using __KERNEL_RCSID() in header files; it confuses ident(1) by
overwriting RCSID in main source files.

XXX
The first argument of __KERNEL_RCSID() is neglected for ELF. If we wish
to have RCSID of header files in kernel binary, we need something like
__FBSDID() macro in FreeBSD.
 1.10 11-May-2018  macallan branches: 1.10.12;
use 128 as IPI_VECTOR to avoid overlap wth hardware interrupts
 1.9 18-Jun-2011  matt branches: 1.9.52;
Use <sys/foo.h> instead of <machine/foo.h> if such a file exists.
Don't assume <sys/cpu.h> includes <powerpc/subarch/cpu*.h>. Include it
explicitly.
 1.8 17-Jun-2011  matt Change from level to ipl since we aren't dealing a mask anymore, just a
simple value.
Fix intr_calculatemasks to deal with ipl isn't a mask. Let establish
and disestablish determine the highest ipl for the interrut source being
modified. No reason to recompute that for every source when only one changes
at a time. Only change idepth while in the loop.
 1.7 24-Apr-2010  kiyohara branches: 1.7.6;
Support 64-bit imask for powerpc/pic.
 1.6 19-Aug-2009  nisimura branches: 1.6.2; 1.6.4;
- Have pic_mpcsoc.c to adapt variations of Moto/Freescale OpenPIC
compliant interrupt controllers. Mostly the refrain of pic_openpic.c
and shall be useful for 85xx/86xx/QorIQ and Tundra product lines.
 1.5 29-Apr-2008  martin Convert to new 2 clause license
 1.4 17-Jan-2008  garbled branches: 1.4.6; 1.4.8; 1.4.10;
Add support to ofppc for the IBM 7044-270 machine. This is a POWER3-II
based machine. Currently the kernel to run on this machine is
incompatible with the standard GENERIC kernel, so for now, we have a
separate GENERIC_B64. Eventually, I hope to combine the two.

Please note, this is a port of 32bit ofppc, not a powerpc64 port.

Thanks to Matt Thomas and Kevin Bowling for helping to make this port
possible.

Summary of changes:

Change ofwpci to use the ofmethod config for configuring the PCI bus,
rather than indirect configuration.
Move the wiring of the interrupt controllers from at the start of the
boot, into the configuration of the first PCI bus.
Rewrite the map_isa_ioregs() hack to work on a machine without BATs
Fix a ton of bugs in the genofw_find_pics routine, and in the map_space code.
Split the pic_openpic into openpic_common and pic_openpic.
Create a new pic_distopenpic driver, for the distributed openpic found on
some newer IBM machines.
Fix a bad panic in pmap_extract on 64bit bridge mode
 1.3 11-Dec-2007  garbled Fix the endless stream of 7's problem on i8259-like interrupt controllers
once and for all. The i8259 does not like to be read in a loop, when an
interrupt comes in, it will return a valid value, however, if you keep
reading it until there are no outstanding interrupts, it will return 7
(which is the lpt interrupt). Change the pic handler to give an argument
to the get_irq functions of mode, which indicates if this is the first
time we are asking, or if we are just rechecking in a loop. Non-i8259
handlers can safely ignore this argument.

Tested to fix the stream of 7's problem on prep and ofppc. Got rid of
the nasty hack in ofppc with this too, and the prep machine seems to take
less interrupts now, which is a good thing.
 1.2 17-Oct-2007  garbled branches: 1.2.2; 1.2.4; 1.2.6; 1.2.8; 1.2.10; 1.2.12; 1.2.14;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.1 02-May-2007  macallan branches: 1.1.2; 1.1.6; 1.1.8;
file picvar.h was initially added on branch ppcoea-renovation.
 1.1.8.1 18-Oct-2007  yamt sync with head.
 1.1.6.1 02-Nov-2007  joerg More diff reduce to HEAD due to botched up merging.
 1.1.2.14 11-Oct-2007  macallan add pic_ops.pic_finish_setup() for additional PIC setup after the CPUs attached
can be NULL.
 1.1.2.13 10-Oct-2007  garbled Change pic_prepivr around a bit. Handle the default IRQ 7 from the 8259
better, and add a new motivr_get_irq(). The motorola machines require an
actual read from the 8259 for PCI irqs, so in that case, we read the
8259, and then read the IVR to ack the irq.

Move i8259_get_irq() to i8259_common.c for above.

Fix some minor typos in the chip id's for prep residual.

Fix ibmnws and prep to properly initialize the prep ivr depending on if
the machine is motorola, or IBM based.

Tested on a 7043 and an MTX604
 1.1.2.12 04-Oct-2007  macallan #define IPI_VECTOR and add a prototype for an MD IPI handler
This should be abstracted away.
 1.1.2.11 09-May-2007  garbled The i8259 and prepivr code had a bunch of functions that were duplicates
of one another. Break those out into i8259_common.c and share that file
between the two of them.
 1.1.2.10 04-May-2007  nisimura follow up to the previous change for struct pic_ops, and make
pic_i8259.c compilable.
 1.1.2.9 04-May-2007  macallan nuke some unused function pointers from struct pic_ops
add a parameter to pic_establish_irq for priority
 1.1.2.8 04-May-2007  garbled Add an i8259 pic. Compile tested only.
Add 8259 initialization code to prepivr. (Forgot to add this when I nuked
init_icu(), oddly enough, my machine didn't care, but I'm sure thats pure
luck.)
There is probably alot more sharing that can take place between these two
files, but I'm not sure how to accomplish it yet because of the PIC_XXX
options. That will be a TODO item.
 1.1.2.7 03-May-2007  garbled Move the functions down from openpic.c into pic_openpic.c, as there
really is no need to have them over there when all the interrupt routines
will be using pic_openpic.c
Change the openpic setup to set all the irqs except 0 to negative polarity.
Set the spurious vector reg to 0xff.
Emit a nice printf showing the version of the openpic, and getrid of the
maxint thing.
Add a global, primary_pic, so machines can elect any registered pic as
the primary interrupt controller.
Clean up a few nits in pic_prepivr to make it more similar to the openpic
one, add a prototype for the setup_prepivr function, etc etc.
 1.1.2.6 03-May-2007  macallan fix merge muckup
 1.1.2.5 03-May-2007  macallan add dummy establish_intr method
 1.1.2.4 03-May-2007  garbled Add some additional functions (pic_establish_irq) to enable use with an 8259
 1.1.2.3 02-May-2007  macallan OpenPIC support
 1.1.2.2 02-May-2007  macallan cosmetics:
- remove CPU number from pic_get_irq()
- add type parameter to enable/reenable
- add IRQ parameter to pic_ack_irq()
... and make intr.c compile again
 1.1.2.1 02-May-2007  macallan first try on a generic interrupt handler.
Features:
- PIC details are hidden by struct pic_ops
- PICs can easily be cascaded
- support for soft interrupts
tested so far only on macppc with a PowerBook 3400c
 1.2.14.2 19-Jan-2008  bouyer Sync with HEAD
 1.2.14.1 13-Dec-2007  bouyer Sync with HEAD
 1.2.12.1 13-Dec-2007  yamt sync with head.
 1.2.10.1 26-Dec-2007  ad Sync with head.
 1.2.8.4 23-Mar-2008  matt sync with HEAD
 1.2.8.3 09-Jan-2008  matt sync with HEAD
 1.2.8.2 06-Nov-2007  matt sync with HEAD
 1.2.8.1 17-Oct-2007  matt file picvar.h was added on branch matt-armv6 on 2007-11-06 23:20:58 +0000
 1.2.6.1 18-Feb-2008  mjf Sync with HEAD.
 1.2.4.3 21-Jan-2008  yamt sync with head
 1.2.4.2 27-Oct-2007  yamt sync with head.
 1.2.4.1 17-Oct-2007  yamt file picvar.h was added on branch yamt-lazymbuf on 2007-10-27 11:28:02 +0000
 1.2.2.2 23-Oct-2007  ad Sync with head.
 1.2.2.1 17-Oct-2007  ad file picvar.h was added on branch vmlocking on 2007-10-23 20:36:24 +0000
 1.4.10.3 11-Aug-2010  yamt sync with head.
 1.4.10.2 19-Aug-2009  yamt sync with head.
 1.4.10.1 16-May-2008  yamt sync with head.
 1.4.8.1 18-May-2008  yamt sync with head.
 1.4.6.1 02-Jun-2008  mjf Sync with HEAD.
 1.6.4.1 30-May-2010  rmind sync with head
 1.6.2.1 30-Apr-2010  uebayasi Sync with HEAD.
 1.7.6.1 23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.9.52.1 21-May-2018  pgoyette Sync with HEAD
 1.10.12.1 20-Apr-2020  bouyer Sync with HEAD
 1.12.4.1 03-Apr-2021  thorpej Sync with HEAD.
 1.12.2.1 03-Apr-2021  thorpej Sync with HEAD.
 1.13.22.1 02-Aug-2025  perseant Sync with HEAD
 1.13.16.1 22-Feb-2025  martin Pull up following revision(s) (requested by jmcneill in ticket #1056):

sys/arch/powerpc/pic/intr.c: revision 1.35
sys/arch/powerpc/pic/intr.c: revision 1.36
sys/arch/powerpc/pic/intr.c: revision 1.37
sys/arch/powerpc/pic/picvar.h: revision 1.14

powerpc: Fix ci_ipending corruption with cascaded pics
A cascaded pic will register pic_handle_intr as its interrupt handler,
but interrupt handlers are called with MSR[EE] = 1. This breaks
assumptions in pic callbacks and can result in eg. corrupt ci_ipending
due to a read/modify/write of the field with nested interrupts.

Fix this by always clearing MSR[EE] at the top of pic_handle_intr.

powerpc: Mask interrupts after returning from handler.
Now that we are explicitly masking interrupts on entry of pic_handle_intr,
we need to disable (instead of store) interrupts after calling
intr_deliver.

powerpc: Don't enable interrupts before calling cascaded intr handler.
Before calling a normal interrupt handler, the pic code adjusts cpl and
enables interrupts. Don't do this with interrupt sources that feed
cascaded pics as the resulting handler will do it anyway, and it can
result in multiple interrupts firing on the parent pic just to service
a single interrupt on the child.

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