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History log of /src/sys/arch/riscv
RevisionDateAuthorComments
 1.3 04-Oct-2021  mrg riscv: fix build with r/o src tree

add 'compile' to the SUBDIR list so that 'make obj' creates the
kernel compile base objdir so <bsd.kernobj.mk> sets KERNOBJDIR
correctly.
 1.2 30-Sep-2021  jmcneill efiboot: Build and install bootriscv64.efi for riscv64 builds.
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file Makefile was added on branch tls-maxphys on 2017-12-03 11:36:38 +0000
 1.1 01-Jun-2019  maxv branches: 1.1.2;
Misc changes in RISC-V. Start changing the memory layout, too.
 1.1.2.2 10-Jun-2019  christos Sync with HEAD
 1.1.2.1 01-Jun-2019  christos file Makefile was added on branch phil-wifi on 2019-06-10 22:06:40 +0000
 1.24 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.23 09-Feb-2023  abs Adjust _all_ cinclude of *.local files

- Ensure always at end
- Use tab rather than spaces
- Add consistent comment
"Pull in optional local configuration - always at end"

The only functional change is that a local file which tried to
override an existing setting (eg with "no foo") would have failed
in some cases before, but now will work
 1.22 09-Feb-2023  abs Ensure GENERIC.local is always at the end of GENERIC

Where a GENERIC config had an existing inclusion of GENERIC.local,
ensure it is always at the end of the file, with a consistent
comment:

# Pull in optional local configuration
cinclude "arch/landisk/conf/GENERIC.local"

This allows GENERIC.local to correctly override all options

(This pass does not affect any GENERIC which did not already have
an include of GENERIC.local)
 1.21 25-Nov-2022  jmcneill Add driver for SiFive FU540 PRCI clock controller.
 1.20 19-Nov-2022  skrll Some comments
 1.19 15-Nov-2022  simonb Include GENERIC.local if it exists.
 1.18 12-Nov-2022  simonb Add NFS_BOOT_DHCP option.
 1.17 12-Oct-2022  simonb "options<space><tab>"
 1.16 29-Sep-2022  riastradh swwdog(4): Add to GENERIC kernels.

Plus a handful of others that I'm familiar with. Lots of special-
purpose kernels should probably have this too but I'm not going
through all the arm, mips, and ppc evaluation board kernels to see
which ones are relevant.

Omitted from systems I know to be very small:
- sun2/GENERIC
- dreamcast/GENERIC
Feel free to remove it from others that need to be kept smaller.

Compile-tested a few of these just in case:
- alpha/GENERIC
- amd64/GENERIC
- evbmips/OCTEON
- i386/GENERIC
- riscv/GENERIC

PR kern/29702
 1.15 27-Sep-2022  skrll Basic ddb and backtrace support.

[ 1.0000000] panic: kernel diagnostic assertion "msgbufaddr != 0" failed: file "/home/nick/netbsd/nbcvs/src/sys/arch/riscv/riscv/riscv_machdep.c", line 564
[ 1.0000000] cpu0: Begin traceback...
[ 1.0000000] trace fp ffffffc000801dd0
[ 1.0000000] fp ffffffc000801e10 ?() at ffffffc0001eee98
[ 1.0000000] fp ffffffc000801e30 ?() at ffffffc0002ad984
[ 1.0000000] fp ffffffc000801ee0 ?() at ffffffc000005430
[ 1.0000000] cpu0: End traceback...
[ 1.0000000] Trapframe @ 0xffffffc000801cb0 (cause=3 (breakpoint), status=0x100, pc=0xffffffc0000007e4, va=0):
[ 1.0000000] ra =0xffffffc0001eee9c, sp =0xffffffc000801dd0, gp =0xffffffc0006a8f40, tp = 0
[ 1.0000000] s0 =0xffffffc000600ac0, s1 = 0x1000, s2 =0xffffffc000438df0, s3 =0xffffffc000801d80
[ 1.0000000] s4 =0xffffffc0001eed78, s5 =0xffffffc0006d55f8, s6 =0xffffffc000801d88, s7 =0xffffffc0006dfdb8
[ 1.0000000] s8 =0xffffffc000428c18, s9 =0xffffffc000801dd0, s10=0xffffffc0000a3822, s11=0xffffffc0006d55f8
[ 1.0000000] a0 = 0x17, a1 = 0xa, a2 = 0, a3 =0xffffffc00041f658
[ 1.0000000] a4 = 0, a5 = 0x1, a5 = 0, a7 = 0x1
[ 1.0000000] t0 =0xffffffc0006dfe30, t1 =0xffffffc000801bb8, t2 =0xffffffc000803000, t3 = 0x75
[ 1.0000000] t4 = 0, t5 = 0x63, t6 = 0x1
[ 1.0000000] kernel: breakpoint
Stopped in pid 0.0 (system) at ffffffc0000007e4: c.ebreak
db>
 1.14 11-Sep-2022  skrll Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.
 1.13 07-Aug-2022  simonb UFS/LFS dirhash:
- Enable UFS_DIRHASH if the architecture or kernel model specific config
file can use 128MB of RAM or more.
- Remove experimental tag from UFS_DIRHASH; it's been with RUMP kernel
and by a number of NetBSD developers for years.
- Add LFS_DIRHASH if LFS was enabled.
- Be somewhat consistent with FS options order.
 1.12 20-Jan-2021  nia do not enable kernel OSS compat in configs without compat_linux

perhaps kernel OSS compat can be merged into compat_linux to avoid
further confusion
 1.11 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.10 01-Jun-2019  maxv branches: 1.10.10;
Misc changes in RISC-V. Start changing the memory layout, too.
 1.9 01-Aug-2018  maxv Unreference IPF/PF from all the config files, and enable NPF instead when
wanted. This also fixes some inconsistencies I saw in several files (eg
IPF options while IPF was not compiled, IPF+PF enabled by default, etc).
 1.8 06-Nov-2017  rin branches: 1.8.2; 1.8.4; 1.8.6;
Revive commented out DISKLABEL_EI option to kernel configuration files
that contain FFS_EI option.
 1.7 14-Sep-2017  mrg clean up COMPAT_* options for native netbsd code:
- new series of files that are useful for saying "i want everything
since netbsd 1.4", etc.
- use the fact COMPAT_* options have future dependancies to remove
many redundant options.

removes about 3000 lines total across kernel configuration files.
tested about 30 random kernels in the changed list.
 1.6 26-Feb-2017  maya Remove commented DISKLABEL_EI for strictly little endian architectures

It will never be useful.
 1.5 26-Feb-2017  rin Add DKWEDGE_METHOD_RDB option, which is enabled for x86, commented out for
other platforms by default.
 1.4 19-Feb-2017  rin PR kern/51208
Add DISKLABEL_EI option (and also FFS_EI if missing), commented out except for
ALL on amd64 and i386.
 1.3 07-Aug-2016  christos branches: 1.3.2;
rename ifmpls to mpls, so we don't have if_ifmpls...
 1.2 07-Aug-2015  maxv branches: 1.2.2;
Remove KMEMSTATS.
 1.1 28-Mar-2015  matt branches: 1.1.2;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.2.5 28-Aug-2017  skrll Sync with HEAD
 1.1.2.4 05-Oct-2016  skrll Sync with HEAD
 1.1.2.3 22-Sep-2015  skrll Sync with HEAD
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file GENERIC was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.2.2.1 20-Mar-2017  pgoyette Sync with HEAD
 1.3.2.1 21-Apr-2017  bouyer Sync with HEAD
 1.8.6.1 10-Jun-2019  christos Sync with HEAD
 1.8.4.1 06-Sep-2018  pgoyette Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)
 1.8.2.2 03-Dec-2017  jdolecek update from HEAD
 1.8.2.1 06-Nov-2017  jdolecek file GENERIC was added on branch tls-maxphys on 2017-12-03 11:36:38 +0000
 1.10.10.2 03-Apr-2021  thorpej Sync with HEAD.
 1.10.10.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.22 01-Apr-2025  nia riscv: Enable audio support for QEMU
 1.21 27-Mar-2025  riastradh virtio(4): Consolidate kernel configs.

No functional change intended.

Leave `# XXX ?' comments where I don't know why the driver in
question is excluded. (Typical reason is that PAGE_SIZE is not 4096
but I didn't investigate -- if you do investigate, please either
update the comment if you determine a reason, or enable the driver if
you don't.)

PR kern/59211: vio9p(4): missing from various GENERICs and MAKEDEVs
 1.20 08-Feb-2025  skrll riscv: Add pseudo-device openfirm

Missed in previous commit
 1.19 25-Jan-2025  skrll risc-v: disable X-Powers AXP Power Management IC for now as it causes problems
 1.18 05-Jan-2025  skrll Add X-Powers AXP Power Management IC and registers attachments
 1.17 02-Jan-2025  skrll risc-v: Add the Designware I2C controller
 1.16 01-Jan-2025  skrll risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.
 1.15 16-Jul-2024  riastradh viocon(4): Add to various kernel configs.
 1.14 17-Apr-2024  skrll branches: 1.14.2;
Re-enable HEARTBEAT
 1.13 06-Apr-2024  skrll Attach qemufwcfg
 1.12 02-Apr-2024  charlotte Mention DKWEDGE_METHOD_TOS in several kernel config files
 1.11 11-Feb-2024  skrll Turn off HEARTBEAT
 1.10 29-Jan-2024  christos PR/57889: Ricardo Branco: ext2fs does not have user immutable and append
file flags, only system ones. Restrict those to the superuser. Before
the behavior was controlled by EXT2FS_SYSTEM_FLAGS. Make that behavior the
default.
 1.9 13-Jan-2024  skrll Attach generic system controllers
 1.8 13-Jan-2024  skrll Group pass 1 attachments
 1.7 03-Sep-2023  skrll Fix and enable MULTIPROCESSOR
 1.6 01-Aug-2023  rjs Include compat config for NetBSD-10.
 1.5 16-Jul-2023  skrll riscv: Enable HEARTBEAT option in GENERIC.common
 1.4 02-Jun-2023  andvar follow the steps of Andrew Doran (ad) commit and fix more s/loose/lose/ typos.
also s/beyound/beyond/ and few others along the way, mainly in comments.
 1.3 01-Jun-2023  andvar fix various typos in comments.
 1.2 08-May-2023  skrll RISC-V: Add the Google Goldfish RTC to the GENERIC.common
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.14.2.1 02-Aug-2025  perseant Sync with HEAD
 1.21 08-Feb-2025  skrll risc-v: add a JH7110 TRNG driver
 1.20 03-Jan-2025  skrll risc-v: add a StarFive JH71[01]0 temperature sensor driver
 1.19 01-Jan-2025  skrll risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.
 1.18 12-Nov-2024  skrll Remove the USB stuff that is already in GENERIC.common
 1.17 11-Nov-2024  skrll risc-v: add a specific driver for the JH7110 STG system controller
 1.16 11-Nov-2024  skrll risc-v: add a JH7110 PCIe PHY driver
 1.15 11-Nov-2024  skrll whitespace
 1.14 11-Nov-2024  skrll Attach GPIO controllers in pass 2
 1.13 11-Nov-2024  skrll risc-v: Add initial JH7110 pin controller driver
 1.12 26-Oct-2024  skrll risc-v: add ethernet support on JH71[01]0 support

At present only the JH7110 EQOS support is enabled as it work.

The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.
 1.11 19-Aug-2024  skrll Add a clock driver for the JH7110 SoC found in the StarFive VisionFive 2
SBC.

It's not fully functional as something is wrong for the
Image-Signal-Process controller which is why it's #if 0'd out.
 1.10 13-Aug-2024  skrll risc-v: Allwinner D1 support

Add the Allwinnder D1 support provided by Rui-Xiang Guo and updated
but me.

https://mail-index.netbsd.org/port-riscv/2024/08/04/msg000127.html

Only driver listed as attaching in

https://github.com/picohive/netbsd-mangopi-mq-pro/blob/main/boot.log

have been added.

There is no need for the platform stuff as the board's u-boot is able
to load bootriscv64.efi and boot a generic kernel.
 1.9 09-Feb-2024  skrll branches: 1.9.2;
Attach ld at sdmmc

The SD card on my Beagle-V now works. Thanks jmcneill!
 1.8 07-Feb-2024  skrll risc-v: add a driver the JH7100 pin controller
 1.7 07-Feb-2024  skrll Use <space><tab> consistently
 1.6 20-Jan-2024  skrll Add bwfm* at sdmmc? for the Broadcom BCM43xxx WiFi Interface
 1.5 20-Jan-2024  skrll Add DesignWare SD/MMC attachment.
 1.4 18-Jan-2024  skrll risc-v: attach the Cadence XHCI usb controller on the JH7100 SoC
 1.3 16-Jan-2024  skrll risc-v: add a StarTech JH7100 SoC clock driver

The JH7100 is seen in the Beagle-V board.
 1.2 13-Jan-2024  skrll risc-v: add a SiFive FU[57]40/ L2 Cache controller driver
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.9.2.1 02-Aug-2025  perseant Sync with HEAD
 1.2 01-Aug-2023  gutteridge INSTALL: add a basic comment and missing RCS ID

(This isn't actually in use at present, but make it look like other
examples.)
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file INSTALL was added on branch tls-maxphys on 2017-12-03 11:36:38 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file INSTALL was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file INSTALL.config was added on branch tls-maxphys on 2017-12-03 11:36:38 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file INSTALL.config was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.11 25-Feb-2024  skrll Warn about building a kernel with the wrong toolchain.

Idea from mrg@
 1.10 26-Jul-2023  rin Use OBJCOPY_STRIPFLAGS instead of STRIPFLAGS.
 1.9 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.8 28-Sep-2022  skrll branches: 1.8.4;
Fix RV32 so it gets to the same point as RV64
 1.7 01-May-2021  skrll Fixup kernel linking and provide a linker script with standard sections
and symbols
 1.6 14-Mar-2020  skrll branches: 1.6.8;
Trailing whitespace
 1.5 16-Jun-2019  maxv Misc changes in RISC-V.
 1.4 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.3 22-Sep-2018  rin - Determine KERN_AS automatically depending on whether OPT_MODULAR is
set or not, in the same way as libcompat.

- Specify OPT_MODULAR in the port Makefile instead of KERN_AS.

Now, KERN_AS=library is used for kernels without module(7) for all ports.

OK christos
 1.2 31-Mar-2015  matt branches: 1.2.2; 1.2.18; 1.2.20; 1.2.22;
Use -mcmodel=medany to get PICish code.
 1.1 28-Mar-2015  matt Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.2.22.3 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.2.22.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.2.22.1 10-Jun-2019  christos Sync with HEAD
 1.2.20.1 30-Sep-2018  pgoyette Ssync with HEAD
 1.2.18.2 03-Dec-2017  jdolecek update from HEAD
 1.2.18.1 31-Mar-2015  jdolecek file Makefile.riscv was added on branch tls-maxphys on 2017-12-03 11:36:38 +0000
 1.2.2.2 06-Apr-2015  skrll Sync with HEAD
 1.2.2.1 31-Mar-2015  skrll file Makefile.riscv was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.6.8.1 13-May-2021  thorpej Sync with HEAD.
 1.8.4.1 11-Sep-2023  martin Pull up following revision(s) (requested by rin in ticket #363):

sys/arch/aarch64/conf/Makefile.aarch64: revision 1.24
sys/arch/aarch64/conf/Makefile.aarch64: revision 1.25
sys/arch/shark/conf/Makefile.shark.inc: revision 1.28
sys/arch/alpha/conf/Makefile.alpha: revision 1.88
sys/arch/mips/conf/Makefile.mips: revision 1.73
sys/conf/Makefile.kern.inc: revision 1.298
sys/conf/Makefile.kern.inc: revision 1.299
sys/arch/cats/conf/Makefile.cats.inc: revision 1.37
sys/arch/arm/conf/Makefile.arm: revision 1.56
sys/arch/arm/conf/Makefile.arm: revision 1.57
sys/arch/riscv/conf/Makefile.riscv: revision 1.10

Always use arm-elf2aout; no a.out support both for binutils{,.old}

Fix kernel size inflation for arm and aarch64 (PR toolchain/57146)

For some conditions, SYSTEM_LD_TAIL is set for arm and aarch64.
Then, ctfmerge(1) in default SYSTEM_LD_TAIL is unintentionally
skipped, which results in the catastrophic kernel size inflation,
as reported in the PR.

Also, introduce and use OBJCOPY_STRIPFLAGS variable instead of
STRIPFLAGS, as strip(1) is replaced by objcopy(1) during MI
kernel build procedure.

For Makefile.{arm,aarch64}, weird logic is used to determine how
to handle debug symbols; MKDEBUG{,KERNEL} are taken into account
later in sys/conf/Makefile.kern.inc.

Use OBJCOPY_STRIPFLAGS instead of STRIPFLAGS.
Simplify fix for PR toolchain/57146

Introduce ARCH_STRIP_SYMBOLS variable to centralize logic for debug
symbols from MD Makefile's to Makefile.kern.inc.
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.3 13-Aug-2024  skrll risc-v: Allwinner D1 support

Add the Allwinnder D1 support provided by Rui-Xiang Guo and updated
but me.

https://mail-index.netbsd.org/port-riscv/2024/08/04/msg000127.html

Only driver listed as attaching in

https://github.com/picohive/netbsd-mangopi-mq-pro/blob/main/boot.log

have been added.

There is no need for the platform stuff as the board's u-boot is able
to load bootriscv64.efi and boot a generic kernel.
 1.2 16-Jan-2024  skrll branches: 1.2.2;
risc-v: add a StarTech JH7100 SoC clock driver

The JH7100 is seen in the Beagle-V board.
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2.2.1 02-Aug-2025  perseant Sync with HEAD
 1.17 01-Jan-2025  skrll risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.
 1.16 23-Nov-2024  skrll risc-v: split db_{read,write}_bytes from db_machdep.c

Another step towards crash(8) support
 1.15 06-Apr-2024  skrll branches: 1.15.2;
Provide and use _ucas_{32,64} implementations
 1.14 03-Sep-2023  skrll Fix and enable MULTIPROCESSOR
 1.13 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.12 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.11 14-Oct-2022  skrll Split out a bunch of functions from locore.S into cpu_switch.S

NFC
 1.10 27-Sep-2022  skrll Basic ddb and backtrace support.

[ 1.0000000] panic: kernel diagnostic assertion "msgbufaddr != 0" failed: file "/home/nick/netbsd/nbcvs/src/sys/arch/riscv/riscv/riscv_machdep.c", line 564
[ 1.0000000] cpu0: Begin traceback...
[ 1.0000000] trace fp ffffffc000801dd0
[ 1.0000000] fp ffffffc000801e10 ?() at ffffffc0001eee98
[ 1.0000000] fp ffffffc000801e30 ?() at ffffffc0002ad984
[ 1.0000000] fp ffffffc000801ee0 ?() at ffffffc000005430
[ 1.0000000] cpu0: End traceback...
[ 1.0000000] Trapframe @ 0xffffffc000801cb0 (cause=3 (breakpoint), status=0x100, pc=0xffffffc0000007e4, va=0):
[ 1.0000000] ra =0xffffffc0001eee9c, sp =0xffffffc000801dd0, gp =0xffffffc0006a8f40, tp = 0
[ 1.0000000] s0 =0xffffffc000600ac0, s1 = 0x1000, s2 =0xffffffc000438df0, s3 =0xffffffc000801d80
[ 1.0000000] s4 =0xffffffc0001eed78, s5 =0xffffffc0006d55f8, s6 =0xffffffc000801d88, s7 =0xffffffc0006dfdb8
[ 1.0000000] s8 =0xffffffc000428c18, s9 =0xffffffc000801dd0, s10=0xffffffc0000a3822, s11=0xffffffc0006d55f8
[ 1.0000000] a0 = 0x17, a1 = 0xa, a2 = 0, a3 =0xffffffc00041f658
[ 1.0000000] a4 = 0, a5 = 0x1, a5 = 0, a7 = 0x1
[ 1.0000000] t0 =0xffffffc0006dfe30, t1 =0xffffffc000801bb8, t2 =0xffffffc000803000, t3 = 0x75
[ 1.0000000] t4 = 0, t5 = 0x63, t6 = 0x1
[ 1.0000000] kernel: breakpoint
Stopped in pid 0.0 (system) at ffffffc0000007e4: c.ebreak
db>
 1.9 19-Sep-2022  skrll Sort. NFC.
 1.8 11-Sep-2022  skrll Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.
 1.7 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.6 21-Oct-2020  christos branches: 1.6.2;
make process_machdep.c included always since it provides register i/o used by
sys_process_getlwpstatus.c which is always included.
 1.5 20-Oct-2020  christos harmonize process_machdep.c inclusion.
 1.4 20-Nov-2019  pgoyette Move all non-emulation-specific coredump code into the coredump module,
and remove all #ifdef COREDUMP conditional compilation. Now, the
coredump module is completely separated from the emulation modules, and
they can all be independently loaded and unloaded.

Welcome to 9.99.18 !
 1.3 16-Jun-2019  maxv Misc changes in RISC-V.
 1.2 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.22;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.22.3 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.1.22.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file files.riscv was added on branch tls-maxphys on 2017-12-03 11:36:38 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file files.riscv was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.6.2.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.15.2.1 02-Aug-2025  perseant Sync with HEAD
 1.8 01-May-2021  skrll Fixup kernel linking and provide a linker script with standard sections
and symbols
 1.7 04-Nov-2020  skrll branches: 1.7.4;
RCSID and whitespace police...
 1.6 16-Jun-2019  maxv branches: 1.6.10;
Misc changes in RISC-V.
 1.5 24-Aug-2015  uebayasi branches: 1.5.16; 1.5.20;
Don't mention stab and DWARF sections, because these (poorly mtaintained)
lists only help to make them harder to read.

If those sections are found in inputs, they simply appear in outputs as
orphaned sections, sorted by section types and attributes.
 1.4 22-Aug-2015  uebayasi .rel/.rela should not be generated in kernels.
 1.3 21-Aug-2015  uebayasi I bet setting search-directory for ld.so is useless in any kernel.
 1.2 20-Aug-2015  uebayasi Indent with 2 spaces.
 1.1 28-Mar-2015  matt branches: 1.1.2;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.2.3 22-Sep-2015  skrll Sync with HEAD
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file kern.ldscript was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.5.20.1 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.5.16.2 03-Dec-2017  jdolecek update from HEAD
 1.5.16.1 24-Aug-2015  jdolecek file kern.ldscript was added on branch tls-maxphys on 2017-12-03 11:36:38 +0000
 1.6.10.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.7.4.1 13-May-2021  thorpej Sync with HEAD.
 1.10 05-Feb-2025  skrll risc-v: add ofctl(8) and /dev/openfirm support
 1.9 07-May-2023  skrll branches: 1.9.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.8 14-Mar-2020  skrll Trailing whitespace
 1.7 28-Jan-2019  dholland Systematize handling of removed drivers.

- Every driver that was removed and whose number hasn't already been
reused is now listed with a commented-out "obsolete" line.
- The format of these has been systematized. Future format changes can
probably be safely done with a script.
- This does not include a few cases of assignments that only lasted a
couple days, or stuff from before major reorgs. Some of these may
be included nonetheless, because there was a lot of ground to cover
and therefore not a lot of time to dig into history in detail.

Note that the obsolete listings do not mean the major numbers can
never be reused; that's up to portmasters and/or core. It does mean
that they won't be reused by accident, however, which in some cases
(depending on the driver, how widely used it was, its family of device
nodes, their default permissions, etc.) can be quite dangerous.

Note that some of the things now explicitly listed as obsolete are
really ancient history. My scan went back as far as when the majors
files were added. (But not before that.)
 1.6 27-Jan-2019  dholland This may have been cutpasted from evbmips, but we don't need to say so.
 1.5 27-Jan-2019  dholland Restore satlink's majors entries commented out and marked obsolete.
Otherwise they might accidentally get reused later and cause a
security problem.
 1.4 27-Jan-2019  maxv Remove the satlink driver. It was disabled everywhere, had no man page and
no use either. Spotted by thorpej in PR/21345, ok christos.
 1.3 23-Sep-2018  maxv Remove ISDN from the kernel. It has remained unmaintained for a long time,
is of poor quality, and is now an obstacle to MP-ification. It was removed
ten years ago from FreeBSD for the same reason.

This retires a big user of the mbuf API, and will ease maintenance of the
kernel.
 1.2 08-Dec-2016  nat branches: 1.2.14; 1.2.16; 1.2.18;
Add a synthesized pc beeper and keyboard bell for platforms with an audio
device.
 1.1 19-Sep-2014  matt branches: 1.1.2; 1.1.4;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.4.1 07-Jan-2017  pgoyette Sync with HEAD. (Note that most of these changes are simply $NetBSD$
tag issues.)
 1.1.2.1 05-Feb-2017  skrll Sync with HEAD
 1.2.18.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.2.18.1 10-Jun-2019  christos Sync with HEAD
 1.2.16.1 30-Sep-2018  pgoyette Ssync with HEAD
 1.2.14.2 03-Dec-2017  jdolecek update from HEAD
 1.2.14.1 08-Dec-2016  jdolecek file majors.riscv was added on branch tls-maxphys on 2017-12-03 11:36:38 +0000
 1.9.6.1 02-Aug-2025  perseant Sync with HEAD
 1.3 01-Jan-2025  skrll risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.
 1.2 13-Aug-2024  skrll risc-v: Allwinner D1 support

Add the Allwinnder D1 support provided by Rui-Xiang Guo and updated
but me.

https://mail-index.netbsd.org/port-riscv/2024/08/04/msg000127.html

Only driver listed as attaching in

https://github.com/picohive/netbsd-mangopi-mq-pro/blob/main/boot.log

have been added.

There is no need for the platform stuff as the board's u-boot is able
to load bootriscv64.efi and boot a generic kernel.
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.58;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.58.1 02-Aug-2025  perseant Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file std.riscv was added on branch tls-maxphys on 2017-12-03 11:36:38 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file std.riscv was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.5 01-Jan-2025  skrll risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.
 1.4 13-Aug-2024  skrll risc-v: Allwinner D1 support

Add the Allwinnder D1 support provided by Rui-Xiang Guo and updated
but me.

https://mail-index.netbsd.org/port-riscv/2024/08/04/msg000127.html

Only driver listed as attaching in

https://github.com/picohive/netbsd-mangopi-mq-pro/blob/main/boot.log

have been added.

There is no need for the platform stuff as the board's u-boot is able
to load bootriscv64.efi and boot a generic kernel.
 1.3 07-May-2023  skrll branches: 1.3.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2 11-Apr-2019  kamil Fix CVS Id usage
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.22;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file std.riscv64 was added on branch tls-maxphys on 2017-12-03 11:36:38 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file std.riscv64 was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.3.6.1 02-Aug-2025  perseant Sync with HEAD
 1.5 24-Mar-2024  skrll Pretty print plic attachment
 1.4 25-Dec-2023  skrll Deliver plic interrupts to the cpu^Whart establishing the interrupt
handler. At least this is known to be a valid hart, but it might share
some interrupts around too.
 1.3 16-Dec-2023  skrll Free memory on failure
 1.2 02-Sep-2023  skrll Be clear about hart vs cpu. NFCI.
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.8 11-Aug-2024  skrll plic: Match thead,c900-plic
 1.7 04-Aug-2024  skrll spaces to tabs
 1.6 24-Mar-2024  skrll branches: 1.6.2;
Pretty print plic attachment
 1.5 09-Feb-2024  andvar s/incompatiable/incompatible/ in error messages.
 1.4 01-Jan-2024  skrll Perform more checks before establishing external interrupt handlers for
each hart. The VisionFive2 DTS list the S7 core with status = "disabled".
 1.3 02-Sep-2023  skrll Be clear about hart vs cpu. NFCI.
 1.2 02-Sep-2023  skrll Simplify plic_fdt_intr_disestablish by calling plic_intr_disestablish
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.6.2.1 02-Aug-2025  perseant Sync with HEAD
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2 02-Sep-2023  skrll Be clear about hart vs cpu. NFCI.
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2 24-Oct-2024  skrll risc-v: (re-) add the usb nodes for beagle-v.

The audio clocks are also added, but no driver exists as yet. USB works
again, but relies on u-boot setup.
 1.1 24-Oct-2024  skrll risc-v: Add max-frequency properties for the mmc controllers on beagle-v

The recent DTS import lost these properties and broke the mmc contollers,
so reinstate them.
 1.1 24-Oct-2024  skrll risc-v: (re-) add the usb nodes for beagle-v.

The audio clocks are also added, but no driver exists as yet. USB works
again, but relies on u-boot setup.
 1.2 24-Oct-2024  skrll risc-v: (re-) add the usb nodes for beagle-v.

The audio clocks are also added, but no driver exists as yet. USB works
again, but relies on u-boot setup.
 1.1 24-Oct-2024  skrll risc-v: Add max-frequency properties for the mmc controllers on beagle-v

The recent DTS import lost these properties and broke the mmc contollers,
so reinstate them.
 1.2 26-Jul-2023  skrll Remove debug printfs
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.4 01-Jan-2024  skrll Perform more checks before establishing external interrupt handlers for
each hart. The VisionFive2 DTS list the S7 core with status = "disabled".
 1.3 03-Sep-2023  skrll Fix and enable MULTIPROCESSOR
 1.2 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.1 12-Jun-2023  skrll Call / define fdtbus_cpus_md_attach for platforms with cpus @ fdt.

The RISC-V binding here seems somewhat of an abuse, but it exists in
mainline linux.
 1.2 15-Jun-2023  skrll G/C file was renamed in recent commit.
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.1 11-Sep-2022  skrll Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.
 1.5 06-Sep-2025  thorpej Refactor the "platform" defitions into fdt_platform.h
 1.4 01-Jan-2025  skrll branches: 1.4.2;
risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.
 1.3 12-Jun-2023  skrll branches: 1.3.6;
sort
 1.2 12-Jun-2023  skrll Call / define fdtbus_cpus_md_attach for platforms with cpus @ fdt.

The RISC-V binding here seems somewhat of an abuse, but it exists in
mainline linux.
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.3.6.1 02-Aug-2025  perseant Sync with HEAD
 1.4.2.1 16-Sep-2025  snj Pull up following revision(s) (requested by rin in ticket #31):

sys/arch/arm/fdt/files.fdt: revision 1.37
sys/arch/riscv/fdt/files.fdt: revision 1.5
sys/dev/fdt/files.fdt: revision 1.75 via patch

Prune fdt_platform.c from sys/dev/fdt/files.fdt and explicitly pull
in at sys/arch/arm/fdt/files.fdt and sys/arch/riscv/fdt/files.fdt.
Unbreaks OCTEON build.
 1.8 09-Feb-2025  skrll risc-v: show cpu number in intc_fdt_intrstr and not hartid.
 1.7 30-Dec-2024  skrll implementationm -> implementation
 1.6 21-Jan-2024  skrll branches: 1.6.2;
Make this compile without MULTIPROCESSOR
 1.5 21-Jan-2024  skrll Remove an empty line
 1.4 21-Jan-2024  skrll spaces -> tab
 1.3 25-Dec-2023  skrll Count interrupts across harts and their local interrupt controllers
correctly.
 1.2 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.6.2.1 02-Aug-2025  perseant Sync with HEAD
 1.1 01-Jan-2025  skrll branches: 1.1.4;
risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.
 1.1.4.2 02-Aug-2025  perseant Sync with HEAD
 1.1.4.1 01-Jan-2025  perseant file pcihost_fdt.c was added on branch perseant-exfatfs on 2025-08-02 05:56:03 +0000
 1.1 01-Jan-2025  skrll branches: 1.1.4;
risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.
 1.1.4.2 02-Aug-2025  perseant Sync with HEAD
 1.1.4.1 01-Jan-2025  perseant file pcihost_fdtvar.h was added on branch perseant-exfatfs on 2025-08-02 05:56:03 +0000
 1.2 01-Jan-2024  skrll Perform more checks before establishing external interrupt handlers for
each hart. The VisionFive2 DTS list the S7 core with status = "disabled".
 1.1 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.4 06-Sep-2025  thorpej Re-factor the console-related code into fdt_console.[ch]
 1.3 06-Sep-2025  thorpej Refactor the "platform" defitions into fdt_platform.h
 1.2 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.6 30-Nov-2024  christos Create a new header lwp_private.h to contain _lwp_getprivate_fast,
_lwp_gettcb_fast, _lwp_settcb and remove them from mcontext.h, so that:
1. we don't need special hacks to hide them
2. we can include <lwp.h> where needed to get the necessary prototypes
without redefining them locally.
 1.5 04-Nov-2024  christos Undo previous lwp.h change.
 1.4 03-Nov-2024  christos Split __lwp_getprivate_fast and __lwp_*tcb from mcontext.h into a separate
lwp.h file.
 1.3 12-Oct-2024  skrll Install pte.h for libkvm
 1.2 12-Jul-2018  maxv branches: 1.2.36;
Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.20; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.20.1 28-Jul-2018  pgoyette Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file Makefile was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2.36.1 02-Aug-2025  perseant Sync with HEAD
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file ansi.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file aout_machdep.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.11 06-Jan-2025  martin PR 58960: fix misunderstanding in semantic and provide both the original
id string as well as _NETBSD_REVISIONID.
Do not rely on string concatenation in the inline assembler, use .ascii
and .asciz for individual string parts instead.
 1.10 05-Jan-2025  martin fix copy&pasto in previous
 1.9 04-Jan-2025  skrll PR 58960: riscv/asm.h: Respect NETBSD_REVISIONID.
 1.8 04-Aug-2024  skrll spaces to tabs
 1.7 07-May-2023  skrll branches: 1.7.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.6 01-May-2021  skrll Provide __CONCAT, __STRING and ___CONCAT
 1.5 17-Apr-2020  joerg branches: 1.5.6;
Mark the .ident section as mergable string section to avoid redundant
entries.
 1.4 14-Mar-2020  skrll branches: 1.4.2;
Trailing whitespace
 1.3 13-Apr-2019  maya Handle changes since the gcc riscv toolchain was upstreamed
 1.2 27-Mar-2015  matt branches: 1.2.16; 1.2.20;
Switch to new ABI (return values now in a0/a1; v0/v1 are no more)
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.2.20.3 21-Apr-2020  martin Sync with HEAD
 1.2.20.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.2.20.1 10-Jun-2019  christos Sync with HEAD
 1.2.16.2 03-Dec-2017  jdolecek update from HEAD
 1.2.16.1 27-Mar-2015  jdolecek file asm.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.4.2.1 20-Apr-2020  bouyer Sync with HEAD
 1.5.6.1 13-May-2021  thorpej Sync with HEAD.
 1.7.6.1 02-Aug-2025  perseant Sync with HEAD
 1.2 04-Aug-2024  skrll spaces to tabs
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.58;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.58.1 02-Aug-2025  perseant Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file bswap.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.3 11-Sep-2022  skrll Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.
 1.2 23-Sep-2019  skrll Provide PRIxBUSADDR, PRIxBUSSIZE, PRIuBUSSIZE, and PRIxBSH for all arches
to follow arm and (generic) mips.

Reviewed by christos.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file bus.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.4 04-Aug-2024  skrll spaces to tabs
 1.3 07-May-2023  skrll branches: 1.3.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2 19-Nov-2022  skrll Fix some types
 1.1 11-Sep-2022  skrll Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.
 1.3.6.1 02-Aug-2025  perseant Sync with HEAD
 1.4 02-Feb-2025  skrll Whitespace
 1.3 07-May-2023  skrll branches: 1.3.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2 19-Nov-2022  skrll Fix some types
 1.1 11-Sep-2022  skrll Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.
 1.3.6.1 02-Aug-2025  perseant Sync with HEAD
 1.5 04-Apr-2020  christos silence lint.
 1.4 15-Apr-2019  maya Avoid -Wconversion warnings
 1.3 28-Oct-2014  dennis branches: 1.3.18; 1.3.22;
Shave an instruction from the generated code for the 32 bit byte
swap inline. Prune 5 or 9 instructions (depending on what you count)
from the 64 bit byte swap inline.
 1.2 28-Oct-2014  dennis Correct 32 and 64 bit byte swap inlines.
 1.1 19-Sep-2014  matt New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.3.22.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.3.22.1 10-Jun-2019  christos Sync with HEAD
 1.3.18.2 03-Dec-2017  jdolecek update from HEAD
 1.3.18.1 28-Oct-2014  jdolecek file byte_swap.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file cdefs.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.16 04-Aug-2024  skrll spaces to tabs
 1.15 25-Dec-2023  skrll branches: 1.15.2;
Count interrupts across harts and their local interrupt controllers
correctly.
 1.14 03-Sep-2023  skrll Fix and enable MULTIPROCESSOR
 1.13 29-Jul-2023  skrll Slight reformatting. NFCI.
 1.12 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.11 25-May-2023  skrll Fix CLKF_INTR so that not all time is shown as being spent in interrupts.
 1.10 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.9 17-Nov-2022  simonb Use better types and struct member names in the clockframe.
Avoid a magic number in CLKF_USERMODE().
 1.8 14-Aug-2021  ryo Improved the performance of kernel profiling on MULTIPROCESSOR, and possible to get profiling data for each CPU.

In the current implementation, locks are acquired at the entrance of the mcount
internal function, so the higher the number of cores, the more lock conflict
occurs, making profiling performance in a MULTIPROCESSOR environment unusable
and slow. Profiling buffers has been changed to be reserved for each CPU,
improving profiling performance in MP by several to several dozen times.

- Eliminated cpu_simple_lock in mcount internal function, using per-CPU buffers.
- Add ci_gmon member to struct cpu_info of each MP arch.
- Add kern.profiling.percpu node in sysctl tree.
- Add new -c <cpuid> option to kgmon(8) to specify the cpuid, like openbsd.
For compatibility, if the -c option is not specified, the entire system can be
operated as before, and the -p option will get the total profiling data for
all CPUs.
 1.7 01-Dec-2019  ad Fix false sharing problems with cpu_info. Identified with tprof(8).
This was a very nice win in my tests on a 48 CPU box.

- Reorganise cpu_data slightly according to usage.
- Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc).
- On x86, put some items in their own cache lines according to usage, like
the IPI bitmask and ci_want_resched.
 1.6 21-Nov-2019  ad mi_userret(): take care of calling preempt(), set spc_curpriority directly,
and remove MD code that does the same.
 1.5 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.4 01-Apr-2015  matt branches: 1.4.16; 1.4.20;
_KMEMUSER only needs struct cpu_info
 1.3 31-Mar-2015  matt Define curcpu() as lwp_getcpu(curlwp) since curlwp is always in the "tp"
(thread pointer) register.
 1.2 28-Mar-2015  matt Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.4.20.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.4.20.1 10-Jun-2019  christos Sync with HEAD
 1.4.16.2 03-Dec-2017  jdolecek update from HEAD
 1.4.16.1 01-Apr-2015  jdolecek file cpu.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.15.2.1 02-Aug-2025  perseant Sync with HEAD
 1.3 15-Oct-2022  simonb Use __volatile so the compiler doesn't optimise out successive calls
to cpu_counter().
Add a 64-bit cycle counter on _LP64.
 1.2 15-Oct-2022  simonb #define<tab>
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file cpu_counter.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.13 25-Nov-2024  skrll risc-v: support crash(8)
 1.12 23-Nov-2024  skrll risc-v: don't include locore.h in db_machdep.h
 1.11 22-Nov-2024  skrll G/C
 1.10 19-Nov-2024  skrll Whitespace
 1.9 02-Sep-2023  skrll branches: 1.9.6;
Fix a comment and enable RISC-V ddb mach commands
 1.8 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.7 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.6 27-Sep-2022  skrll Basic ddb and backtrace support.

[ 1.0000000] panic: kernel diagnostic assertion "msgbufaddr != 0" failed: file "/home/nick/netbsd/nbcvs/src/sys/arch/riscv/riscv/riscv_machdep.c", line 564
[ 1.0000000] cpu0: Begin traceback...
[ 1.0000000] trace fp ffffffc000801dd0
[ 1.0000000] fp ffffffc000801e10 ?() at ffffffc0001eee98
[ 1.0000000] fp ffffffc000801e30 ?() at ffffffc0002ad984
[ 1.0000000] fp ffffffc000801ee0 ?() at ffffffc000005430
[ 1.0000000] cpu0: End traceback...
[ 1.0000000] Trapframe @ 0xffffffc000801cb0 (cause=3 (breakpoint), status=0x100, pc=0xffffffc0000007e4, va=0):
[ 1.0000000] ra =0xffffffc0001eee9c, sp =0xffffffc000801dd0, gp =0xffffffc0006a8f40, tp = 0
[ 1.0000000] s0 =0xffffffc000600ac0, s1 = 0x1000, s2 =0xffffffc000438df0, s3 =0xffffffc000801d80
[ 1.0000000] s4 =0xffffffc0001eed78, s5 =0xffffffc0006d55f8, s6 =0xffffffc000801d88, s7 =0xffffffc0006dfdb8
[ 1.0000000] s8 =0xffffffc000428c18, s9 =0xffffffc000801dd0, s10=0xffffffc0000a3822, s11=0xffffffc0006d55f8
[ 1.0000000] a0 = 0x17, a1 = 0xa, a2 = 0, a3 =0xffffffc00041f658
[ 1.0000000] a4 = 0, a5 = 0x1, a5 = 0, a7 = 0x1
[ 1.0000000] t0 =0xffffffc0006dfe30, t1 =0xffffffc000801bb8, t2 =0xffffffc000803000, t3 = 0x75
[ 1.0000000] t4 = 0, t5 = 0x63, t6 = 0x1
[ 1.0000000] kernel: breakpoint
Stopped in pid 0.0 (system) at ffffffc0000007e4: c.ebreak
db>
 1.5 18-May-2021  skrll Use #define<tab> in this file
 1.4 18-May-2021  skrll Remove argument names from function declaration prototypes.
Misc tidyup.
 1.3 14-Apr-2021  dholland branches: 1.3.2; 1.3.4;
Add a ddb disassembler for riscv.

builds, but not really tested yet.
 1.2 06-Nov-2017  christos branches: 1.2.2; 1.2.20;
Cleanup and clarify the ELFSIZE mess:

We now have 2 variables automatically set in elf_machdep.h:

ARCH_ELFSIZE: the size for userland binaries
KERN_ELFSIZE: the size for the kernel binaries

DB_ELFSIZE has been deleted and KERN_ELFSIZE should have always the
same values DB_ELFSIZE used to have.

In sys/exec_elf.h, if ELFSIZE is not set, it is set to KERN_ELFSIZE
for the kernel and ARCH_ELFSIZE for userland. These defaults should
eliminate the need for most manual ELFSIZE setting.
 1.1 19-Sep-2014  matt New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.2.20.1 17-Apr-2021  thorpej Sync with HEAD.
 1.2.2.2 03-Dec-2017  jdolecek update from HEAD
 1.2.2.1 06-Nov-2017  jdolecek file db_machdep.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.3.4.1 31-May-2021  cjep sync with head
 1.3.2.1 17-Jun-2021  thorpej Sync w/ HEAD.
 1.9.6.1 02-Aug-2025  perseant Sync with HEAD
 1.2 24-May-2022  andvar s/dosen't/doesn't/ in copy pasted comment.
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file disklabel.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.10 04-Aug-2024  skrll spaces to tabs
 1.9 03-Dec-2022  skrll branches: 1.9.8;
Correct some pre-existing relocations and add some new ones.
 1.8 14-Mar-2020  skrll Trailing whitespace
 1.7 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.6 06-Nov-2017  christos branches: 1.6.2; 1.6.6;
Cleanup and clarify the ELFSIZE mess:

We now have 2 variables automatically set in elf_machdep.h:

ARCH_ELFSIZE: the size for userland binaries
KERN_ELFSIZE: the size for the kernel binaries

DB_ELFSIZE has been deleted and KERN_ELFSIZE should have always the
same values DB_ELFSIZE used to have.

In sys/exec_elf.h, if ELFSIZE is not set, it is set to KERN_ELFSIZE
for the kernel and ARCH_ELFSIZE for userland. These defaults should
eliminate the need for most manual ELFSIZE setting.
 1.5 28-May-2015  matt add ELF64_MACHDEP_ID
 1.4 01-Apr-2015  matt Add two new relocs for compressed branches.
 1.3 27-Mar-2015  matt Fix one error and make life for ld.elf_so a little easier.
 1.2 27-Mar-2015  matt Switch to new ABI (return values now in a0/a1; v0/v1 are no more)
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.2 06-Jun-2015  skrll Sync with HEAD
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.6.6.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.6.6.1 10-Jun-2019  christos Sync with HEAD
 1.6.2.2 03-Dec-2017  jdolecek update from HEAD
 1.6.2.1 06-Nov-2017  jdolecek file elf_machdep.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.9.8.1 02-Aug-2025  perseant Sync with HEAD
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file endian.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file endian_machdep.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.5 12-May-2024  riastradh riscv fenv.h: Make sure FE_* exception constants have type int.

This may not be formally required by the standard, but the values
must be representable by int since that's the type that functions
like fetestexcept and feclearexcept traffic in. And this is less
work than changing all the printf %d users in tree.
 1.4 10-May-2024  skrll Use __BIT and fix FE_INEXACT
 1.3 14-Mar-2020  skrll Trailing whitespace
 1.2 22-Mar-2017  chs branches: 1.2.12; 1.2.16;
provide a common softfloat fenv implemenation and use it for softfloat builds.
restore ABI compatibility with previous releases for ieeefp.h on sh3.
add namespace.h protection for all the fenv interfaces.
use MKSOFTFLOAT on sh3 instead of assuming softfloat.
standardize on comparing MKSOFTFLOAT with "no".
remove the arm-specific softfloat fenv code (which also had several bugs).
fix logic errors in the arm hardfloat feraiseexcept() and feupdateenv().
 1.1 19-Sep-2014  matt branches: 1.1.2; 1.1.4; 1.1.6;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.6.1 21-Apr-2017  bouyer Sync with HEAD
 1.1.4.1 26-Apr-2017  pgoyette Sync with HEAD
 1.1.2.1 28-Aug-2017  skrll Sync with HEAD
 1.2.16.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.2.12.2 03-Dec-2017  jdolecek update from HEAD
 1.2.12.1 22-Mar-2017  jdolecek file fenv.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2 30-Oct-2024  riastradh Sprinkle <sys/featuretest.h> where _*_SOURCE macros are consulted.

Otherwise, the feature tests might come out wrong. For example,
header files that check for _NETBSD_SOURCE won't get the default when
no other _*_SOURCE macros are defined; header files that check for
_POSIX_C_SOURCE might miss _XOPEN_SOURCE, which is supposed to imply
a corresponding _POSIX_C_SOURCE.

PR lib/58752: various header files test _*_SOURCE macros but don't
include sys/featuretest.h
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.58;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.58.1 02-Aug-2025  perseant Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file float.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.6 23-Jun-2023  skrll Pad the trapframe so it's a multiple of 16 bytes so that when a trapframe
is created on the stack SP remains 16-byte aligned as per the ABI
requirements.

Patch from Rin with some updates from me.
 1.5 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.4 04-Nov-2020  skrll Fix some of the previous - I must have compile tested the wrong tree
 1.3 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.2 14-Mar-2020  skrll branches: 1.2.4;
Trailing whitespace
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file frame.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2.4.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.2 13-Apr-2019  maya Our current configuration is that long double is 128bit, so reflect
that in the relevant headers.

Taken from sparc64.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file ieee.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2 14-Mar-2020  skrll Trailing whitespace
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file ieeefp.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.5 02-Feb-2024  andvar fix various typos in comments.
 1.4 19-Apr-2021  dholland Make the riscv disassembler work, as best as I can test from amd64 userspace.
 1.3 14-Apr-2021  dholland Add a ddb disassembler for riscv.

builds, but not really tested yet.
 1.2 04-Nov-2020  skrll branches: 1.2.2;
RCSID and whitespace police...
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.34;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.34.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file insn.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2.2.1 17-Apr-2021  thorpej Sync with HEAD.
 1.3 12-Jan-2025  skrll risc-v: Fix UINT32_C.

PR port-riscv/58766 ntpd / ntpdate setting time on risc64 fails to work
 1.2 04-Jul-2023  riastradh branches: 1.2.6;
riscv: Fix (U)INT64_C suffix to match gcc's built-in idea of types.

XXX pullup-10
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file int_const.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2.6.1 02-Aug-2025  perseant Sync with HEAD
 1.4 17-Apr-2019  mrg fix for riscv32.
 1.3 16-Apr-2019  maya We're now using gcc netbsd-stdint.h instead of our own definitions, so
match those with the format types

XXX wrong for 32bit.
XXX unclear if changing the fast types was the right call
 1.2 13-Apr-2019  maya Provide defines for the 64bit case.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file int_fmtio.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file int_limits.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file int_mwgwtypes.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file int_types.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.7 19-Nov-2024  skrll risc-v: expose intr_establish_xname
 1.6 04-Aug-2024  skrll spaces to tabs
 1.5 03-Sep-2023  skrll branches: 1.5.6;
Fix and enable MULTIPROCESSOR
 1.4 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.3 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2 28-Mar-2015  matt branches: 1.2.16;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.2.16.2 03-Dec-2017  jdolecek update from HEAD
 1.2.16.1 28-Mar-2015  jdolecek file intr.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.5.6.1 02-Aug-2025  perseant Sync with HEAD
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file kcore.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file limits.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.1 05-May-2021  jmcneill branches: 1.1.4;
Add loadfile_machdep.h for riscv
 1.1.4.2 13-May-2021  thorpej Sync with HEAD.
 1.1.4.1 05-May-2021  thorpej file loadfile_machdep.h was added on branch thorpej-i2c-spi-conf on 2021-05-13 00:47:27 +0000
 1.4 26-Jun-2015  matt branches: 1.4.16;
Move the riscv lock.h which uses only compiler builtin atomic primitives
to a common location which can be used by others and make riscv's lock.h
use it.
 1.3 26-Jun-2015  matt Fix c&p error.
 1.2 29-Mar-2015  matt Use C11 atomic builtins instead of __asm.
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.2 22-Sep-2015  skrll Sync with HEAD
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.4.16.2 03-Dec-2017  jdolecek update from HEAD
 1.4.16.1 26-Jun-2015  jdolecek file lock.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.14 22-Nov-2024  skrll risc-v: split userret into its own header as per other ports

Helps with crash(8)
 1.13 02-May-2024  skrll branches: 1.13.2;
risc-v: fix the error code when uvm_fault fails with cpu_set_onfault

Return the error from uvm_fault instead of EFAULT unconditionally when
faulting with cpu_set_onfault to fix several atf tests.
 1.12 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.11 20-Sep-2022  skrll Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|

Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3

Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes

Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509
 1.10 05-Oct-2021  jmcneill #define<tab>
 1.9 05-Oct-2021  skrll Fix riscv32 GENERIC build
 1.8 01-May-2021  skrll Sprinkle #ifdef FPE for now
 1.7 04-Nov-2020  skrll branches: 1.7.4;
RCSID and whitespace police...
 1.6 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.5 14-Mar-2020  skrll branches: 1.5.4;
Trailing whitespace
 1.4 11-Apr-2019  kamil Fix a typo in a comment
 1.3 16-Mar-2017  chs branches: 1.3.12; 1.3.16;
allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.
 1.2 28-Mar-2015  matt branches: 1.2.2; 1.2.4;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.2 28-Aug-2017  skrll Sync with HEAD
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.2.4.1 21-Apr-2017  bouyer Sync with HEAD
 1.2.2.1 20-Mar-2017  pgoyette Sync with HEAD
 1.3.16.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.3.16.1 10-Jun-2019  christos Sync with HEAD
 1.3.12.2 03-Dec-2017  jdolecek update from HEAD
 1.3.12.1 16-Mar-2017  jdolecek file locore.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.5.4.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.7.4.1 13-May-2021  thorpej Sync with HEAD.
 1.13.2.1 02-Aug-2025  perseant Sync with HEAD
 1.2 04-Nov-2024  christos Undo previous lwp.h change.
 1.1 03-Nov-2024  christos Split __lwp_getprivate_fast and __lwp_*tcb from mcontext.h into a separate
lwp.h file.
 1.1 30-Nov-2024  christos branches: 1.1.4;
Create a new header lwp_private.h to contain _lwp_getprivate_fast,
_lwp_gettcb_fast, _lwp_settcb and remove them from mcontext.h, so that:
1. we don't need special hacks to hide them
2. we can include <lwp.h> where needed to get the necessary prototypes
without redefining them locally.
 1.1.4.2 02-Aug-2025  perseant Sync with HEAD
 1.1.4.1 30-Nov-2024  perseant file lwp_private.h was added on branch perseant-exfatfs on 2025-08-02 05:56:03 +0000
 1.6 02-Feb-2025  skrll KNF - sort includes.
 1.5 12-Jun-2023  skrll branches: 1.5.6;
risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.4 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.3 16-Oct-2022  skrll Map the DTB using VM_KERNEL_DTB_BASE and CONSADDR using VM_KERNEL_IO_BASE
 1.2 28-Sep-2022  skrll Use legacy SBI Console GetChar for earlycons. It works on qemu.
 1.1 20-Sep-2022  skrll Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|

Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3

Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes

Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509
 1.5.6.1 02-Aug-2025  perseant Sync with HEAD
 1.3 16-Apr-2019  maya RISC-V ELF psABI says ILP32 also defaults to 128bit long double.
 1.2 13-Apr-2019  maya Our current configuration is that long double is 128bit, so reflect
that in the relevant headers.

Taken from sparc64.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file math.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.12 30-Nov-2024  christos Create a new header lwp_private.h to contain _lwp_getprivate_fast,
_lwp_gettcb_fast, _lwp_settcb and remove them from mcontext.h, so that:
1. we don't need special hacks to hide them
2. we can include <lwp.h> where needed to get the necessary prototypes
without redefining them locally.
 1.11 04-Nov-2024  christos Undo previous lwp.h change.
 1.10 03-Nov-2024  christos Split __lwp_getprivate_fast and __lwp_*tcb from mcontext.h into a separate
lwp.h file.
 1.9 31-May-2024  skrll branches: 1.9.2;
Add more ABI register defines - should have been committed with previous
change.
 1.8 04-May-2024  skrll Fix the __greg_t typedef for riscv32
 1.7 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.6 14-Mar-2020  skrll Trailing whitespace
 1.5 15-Feb-2018  kamil branches: 1.5.4;
Introduce _UC_MACHINE_FP() as a macro

_UC_MACHINE_FP() is a helper macro to extract from mcontext a frame pointer.

Don't rely on this interface as a compiler might strip frame pointer or
optimize it making this interface unreliable.


For hppa assume a small frame context, for larger frames FP might be located
in a different register (4 instead of 3).

For ia64 there is no strict frame pointer, and registers might rotate.
Reuse 79 following:

./gcc/config/ia64/ia64.h:#define HARD_FRAME_POINTER_REGNUM LOC_REG (79)

Once ia64 will mature, this should be revisited.

A macro can encapsulate a real function for extracting Frame Pointer on
more complex CPUs / ABIs.


For the remaining CPUs, reuse standard register as defined in appropriate ABI.

The direct users of this macro are LLVM and GCC with Sanitizers.

Proposed on tech-userlevel@.

Sponsored by <The NetBSD Foundation>
 1.4 01-Apr-2015  matt branches: 1.4.10; 1.4.16;
Add _REG_S0
 1.3 27-Mar-2015  matt Switch to new ABI (return values now in a0/a1; v0/v1 are no more)
 1.2 24-Oct-2014  dennis branches: 1.2.2;
Fix a typo: the PC is likely in _REG_PC
 1.1 19-Sep-2014  matt New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.2.2.1 06-Apr-2015  skrll Sync with HEAD
 1.4.16.2 03-Dec-2017  jdolecek update from HEAD
 1.4.16.1 01-Apr-2015  jdolecek file mcontext.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.4.10.3 21-Mar-2018  martin Pull up the following, requested by kamil in ticket #552:

external/gpl3/gcc{.old}/dist/libsanitizer/asan/asan_linux.cc 1.4
sys/arch/aarch64/include/mcontext.h 1.2
sys/arch/alpha/include/mcontext.h 1.9
sys/arch/amd64/include/mcontext.h 1.19
sys/arch/arm/include/mcontext.h 1.19
sys/arch/hppa/include/mcontext.h 1.9
sys/arch/i386/include/mcontext.h 1.14
sys/arch/ia64/include/mcontext.h 1.6
sys/arch/m68k/include/mcontext.h 1.10
sys/arch/mips/include/mcontext.h 1.22
sys/arch/or1k/include/mcontext.h 1.2
sys/arch/powerpc/include/mcontext.h 1.18
sys/arch/riscv/include/mcontext.h 1.5
sys/arch/sh3/include/mcontext.h 1.11
sys/arch/sparc/include/mcontext.h 1.14-1.17
sys/arch/sparc64/include/mcontext.h 1.10
sys/arch/vax/include/mcontext.h 1.9
tests/lib/libc/sys/Makefile 1.50
tests/lib/libc/sys/t_ucontext.c 1.2-1.5
sys/arch/hppa/include/mcontext.h 1.10
sys/arch/ia64/include/mcontext.h 1.7

- Introduce _UC_MACHINE_FP(). _UC_MACHINE_FP() is a helper
macro to extract from mcontext a frame pointer.
- Add new tests in lib/libc/sys/t_ucontext:
* ucontext_sp (testing _UC_MACHINE_SP)
* ucontext_fp (testing _UC_MACHINE_FP)
* ucontext_pc (testing _UC_MACHINE_PC)
* ucontext_intrv (testing _UC_MACHINE_INTRV)

Add a dummy implementation of _UC_MACHINE_INTRV() for ia64.

Implement _UC_MACHINE_INTRV() for hppa.

Make the t_ucontext.c test more portable.

We now have _UC_MACHINE_FP.
 1.4.10.2 26-Feb-2018  snj revert ticket 552, which broke the build
 1.4.10.1 25-Feb-2018  snj Pull up following revision(s) (requested by kamil in ticket #552):
sys/arch/aarch64/include/mcontext.h: 1.2
sys/arch/alpha/include/mcontext.h: 1.9
sys/arch/amd64/include/mcontext.h: 1.19
sys/arch/arm/include/mcontext.h: 1.19
sys/arch/hppa/include/mcontext.h: 1.9
sys/arch/i386/include/mcontext.h: 1.14
sys/arch/ia64/include/mcontext.h: 1.6
sys/arch/m68k/include/mcontext.h: 1.10
sys/arch/mips/include/mcontext.h: 1.22
sys/arch/or1k/include/mcontext.h: 1.2
sys/arch/powerpc/include/mcontext.h: 1.18
sys/arch/riscv/include/mcontext.h: 1.5
sys/arch/sh3/include/mcontext.h: 1.11
sys/arch/sparc/include/mcontext.h: 1.14-1.17
sys/arch/sparc64/include/mcontext.h: 1.10
sys/arch/vax/include/mcontext.h: 1.9
tests/lib/libc/sys/Makefile: 1.50
tests/lib/libc/sys/t_ucontext.c: 1.2
Introduce _UC_MACHINE_FP() as a macro
_UC_MACHINE_FP() is a helper macro to extract from mcontext a frame pointer.
Don't rely on this interface as a compiler might strip frame pointer or
optimize it making this interface unreliable.
For hppa assume a small frame context, for larger frames FP might be located
in a different register (4 instead of 3).
For ia64 there is no strict frame pointer, and registers might rotate.
Reuse 79 following:
./gcc/config/ia64/ia64.h:#define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
Once ia64 will mature, this should be revisited.
A macro can encapsulate a real function for extracting Frame Pointer on
more complex CPUs / ABIs.
For the remaining CPUs, reuse standard register as defined in appropriate ABI.
The direct users of this macro are LLVM and GCC with Sanitizers.
Proposed on tech-userlevel@.
Sponsored by <The NetBSD Foundation>
--
Improve _UC_MACHINE_FP() for SPARC/SPARC64
Introduce a static inline function _uc_machine_fp() that contains improved
caluclation of a frame pointer.
Algorithm:
uptr *stk_ptr;
# if defined (__arch64__)
stk_ptr = (uptr *) (*sp + 2047);
# else
stk_ptr = (uptr *) *sp;
# endif
*bp = stk_ptr[15];
Noted by <mrg>
--
Make _UC_MACHINE_FP() compile again and fix it so that it does not add
the offset twice.
--
fix _UC_MACHINE32_FP() -- use 32 bit pointer value so that [15] is
the right offset. do this by using __greg32_t, which is only in
the sparc64 version, and these are only useful there, so move them.
--
Add new tests in lib/libc/sys/t_ucontext
New tests:
- ucontext_sp
- ucontext_fp
- ucontext_pc
- ucontext_intrv
They test respectively:
- _UC_MACHINE_SP
- _UC_MACHINE_FP
- _UC_MACHINE_PC
- _UC_MACHINE_INTRV
These tests attempt to access and print the values from ucontext, without
interpreting the values.
This is a follow up of the _UC_MACHINE_FP() introduction.
These tests use PRIxREGISTER, and require to be built with -D_KERNTYPES.
Sponsored by <The NetBSD Foundation>
 1.5.4.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.9.2.1 02-Aug-2025  perseant Sync with HEAD
 1.7 25-Nov-2024  skrll risc-v: support crash(8)
 1.6 12-Jul-2023  riastradh branches: 1.6.6;
machine/mutex.h: Sprinkle sys/types.h, omit machine/lock.h.

Turns out machine/lock.h is not needed for __cpu_simple_lock_t, which
always comes from sys/types.h. And, really, sys/types.h (or at least
sys/stdint.h) is needed for uintN_t and uintptr_t.
 1.5 09-Jul-2023  riastradh machine/mutex.h: Sprinkle includes so this can be used by crash(8).

XXX pullup-10
 1.4 25-Aug-2021  thorpej branches: 1.4.4;
- In kern_mutex.c, if MUTEX_CAS() is not defined, define it in terms of
atomic_cas_ulong().
- For arm, ia64, m68k, mips, or1k, riscv, vax: don't define our own
MUTEX_CAS(), as they either use atomic_cas_ulong() or equivalent
(atomic_cas_uint() on m68k).
- For alpha and sparc64, don't define MUTEX_CAS() in terms of their own
_lock_cas(), which has its own memory barriers; the call sites in
kern_mutex.c already have the appropriate memory barrier calls. Thus,
alpha and sparc64 can use default definition.
- For sh3, don't define MUTEX_CAS() in terms of its own _lock_cas();
atomic_cas_ulong() is strong-aliased to _lock_cas(), therefore defining
our own MUTEX_CAS() is redundant.

Per thread:
https://mail-index.netbsd.org/tech-kern/2021/07/25/msg027562.html
 1.3 29-Nov-2019  riastradh Nix now-unused definitions of MUTEX_GIVE/MUTEX_RECEIVE.
 1.2 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file mutex.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.4.4.1 09-Aug-2023  martin Pull up following revision(s) (requested by maya in ticket #316):

sys/arch/m68k/include/mutex.h: revision 1.13
sys/arch/arm/include/cpu.h: revision 1.125
sys/arch/sun68k/include/intr.h: revision 1.21
sys/arch/arm/include/mutex.h: revision 1.28
sys/sys/rwlock.h: revision 1.18
sys/arch/powerpc/include/mutex.h: revision 1.7
sys/arch/arm/include/mutex.h: revision 1.29
sys/arch/powerpc/include/mutex.h: revision 1.8
sys/uvm/uvm_param.h: revision 1.42
sys/sys/ksem.h: revision 1.16
sys/arch/x86/include/mutex.h: revision 1.10
sys/sys/proc.h: revision 1.372
sys/sys/ksem.h: revision 1.17
sys/arch/ia64/include/mutex.h: revision 1.8
sys/arch/evbarm/include/intr.h: revision 1.29
sys/sys/lua.h: revision 1.9
sys/arch/next68k/include/intr.h: revision 1.23
sys/arch/ia64/include/mutex.h: revision 1.9
sys/arch/hp300/include/intr.h: revision 1.35
sys/arch/hp300/include/intr.h: revision 1.36
sys/arch/sparc/include/cpu.h: revision 1.111
sys/arch/hppa/include/mutex.h: revision 1.16
sys/arch/vax/include/intr.h: revision 1.31
sys/arch/hppa/include/mutex.h: revision 1.17
sys/arch/news68k/include/intr.h: revision 1.28
sys/arch/hppa/include/mutex.h: revision 1.18
sys/arch/hppa/include/intr.h: revision 1.3
sys/arch/hppa/include/mutex.h: revision 1.19
sys/arch/hppa/include/intr.h: revision 1.4
sys/sys/sched.h: revision 1.92
sys/opencrypto/cryptodev.h: revision 1.51
sys/arch/vax/include/mutex.h: revision 1.20
sys/arch/sparc64/include/mutex.h: revision 1.10
sys/arch/ia64/include/sapicvar.h: revision 1.2
sys/arch/riscv/include/mutex.h: revision 1.5
sys/arch/amiga/dev/grfabs_cc.c: revision 1.39
sys/external/bsd/drm2/include/linux/idr.h: revision 1.11
sys/arch/riscv/include/mutex.h: revision 1.6
sys/ddb/files.ddb: revision 1.16
sys/arch/mac68k/include/intr.h: revision 1.32
share/man/man4/ddb.4: revision 1.203
sys/ddb/db_command.c: revision 1.183
sys/arch/mips/include/mutex.h: revision 1.10
sys/ddb/db_command.c: revision 1.184
sys/arch/x68k/include/intr.h: revision 1.22
sys/arch/sparc/include/psl.h: revision 1.51
sys/arch/or1k/include/mutex.h: revision 1.4
sys/arch/mips/include/mutex.h: revision 1.11
sys/arch/arm/xscale/pxa2x0_intr.h: revision 1.16
sys/arch/sparc64/include/cpu.h: revision 1.134
sys/arch/sparc/include/psl.h: revision 1.52
sys/arch/or1k/include/mutex.h: revision 1.5
sys/arch/mvme68k/include/intr.h: revision 1.22
sys/arch/luna68k/include/intr.h: revision 1.16
external/cddl/osnet/sys/sys/kcondvar.h: revision 1.6
sys/arch/sparc/include/mutex.h: revision 1.12
sys/arch/sparc/include/mutex.h: revision 1.13
sys/arch/usermode/include/mutex.h: revision 1.5
sys/arch/usermode/include/mutex.h: revision 1.6
sys/kern/kern_core.c: revision 1.38
usr.sbin/crash/Makefile: revision 1.49
sys/arch/amiga/include/intr.h: revision 1.23
sys/arch/alpha/include/mutex.h: revision 1.12
sys/arch/alpha/include/mutex.h: revision 1.13
sys/arch/evbarm/lubbock/sacc_obio.c: revision 1.16
sys/ddb/ddb.h: revision 1.6
sys/arch/sparc64/include/mutex.h: revision 1.8
sys/arch/sh3/include/mutex.h: revision 1.12
sys/arch/evbarm/lubbock/sacc_obio.c: revision 1.17
sys/ddb/db_syncobj.c: revision 1.1
sys/arch/vax/include/mutex.h: revision 1.18
sys/arch/sparc64/include/psl.h: revision 1.63
sys/arch/sparc64/include/mutex.h: revision 1.9
sys/arch/sh3/include/mutex.h: revision 1.13
sys/arch/evbarm/lubbock/obio.c: revision 1.13
sys/arch/atari/include/intr.h: revision 1.23
sys/ddb/db_syncobj.c: revision 1.2
sys/arch/vax/include/mutex.h: revision 1.19
sys/arch/evbarm/g42xxeb/obio.c: revision 1.14
sys/arch/evbarm/g42xxeb/obio.c: revision 1.15
sys/arch/cesfic/include/intr.h: revision 1.14
sys/ddb/db_syncobj.h: revision 1.1
sys/arch/x86/include/cpu.h: revision 1.134
sys/arch/evbarm/g42xxeb/obio.c: revision 1.16
sys/arch/cesfic/include/intr.h: revision 1.15
sys/arch/arm/xscale/pxa2x0_intr.c: revision 1.26
sys/sys/cpu_data.h: revision 1.54
sys/arch/m68k/include/mutex.h: revision 1.12
sys/arch/ia64/acpi/madt.c: revision 1.6

sys/rwlock.h: Make this more self-contained for bool.

machine/mutex.h: Sprinkle includes so this can be used by crash(8).

ddb: New `show all tstiles' command.
Shows who's waiting for which locks and what the owner is up to.

Include psl.h for ipl_cookie_t if __MUTEX_PRIVATE

sys: Rip <sys/resourcevar.h> out of <uvm/uvm_param.h>.

And thus out of <sys/param.h>, which is exceedingly overused and
fragile and delenda est.

Should fix (some) issues with the recent inclusion of machine/lock.h
in various machine/mutex.h files.

arm/mutex.h: Need machine/intr.h, machine/lock.h.

For ipl_cookie_t and __cpu_simple_lock_t.
evbarm/intr.h: Define ipl_cookie_t before including ARM_INTR_IMPL.

Otherwise arm/mutex.h doesn't work, due to a cyclic dependency which
should really be fixed.
opencrypto/cryptodev.h: Fix includes.
- Move sys/condvar.h under #ifdef _KERNEL.
- Add some other necessary includes and forward declarations.
- Sort.

hp300/intr.h: Fix missing includes.
linux/idr.h: Need <sys/mutex.h> for kmutex_t.
amiga/intr.h: Don't define spl*() functions if !_KERNEL.

This is used by crash(8) now, and what's important is ipl_cookie_t.
cesfic/intr.h: Expose ipl_cookie_t to userland for crash(8).
cesfic/intr.h: Expose ipl_cookie_t to userland only with _KMEMUSER.

Probably not necessary but let's be a little more cautious about
this.

atari/intr.h: Expose ipl_cookie_t with _KMEMUSER for crash(8).

arm/cpu.h: Need sys/param.h for COHERENCY_UNIT.

Nix machine/param.h -- not meant to be used directly, pulled in by
sys/param.h.

Move the definition of ipl_cookie_t out of the kernel-only sections,
some _KMEMUSER applications need it.

ddb: Cast pointer to uintptr_t first before db_expr_t.

hppa/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

luna68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

mvme68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

news68k/intr.h: Fix includes. Put some definitions under _KERNEL.

next68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

sys/ksem.h: Hack around fstat(8) abuse of _KERNEL.

sun68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

vax/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

x68k/intr.h: Put functions under _KERNEL so crash(8) can use this.

Make ipl_cookie_t visible for _KMEMUSER userland applications.

fix editor mishap in previous

Explicitly include <sys/mutex.h> for kmutex_t.

Replace kmutex_t * (which may be undefined here) with struct kmutex *,
suggested by Taylor.

hp300/intr.h: Put most of this under #ifdef _KERNEL.
Only ipl_cookie_t really needs to be exposed now, for crash(8).

mac68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).
Make inclusion of sys/intr.h explicit for spl*.

fix hppa and vax builds.

machine/lock.h isn't necessary for __cpu_simple_lock_t, it's in
sys/types.h. avoids cpu_data.h vs sched.h include order issues.

move the hppa ipl_t typedef with the moved usage of it.
machine/mutex.h: Sprinkle sys/types.h, omit machine/lock.h.

Turns out machine/lock.h is not needed for __cpu_simple_lock_t, which
always comes from sys/types.h. And, really, sys/types.h (or at least
sys/stdint.h) is needed for uintN_t and uintptr_t.

ddb: Cast pointer to uintptr_t, then to db_expr_t.
Avoids warnings about conversion between pointer and integer of
different size on some architectures.

re-fix hppa builds.

this file uses __cpu_simple_lock(), not just the underlying type,
so it does need machine/lock.h.

Break cycle by using `struct kmutex *' instead of `kmutex_t *'.
sys/sched.h included sys/mutex.h
which includes sys/intr.h
which includes machine/intr.h
which on cats includes arm/footbridge/footbridge_intr.h
which includes arm/cpu.h
which includes sys/cpu_data.h
which includes sys/sched.h

But there was never any real need for sys/mutex.h in sys/sched.h,
because it only uses pointers to the opaque struct kmutex. Cycle
broken by using `struct kmutex *' instead of pulling in sys/mutex.h
for the definition of kmutex_t.

Side effect: This revealed that sys/cpu_data.h needed sys/intr.h
(which was pulled in accidentally by sys/mutex.h via sys/sched.h) for
SOFTINT_COUNT. Also revealed some other machine/cpu.h header files
were missing includes of sys/mutex.h for kmutex_t.

ia64: Need sys/types.h for u_int, vaddr_t; sys/mutex.h for kmutex_t.

explicitly include no longer implicitly included sys/mutex.h.

arm/xscale: Use sys/bitops.h fls32 - 1 instead of 31 - __builtin_clz.
Sidesteps namespace collision with `#define bits ...' in net/zlib.c.

complete the previous - there were two calls to find_first_bit() to fix.

arm/xscale: Missed a spot with previous find_first_bit commit.

evbarm/g42xxeb: Fix off-by-one in previous.

The original find_first_bit(x) was 31 - __builtin_clz((uint32_t)x),
which is equivalent to fls32(x) - 1, not to fls32(x).

Note that fls32 is 1-based and returns 0 for x=0.
 1.6.6.1 02-Aug-2025  perseant Sync with HEAD
 1.2 28-May-2024  skrll Change MIPS to RISC-V.
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file netbsd32_machdep.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.8 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.7 12-Oct-2022  simonb NKMEMPAGES_MIN_DEFAULT is in pages not bytes (hint is in the name).
Also set NKMEMPAGES_MAX_UNLIMITED while we're here.
 1.6 19-Jul-2021  christos Remove definitions for CACHE_LINE_SIZE and COHERENCY_UNIT which are the same
as the default.
 1.5 31-May-2021  simonb Include "opt_param.h" (ifdef _KERNEL_OPT) everywhere that MSGBUFSIZE is
referenced since some sources include <machine/param.h>.
 1.4 01-May-2021  skrll Bump MSGBUFSIZE (if not defined)

Provide COHERENCY_UNIT and CACHE_LINE_SIZE

Also provide MAXCPUS
 1.3 01-Jun-2019  maxv branches: 1.3.14;
Misc changes in RISC-V. Start changing the memory layout, too.
 1.2 07-Jan-2019  jdolecek move DEV_BSIZE, DEV_BSHIFT out of MD param.h, they are same on all ports

also move BLKDEV_IOSIZE, MAXPHYS, but allow override since some ports
have different value (powerpc uses NBPG for BLKDEV_IOSIZE, sun2/sun3
have lower MAXPHYS)
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.20; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.20.1 18-Jan-2019  pgoyette Synch with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file param.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.3.14.3 01-Aug-2021  thorpej Sync with HEAD.
 1.3.14.2 17-Jun-2021  thorpej Sync w/ HEAD.
 1.3.14.1 13-May-2021  thorpej Sync with HEAD.
 1.3 04-Aug-2024  skrll spaces to tabs
 1.2 07-May-2023  skrll branches: 1.2.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file pcb.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2.6.1 02-Aug-2025  perseant Sync with HEAD
 1.1 01-Jan-2025  skrll branches: 1.1.4;
risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.
 1.1.4.2 02-Aug-2025  perseant Sync with HEAD
 1.1.4.1 01-Jan-2025  perseant file pci_machdep.h was added on branch perseant-exfatfs on 2025-08-02 05:56:03 +0000
 1.25 12-Oct-2025  thorpej Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/
 1.24 04-Aug-2024  skrll branches: 1.24.2;
spaces to tabs
 1.23 01-Jan-2024  skrll branches: 1.23.2;
risc-v: probe the number of supported ASIDs

Flush the entire TLB if no ASIDs are supported on pmap_activate.
 1.22 06-Oct-2023  skrll Not all RISC-V CPUs have ASIDs
 1.21 03-Sep-2023  skrll Fix and enable MULTIPROCESSOR
 1.20 12-Aug-2023  skrll risc-v: Use 'onproc' for 2nd arg of pmap_md_page_syncicache

Match other definitions of pmap_md_page_syncicache argument naming by
renaming the 2nd arg to 'onproc'
 1.19 26-Jul-2023  skrll G/C pmap_md_kernel_*
 1.18 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.17 08-May-2023  skrll Remove some #if 0'ed code
 1.16 08-May-2023  skrll KNF
 1.15 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.14 23-Dec-2022  skrll Fix RV builds
 1.13 20-Oct-2022  skrll Add the "memory" clobber in two places that it's needed.
 1.12 18-Oct-2022  skrll Correct XSEGSHIFT for RV32 case
 1.11 15-Oct-2022  simonb #define<tab>
 1.10 20-Sep-2022  skrll Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|

Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3

Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes

Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509
 1.9 01-May-2021  skrll Fixup some pmap / VM related #defines and code
 1.8 20-Dec-2020  skrll branches: 1.8.4;
Support __HAVE_PMAP_PV_TRACK in sys/uvm/pmap based pmaps (aka common pmap)
 1.7 15-Nov-2020  skrll This file is #define<space>
 1.6 10-Aug-2020  skrll branches: 1.6.2;
Whitespace
 1.5 07-Aug-2020  skrll Provide a pmap_segtab_deactivate for symmetry with pmap_segtab_activate
and use it in pmap_deactivate

Call pmap_md_xtab_{,de}activate from pmap_segtab_{,de}activate to be used
for PMAP_HWPAGEWALKER and any caches ops that might be required.

Provide empty (for now) pmap_md_xtab_{,de}activate functions on the
platforms that use sys/uvm/pmap
 1.4 11-Mar-2020  thorpej With DEBUG defined, it's possible to execute a TLB-vs-segmap consistency
check from a (soft) interrupt handler. But if a platform does not otherwise
require the pmap_tlb_miss_lock, then where will be a brief window of
inconsistency that, while harmless, will still fire an assertion in the
consistency check.

Fix this with the following changes:
1- Refactor the pmap_tlb_miss_lock into MI code and rename it from
pmap_tlb_miss_lock_{enter,exit}() to pmap_tlb_miss_lock_{enter,exit}().
MD code can still define the "md" hooks as necessary, and if so, will
override the common implementation.
2- Provde a pmap_bootstrap_common() function to perform common pmap bootstrap
operations, namely initializing the pmap_tlb_miss_lock if it's needed.
If MD code overrides the implementation, it's responsible for initializing
its own lock.
3- Call pmap_bootstrap_common() from the mips, powerpc booke, and riscv
pmap_bootstrap() routines. (This required adding one for riscv.)
4- Switch powerpc booke to the common pmap_tlb_miss_lock.
5- Enable pmap_tlb_miss_lock if DEBUG is defined, even if it's not otherwise
required.

PR port-mips/55062 (Failed assertion in pmap_md_tlb_check_entry())
 1.3 16-Jun-2019  maxv Misc changes in RISC-V.
 1.2 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.3 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.1.22.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file pmap.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.6.2.2 03-Jan-2021  thorpej Sync w/ HEAD.
 1.6.2.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.8.4.1 13-May-2021  thorpej Sync with HEAD.
 1.23.2.1 02-Aug-2025  perseant Sync with HEAD
 1.24.2.1 26-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #67):

sys/arch/riscv/include/sysreg.h: revision 1.34
sys/arch/riscv/include/pte.h: revision 1.15
sys/arch/riscv/include/pte.h: revision 1.16
sys/arch/riscv/riscv/genassym.cf: revision 1.17
sys/arch/riscv/riscv/locore.S: revision 1.47
sys/arch/riscv/riscv/bus_space.c: revision 1.3
sys/arch/riscv/include/pmap.h: revision 1.25
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.22
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.23
sys/arch/riscv/riscv/cpu.c: revision 1.10
sys/arch/riscv/riscv/riscv_machdep.c: revision 1.46

Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.

Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/


Fix RV32 build. Svpbmt and Memory Attribute Extension (XTheadMae) are
SV39 and above only.
 1.2 12-Jul-2018  maxv Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.20; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.20.1 28-Jul-2018  pgoyette Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file pmc.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.6 04-Aug-2024  skrll spaces to tabs
 1.5 08-May-2023  skrll branches: 1.5.6;
Don't expose vaddr_t or register_t to userland. The gdb configure script
needs this so it can detect struct lwp correctly.
 1.4 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.3 31-Mar-2015  matt branches: 1.3.16;
Optimize the exception handle a little bit more.
 1.2 31-Mar-2015  matt Add a md_tp member to mdlwp so that the exception handler can temporarily
store the user's thread pointer before saving it in the trapframe.
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.3.16.2 03-Dec-2017  jdolecek update from HEAD
 1.3.16.1 31-Mar-2015  jdolecek file proc.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.5.6.1 02-Aug-2025  perseant Sync with HEAD
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file profile.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.17 13-Oct-2025  skrll risc-v: pte_make_enter set PTE_D when page is known to be modified.

PR/59696: pte_make_enter() appears to have bug vis a vis already-modified managed pages
 1.16 12-Oct-2025  skrll Fix RV32 build. Svpbmt and Memory Attribute Extension (XTheadMae) are
SV39 and above only.
 1.15 12-Oct-2025  thorpej Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/
 1.14 12-Oct-2024  skrll branches: 1.14.2;
Install pte.h for libkvm
 1.13 07-May-2023  skrll branches: 1.13.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.12 22-Apr-2023  skrll G/C pte_index
 1.11 12-Nov-2022  skrll Note some SV39 PTE bits defined in extensions.

Fix pte_nv_entry for the kernel.

Fix pte_pde_ptpage. PTE.{X,W,R} must be zero for pointer to next level.
 1.10 18-Oct-2022  skrll Some fixes from Simon.
 1.9 15-Oct-2022  simonb #define<tab>
 1.8 30-Sep-2022  skrll Don't set A, D in page table pointers, but do set them in leaf entries.

Beagle-v now boots to the msgbufaddr panic same as qemu
 1.7 21-Sep-2022  skrll Use c99 types. NFC.
 1.6 01-May-2021  skrll Fixup some pmap / VM related #defines and code
 1.5 01-Nov-2020  skrll branches: 1.5.4;
Comments from zmcgrew@
 1.4 14-Mar-2020  skrll branches: 1.4.4;
Trailing whitespace
 1.3 16-Jun-2019  maxv Misc changes in RISC-V.
 1.2 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.3 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.1.22.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file pte.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.4.4.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.5.4.1 13-May-2021  thorpej Sync with HEAD.
 1.13.6.1 02-Aug-2025  perseant Sync with HEAD
 1.14.2.2 26-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #68):

sys/arch/riscv/include/pte.h: revision 1.17

risc-v: pte_make_enter set PTE_D when page is known to be modified.

PR/59696: pte_make_enter() appears to have bug vis a vis=20
already-modified managed pages
 1.14.2.1 26-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #67):

sys/arch/riscv/include/sysreg.h: revision 1.34
sys/arch/riscv/include/pte.h: revision 1.15
sys/arch/riscv/include/pte.h: revision 1.16
sys/arch/riscv/riscv/genassym.cf: revision 1.17
sys/arch/riscv/riscv/locore.S: revision 1.47
sys/arch/riscv/riscv/bus_space.c: revision 1.3
sys/arch/riscv/include/pmap.h: revision 1.25
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.22
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.23
sys/arch/riscv/riscv/cpu.c: revision 1.10
sys/arch/riscv/riscv/riscv_machdep.c: revision 1.46

Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.

Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/


Fix RV32 build. Svpbmt and Memory Attribute Extension (XTheadMae) are
SV39 and above only.
 1.6 03-May-2024  skrll Use the _X_FOO register macros instead of magic numbers.
 1.5 14-Sep-2023  rin riscv: ptrace: Add PTRACE_ILLEGAL_ASM for ATF

All related tests successfully pass.
 1.4 24-Aug-2023  rin riscv: Add PTRACE_BREAKPOINT and friends for ATF

Since its size must be determined a priori, explicitly use
c.ebreak for sure.

Now, related tests in ATF successfully pass for riscv64,
as far as I can see.
 1.3 18-Jun-2019  kamil Introduce PTRACE_REG_FP() a helper macro to retrieve the frame pointer

The macro is dummy for ia64 (the FP register is unknown and can change
freely) and sparc/sparc64 (not stored in struct reg).
 1.2 15-Sep-2015  christos branches: 1.2.16; 1.2.20;
Provide access to pc/sp/syscall-return registers like we have for mcontext
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.1 22-Sep-2015  skrll Sync with HEAD
 1.2.20.1 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.2.16.2 03-Dec-2017  jdolecek update from HEAD
 1.2.16.1 15-Sep-2015  jdolecek file ptrace.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.10 13-Dec-2022  skrll KNF
 1.9 12-Oct-2022  simonb Fix a tyop regname in a comment.
 1.8 07-Nov-2020  skrll Whitespace
 1.7 07-Nov-2020  skrll Indent and annotate FP registers much like the general registers
 1.6 07-Nov-2020  skrll Note if a register is Caller / Callee saved
 1.5 04-Nov-2020  skrll whitespace in comments
 1.4 04-Nov-2020  skrll typo in comment
 1.3 04-Nov-2020  skrll Remove incorrect comment
 1.2 27-Mar-2015  matt branches: 1.2.16; 1.2.32;
Switch to new ABI (return values now in a0/a1; v0/v1 are no more)
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.2.32.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.2.16.2 03-Dec-2017  jdolecek update from HEAD
 1.2.16.1 27-Mar-2015  jdolecek file reg.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2 29-Nov-2019  riastradh Largely eliminate the MD rwlock.h header file.

This was full of definitions that have been obsolete for over a
decade. The file still remains for __HAVE_RW_STUBS but that's all.
Used only internally in kern_rwlock.c now, not by <sys/rwlock.h>.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file rwlock.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2 27-Mar-2015  matt branches: 1.2.16;
Switch to new ABI (return values now in a0/a1; v0/v1 are no more)
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.2.16.2 03-Dec-2017  jdolecek update from HEAD
 1.2.16.1 27-Mar-2015  jdolecek file setjmp.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file signal.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file sysarch.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.34 12-Oct-2025  thorpej Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/
 1.33 14-May-2024  riastradh branches: 1.33.4;
riscv: No volatile needed on asm to _read_ rounding mode, exceptions.

These instructions can be omitted if the return values are unused.
In contrast, _writes_ to the rounding mode or exceptions must not be
omitted (even if we ignore the return value, which is the old value
of the field).

I think "memory" is the wrong clobber on these asm blocks too; they
can't be reordered around _floating-point_ instructions, while
reordering around loads and stores is fine. But I don't know how to
spell the right thing in gcclish.
 1.32 14-May-2024  riastradh riscv: Fix reading and writing frm and fflags.

The FRRM/FSRM and FRFLAGS/FSFLAGS instructions do all the masking and
shifting needed -- __SHIFTIN/__SHIFTOUT is wrong.
 1.31 05-Feb-2024  andvar fix various typos in comments.
 1.30 25-Dec-2023  skrll G/C ununsed and incorrect SIE_IM
 1.29 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.28 03-Dec-2022  skrll leading whitespace... oops
 1.27 18-Nov-2022  skrll Fix SR_WPRI.

Tweak csr_cycle_read and csr_asid_write for code style, and add some
KNF whitespace.
 1.26 17-Nov-2022  simonb Document lots of bits.
Remove bits no longer in the RISC-V supervisor spec.
Update defines for the user-mode sstatus value.
 1.25 15-Nov-2022  simonb Use similar macro-magic to aarch64 armreg.h to add per-csr
read/write/set-bits/clear-bits inline functions. Keep the
open-coded 32-bit version of riscvreg_cycle_read() than reads
a 64-bit cycle counter values.

Added benefit of fixing these so that the inline asm uses __volatile
and aren't opmtimised to nops by the compiler.
 1.24 13-Nov-2022  skrll Comment fix
 1.23 12-Nov-2022  skrll Use uintptr_t consistently rather than register_t
 1.22 11-Nov-2022  simonb The supervisor status register is the native word width, not fixed
at 32 bits.
 1.21 08-Nov-2022  simonb Parentheses police.
 1.20 08-Nov-2022  simonb Add cause register trap types, and some macros to access cause register
fields.
 1.19 08-Nov-2022  skrll whitepsace nit
 1.18 15-Oct-2022  skrll Fix typo in SATP_MODE_SV64
 1.17 15-Oct-2022  simonb Consistency nit: use "__volatile" instead of "volatile" with asm()s.
 1.16 15-Oct-2022  simonb Add SATP modes for bare, SV57 and SV64.
 1.15 15-Oct-2022  simonb #define<tab>
 1.14 10-Sep-2022  skrll Remove unnecessary cast.
 1.13 01-May-2021  skrll Provide riscvreg_satp_{read,write}
 1.12 01-May-2021  skrll Indent the FCSR_FRM value #defines
 1.11 16-Dec-2020  christos branches: 1.11.4;
interupt -> interrupt
 1.10 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.9 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.8 02-Nov-2020  skrll Add SATP_MODE values
 1.7 02-Nov-2020  skrll Whitespace
 1.6 01-Nov-2020  skrll Update CAUSE_* defines to reflect riscv-privileged-20190608.pdf
 1.5 14-Mar-2020  skrll branches: 1.5.4;
Trailing whitespace
 1.4 16-Jun-2019  maxv Misc changes in RISC-V.
 1.3 31-Mar-2015  matt branches: 1.3.16; 1.3.20;
No more fatc (replaced by sfence.vm instruction).
 1.2 28-Mar-2015  matt Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.3.20.2 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.3.20.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.3.16.2 03-Dec-2017  jdolecek update from HEAD
 1.3.16.1 31-Mar-2015  jdolecek file sysreg.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.5.4.2 03-Jan-2021  thorpej Sync w/ HEAD.
 1.5.4.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.11.4.1 13-May-2021  thorpej Sync with HEAD.
 1.33.4.1 26-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #67):

sys/arch/riscv/include/sysreg.h: revision 1.34
sys/arch/riscv/include/pte.h: revision 1.15
sys/arch/riscv/include/pte.h: revision 1.16
sys/arch/riscv/riscv/genassym.cf: revision 1.17
sys/arch/riscv/riscv/locore.S: revision 1.47
sys/arch/riscv/riscv/bus_space.c: revision 1.3
sys/arch/riscv/include/pmap.h: revision 1.25
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.22
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.23
sys/arch/riscv/riscv/cpu.c: revision 1.10
sys/arch/riscv/riscv/riscv_machdep.c: revision 1.46

Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.

Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/


Fix RV32 build. Svpbmt and Memory Attribute Extension (XTheadMae) are
SV39 and above only.
 1.19 23-Nov-2024  skrll risc-v: add __HAVE_MM_MD_KERNACC (basic) support.
 1.18 04-Aug-2024  skrll spaces to tabs
 1.17 06-Apr-2024  skrll branches: 1.17.2;
Provide and use _ucas_{32,64} implementations
 1.16 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.15 08-Nov-2022  simonb Add a #define for XLEN, the RISC-V native base integer ISA width.
 1.14 18-Oct-2022  skrll VSXLEN=64 supports 16-bit ASID space so change tlb_asid_t to be big
enough. Spotted by Simon.
 1.13 11-Sep-2022  skrll Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.
 1.12 03-May-2021  skrll Sort __HAVE_ #defines. NFCI.
 1.11 01-May-2021  skrll Make paddr_t/psize_t __uint64_t for both 32 and 64 bit ports
 1.10 01-Apr-2021  simonb branches: 1.10.2;
Whitespace: #define<tab>
 1.9 22-Mar-2020  ad branches: 1.9.4; 1.9.6;
Temporarily mark hppa, mips, powerpc and riscv with __HAVE_UNLOCKED_PMAP,
for the benefit of UVM.

These need some pmap changes to support concurrent faults on the same
object. I have changes to do just that, but they're a work in progress.
 1.8 14-Mar-2020  skrll Trailing whitespace
 1.7 12-Jul-2018  maxv Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.
 1.6 26-Jan-2017  christos branches: 1.6.12; 1.6.14; 1.6.16;
provide __HAVE_COMPAT_NETBSD32 and fix multiple include protection consistently.
 1.5 23-Jan-2016  christos branches: 1.5.2; 1.5.4;
expose the kernel types for standalone code.
 1.4 23-Jan-2016  christos Hide {p,v}{addr,size}_t and register_t (and a couple more types that
are machine-specific) from userland unless _KERNEL/_KMEMUSER and a
new _KERNTYPES variables is defined. The _KERNTYPES should be fixed
for many subsystems that should not be using it (rump)...
 1.3 27-Aug-2015  pooka Fix PTHREAD_FOO_INITIALIZER for C++ by not using volatile in the relevant
pthread types in C++ builds, attempt 2.

The problem with attempt 1 was making assumptions of what the MD
__cpu_simple_lock_t (declared volatile) looks like. To get a same type
except non-volatile, we change the MD type to __cpu_simple_lock_nv_t
and typedef __cpu_simple_lock_t as a volatile __cpu_simple_lock_nv_t.
IMO, __cpu_simple_lock_t should not be volatile at all, but changing it
now is too risky.

Fixes at least Rumprun w/ gcc 5.1/5.2. Furthermore, the mpd application
(and possibly others) will no longer require NetBSD-specific patches.

Tested: build.sh for i386, Rumprun for x86_64 w/ gcc 5.2.

Based on the patch from Christos in lib/49989.
 1.2 28-Mar-2015  matt Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.4 05-Feb-2017  skrll Sync with HEAD
 1.1.2.3 19-Mar-2016  skrll Sync with HEAD
 1.1.2.2 22-Sep-2015  skrll Sync with HEAD
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.5.4.1 21-Apr-2017  bouyer Sync with HEAD
 1.5.2.1 20-Mar-2017  pgoyette Sync with HEAD
 1.6.16.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.6.16.1 10-Jun-2019  christos Sync with HEAD
 1.6.14.1 28-Jul-2018  pgoyette Sync with HEAD
 1.6.12.2 03-Dec-2017  jdolecek update from HEAD
 1.6.12.1 26-Jan-2017  jdolecek file types.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.9.6.1 03-Apr-2021  thorpej Sync with HEAD.
 1.9.4.1 03-Apr-2021  thorpej Sync with HEAD.
 1.10.2.1 13-May-2021  thorpej Sync with HEAD.
 1.17.2.1 02-Aug-2025  perseant Sync with HEAD
 1.1 22-Nov-2024  skrll branches: 1.1.4;
risc-v: split userret into its own header as per other ports

Helps with crash(8)
 1.1.4.2 02-Aug-2025  perseant Sync with HEAD
 1.1.4.1 22-Nov-2024  perseant file userret.h was added on branch perseant-exfatfs on 2025-08-02 05:56:04 +0000
 1.14 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.13 16-Oct-2022  skrll Map the DTB using VM_KERNEL_DTB_BASE and CONSADDR using VM_KERNEL_IO_BASE
 1.12 15-Oct-2022  skrll Update a comment
 1.11 12-Oct-2022  simonb Set RISCV_DIRECTMAP_SIZE to 2^64-PAGESIZE, since 2^64 is effectively 0
for a 64bit constant.
Bump VM_PHYSSEG_MAX from 1 to 16.
 1.10 20-Sep-2022  skrll Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|

Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3

Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes

Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509
 1.9 01-May-2021  skrll Fixup some pmap / VM related #defines and code
 1.8 26-Feb-2021  simonb branches: 1.8.4;
Drop 64-bit default stack sizes back to 4MB.
 1.7 07-Nov-2020  skrll Use lower case for hex constants
 1.6 06-Oct-2020  christos branches: 1.6.2;
GC unused MAXTSIZ32
 1.5 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.4 31-May-2018  mrg branches: 1.4.2;
it's called VM_MAXUSER_ADDRESS32 not VM_MAXUSER32_ADDRESS.

fixes mips64 builds, and likely fixes riscv when it happens again.
 1.3 24-Jun-2017  joerg branches: 1.3.4; 1.3.6;
Update VM_DEFAULT_ADDRESS32_TOPDOWN to include guard area.
 1.2 23-Jun-2017  joerg Recommit exec_subr.c revision 1.79:
Always include a 1MB guard area beyond the end of stack. While ASLR will
normally create a guard area as well, this provides a deterministic area
for all binaries.

Mitigates the rest of CVE-2017-1000374 and CVE-2017-1000375 from
Qualys.

Additionally, change VM_DEFAULT_ADDRESS_TOPDOWN to include
user_stack_guard_size in the size reservation.
 1.1 19-Sep-2014  matt branches: 1.1.2; 1.1.12;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.12.1 31-Aug-2017  bouyer Pull up following revision(s) (requested by joerg in ticket #234):
sys/arch/amd64/include/vmparam.h: revision 1.43
sys/kern/exec_subr.c: revision 1.79
lib/libpthread/pthread_int.h: revision 1.94
sys/arch/mips/include/vmparam.h: revision 1.58
sys/arch/mips/include/vmparam.h: revision 1.59
lib/libpthread/TODO: revision 1.19
sys/arch/powerpc/include/vmparam.h: revision 1.20
sys/arch/riscv/include/vmparam.h: revision 1.2
sys/arch/riscv/include/vmparam.h: revision 1.3
sys/arch/i386/include/vmparam.h: revision 1.85
tests/lib/libpthread/t_join.c: revision 1.9
sys/uvm/uvm_meter.c: revision 1.66
sys/uvm/uvm_param.h: revision 1.36
sys/kern/exec_subr.c: revision 1.80
sys/uvm/uvm_param.h: revision 1.37
sys/kern/exec_subr.c: revision 1.81
sys/kern/exec_subr.c: revision 1.82
lib/libpthread/pthread_attr_getguardsize.3: revision 1.4
lib/libpthread/pthread.c: revision 1.148
lib/libpthread/pthread_attr.c: revision 1.17
sys/arch/amd64/include/vmparam.h: revision 1.42
Always include a 1MB guard area beyond the end of stack. While ASLR will
normally create a guard area as well, this provides a deterministic area
for all binaries.
Mitigates the rest of CVE-2017-1000374 and CVE-2017-1000375 from
Qualys.
Revert for the moment, creates problems on i386.
Recommit exec_subr.c revision 1.79:
Always include a 1MB guard area beyond the end of stack. While ASLR will
normally create a guard area as well, this provides a deterministic area
for all binaries.
Mitigates the rest of CVE-2017-1000374 and CVE-2017-1000375 from
Qualys.
Additionally, change VM_DEFAULT_ADDRESS_TOPDOWN to include
user_stack_guard_size in the size reservation.
Update VM_DEFAULT_ADDRESS32_TOPDOWN to include guard area.
Export the guard size of the main thread via vm.guard_size. Add a
complementary writable sysctl for the initial guard size of threads
created via pthread_create. Let the existing attribut accessors do the
right thing. Raise the default guard size for threads to 64KB.
 1.1.2.1 28-Aug-2017  skrll Sync with HEAD
 1.3.6.1 25-Jun-2018  pgoyette Sync with HEAD
 1.3.4.2 03-Dec-2017  jdolecek update from HEAD
 1.3.4.1 24-Jun-2017  jdolecek file vmparam.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.4.2.1 10-Jun-2019  christos Sync with HEAD
 1.6.2.2 03-Apr-2021  thorpej Sync with HEAD.
 1.6.2.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.8.4.1 13-May-2021  thorpej Sync with HEAD.
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file wchar_limits.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.7 15-Aug-2024  skrll KNF
 1.6 19-Jan-2024  skrll branches: 1.6.2;
Use fdt_cpu_rootconf
 1.5 10-Jul-2023  rin riscv: Add FDT-based initrd, rndseed, and efirng support.

Can be used from our in-tree bootrisv64.efi.
 1.4 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.3 01-May-2021  skrll Enable interrupts at the end of cpu_configure
 1.2 04-Nov-2020  skrll branches: 1.2.4;
RCSID and whitespace police...
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.34;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.34.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file autoconf.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file autoconf.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.2.4.1 13-May-2021  thorpej Sync with HEAD.
 1.6.2.1 02-Aug-2025  perseant Sync with HEAD
 1.11 26-Sep-2025  skrll risc-v: Adjust barriers issued in bus_dmamap_sync for the coherent case.

PR/59653

This change adjusts the memory barriers issued by bus_dmamap_sync for
the coherent case. In the non-coherent case the CPU cache operations
are expected to provide any, and all required barriers.

These barriers are emitted after bouncing for PREWRITE and before
bouncing for POSTREAD.

Net change:

op old new
 1.10 02-Mar-2025  riastradh branches: 1.10.2;
riscv/bus_dma: Handle pmap_extract failure.

That is, when the va is not mapped in the pmap.

Otherwise this trips over uninitialized memory, e.g.:

[ 1.0000000] panic: kernel diagnostic assertion "(vaddr & PAGE_MASK) == (curaddr & PAGE_MASK)" failed: file "/tmp/build/2025.02.22.19.09.05-riscv-riscv64/src/sys/arch/riscv/riscv/bus_dma.c", line 1568 va 0xffffffc000a01718 curaddr 0x1

https://releng.netbsd.org/b5reports/riscv-riscv64/2025/2025.02.22.19.09.05/install.log

Perhaps the caller should guarantee that the va is valid, but

(a) for some reason this doesn't work when the va is on the stack,
(b) this is not documented in bus_dma(9), and
(c) if pmap_extract failure should lead to panic then it should do so
intentionally instead of accidentally tripping over a subsequent
assertion.

XXX Do this consistently across bus_dma implementations.
 1.9 10-Dec-2024  skrll risc-v: bus_dma: Sprinkle error check with __predict_{true,false}.

Apply the same sprinkling of __predict_{true,false} to bus_dmamap_load*(),
and bus_dmamap_sync() that the arm version got to improve performance.
 1.8 21-Oct-2024  skrll Sync a comment with the arm version.

XXX need to fix the copy pasta
 1.7 20-Oct-2024  skrll Revert previous - I misread the code.
 1.6 20-Oct-2024  skrll G/C an unused event counter.
 1.5 20-Oct-2024  skrll More KNF
 1.4 20-Oct-2024  skrll Apply the same fix that was applied to the arm version of this.

_bus_dmatag_subregion is always EOPNOTSUPP for !_RISCV_NEED_BUS_DMA_BOUNCE
No need to check {min,max}_addr. Compiler did the right thing, but...
 1.3 20-Oct-2024  skrll KNF
 1.2 08-Feb-2024  skrll branches: 1.2.2;
Define _RISCV_NEED_BUS_DMA_BOUNCE.

Pointed out as being needed by jmcneill. Thanks!
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2.2.1 02-Aug-2025  perseant Sync with HEAD
 1.10.2.1 01-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #38):

sys/arch/riscv/riscv/bus_dma.c: revision 1.11

risc-v: Adjust barriers issued in bus_dmamap_sync for the coherent case.
PR/59653

This change adjusts the memory barriers issued by bus_dmamap_sync for
the coherent case. In the non-coherent case the CPU cache operations
are expected to provide any, and all required barriers.
These barriers are emitted after bouncing for PREWRITE and before
bouncing for POSTREAD.

Net change:
op old new
 1.3 12-Oct-2025  thorpej Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/
 1.2 07-May-2023  skrll branches: 1.2.8;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.1 11-Sep-2022  skrll Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.
 1.2.8.1 26-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #67):

sys/arch/riscv/include/sysreg.h: revision 1.34
sys/arch/riscv/include/pte.h: revision 1.15
sys/arch/riscv/include/pte.h: revision 1.16
sys/arch/riscv/riscv/genassym.cf: revision 1.17
sys/arch/riscv/riscv/locore.S: revision 1.47
sys/arch/riscv/riscv/bus_space.c: revision 1.3
sys/arch/riscv/include/pmap.h: revision 1.25
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.22
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.23
sys/arch/riscv/riscv/cpu.c: revision 1.10
sys/arch/riscv/riscv/riscv_machdep.c: revision 1.46

Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.

Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/


Fix RV32 build. Svpbmt and Memory Attribute Extension (XTheadMae) are
SV39 and above only.
 1.5 13-Jul-2024  skrll Fix the register for argument 0 of the panic calls.

Found by new binutils.
 1.4 07-May-2023  skrll branches: 1.4.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.3 31-Oct-2022  simonb In bus_space_write_{1,2,4,8} store the correct register in write to device.
 1.2 31-Oct-2022  simonb Fix tyop in END for generic_bs_r_8.
 1.1 11-Sep-2022  skrll Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.
 1.4.6.1 02-Aug-2025  perseant Sync with HEAD
 1.3 07-Feb-2024  msaitoh Remove ryo@'s mail addresses.
 1.2 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.1 11-Sep-2022  skrll Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.9 04-Aug-2024  skrll spaces to tabs
 1.8 07-Apr-2024  riastradh branches: 1.8.2;
riscv: Schedule next hardclock tick in the future, not the past.

If we have missed hardclock ticks, schedule up to one tick interval
in the future anyway; don't try to play hardclock catchup by
scheduling for when the next hardclock tick _should_ have been, in
the past, leading to ticking as fast as possible until we've caught
up. as fast as possible until we've caught up.

Playing hardclock catchup triggers heartbeat panics when continuing
from ddb, if you've been in ddb for >15sec. Other hardclock drivers
like x86 lapic don't play hardclock catchup either.

PR kern/57920
 1.7 18-Jan-2024  skrll Provide a working delay(9)
 1.6 26-Jul-2023  skrll Attach the clock event counter for each cpu^Whart.
 1.5 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.4 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.3 04-Nov-2020  skrll RCSID and whitespace police...
 1.2 01-Nov-2020  skrll Don't shadow 'hz'
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.34;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.34.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file clock_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file clock_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.8.2.1 02-Aug-2025  perseant Sync with HEAD
 1.2 06-Apr-2024  skrll Fix riscv32 build
 1.1 06-Apr-2024  skrll Provide and use _ucas_{32,64} implementations
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file core32_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file core32_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.6 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.5 04-Nov-2020  skrll RCSID and whitespace police...
 1.4 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.3 20-Nov-2019  pgoyette branches: 1.3.8;
Move all non-emulation-specific coredump code into the coredump module,
and remove all #ifdef COREDUMP conditional compilation. Now, the
coredump module is completely separated from the emulation modules, and
they can all be independently loaded and unloaded.

Welcome to 9.99.18 !
 1.2 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.22;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.22.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file core_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file core_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.3.8.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.10 12-Oct-2025  thorpej Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/
 1.9 07-Oct-2025  skrll Attach the fpu {loads,save,reenable} event counters.
 1.8 07-Oct-2025  skrll whitespace
 1.7 10-Aug-2024  skrll branches: 1.7.2;
Recognise the T-Head 9-Series CPU^Whart.

From Rui-Xiang Guo.
 1.6 07-Apr-2024  riastradh branches: 1.6.2;
riscv: Make sure cpu0->ci_cpu_freq is initialized by cpu_attach.

Otherwise this stays zero, which screws up cpu_ipi_wait.
 1.5 03-Sep-2023  skrll Fix and enable MULTIPROCESSOR
 1.4 28-Aug-2023  skrll Remove duplicate .ci_cpl initialiser.
 1.3 24-Jun-2023  skrll Always initialise ci_tlb_info in cpu_info_store[0].

Fixes non-MP boot for me.
 1.2 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.6.2.1 02-Aug-2025  perseant Sync with HEAD
 1.7.2.2 26-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #67):

sys/arch/riscv/include/sysreg.h: revision 1.34
sys/arch/riscv/include/pte.h: revision 1.15
sys/arch/riscv/include/pte.h: revision 1.16
sys/arch/riscv/riscv/genassym.cf: revision 1.17
sys/arch/riscv/riscv/locore.S: revision 1.47
sys/arch/riscv/riscv/bus_space.c: revision 1.3
sys/arch/riscv/include/pmap.h: revision 1.25
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.22
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.23
sys/arch/riscv/riscv/cpu.c: revision 1.10
sys/arch/riscv/riscv/riscv_machdep.c: revision 1.46

Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.

Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/


Fix RV32 build. Svpbmt and Memory Attribute Extension (XTheadMae) are
SV39 and above only.
 1.7.2.1 09-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #48):

sys/arch/riscv/riscv/trap.c: revision 1.31
sys/arch/riscv/riscv/cpu.c: revision 1.8
sys/arch/riscv/riscv/cpu.c: revision 1.9

whitespace

Attach the fpu {loads,save,reenable} event counters.
 1.2 04-Nov-2020  skrll RCSID and whitespace police...
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.34;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.34.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file cpu_mainbus.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file cpu_mainbus.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.6 06-Sep-2025  riastradh paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs
 1.5 03-May-2024  skrll branches: 1.5.4;
Small simplification. NFCI.
 1.4 03-Sep-2023  skrll Fix and enable MULTIPROCESSOR
 1.3 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.2 04-Nov-2020  skrll RCSID and whitespace police...
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.34;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.34.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file cpu_subr.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file cpu_subr.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.5.4.1 19-Oct-2025  martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
 1.7 20-Apr-2025  skrll PR/59304: kernel longjmp(9) fails to make setjmp(9) return 1

Fix riscv longjmp.
 1.6 02-May-2024  skrll branches: 1.6.2;
risc-v: fix the error code when uvm_fault fails with cpu_set_onfault

Return the error from uvm_fault instead of EFAULT unconditionally when
faulting with cpu_set_onfault to fix several atf tests.
 1.5 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.4 01-Mar-2023  riastradh riscv: Optimization: Omit needless membar when triggering softint.

When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.

PR kern/57240
 1.3 23-Feb-2023  riastradh riscv: Add missing barriers in cpu_switchto.

Details in comments.

PR kern/57240
 1.2 04-Dec-2022  skrll branches: 1.2.2;
Restore t5 and t6 from the correct locations in exception_kernexit.

From Simon.
 1.1 14-Oct-2022  skrll Split out a bunch of functions from locore.S into cpu_switch.S

NFC
 1.2.2.1 31-Jul-2023  martin Pull up following revision(s) (requested by riastradh in ticket #264):

sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
sys/arch/aarch64/aarch64/locore.S: revision 1.91
sys/arch/mips/include/asm.h: revision 1.74
sys/arch/hppa/include/cpu.h: revision 1.13
sys/arch/arm/arm/armv6_start.S: revision 1.38
sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
sys/arch/mips/mips/locore.S: revision 1.229
sys/arch/aarch64/aarch64/cpuswitch.S: revision 1.40
sys/arch/alpha/include/asm.h: revision 1.45
sys/arch/sparc64/sparc64/locore.s: revision 1.432
sys/arch/vax/vax/subr.S: revision 1.42
sys/arch/mips/mips/locore_mips3.S: revision 1.116
sys/arch/riscv/riscv/cpu_switch.S: revision 1.3
sys/arch/ia64/ia64/machdep.c: revision 1.44
sys/arch/arm/arm32/cpuswitch.S: revision 1.106
sys/arch/sparc/sparc/locore.s: revision 1.284

aarch64: Add missing barriers in cpu_switchto.
Details in comments.

Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.

PR kern/57240

alpha: Add missing barriers in cpu_switchto.
Details in comments.

arm32: Add missing barriers in cpu_switchto.
Details in comments.

hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?

ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)

mips: Add missing barriers in cpu_switchto.
Details in comments.

powerpc: Add missing barriers in cpu_switchto.
Details in comments.

riscv: Add missing barriers in cpu_switchto.
Details in comments.

sparc: Add missing barriers in cpu_switchto.

sparc64: Add missing barriers in cpu_switchto.
Details in comments.

vax: Note where cpu_switchto needs barriers.

Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.
 1.6.2.1 02-Aug-2025  perseant Sync with HEAD
 1.13 24-Nov-2024  skrll risc-v: don't KASSERT in the disassembler.
 1.12 24-Sep-2024  andvar remove commented warnx() call, it looks like unintended development leftover.
 1.11 04-Aug-2024  skrll spaces to tabs
 1.10 07-May-2023  skrll branches: 1.10.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.9 28-May-2022  andvar fix various typos, mainly in comments.
 1.8 23-May-2021  dholland Improve ddb disassembly for mips (and riscv, cribbed from mips).

- use db_read_bytes to get instructions
- move the address check logic previously attached only to fetching
instructions for disassembly to db_read_bytes (and db_write_bytes)

Motivated by related x86 changes this afternoon.

Note that the address check logic is not as sophisticated as what the
x86 code does, but it's what we had before. (Except that riscv will
now also try to fetch usermode instructions instead of just failing.)
 1.7 01-May-2021  skrll branches: 1.7.2;
Trailing whitespace
 1.6 20-Apr-2021  skrll branches: 1.6.2;
KNF
 1.5 20-Apr-2021  skrll compile fixes
 1.4 19-Apr-2021  dholland Make the riscv disassembler work, as best as I can test from amd64 userspace.
 1.3 14-Apr-2021  dholland Add a ddb disassembler for riscv.

builds, but not really tested yet.
 1.2 04-Nov-2020  skrll branches: 1.2.2;
RCSID and whitespace police...
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.34;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.34.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file db_disasm.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file db_disasm.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.2.2.1 17-Apr-2021  thorpej Sync with HEAD.
 1.6.2.2 17-Jun-2021  thorpej Sync w/ HEAD.
 1.6.2.1 13-May-2021  thorpej Sync with HEAD.
 1.7.2.1 31-May-2021  cjep sync with head
 1.10.6.1 02-Aug-2025  perseant Sync with HEAD
 1.6 25-Nov-2024  skrll risc-v: support crash(8)
 1.5 22-Dec-2023  skrll branches: 1.5.2;
Minor stylistic changes. NFCI.
 1.4 03-Sep-2023  skrll Fix and enable MULTIPROCESSOR
 1.3 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.2 26-Oct-2022  riastradh ddb/db_active.h: New home for extern db_active.

This can be included unconditionally, and db_active can then be
queried unconditionally; if DDB is not in the kernel, then db_active
is a constant zero. Reduces need for #include opt_ddb.h, #ifdef DDB.
 1.1 27-Sep-2022  skrll Basic ddb and backtrace support.

[ 1.0000000] panic: kernel diagnostic assertion "msgbufaddr != 0" failed: file "/home/nick/netbsd/nbcvs/src/sys/arch/riscv/riscv/riscv_machdep.c", line 564
[ 1.0000000] cpu0: Begin traceback...
[ 1.0000000] trace fp ffffffc000801dd0
[ 1.0000000] fp ffffffc000801e10 ?() at ffffffc0001eee98
[ 1.0000000] fp ffffffc000801e30 ?() at ffffffc0002ad984
[ 1.0000000] fp ffffffc000801ee0 ?() at ffffffc000005430
[ 1.0000000] cpu0: End traceback...
[ 1.0000000] Trapframe @ 0xffffffc000801cb0 (cause=3 (breakpoint), status=0x100, pc=0xffffffc0000007e4, va=0):
[ 1.0000000] ra =0xffffffc0001eee9c, sp =0xffffffc000801dd0, gp =0xffffffc0006a8f40, tp = 0
[ 1.0000000] s0 =0xffffffc000600ac0, s1 = 0x1000, s2 =0xffffffc000438df0, s3 =0xffffffc000801d80
[ 1.0000000] s4 =0xffffffc0001eed78, s5 =0xffffffc0006d55f8, s6 =0xffffffc000801d88, s7 =0xffffffc0006dfdb8
[ 1.0000000] s8 =0xffffffc000428c18, s9 =0xffffffc000801dd0, s10=0xffffffc0000a3822, s11=0xffffffc0006d55f8
[ 1.0000000] a0 = 0x17, a1 = 0xa, a2 = 0, a3 =0xffffffc00041f658
[ 1.0000000] a4 = 0, a5 = 0x1, a5 = 0, a7 = 0x1
[ 1.0000000] t0 =0xffffffc0006dfe30, t1 =0xffffffc000801bb8, t2 =0xffffffc000803000, t3 = 0x75
[ 1.0000000] t4 = 0, t5 = 0x63, t6 = 0x1
[ 1.0000000] kernel: breakpoint
Stopped in pid 0.0 (system) at ffffffc0000007e4: c.ebreak
db>
 1.5.2.1 02-Aug-2025  perseant Sync with HEAD
 1.14 25-Nov-2024  skrll risc-v: support crash(8)
 1.13 23-Nov-2024  skrll risc-v: split db_{read,write}_bytes from db_machdep.c

Another step towards crash(8) support
 1.12 23-Nov-2024  skrll risc-v: don't include locore.h in db_machdep.h
 1.11 12-Jun-2023  skrll branches: 1.11.6;
risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.10 12-Oct-2022  simonb Nuke funny trailing whitespace.
 1.9 27-Sep-2022  skrll Basic ddb and backtrace support.

[ 1.0000000] panic: kernel diagnostic assertion "msgbufaddr != 0" failed: file "/home/nick/netbsd/nbcvs/src/sys/arch/riscv/riscv/riscv_machdep.c", line 564
[ 1.0000000] cpu0: Begin traceback...
[ 1.0000000] trace fp ffffffc000801dd0
[ 1.0000000] fp ffffffc000801e10 ?() at ffffffc0001eee98
[ 1.0000000] fp ffffffc000801e30 ?() at ffffffc0002ad984
[ 1.0000000] fp ffffffc000801ee0 ?() at ffffffc000005430
[ 1.0000000] cpu0: End traceback...
[ 1.0000000] Trapframe @ 0xffffffc000801cb0 (cause=3 (breakpoint), status=0x100, pc=0xffffffc0000007e4, va=0):
[ 1.0000000] ra =0xffffffc0001eee9c, sp =0xffffffc000801dd0, gp =0xffffffc0006a8f40, tp = 0
[ 1.0000000] s0 =0xffffffc000600ac0, s1 = 0x1000, s2 =0xffffffc000438df0, s3 =0xffffffc000801d80
[ 1.0000000] s4 =0xffffffc0001eed78, s5 =0xffffffc0006d55f8, s6 =0xffffffc000801d88, s7 =0xffffffc0006dfdb8
[ 1.0000000] s8 =0xffffffc000428c18, s9 =0xffffffc000801dd0, s10=0xffffffc0000a3822, s11=0xffffffc0006d55f8
[ 1.0000000] a0 = 0x17, a1 = 0xa, a2 = 0, a3 =0xffffffc00041f658
[ 1.0000000] a4 = 0, a5 = 0x1, a5 = 0, a7 = 0x1
[ 1.0000000] t0 =0xffffffc0006dfe30, t1 =0xffffffc000801bb8, t2 =0xffffffc000803000, t3 = 0x75
[ 1.0000000] t4 = 0, t5 = 0x63, t6 = 0x1
[ 1.0000000] kernel: breakpoint
Stopped in pid 0.0 (system) at ffffffc0000007e4: c.ebreak
db>
 1.8 23-May-2021  dholland Improve ddb disassembly for mips (and riscv, cribbed from mips).

- use db_read_bytes to get instructions
- move the address check logic previously attached only to fetching
instructions for disassembly to db_read_bytes (and db_write_bytes)

Motivated by related x86 changes this afternoon.

Note that the address check logic is not as sophisticated as what the
x86 code does, but it's what we had before. (Except that riscv will
now also try to fetch usermode instructions instead of just failing.)
 1.7 14-Apr-2021  dholland branches: 1.7.2; 1.7.4;
Add a ddb disassembler for riscv.

builds, but not really tested yet.
 1.6 04-Nov-2020  skrll branches: 1.6.2;
RCSID and whitespace police...
 1.5 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.4 14-Mar-2020  skrll branches: 1.4.4;
Trailing whitespace
 1.3 16-Jun-2019  maxv Misc changes in RISC-V.
 1.2 23-Apr-2018  christos branches: 1.2.2;
PR/53206: David Binderman: fix array bounds comparison in KASSERT.
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.20;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.20.1 02-May-2018  pgoyette Synch with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file db_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file db_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.2.2.2 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.2.2.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.4.4.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.6.2.1 17-Apr-2021  thorpej Sync with HEAD.
 1.7.4.1 31-May-2021  cjep sync with head
 1.7.2.1 17-Jun-2021  thorpej Sync w/ HEAD.
 1.11.6.1 02-Aug-2025  perseant Sync with HEAD
 1.1 23-Nov-2024  skrll branches: 1.1.4;
risc-v: split db_{read,write}_bytes from db_machdep.c

Another step towards crash(8) support
 1.1.4.2 02-Aug-2025  perseant Sync with HEAD
 1.1.4.1 23-Nov-2024  perseant file db_memrw.c was added on branch perseant-exfatfs on 2025-08-02 05:56:04 +0000
 1.7 25-Nov-2024  skrll risc-v: support crash(8)
 1.6 23-Nov-2024  skrll risc-v: don't include locore.h in db_machdep.h
 1.5 19-Nov-2024  skrll risc-v: use the provided printf like function in db_stack_trace_print
 1.4 07-May-2023  skrll branches: 1.4.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.3 27-Sep-2022  skrll Basic ddb and backtrace support.

[ 1.0000000] panic: kernel diagnostic assertion "msgbufaddr != 0" failed: file "/home/nick/netbsd/nbcvs/src/sys/arch/riscv/riscv/riscv_machdep.c", line 564
[ 1.0000000] cpu0: Begin traceback...
[ 1.0000000] trace fp ffffffc000801dd0
[ 1.0000000] fp ffffffc000801e10 ?() at ffffffc0001eee98
[ 1.0000000] fp ffffffc000801e30 ?() at ffffffc0002ad984
[ 1.0000000] fp ffffffc000801ee0 ?() at ffffffc000005430
[ 1.0000000] cpu0: End traceback...
[ 1.0000000] Trapframe @ 0xffffffc000801cb0 (cause=3 (breakpoint), status=0x100, pc=0xffffffc0000007e4, va=0):
[ 1.0000000] ra =0xffffffc0001eee9c, sp =0xffffffc000801dd0, gp =0xffffffc0006a8f40, tp = 0
[ 1.0000000] s0 =0xffffffc000600ac0, s1 = 0x1000, s2 =0xffffffc000438df0, s3 =0xffffffc000801d80
[ 1.0000000] s4 =0xffffffc0001eed78, s5 =0xffffffc0006d55f8, s6 =0xffffffc000801d88, s7 =0xffffffc0006dfdb8
[ 1.0000000] s8 =0xffffffc000428c18, s9 =0xffffffc000801dd0, s10=0xffffffc0000a3822, s11=0xffffffc0006d55f8
[ 1.0000000] a0 = 0x17, a1 = 0xa, a2 = 0, a3 =0xffffffc00041f658
[ 1.0000000] a4 = 0, a5 = 0x1, a5 = 0, a7 = 0x1
[ 1.0000000] t0 =0xffffffc0006dfe30, t1 =0xffffffc000801bb8, t2 =0xffffffc000803000, t3 = 0x75
[ 1.0000000] t4 = 0, t5 = 0x63, t6 = 0x1
[ 1.0000000] kernel: breakpoint
Stopped in pid 0.0 (system) at ffffffc0000007e4: c.ebreak
db>
 1.2 04-Nov-2020  skrll RCSID and whitespace police...
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.34;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.34.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file db_trace.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file db_trace.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.4.6.1 02-Aug-2025  perseant Sync with HEAD
 1.3 29-Sep-2022  skrll Remove unnecessary include of <sys/malloc.h>.
 1.2 04-Nov-2020  skrll RCSID and whitespace police...
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.34;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.34.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file exec_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file exec_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.2 04-Nov-2020  skrll RCSID and whitespace police...
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.34;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.34.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file fixup.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file fixup.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.3 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2 03-Aug-2021  andvar Fix various typos in comments. Also add missing NetBSD RCS Id in some of these files.
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file fpu.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file fpu.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.17 12-Oct-2025  thorpej Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/
 1.16 06-Apr-2024  skrll branches: 1.16.4;
Provide and use _ucas_{32,64} implementations
 1.15 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.14 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.13 16-Oct-2022  skrll Map the DTB using VM_KERNEL_DTB_BASE and CONSADDR using VM_KERNEL_IO_BASE
 1.12 20-Sep-2022  skrll Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|

Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3

Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes

Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509
 1.11 11-Sep-2022  skrll Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.
 1.10 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.9 04-Nov-2020  skrll Fix some of the previous - I must have compile tested the wrong tree
 1.8 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.7 08-Jan-2020  ad branches: 1.7.6;
Hopefully fix some problems seen with MP support on non-x86, in particular
where curcpu() is defined as curlwp->l_cpu:

- mi_switch(): undo the ~2007ish optimisation to unlock curlwp before
calling cpu_switchto(). It's not safe to let other actors mess with the
LWP (in particular l->l_cpu) while it's still context switching. This
removes l->l_ctxswtch.

- Move the LP_RUNNING flag into l->l_flag and rename to LW_RUNNING since
it's now covered by the LWP's lock.

- Ditch lwp_exit_switchaway() and just call mi_switch() instead. Everything
is in cache anyway so it wasn't buying much by trying to avoid saving old
state. This means cpu_switchto() will never be called with prevlwp ==
NULL.

- Remove some KERNEL_LOCK handling which hasn't been needed for years.
 1.6 23-Nov-2019  ad branches: 1.6.2;
cpu_need_resched():

- Remove all code that should be MI, leaving the bare minimum under arch/.
- Make the required actions very explicit.
- Pass in LWP pointer for convenience.
- When a trap is required on another CPU, have the IPI set it locally.
- Expunge cpu_did_resched().
 1.5 16-Jun-2019  maxv Misc changes in RISC-V.
 1.4 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.3 31-Mar-2015  matt branches: 1.3.2; 1.3.18; 1.3.22;
Optimize the exception handle a little bit more.
 1.2 31-Mar-2015  matt Add L_MD_TP
 1.1 28-Mar-2015  matt Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.3.22.3 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.3.22.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.3.22.1 10-Jun-2019  christos Sync with HEAD
 1.3.18.2 03-Dec-2017  jdolecek update from HEAD
 1.3.18.1 31-Mar-2015  jdolecek file genassym.cf was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.3.2.2 06-Apr-2015  skrll Sync with HEAD
 1.3.2.1 31-Mar-2015  skrll file genassym.cf was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.6.2.1 17-Jan-2020  ad Sync with head.
 1.7.6.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.16.4.1 26-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #67):

sys/arch/riscv/include/sysreg.h: revision 1.34
sys/arch/riscv/include/pte.h: revision 1.15
sys/arch/riscv/include/pte.h: revision 1.16
sys/arch/riscv/riscv/genassym.cf: revision 1.17
sys/arch/riscv/riscv/locore.S: revision 1.47
sys/arch/riscv/riscv/bus_space.c: revision 1.3
sys/arch/riscv/include/pmap.h: revision 1.25
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.22
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.23
sys/arch/riscv/riscv/cpu.c: revision 1.10
sys/arch/riscv/riscv/riscv_machdep.c: revision 1.46

Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.

Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/


Fix RV32 build. Svpbmt and Memory Attribute Extension (XTheadMae) are
SV39 and above only.
 1.3 19-Nov-2024  skrll risc-v: expose intr_establish_xname
 1.2 12-Jun-2023  skrll branches: 1.2.6;
risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2.6.1 02-Aug-2025  perseant Sync with HEAD
 1.2 03-Sep-2023  skrll Fix and enable MULTIPROCESSOR
 1.1 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.6 18-Jan-2024  msaitoh s/FALLTHOUGH/FALLTHROUGH/ in comment.
 1.5 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.4 04-Nov-2020  skrll RCSID and whitespace police...
 1.3 14-Mar-2020  skrll branches: 1.3.4;
Trailing whitespace
 1.2 03-Nov-2017  maxv branches: 1.2.2; 1.2.6;
Handle absolute relocations coming from the kernel: preserve SHN_ABS in
the kernel and module symbols, and when relocating a symbol that has
SHN_ABS, take its value as-is and don't return an error if it equals zero.

Sent on tech-kern@.
 1.1 28-Mar-2015  matt branches: 1.1.2;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file kobj_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.2.6.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.2.2.2 03-Dec-2017  jdolecek update from HEAD
 1.2.2.1 03-Nov-2017  jdolecek file kobj_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.3.4.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.47 12-Oct-2025  thorpej Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/
 1.46 02-Mar-2025  skrll branches: 1.46.2;
risc-v: ensure the boot stacks are mapped so that pmap_extract works
 1.45 09-Feb-2024  andvar branches: 1.45.2;
fix spelling mistakes, mainly in comments and log messages.
 1.44 02-Feb-2024  andvar fix various typos in comments.
 1.43 03-Sep-2023  skrll Fix and enable MULTIPROCESSOR
 1.42 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.41 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.40 19-Nov-2022  skrll Fix CONSADDR and save a label
 1.39 16-Oct-2022  skrll Map the DTB using VM_KERNEL_DTB_BASE and CONSADDR using VM_KERNEL_IO_BASE
 1.38 16-Oct-2022  skrll Use a local label
 1.37 16-Oct-2022  skrll More register re-org
 1.36 16-Oct-2022  skrll Fix after register re-org
 1.35 15-Oct-2022  skrll More register use re-org.
 1.34 15-Oct-2022  skrll Shuffle some register usage
 1.33 15-Oct-2022  skrll Comment re-arragement
 1.32 15-Oct-2022  skrll Remove unnecessary register assignments
 1.31 14-Oct-2022  skrll Pretty print
 1.30 14-Oct-2022  skrll Split out a bunch of functions from locore.S into cpu_switch.S

NFC
 1.29 30-Sep-2022  skrll Don't set A, D in page table pointers, but do set them in leaf entries.

Beagle-v now boots to the msgbufaddr panic same as qemu
 1.28 28-Sep-2022  skrll Use legacy SBI Console GetChar for earlycons. It works on qemu.
 1.27 28-Sep-2022  skrll Fix RV32 so it gets to the same point as RV64
 1.26 27-Sep-2022  skrll Basic ddb and backtrace support.

[ 1.0000000] panic: kernel diagnostic assertion "msgbufaddr != 0" failed: file "/home/nick/netbsd/nbcvs/src/sys/arch/riscv/riscv/riscv_machdep.c", line 564
[ 1.0000000] cpu0: Begin traceback...
[ 1.0000000] trace fp ffffffc000801dd0
[ 1.0000000] fp ffffffc000801e10 ?() at ffffffc0001eee98
[ 1.0000000] fp ffffffc000801e30 ?() at ffffffc0002ad984
[ 1.0000000] fp ffffffc000801ee0 ?() at ffffffc000005430
[ 1.0000000] cpu0: End traceback...
[ 1.0000000] Trapframe @ 0xffffffc000801cb0 (cause=3 (breakpoint), status=0x100, pc=0xffffffc0000007e4, va=0):
[ 1.0000000] ra =0xffffffc0001eee9c, sp =0xffffffc000801dd0, gp =0xffffffc0006a8f40, tp = 0
[ 1.0000000] s0 =0xffffffc000600ac0, s1 = 0x1000, s2 =0xffffffc000438df0, s3 =0xffffffc000801d80
[ 1.0000000] s4 =0xffffffc0001eed78, s5 =0xffffffc0006d55f8, s6 =0xffffffc000801d88, s7 =0xffffffc0006dfdb8
[ 1.0000000] s8 =0xffffffc000428c18, s9 =0xffffffc000801dd0, s10=0xffffffc0000a3822, s11=0xffffffc0006d55f8
[ 1.0000000] a0 = 0x17, a1 = 0xa, a2 = 0, a3 =0xffffffc00041f658
[ 1.0000000] a4 = 0, a5 = 0x1, a5 = 0, a7 = 0x1
[ 1.0000000] t0 =0xffffffc0006dfe30, t1 =0xffffffc000801bb8, t2 =0xffffffc000803000, t3 = 0x75
[ 1.0000000] t4 = 0, t5 = 0x63, t6 = 0x1
[ 1.0000000] kernel: breakpoint
Stopped in pid 0.0 (system) at ffffffc0000007e4: c.ebreak
db>
 1.25 20-Sep-2022  skrll Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|

Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3

Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes

Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509
 1.24 10-Apr-2022  andvar fix various typos in comments and output/log messages.
 1.23 03-Aug-2021  andvar Fix various typos in comments. Also add missing NetBSD RCS Id in some of these files.
 1.22 16-May-2021  skrll s/ENTRY/ENTRY_NP/ in a few places
 1.21 01-May-2021  skrll branches: 1.21.2;
Quick hack to make this link
 1.20 08-Nov-2020  skrll branches: 1.20.4;
Fix register usage
 1.19 08-Nov-2020  skrll Fix a typo
 1.18 08-Nov-2020  skrll Remove unnecessary local labels
 1.17 08-Nov-2020  skrll Use correct instruction to load address of exception_userexit into RA
 1.16 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.15 04-Nov-2020  skrll RCSID and whitespace police...
 1.14 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.13 31-Oct-2020  skrll branches: 1.13.2;
Use the 'mv' pseudo-instruction instead of the 'move' equivalent as 'mv'
is mentioned in the ISA documentation and it's used elsewhere. That is,
let's use 'mv' everywhere for consistency.
 1.12 14-Mar-2020  skrll Trailing whitespace
 1.11 08-Jan-2020  skrll oldlwp is always non-NULL in cpu_switchto so remove the test for NULL.
 1.10 08-Jan-2020  ad Hopefully fix some problems seen with MP support on non-x86, in particular
where curcpu() is defined as curlwp->l_cpu:

- mi_switch(): undo the ~2007ish optimisation to unlock curlwp before
calling cpu_switchto(). It's not safe to let other actors mess with the
LWP (in particular l->l_cpu) while it's still context switching. This
removes l->l_ctxswtch.

- Move the LP_RUNNING flag into l->l_flag and rename to LW_RUNNING since
it's now covered by the LWP's lock.

- Ditch lwp_exit_switchaway() and just call mi_switch() instead. Everything
is in cache anyway so it wasn't buying much by trying to avoid saving old
state. This means cpu_switchto() will never be called with prevlwp ==
NULL.

- Remove some KERNEL_LOCK handling which hasn't been needed for years.
 1.9 16-Jun-2019  maxv branches: 1.9.4;
Misc changes in RISC-V.
 1.8 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.7 05-Feb-2018  maya branches: 1.7.4;
Fix tyop
 1.6 05-Dec-2016  kamil branches: 1.6.14;
Fix cpu_switchto(9) prototype in a comment
 1.5 31-Mar-2015  matt branches: 1.5.2; 1.5.4;
Accept the one instruction penalty and just use PTR_LA instead of doing
the relocs ourselves.
 1.4 31-Mar-2015  matt Fix botch on putting user stack pointer into trapframe.
 1.3 31-Mar-2015  matt Optimize the exception handle a little bit more.
 1.2 31-Mar-2015  matt Since there is only "scratch" system register for use on exception, come
up with a new scheme for its use. Use PTR_LA, INT_S/INT_L, etc. Disable
interrupts when returning from exceptions. Use L_CPU(tp) to get the curcpu
pointer.

When the cpu gets an exception from kernel mode, the sscratch register will be
0 and curlwp will be in the "tp" register. When the cpu gets an exception from
user mode, the sscratch register will be a pointer to the current lwp.

When an exception happends, the sp is atomically swapped with the sscratch
register.

If the sp is zero, the exception was a kernel exception and the
kernel exception path is taken: sp and sscratch are swapped again
so sscratch is zero again and then a trapframe is allocated from
the kernel stack. The t1 register is saved and then the pre-trapframe
sp is written to the trapframe.

If sp was non-zero, the exception was from user mode. The tp register
is temporarily saved in L_MD_TP(sp) and sp is moved tp. tp now
contains a pointer to the current lwp. A pointer to the user
trapframe is loaded from L_MD_UTF(tp). Then t1 is saved in the
trapframe so it can be used. The old sp is fetched from sscratch
while sscratch is zeroed (indicated kernel mode). The old sp is
saved in the trapframe.

Upon exiting the exception, if the exception is returning to user
mode, the contents of tp is written to sscratch.
 1.1 28-Mar-2015  matt Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.5.4.1 07-Jan-2017  pgoyette Sync with HEAD. (Note that most of these changes are simply $NetBSD$
tag issues.)
 1.5.2.3 05-Feb-2017  skrll Sync with HEAD
 1.5.2.2 06-Apr-2015  skrll Sync with HEAD
 1.5.2.1 31-Mar-2015  skrll file locore.S was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.6.14.2 03-Dec-2017  jdolecek update from HEAD
 1.6.14.1 05-Dec-2016  jdolecek file locore.S was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.7.4.3 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.7.4.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.7.4.1 10-Jun-2019  christos Sync with HEAD
 1.9.4.1 17-Jan-2020  ad Sync with head.
 1.13.2.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.20.4.2 17-Jun-2021  thorpej Sync w/ HEAD.
 1.20.4.1 13-May-2021  thorpej Sync with HEAD.
 1.21.2.1 31-May-2021  cjep sync with head
 1.45.2.1 02-Aug-2025  perseant Sync with HEAD
 1.46.2.1 26-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #67):

sys/arch/riscv/include/sysreg.h: revision 1.34
sys/arch/riscv/include/pte.h: revision 1.15
sys/arch/riscv/include/pte.h: revision 1.16
sys/arch/riscv/riscv/genassym.cf: revision 1.17
sys/arch/riscv/riscv/locore.S: revision 1.47
sys/arch/riscv/riscv/bus_space.c: revision 1.3
sys/arch/riscv/include/pmap.h: revision 1.25
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.22
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.23
sys/arch/riscv/riscv/cpu.c: revision 1.10
sys/arch/riscv/riscv/riscv_machdep.c: revision 1.46

Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.

Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/


Fix RV32 build. Svpbmt and Memory Attribute Extension (XTheadMae) are
SV39 and above only.
 1.7 04-Aug-2024  skrll spaces to tabs
 1.6 07-May-2023  skrll branches: 1.6.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.5 11-Sep-2022  skrll Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.
 1.4 07-Aug-2021  thorpej Merge thorpej-cfargs2.
 1.3 24-Apr-2021  thorpej branches: 1.3.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).
 1.2 04-Nov-2020  skrll branches: 1.2.2;
RCSID and whitespace police...
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.34;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.34.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file mainbus.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file mainbus.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.2.2.1 21-Mar-2021  thorpej Give config_found() the same variadic arguments treatment as
config_search(). This commit only adds the CFARG_EOL sentinel
to the existing config_found() calls. Conversion of config_found_sm_loc()
and config_found_ia() call sites will be in subsequent commits.
 1.3.8.1 04-Aug-2021  thorpej Adapt to CFARGS().
 1.6.6.1 02-Aug-2025  perseant Sync with HEAD
 1.5 04-Nov-2020  skrll RCSID and whitespace police...
 1.4 14-Mar-2020  skrll branches: 1.4.4;
Trailing whitespace
 1.3 16-Mar-2017  chs branches: 1.3.12; 1.3.16;
allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.
 1.2 26-Nov-2015  martin branches: 1.2.2; 1.2.4;
We never exec(2) with a kernel vmspace, so do not test for that, but instead
KASSERT() that we don't.
When calculating the load address for the interpreter (e.g. ld.elf_so),
we need to take into account wether the exec'd process will run with
topdown memory or bottom up. We can not use the current vmspace's flags
to test for that, as this happens too early. Luckily the execpack already
knows what the new state will be later, so instead of testing the current
vmspace, pass the info as additional argument to struct emul
e_vm_default_addr.
Fix all such functions and adopt all callers.
 1.1 28-Mar-2015  matt branches: 1.1.2;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.2.4 28-Aug-2017  skrll Sync with HEAD
 1.1.2.3 27-Dec-2015  skrll Sync with HEAD (as of 26th Dec)
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file netbsd32_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.2.4.1 21-Apr-2017  bouyer Sync with HEAD
 1.2.2.1 20-Mar-2017  pgoyette Sync with HEAD
 1.3.16.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.3.12.2 03-Dec-2017  jdolecek update from HEAD
 1.3.12.1 16-Mar-2017  jdolecek file netbsd32_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.4.4.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.23 12-Oct-2025  skrll Fix RV32 build. Svpbmt and Memory Attribute Extension (XTheadMae) are
SV39 and above only.
 1.22 12-Oct-2025  thorpej Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/
 1.21 13-Jul-2025  andvar branches: 1.21.2;
s/pmap_growkernal/pmap_growkernel/ in comment.
 1.20 01-Jan-2024  skrll branches: 1.20.2;
risc-v: probe the number of supported ASIDs

Flush the entire TLB if no ASIDs are supported on pmap_activate.
 1.19 03-Sep-2023  skrll Fix and enable MULTIPROCESSOR
 1.18 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.17 10-Jun-2023  skrll Whitespace.
 1.16 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.15 23-Dec-2022  skrll Fix RV builds
 1.14 15-Nov-2022  simonb Use similar macro-magic to aarch64 armreg.h to add per-csr
read/write/set-bits/clear-bits inline functions. Keep the
open-coded 32-bit version of riscvreg_cycle_read() than reads
a 64-bit cycle counter values.

Added benefit of fixing these so that the inline asm uses __volatile
and aren't opmtimised to nops by the compiler.
 1.13 16-Oct-2022  skrll tlb_update_addr gets called with the KERNEL_PID (ASID) so handle this
case.
 1.12 15-Oct-2022  simonb #define<tab>
 1.11 20-Sep-2022  skrll Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|

Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3

Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes

Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509
 1.10 30-Oct-2021  skrll Fix thinko in tlb_record_asids memset size calculation.
 1.9 07-Oct-2021  skrll Hacky build fixes
 1.8 02-Oct-2021  skrll Pass the pmap in tlb_set_asid for the benefit of aarch64.
 1.7 01-May-2021  skrll Fixup some pmap / VM related #defines and code
 1.6 14-Mar-2020  skrll branches: 1.6.8;
Trailing whitespace
 1.5 11-Mar-2020  thorpej With DEBUG defined, it's possible to execute a TLB-vs-segmap consistency
check from a (soft) interrupt handler. But if a platform does not otherwise
require the pmap_tlb_miss_lock, then where will be a brief window of
inconsistency that, while harmless, will still fire an assertion in the
consistency check.

Fix this with the following changes:
1- Refactor the pmap_tlb_miss_lock into MI code and rename it from
pmap_tlb_miss_lock_{enter,exit}() to pmap_tlb_miss_lock_{enter,exit}().
MD code can still define the "md" hooks as necessary, and if so, will
override the common implementation.
2- Provde a pmap_bootstrap_common() function to perform common pmap bootstrap
operations, namely initializing the pmap_tlb_miss_lock if it's needed.
If MD code overrides the implementation, it's responsible for initializing
its own lock.
3- Call pmap_bootstrap_common() from the mips, powerpc booke, and riscv
pmap_bootstrap() routines. (This required adding one for riscv.)
4- Switch powerpc booke to the common pmap_tlb_miss_lock.
5- Enable pmap_tlb_miss_lock if DEBUG is defined, even if it's not otherwise
required.

PR port-mips/55062 (Failed assertion in pmap_md_tlb_check_entry())
 1.4 16-Jun-2019  maxv Misc changes in RISC-V.
 1.3 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.2 31-Mar-2015  matt branches: 1.2.2; 1.2.18; 1.2.22;
Use sfence.vm instruction and change ptbr cse to sptbr csr
 1.1 28-Mar-2015  matt Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.2.22.3 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.2.22.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.2.22.1 10-Jun-2019  christos Sync with HEAD
 1.2.18.2 03-Dec-2017  jdolecek update from HEAD
 1.2.18.1 31-Mar-2015  jdolecek file pmap_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2.2.2 06-Apr-2015  skrll Sync with HEAD
 1.2.2.1 31-Mar-2015  skrll file pmap_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.6.8.1 13-May-2021  thorpej Sync with HEAD.
 1.20.2.1 02-Aug-2025  perseant Sync with HEAD
 1.21.2.1 26-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #67):

sys/arch/riscv/include/sysreg.h: revision 1.34
sys/arch/riscv/include/pte.h: revision 1.15
sys/arch/riscv/include/pte.h: revision 1.16
sys/arch/riscv/riscv/genassym.cf: revision 1.17
sys/arch/riscv/riscv/locore.S: revision 1.47
sys/arch/riscv/riscv/bus_space.c: revision 1.3
sys/arch/riscv/include/pmap.h: revision 1.25
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.22
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.23
sys/arch/riscv/riscv/cpu.c: revision 1.10
sys/arch/riscv/riscv/riscv_machdep.c: revision 1.46

Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.

Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/


Fix RV32 build. Svpbmt and Memory Attribute Extension (XTheadMae) are
SV39 and above only.
 1.5 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.4 04-Nov-2020  skrll RCSID and whitespace police...
 1.3 14-Mar-2020  skrll branches: 1.3.4;
Trailing whitespace
 1.2 16-Mar-2017  chs branches: 1.2.12; 1.2.16;
allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.4; 1.1.6;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.6.1 21-Apr-2017  bouyer Sync with HEAD
 1.1.4.1 20-Mar-2017  pgoyette Sync with HEAD
 1.1.2.3 28-Aug-2017  skrll Sync with HEAD
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file process_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.2.16.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.2.12.2 03-Dec-2017  jdolecek update from HEAD
 1.2.12.1 16-Mar-2017  jdolecek file process_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.3.4.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.3 04-Nov-2020  skrll RCSID and whitespace police...
 1.2 14-Mar-2020  skrll branches: 1.2.4;
Trailing whitespace
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.22;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.22.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file procfs_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file procfs_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.2.4.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.46 12-Oct-2025  thorpej Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/
 1.45 06-Sep-2025  thorpej Re-factor the console-related code into fdt_console.[ch]
 1.44 06-Sep-2025  thorpej Refactor the "platform" defitions into fdt_platform.h
 1.43 02-Mar-2025  skrll branches: 1.43.2;
risc-v: ensure the boot stacks are mapped so that pmap_extract works
 1.42 04-Jan-2025  skrll Style change in mm_md_kernacc. NFC.
 1.41 24-Nov-2024  skrll risc-v: fix riscv32 build
 1.40 23-Nov-2024  skrll risc-v: add __HAVE_MM_MD_KERNACC (basic) support.
 1.39 22-Nov-2024  skrll risc-v: split userret into its own header as per other ports

Helps with crash(8)
 1.38 15-Aug-2024  skrll Add a comment.
 1.37 05-Mar-2024  thorpej branches: 1.37.2;
Move the at-shutdown call to resettodr() from cpu_reboot() to kern_reboot().

It's a small step, but it's a step.
 1.36 18-Jan-2024  skrll Provide a working delay(9)
 1.35 22-Dec-2023  skrll Minor stylistic changes. NFCI.
 1.34 03-Sep-2023  skrll Fix and enable MULTIPROCESSOR
 1.33 24-Aug-2023  rin riscv: cpu_setmcontext: Do not unconditionally update tp register

Conserve tp register for _UC_CPU and update later if _UC_TLSBASE is
specified. This is what powerpc does, which also uses a general
purpose register for TLS pointer.

Found by tests/lib/libpthread/t_swapcontext:swapcontext1, which
successfully passes now.
 1.32 04-Aug-2023  mrg avoid comparing arrays directly, compare the address of their first element.

found by GCC 12.
 1.31 10-Jul-2023  rin riscv: Add FDT-based initrd, rndseed, and efirng support.

Can be used from our in-tree bootrisv64.efi.
 1.30 10-Jul-2023  rin fdt(4): Factor out bootargs support from evbarm and riscv.
 1.29 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.28 28-May-2023  skrll Second arg to fdt_memory_remove_range is a size so pass dtbsize and not
dtb + dtbsize
 1.27 14-May-2023  skrll Check for RB_HALT in cpu_reboot.
 1.26 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.25 17-Nov-2022  simonb Use updated defines for the user-mode sstatus value.
 1.24 15-Nov-2022  simonb Use similar macro-magic to aarch64 armreg.h to add per-csr
read/write/set-bits/clear-bits inline functions. Keep the
open-coded 32-bit version of riscvreg_cycle_read() than reads
a 64-bit cycle counter values.

Added benefit of fixing these so that the inline asm uses __volatile
and aren't opmtimised to nops by the compiler.
 1.23 18-Oct-2022  skrll remove a stray comment
 1.22 16-Oct-2022  skrll Re-orgnaise a litte. From Simon.
 1.21 16-Oct-2022  skrll Map the DTB using VM_KERNEL_DTB_BASE and CONSADDR using VM_KERNEL_IO_BASE
 1.20 15-Oct-2022  simonb #define<tab>
 1.19 28-Sep-2022  skrll Use legacy SBI Console GetChar for earlycons. It works on qemu.
 1.18 20-Sep-2022  skrll Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|

Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3

Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes

Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509
 1.17 20-Sep-2022  skrll Whitespace
 1.16 20-Sep-2022  skrll KNF
 1.15 07-Oct-2021  skrll Hacky build fixes
 1.14 01-May-2021  skrll Sprinkle #ifdef FPE for now
 1.13 04-Nov-2020  skrll branches: 1.13.4;
Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.12 04-Nov-2020  skrll RCSID and whitespace police...
 1.11 11-Jun-2020  ad branches: 1.11.2;
uvm_availmem(): give it a boolean argument to specify whether a recent
cached value will do, or if the very latest total must be fetched. It can
be called thousands of times a second and fetching the totals impacts not
only the calling LWP but other CPUs doing unrelated activity in the VM
system.
 1.10 14-Mar-2020  skrll Trailing whitespace
 1.9 11-Mar-2020  thorpej With DEBUG defined, it's possible to execute a TLB-vs-segmap consistency
check from a (soft) interrupt handler. But if a platform does not otherwise
require the pmap_tlb_miss_lock, then where will be a brief window of
inconsistency that, while harmless, will still fire an assertion in the
consistency check.

Fix this with the following changes:
1- Refactor the pmap_tlb_miss_lock into MI code and rename it from
pmap_tlb_miss_lock_{enter,exit}() to pmap_tlb_miss_lock_{enter,exit}().
MD code can still define the "md" hooks as necessary, and if so, will
override the common implementation.
2- Provde a pmap_bootstrap_common() function to perform common pmap bootstrap
operations, namely initializing the pmap_tlb_miss_lock if it's needed.
If MD code overrides the implementation, it's responsible for initializing
its own lock.
3- Call pmap_bootstrap_common() from the mips, powerpc booke, and riscv
pmap_bootstrap() routines. (This required adding one for riscv.)
4- Switch powerpc booke to the common pmap_tlb_miss_lock.
5- Enable pmap_tlb_miss_lock if DEBUG is defined, even if it's not otherwise
required.

PR port-mips/55062 (Failed assertion in pmap_md_tlb_check_entry())
 1.8 31-Dec-2019  ad Rename uvm_free() -> uvm_availmem().
 1.7 21-Dec-2019  ad uvmexp.free -> uvm_free()
 1.6 23-Nov-2019  ad cpu_need_resched():

- Remove all code that should be MI, leaving the bare minimum under arch/.
- Make the required actions very explicit.
- Pass in LWP pointer for convenience.
- When a trap is required on another CPU, have the IPI set it locally.
- Expunge cpu_did_resched().
 1.5 21-Nov-2019  ad mi_userret(): take care of calling preempt(), set spc_curpriority directly,
and remove MD code that does the same.
 1.4 06-Apr-2019  kamil Centralized shared part of child_return() into MI part

Add a new function md_child_return() for MD specific bits only.

New child_return() is now part of MI and central code that handles
uniformly tracing code (KTR and ptrace(2)).

Synchronize value passed to ktrsysret() among ports to SYS_fork. This is
a traditional value and accessing p_lflag to check for PL_PPWAIT shall
use locking against proc_lock. Returning SYS_fork vs SYS_vfork still isn't
correct enough as there are more entry points to forking code. Instead of
making it too good, just settle with plain SYS_fork for all ports.
 1.3 03-Apr-2019  kamil Rework the fork(2)/vfork(2) event signalling under ptrace(2)

Remove the constraint of SIGTRAP event being maskable by a tracee.

Now all SIGTRAP TRAP_CHLD events are delivered to debugger.

This code touches MD specific logic and the child_return routine.
It's an intermediate step with a room for refactoring in future and
right now the least invasive approach. This allows to assert expected
behavior in already existing ATF tests and make the code prettier
in future keeping the same semantics. Probably there is a need for a MI
wrapper of child_return for shared functionality between ports.
 1.2 16-Mar-2017  chs branches: 1.2.12; 1.2.16;
allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.4; 1.1.6;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.6.1 21-Apr-2017  bouyer Sync with HEAD
 1.1.4.1 20-Mar-2017  pgoyette Sync with HEAD
 1.1.2.3 28-Aug-2017  skrll Sync with HEAD
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file riscv_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.2.16.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.2.16.1 10-Jun-2019  christos Sync with HEAD
 1.2.12.2 03-Dec-2017  jdolecek update from HEAD
 1.2.12.1 16-Mar-2017  jdolecek file riscv_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.11.2.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.13.4.1 13-May-2021  thorpej Sync with HEAD.
 1.37.2.1 02-Aug-2025  perseant Sync with HEAD
 1.43.2.1 26-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #67):

sys/arch/riscv/include/sysreg.h: revision 1.34
sys/arch/riscv/include/pte.h: revision 1.15
sys/arch/riscv/include/pte.h: revision 1.16
sys/arch/riscv/riscv/genassym.cf: revision 1.17
sys/arch/riscv/riscv/locore.S: revision 1.47
sys/arch/riscv/riscv/bus_space.c: revision 1.3
sys/arch/riscv/include/pmap.h: revision 1.25
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.22
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.23
sys/arch/riscv/riscv/cpu.c: revision 1.10
sys/arch/riscv/riscv/riscv_machdep.c: revision 1.46

Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.

Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/


Fix RV32 build. Svpbmt and Memory Attribute Extension (XTheadMae) are
SV39 and above only.
 1.2 03-Sep-2023  skrll Fix and enable MULTIPROCESSOR
 1.1 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file sig32_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file sig32_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.6 04-Aug-2024  skrll spaces to tabs
 1.5 07-May-2023  skrll branches: 1.5.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.4 04-Nov-2020  skrll RCSID and whitespace police...
 1.3 14-Mar-2020  skrll branches: 1.3.4;
Trailing whitespace
 1.2 27-Nov-2018  maxv Fix widespread leak in the sendsig_siginfo() functions. sigframe_siginfo
has padding, so zero it out properly. While here I'm also zeroing out some
other things in several ports, for safety. Same problem in netbsd32, so
fix that too.

I can't compile-test on each architecture, but there should be no
breakage (tm).

Overall this fixes at least 14 info leaks. Prompted by the discovery by
KLEAK of a leak in amd64's sendsig_siginfo.
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.12; 1.1.18; 1.1.20; 1.1.22;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.22.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.20.1 26-Dec-2018  pgoyette Sync with HEAD, resolve a few conflicts
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file sig_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.12.1 27-Jan-2019  martin Pull up following revision(s) (requested by maxv in ticket #1173):
sys/arch/hppa/hppa/sig_machdep.c: revision 1.26
sys/arch/arm/arm/sig_machdep.c: revision 1.51
sys/arch/i386/i386/machdep.c: revision 1.813
sys/arch/alpha/alpha/machdep.c: revision 1.352
sys/arch/m68k/m68k/sig_machdep.c: revision 1.50
sys/arch/usermode/target/i386/cpu_i386.c: revision 1.8
sys/arch/sparc64/sparc64/machdep.c: revision 1.289
sys/arch/sparc64/sparc64/netbsd32_machdep.c: revision 1.111
sys/arch/powerpc/powerpc/sig_machdep.c: revision 1.46
sys/arch/amd64/amd64/netbsd32_machdep.c: revision 1.117
sys/arch/sh3/sh3/sh3_machdep.c: revision 1.106
sys/arch/mips/mips/netbsd32_machdep.c: revision 1.16
sys/arch/mips/mips/sig_machdep.c: revision 1.24
sys/arch/riscv/riscv/sig_machdep.c: revision 1.2
sys/arch/usermode/target/x86_64/cpu_x86_64.c: revision 1.7
sys/arch/vax/vax/sig_machdep.c: revision 1.23

Fix widespread leak in the sendsig_siginfo() functions. sigframe_siginfo
has padding, so zero it out properly. While here I'm also zeroing out some
other things in several ports, for safety. Same problem in netbsd32, so
fix that too.

I can't compile-test on each architecture, but there should be no
breakage (tm).

Overall this fixes at least 14 info leaks. Prompted by the discovery by
KLEAK of a leak in amd64's sendsig_siginfo.
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file sig_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.3.4.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.5.6.1 02-Aug-2025  perseant Sync with HEAD
 1.3 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2 04-Nov-2020  skrll RCSID and whitespace police...
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.34;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.34.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file softint_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file softint_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.8 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.7 10-Jun-2023  skrll Remove magic numbers. NFCI.

Copyright maintenance while I'm here.
 1.6 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.5 10-Nov-2020  skrll Revamp to the point it builds, but needs more work
 1.4 04-Nov-2020  skrll RCSID and whitespace police...
 1.3 14-Mar-2020  skrll branches: 1.3.4;
Trailing whitespace
 1.2 31-Mar-2015  matt branches: 1.2.2; 1.2.18; 1.2.22;
Get curcpu() from L_CPU(tp)
 1.1 28-Mar-2015  matt Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.2.22.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.2.18.2 03-Dec-2017  jdolecek update from HEAD
 1.2.18.1 31-Mar-2015  jdolecek file spl.S was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2.2.2 06-Apr-2015  skrll Sync with HEAD
 1.2.2.1 31-Mar-2015  skrll file spl.S was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.3.4.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.2 04-Nov-2020  skrll RCSID and whitespace police...
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.34;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.34.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file stubs.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file stubs.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.2 04-Nov-2020  skrll RCSID and whitespace police...
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.34;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.34.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file sys_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file sys_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.6 22-Nov-2024  skrll risc-v: split userret into its own header as per other ports

Helps with crash(8)
 1.5 05-Oct-2023  ad branches: 1.5.6;
Arrange to update cached LWP credentials in userret() rather than during
syscall/trap entry, eliminating a test+branch on every syscall/trap.

This wasn't possible in the 3.99.x timeframe when l->l_cred came about
because there wasn't a reliable/timely way to force an ONPROC LWP running on
a remote CPU into the kernel (which is just about the only new thing in
this scheme).
 1.4 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.3 07-Oct-2021  skrll Hacky build fixes
 1.2 14-Mar-2020  skrll Trailing whitespace
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.22;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.22.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file syscall.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file syscall.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.5.6.1 02-Aug-2025  perseant Sync with HEAD
 1.31 07-Oct-2025  skrll whitespace
 1.30 25-Nov-2024  skrll branches: 1.30.2;
risc-v: support crash(8)
 1.29 23-Nov-2024  skrll risc-v: don't include locore.h in db_machdep.h
 1.28 22-Nov-2024  skrll risc-v: split userret into its own header as per other ports

Helps with crash(8)
 1.27 04-Aug-2024  skrll spaces to tabs
 1.26 02-May-2024  skrll branches: 1.26.2;
risc-v: fix the error code when uvm_fault fails with cpu_set_onfault

Return the error from uvm_fault instead of EFAULT unconditionally when
faulting with cpu_set_onfault to fix several atf tests.
 1.25 01-Apr-2024  skrll Return the correct error from {fetch,store}_user_data and fix

futex_wake_op_op: [0.273033s] Failed: /usr/src/tests/lib/libc/sys/t_futex_ops.c:942: Expected errno 14, got 1, in __futex(&futex_word, FUTEX_WAKE_OP | flags, 0, NULL, NULL, 0, op) == -1
 1.24 07-Sep-2023  skrll Handle CAUSE_LOAD_PAGE_FAULT in trap_pagefault_fixup
 1.23 22-Aug-2023  rin riscv/trap.c: Dump cause register for unhandled page fault
 1.22 22-Aug-2023  rin riscv/trap.c: Handle userland breakpoint exception

Now, gdb 13 works for riscv64 to some extent :)
 1.21 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.20 26-Feb-2023  skrll ci_data.cpu_kcpuset -> ci_kcpuset

NFCI.
 1.19 15-Oct-2022  simonb #define<tab>
 1.18 27-Sep-2022  skrll Basic ddb and backtrace support.

[ 1.0000000] panic: kernel diagnostic assertion "msgbufaddr != 0" failed: file "/home/nick/netbsd/nbcvs/src/sys/arch/riscv/riscv/riscv_machdep.c", line 564
[ 1.0000000] cpu0: Begin traceback...
[ 1.0000000] trace fp ffffffc000801dd0
[ 1.0000000] fp ffffffc000801e10 ?() at ffffffc0001eee98
[ 1.0000000] fp ffffffc000801e30 ?() at ffffffc0002ad984
[ 1.0000000] fp ffffffc000801ee0 ?() at ffffffc000005430
[ 1.0000000] cpu0: End traceback...
[ 1.0000000] Trapframe @ 0xffffffc000801cb0 (cause=3 (breakpoint), status=0x100, pc=0xffffffc0000007e4, va=0):
[ 1.0000000] ra =0xffffffc0001eee9c, sp =0xffffffc000801dd0, gp =0xffffffc0006a8f40, tp = 0
[ 1.0000000] s0 =0xffffffc000600ac0, s1 = 0x1000, s2 =0xffffffc000438df0, s3 =0xffffffc000801d80
[ 1.0000000] s4 =0xffffffc0001eed78, s5 =0xffffffc0006d55f8, s6 =0xffffffc000801d88, s7 =0xffffffc0006dfdb8
[ 1.0000000] s8 =0xffffffc000428c18, s9 =0xffffffc000801dd0, s10=0xffffffc0000a3822, s11=0xffffffc0006d55f8
[ 1.0000000] a0 = 0x17, a1 = 0xa, a2 = 0, a3 =0xffffffc00041f658
[ 1.0000000] a4 = 0, a5 = 0x1, a5 = 0, a7 = 0x1
[ 1.0000000] t0 =0xffffffc0006dfe30, t1 =0xffffffc000801bb8, t2 =0xffffffc000803000, t3 = 0x75
[ 1.0000000] t4 = 0, t5 = 0x63, t6 = 0x1
[ 1.0000000] kernel: breakpoint
Stopped in pid 0.0 (system) at ffffffc0000007e4: c.ebreak
db>
 1.17 21-Sep-2022  skrll Add some causes and convenience macros
 1.16 07-Oct-2021  skrll Hacky build fixes
 1.15 20-Dec-2020  skrll Support __HAVE_PMAP_PV_TRACK in sys/uvm/pmap based pmaps (aka common pmap)
 1.14 14-Nov-2020  skrll Improve dump_trapframe output layout and fix printing of s6/s7
 1.13 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.12 04-Nov-2020  skrll RCSID and whitespace police...
 1.11 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.10 01-Nov-2020  skrll Update CAUSE_* defines to reflect riscv-privileged-20190608.pdf
 1.9 01-Nov-2020  skrll Remove unused variable
 1.8 01-Nov-2020  skrll Typo in a trap name
 1.7 30-Jun-2020  maxv branches: 1.7.2;
Make copystr() a MI C function, part of libkern and shared on all
architectures.

Notes:

- On alpha and ia64 the function is kept but gets renamed locally to avoid
symbol collision. This is because on these two arches, I am not sure
whether the ASM callers do not rely on fixed registers, so I prefer to
keep the ASM body for now.
- On Vax, only the symbol is removed, because the body is used from other
functions.
- On RISC-V, this change fixes a bug: copystr() was just a wrapper around
strlcpy(), but strlcpy() makes the operation less safe (strlen on the
source beyond its size).
- The kASan, kCSan and kMSan wrappers are removed, because now that
copystr() is in C, the compiler transformations are applied to it,
without the need for manual wrappers.

Could test on amd64 only, but should be fine.
 1.6 06-Apr-2020  skrll Whitespace
 1.5 14-Mar-2020  skrll Trailing whitespace
 1.4 21-Nov-2019  ad mi_userret(): take care of calling preempt(), set spc_curpriority directly,
and remove MD code that does the same.
 1.3 16-Jun-2019  maxv Misc changes in RISC-V.
 1.2 06-Apr-2019  thorpej Overhaul the API used to fetch and store individual memory cells in
userspace. The old fetch(9) and store(9) APIs (fubyte(), fuword(),
subyte(), suword(), etc.) are retired and replaced with new ufetch(9)
and ustore(9) APIs that can return proper error codes, etc. and are
implemented consistently across all platforms. The interrupt-safe
variants are no longer supported (and several of the existing attempts
at fuswintr(), etc. were buggy and not actually interrupt-safe).

Also augmement the ucas(9) API, making it consistently available on
all plaforms, supporting uniprocessor and multiprocessor systems, even
those that do not have CAS or LL/SC primitives.

Welcome to NetBSD 8.99.37.
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.22;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.22.3 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.1.22.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file trap.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file trap.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.7.2.2 03-Jan-2021  thorpej Sync w/ HEAD.
 1.7.2.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.26.2.1 02-Aug-2025  perseant Sync with HEAD
 1.30.2.1 09-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #48):

sys/arch/riscv/riscv/trap.c: revision 1.31
sys/arch/riscv/riscv/cpu.c: revision 1.8
sys/arch/riscv/riscv/cpu.c: revision 1.9

whitespace

Attach the fpu {loads,save,reenable} event counters.
 1.9 04-Aug-2024  skrll spaces to tabs
 1.8 07-May-2023  skrll branches: 1.8.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.7 04-Dec-2022  skrll ASSERT that md_astpending it zero for the new lwp.
 1.6 15-Nov-2022  simonb Use similar macro-magic to aarch64 armreg.h to add per-csr
read/write/set-bits/clear-bits inline functions. Keep the
open-coded 32-bit version of riscvreg_cycle_read() than reads
a 64-bit cycle counter values.

Added benefit of fixing these so that the inline asm uses __volatile
and aren't opmtimised to nops by the compiler.
 1.5 29-Sep-2022  skrll Remove unnecessary include of <sys/malloc.h>.
 1.4 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.3 14-Mar-2020  skrll branches: 1.3.4;
Trailing whitespace
 1.2 13-Nov-2019  pgoyette Clean-up unnecessary inclusions of opt_coredump.h
 1.1 28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.22;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.22.2 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.1.22.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 28-Mar-2015  jdolecek file vm_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2 06-Apr-2015  skrll Sync with HEAD
 1.1.2.1 28-Mar-2015  skrll file vm_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.3.4.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.8.6.1 02-Aug-2025  perseant Sync with HEAD
 1.4 06-Sep-2025  thorpej Step towards modularizing the Flattened Device Tree code.

Define attributes for each of the specific device bindings: clock,
dai, dma, gpio, i2c, iommu, mbox, mmc_pwrseq, phy, power, power domain,
pwm, regulator, reset controller, spi, system controller, pin
controller. Include these support files only if either a provider
or consumer with one of these attributes is present in the kernel
config.

Add the necessary attributes to the device / attach declarations for
each provider and consumer.

There are some bindings that are consumed by generic code (iommu, pinctrl,
power, power domain). Provide weak stubs for these routines to handle
situations where there is no provider.

No actual code changed; NFCI.
 1.3 13-Jan-2024  skrll risc-v: add a SiFive FU[57]40/ L2 Cache controller driver
 1.2 03-Dec-2022  skrll Trailing whitespace
 1.1 25-Nov-2022  jmcneill Add driver for SiFive FU540 PRCI clock controller.
 1.2 14-Jan-2024  skrll risc-v: the SiFive FU[57]40 cache controller is present in the JH71x0 SoCs.
 1.1 13-Jan-2024  skrll risc-v: add a SiFive FU[57]40/ L2 Cache controller driver
 1.1 25-Nov-2022  jmcneill Add driver for SiFive FU540 PRCI clock controller.
 1.1 30-Sep-2021  jmcneill efiboot: Build and install bootriscv64.efi for riscv64 builds.
 1.1 30-Sep-2021  jmcneill efiboot: Build and install bootriscv64.efi for riscv64 builds.
 1.12 06-Sep-2025  thorpej Step towards modularizing the Flattened Device Tree code.

Define attributes for each of the specific device bindings: clock,
dai, dma, gpio, i2c, iommu, mbox, mmc_pwrseq, phy, power, power domain,
pwm, regulator, reset controller, spi, system controller, pin
controller. Include these support files only if either a provider
or consumer with one of these attributes is present in the kernel
config.

Add the necessary attributes to the device / attach declarations for
each provider and consumer.

There are some bindings that are consumed by generic code (iommu, pinctrl,
power, power domain). Provide weak stubs for these routines to handle
situations where there is no provider.

No actual code changed; NFCI.
 1.11 08-Feb-2025  skrll risc-v: add a JH7110 TRNG driver
 1.10 03-Jan-2025  skrll risc-v: add a StarFive JH71[01]0 temperature sensor driver
 1.9 01-Jan-2025  skrll risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.
 1.8 11-Nov-2024  skrll risc-v: add a specific driver for the JH7110 STG system controller
 1.7 11-Nov-2024  skrll risc-v: add a JH7110 PCIe PHY driver
 1.6 11-Nov-2024  skrll risc-v: Add initial JH7110 pin controller driver
 1.5 26-Oct-2024  skrll risc-v: add ethernet support on JH71[01]0 support

At present only the JH7110 EQOS support is enabled as it work.

The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.
 1.4 27-Jul-2024  skrll risc-v: split the jh7100 clock controller driver

In preparation for the JH7110 clock driver split the clock definition
and attachment code from the clock handling macros / methods.
 1.3 07-Feb-2024  skrll branches: 1.3.2;
risc-v: add a driver the JH7100 pin controller
 1.2 18-Jan-2024  skrll risc-v: attach the Cadence XHCI usb controller on the JH7100 SoC
 1.1 16-Jan-2024  skrll risc-v: add a StarTech JH7100 SoC clock driver

The JH7100 is seen in the Beagle-V board.
 1.3.2.1 02-Aug-2025  perseant Sync with HEAD
 1.6 18-Jan-2025  skrll risc-v: StarFive JH7100: add the temperature sensor clocks to the clock driver
 1.5 18-Jan-2025  skrll risc-v: add support for the StarFive JH7100 audio clocks
 1.4 18-Sep-2024  skrll #define<space> consistency
 1.3 27-Jul-2024  skrll risc-v: split the jh7100 clock controller driver

In preparation for the JH7110 clock driver split the clock definition
and attachment code from the clock handling macros / methods.
 1.2 17-Jan-2024  skrll branches: 1.2.2;
Implement jh7100_clkc_fracdiv_get_rate
 1.1 16-Jan-2024  skrll risc-v: add a StarTech JH7100 SoC clock driver

The JH7100 is seen in the Beagle-V board.
 1.2.2.1 02-Aug-2025  perseant Sync with HEAD
 1.3 27-Jul-2024  skrll risc-v: split the jh7100 clock controller driver

In preparation for the JH7110 clock driver split the clock definition
and attachment code from the clock handling macros / methods.
 1.2 17-Jan-2024  skrll branches: 1.2.2;
Fix types of constants
 1.1 16-Jan-2024  skrll risc-v: add a StarTech JH7100 SoC clock driver

The JH7100 is seen in the Beagle-V board.
 1.2.2.1 02-Aug-2025  perseant Sync with HEAD
 1.1 26-Oct-2024  skrll branches: 1.1.4;
risc-v: add ethernet support on JH71[01]0 support

At present only the JH7110 EQOS support is enabled as it work.

The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.
 1.1.4.2 02-Aug-2025  perseant Sync with HEAD
 1.1.4.1 26-Oct-2024  perseant file jh7100_gmac.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
 1.3 18-Sep-2024  skrll #define<space> consistency
 1.2 08-Feb-2024  skrll branches: 1.2.2;
Some fixes from Roland Illig
- fix a locking bug
- '\n' at the end of error messages
 1.1 07-Feb-2024  skrll risc-v: add a driver the JH7100 pin controller
 1.2.2.1 02-Aug-2025  perseant Sync with HEAD
 1.8 17-Jan-2025  skrll branches: 1.8.4;
risc-v: Don't attach the JH7110 ISP clock controller

Something isn't quite right with the ISP clock controller and it causes
problems with sysctl -A. As it's not currently used don't attach it.
 1.7 17-Jan-2025  skrll Order the clock controllers consistently. NFC.
 1.6 20-Sep-2024  rin riscv/jh7110_clkc: Missing <sys/kmem.h> include
 1.5 18-Sep-2024  skrll risc-v: add reset support to the JH7110 SOC clock controller driver
 1.4 18-Sep-2024  skrll Match "Image-Signal-Process" clock controller and only aprint_debug the
state of "System" and "Always-On" clocks.
 1.3 18-Sep-2024  skrll #define<space> consistency
 1.2 09-Sep-2024  skrll Whitespace
 1.1 19-Aug-2024  skrll Add a clock driver for the JH7110 SoC found in the StarFive VisionFive 2
SBC.

It's not fully functional as something is wrong for the
Image-Signal-Process controller which is why it's #if 0'd out.
 1.8.4.2 02-Aug-2025  perseant Sync with HEAD
 1.8.4.1 17-Jan-2025  perseant file jh7110_clkc.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
 1.2 17-Nov-2024  skrll branches: 1.2.4;
Miscellaneous cleanup.
 1.1 26-Oct-2024  skrll risc-v: add ethernet support on JH71[01]0 support

At present only the JH7110 EQOS support is enabled as it work.

The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.
 1.2.4.2 02-Aug-2025  perseant Sync with HEAD
 1.2.4.1 17-Nov-2024  perseant file jh7110_eqos.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
 1.2 09-Jan-2025  skrll branches: 1.2.4;
Fix error reporting to not include two ": "
 1.1 01-Jan-2025  skrll risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.
 1.2.4.2 02-Aug-2025  perseant Sync with HEAD
 1.2.4.1 09-Jan-2025  perseant file jh7110_pcie.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
 1.3 01-Jan-2025  skrll branches: 1.3.4;
spaces to tab
 1.2 12-Nov-2024  skrll Remove #if 0 / #endif blocks
 1.1 11-Nov-2024  skrll risc-v: add a JH7110 PCIe PHY driver
 1.3.4.2 02-Aug-2025  perseant Sync with HEAD
 1.3.4.1 01-Jan-2025  perseant file jh7110_pciephy.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
 1.1 11-Nov-2024  skrll branches: 1.1.4;
risc-v: Add initial JH7110 pin controller driver
 1.1.4.2 02-Aug-2025  perseant Sync with HEAD
 1.1.4.1 11-Nov-2024  perseant file jh7110_pinctrl.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
 1.1 11-Nov-2024  skrll branches: 1.1.4;
risc-v: add a specific driver for the JH7110 STG system controller
 1.1.4.2 02-Aug-2025  perseant Sync with HEAD
 1.1.4.1 11-Nov-2024  perseant file jh7110_syscon.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
 1.2 09-Feb-2025  skrll branches: 1.2.4;
risc-v: JH7110 TRNG aprint_verbose the features and build conf registers
 1.1 08-Feb-2025  skrll risc-v: add a JH7110 TRNG driver
 1.2.4.2 02-Aug-2025  perseant Sync with HEAD
 1.2.4.1 09-Feb-2025  perseant file jh7110_trng.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
 1.4 18-Sep-2024  skrll branches: 1.4.4;
#define<space> consistency
 1.3 19-Aug-2024  skrll Add a clock driver for the JH7110 SoC found in the StarFive VisionFive 2
SBC.

It's not fully functional as something is wrong for the
Image-Signal-Process controller which is why it's #if 0'd out.
 1.2 04-Aug-2024  skrll spaces to tabs
 1.1 27-Jul-2024  skrll risc-v: split the jh7100 clock controller driver

In preparation for the JH7110 clock driver split the clock definition
and attachment code from the clock handling macros / methods.
 1.4.4.2 02-Aug-2025  perseant Sync with HEAD
 1.4.4.1 18-Sep-2024  perseant file jh71x0_clkc.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
 1.5 12-Oct-2024  skrll branches: 1.5.4;
Consistency of #define<space>
 1.4 18-Sep-2024  skrll risc-v: add reset support to the JH7110 SOC clock controller driver
 1.3 25-Aug-2024  skrll Whitespace
 1.2 19-Aug-2024  skrll Add a clock driver for the JH7110 SoC found in the StarFive VisionFive 2
SBC.

It's not fully functional as something is wrong for the
Image-Signal-Process controller which is why it's #if 0'd out.
 1.1 27-Jul-2024  skrll risc-v: split the jh7100 clock controller driver

In preparation for the JH7110 clock driver split the clock definition
and attachment code from the clock handling macros / methods.
 1.5.4.2 02-Aug-2025  perseant Sync with HEAD
 1.5.4.1 12-Oct-2024  perseant file jh71x0_clkc.h was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
 1.1 26-Oct-2024  skrll branches: 1.1.4;
risc-v: add ethernet support on JH71[01]0 support

At present only the JH7110 EQOS support is enabled as it work.

The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.
 1.1.4.2 02-Aug-2025  perseant Sync with HEAD
 1.1.4.1 26-Oct-2024  perseant file jh71x0_eth.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
 1.1 26-Oct-2024  skrll branches: 1.1.4;
risc-v: add ethernet support on JH71[01]0 support

At present only the JH7110 EQOS support is enabled as it work.

The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.
 1.1.4.2 02-Aug-2025  perseant Sync with HEAD
 1.1.4.1 26-Oct-2024  perseant file jh71x0_eth.h was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
 1.1 03-Jan-2025  skrll branches: 1.1.4;
risc-v: add a StarFive JH71[01]0 temperature sensor driver
 1.1.4.2 02-Aug-2025  perseant Sync with HEAD
 1.1.4.1 03-Jan-2025  perseant file jh71x0_temp.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
 1.3 18-Sep-2024  skrll #define<space> consistency
 1.2 25-Aug-2024  skrll spaces to tab
 1.1 18-Jan-2024  skrll branches: 1.1.2;
risc-v: attach the Cadence XHCI usb controller on the JH7100 SoC
 1.1.2.1 02-Aug-2025  perseant Sync with HEAD
 1.3 19-Sep-2025  mrg mirror the GCC 14 warning from the other files.sunxi.
 1.2 06-Sep-2025  thorpej Step towards modularizing the Flattened Device Tree code.

Define attributes for each of the specific device bindings: clock,
dai, dma, gpio, i2c, iommu, mbox, mmc_pwrseq, phy, power, power domain,
pwm, regulator, reset controller, spi, system controller, pin
controller. Include these support files only if either a provider
or consumer with one of these attributes is present in the kernel
config.

Add the necessary attributes to the device / attach declarations for
each provider and consumer.

There are some bindings that are consumed by generic code (iommu, pinctrl,
power, power domain). Provide weak stubs for these routines to handle
situations where there is no provider.

No actual code changed; NFCI.
 1.1 13-Aug-2024  skrll risc-v: Allwinner D1 support

Add the Allwinnder D1 support provided by Rui-Xiang Guo and updated
but me.

https://mail-index.netbsd.org/port-riscv/2024/08/04/msg000127.html

Only driver listed as attaching in

https://github.com/picohive/netbsd-mangopi-mq-pro/blob/main/boot.log

have been added.

There is no need for the platform stuff as the board's u-boot is able
to load bootriscv64.efi and boot a generic kernel.
 1.1 13-Aug-2024  skrll risc-v: Allwinner D1 support

Add the Allwinnder D1 support provided by Rui-Xiang Guo and updated
but me.

https://mail-index.netbsd.org/port-riscv/2024/08/04/msg000127.html

Only driver listed as attaching in

https://github.com/picohive/netbsd-mangopi-mq-pro/blob/main/boot.log

have been added.

There is no need for the platform stuff as the board's u-boot is able
to load bootriscv64.efi and boot a generic kernel.
 1.1 13-Aug-2024  skrll risc-v: Allwinner D1 support

Add the Allwinnder D1 support provided by Rui-Xiang Guo and updated
but me.

https://mail-index.netbsd.org/port-riscv/2024/08/04/msg000127.html

Only driver listed as attaching in

https://github.com/picohive/netbsd-mangopi-mq-pro/blob/main/boot.log

have been added.

There is no need for the platform stuff as the board's u-boot is able
to load bootriscv64.efi and boot a generic kernel.
 1.1 13-Aug-2024  skrll risc-v: Allwinner D1 support

Add the Allwinnder D1 support provided by Rui-Xiang Guo and updated
but me.

https://mail-index.netbsd.org/port-riscv/2024/08/04/msg000127.html

Only driver listed as attaching in

https://github.com/picohive/netbsd-mangopi-mq-pro/blob/main/boot.log

have been added.

There is no need for the platform stuff as the board's u-boot is able
to load bootriscv64.efi and boot a generic kernel.

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