| History log of /src/sys/arch/riscv/dev |
| Revision | Date | Author | Comments |
| 1.5 | 24-Mar-2024 |
skrll | Pretty print plic attachment
|
| 1.4 | 25-Dec-2023 |
skrll | Deliver plic interrupts to the cpu^Whart establishing the interrupt
handler. At least this is known to be a valid hart, but it might share
some interrupts around too.
|
| 1.3 | 16-Dec-2023 |
skrll | Free memory on failure
|
| 1.2 | 02-Sep-2023 |
skrll | Be clear about hart vs cpu. NFCI.
|
| 1.1 | 07-May-2023 |
skrll | RISC-V support that works on QEMU with a single hart.
Thanks for Simon Burge for plic(4).
|
| 1.8 | 11-Aug-2024 |
skrll | plic: Match thead,c900-plic
|
| 1.7 | 04-Aug-2024 |
skrll | spaces to tabs
|
| 1.6 | 24-Mar-2024 |
skrll | branches: 1.6.2;
Pretty print plic attachment
|
| 1.5 | 09-Feb-2024 |
andvar | s/incompatiable/incompatible/ in error messages.
|
| 1.4 | 01-Jan-2024 |
skrll | Perform more checks before establishing external interrupt handlers for
each hart. The VisionFive2 DTS list the S7 core with status = "disabled".
|
| 1.3 | 02-Sep-2023 |
skrll | Be clear about hart vs cpu. NFCI.
|
| 1.2 | 02-Sep-2023 |
skrll | Simplify plic_fdt_intr_disestablish by calling plic_intr_disestablish
|
| 1.1 | 07-May-2023 |
skrll | RISC-V support that works on QEMU with a single hart.
Thanks for Simon Burge for plic(4).
|
| 1.6.2.1 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.1 | 07-May-2023 |
skrll | RISC-V support that works on QEMU with a single hart.
Thanks for Simon Burge for plic(4).
|
| 1.2 | 02-Sep-2023 |
skrll | Be clear about hart vs cpu. NFCI.
|
| 1.1 | 07-May-2023 |
skrll | RISC-V support that works on QEMU with a single hart.
Thanks for Simon Burge for plic(4).
|
