Pretty print plic attachment

Deliver plic interrupts to the cpu^Whart establishing the interrupt
handler. At least this is known to be a valid hart, but it might share
some interrupts around too.

Free memory on failure

Be clear about hart vs cpu. NFCI.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

plic: Match thead,c900-plic

spaces to tabs

branches: 1.6.2;
Pretty print plic attachment

s/incompatiable/incompatible/ in error messages.

Perform more checks before establishing external interrupt handlers for
each hart. The VisionFive2 DTS list the S7 core with status = "disabled".

Be clear about hart vs cpu. NFCI.

Simplify plic_fdt_intr_disestablish by calling plic_intr_disestablish

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Be clear about hart vs cpu. NFCI.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).