Remove debug printfs

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Perform more checks before establishing external interrupt handlers for
each hart. The VisionFive2 DTS list the S7 core with status = "disabled".

Fix and enable MULTIPROCESSOR

risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Call / define fdtbus_cpus_md_attach for platforms with cpus @ fdt.

The RISC-V binding here seems somewhat of an abuse, but it exists in
mainline linux.

G/C file was renamed in recent commit.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.

Refactor the "platform" defitions into fdt_platform.h

branches: 1.4.2;
risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.

branches: 1.3.6;
sort

Call / define fdtbus_cpus_md_attach for platforms with cpus @ fdt.

The RISC-V binding here seems somewhat of an abuse, but it exists in
mainline linux.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

risc-v: show cpu number in intc_fdt_intrstr and not hartid.

implementationm -> implementation

branches: 1.6.2;
Make this compile without MULTIPROCESSOR

Remove an empty line

spaces -> tab

Count interrupts across harts and their local interrupt controllers
correctly.

risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

branches: 1.1.4;
risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.

branches: 1.1.4;
risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.

Perform more checks before establishing external interrupt handlers for
each hart. The VisionFive2 DTS list the S7 core with status = "disabled".

risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.

Re-factor the console-related code into fdt_console.[ch]

Refactor the "platform" defitions into fdt_platform.h

risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).