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History log of /src/sys/arch/riscv/fdt/cpu_fdt.c
RevisionDateAuthorComments
 1.4  01-Jan-2024  skrll Perform more checks before establishing external interrupt handlers for
each hart. The VisionFive2 DTS list the S7 core with status = "disabled".
 1.3  03-Sep-2023  skrll Fix and enable MULTIPROCESSOR
 1.2  12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.1  07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

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