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History log of /src/sys/arch/riscv/include
RevisionDateAuthorComments
 1.6 30-Nov-2024  christos Create a new header lwp_private.h to contain _lwp_getprivate_fast,
_lwp_gettcb_fast, _lwp_settcb and remove them from mcontext.h, so that:
1. we don't need special hacks to hide them
2. we can include <lwp.h> where needed to get the necessary prototypes
without redefining them locally.
 1.5 04-Nov-2024  christos Undo previous lwp.h change.
 1.4 03-Nov-2024  christos Split __lwp_getprivate_fast and __lwp_*tcb from mcontext.h into a separate
lwp.h file.
 1.3 12-Oct-2024  skrll Install pte.h for libkvm
 1.2 12-Jul-2018  maxv branches: 1.2.36;
Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.20; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.20.1 28-Jul-2018  pgoyette Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file Makefile was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2.36.1 02-Aug-2025  perseant Sync with HEAD
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file ansi.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file aout_machdep.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.11 06-Jan-2025  martin PR 58960: fix misunderstanding in semantic and provide both the original
id string as well as _NETBSD_REVISIONID.
Do not rely on string concatenation in the inline assembler, use .ascii
and .asciz for individual string parts instead.
 1.10 05-Jan-2025  martin fix copy&pasto in previous
 1.9 04-Jan-2025  skrll PR 58960: riscv/asm.h: Respect NETBSD_REVISIONID.
 1.8 04-Aug-2024  skrll spaces to tabs
 1.7 07-May-2023  skrll branches: 1.7.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.6 01-May-2021  skrll Provide __CONCAT, __STRING and ___CONCAT
 1.5 17-Apr-2020  joerg branches: 1.5.6;
Mark the .ident section as mergable string section to avoid redundant
entries.
 1.4 14-Mar-2020  skrll branches: 1.4.2;
Trailing whitespace
 1.3 13-Apr-2019  maya Handle changes since the gcc riscv toolchain was upstreamed
 1.2 27-Mar-2015  matt branches: 1.2.16; 1.2.20;
Switch to new ABI (return values now in a0/a1; v0/v1 are no more)
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.2.20.3 21-Apr-2020  martin Sync with HEAD
 1.2.20.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.2.20.1 10-Jun-2019  christos Sync with HEAD
 1.2.16.2 03-Dec-2017  jdolecek update from HEAD
 1.2.16.1 27-Mar-2015  jdolecek file asm.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.4.2.1 20-Apr-2020  bouyer Sync with HEAD
 1.5.6.1 13-May-2021  thorpej Sync with HEAD.
 1.7.6.1 02-Aug-2025  perseant Sync with HEAD
 1.2 04-Aug-2024  skrll spaces to tabs
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.58;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.58.1 02-Aug-2025  perseant Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file bswap.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.3 11-Sep-2022  skrll Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.
 1.2 23-Sep-2019  skrll Provide PRIxBUSADDR, PRIxBUSSIZE, PRIuBUSSIZE, and PRIxBSH for all arches
to follow arm and (generic) mips.

Reviewed by christos.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file bus.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.4 04-Aug-2024  skrll spaces to tabs
 1.3 07-May-2023  skrll branches: 1.3.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2 19-Nov-2022  skrll Fix some types
 1.1 11-Sep-2022  skrll Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.
 1.3.6.1 02-Aug-2025  perseant Sync with HEAD
 1.4 02-Feb-2025  skrll Whitespace
 1.3 07-May-2023  skrll branches: 1.3.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2 19-Nov-2022  skrll Fix some types
 1.1 11-Sep-2022  skrll Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.
 1.3.6.1 02-Aug-2025  perseant Sync with HEAD
 1.5 04-Apr-2020  christos silence lint.
 1.4 15-Apr-2019  maya Avoid -Wconversion warnings
 1.3 28-Oct-2014  dennis branches: 1.3.18; 1.3.22;
Shave an instruction from the generated code for the 32 bit byte
swap inline. Prune 5 or 9 instructions (depending on what you count)
from the 64 bit byte swap inline.
 1.2 28-Oct-2014  dennis Correct 32 and 64 bit byte swap inlines.
 1.1 19-Sep-2014  matt New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.3.22.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.3.22.1 10-Jun-2019  christos Sync with HEAD
 1.3.18.2 03-Dec-2017  jdolecek update from HEAD
 1.3.18.1 28-Oct-2014  jdolecek file byte_swap.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file cdefs.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.16 04-Aug-2024  skrll spaces to tabs
 1.15 25-Dec-2023  skrll branches: 1.15.2;
Count interrupts across harts and their local interrupt controllers
correctly.
 1.14 03-Sep-2023  skrll Fix and enable MULTIPROCESSOR
 1.13 29-Jul-2023  skrll Slight reformatting. NFCI.
 1.12 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.11 25-May-2023  skrll Fix CLKF_INTR so that not all time is shown as being spent in interrupts.
 1.10 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.9 17-Nov-2022  simonb Use better types and struct member names in the clockframe.
Avoid a magic number in CLKF_USERMODE().
 1.8 14-Aug-2021  ryo Improved the performance of kernel profiling on MULTIPROCESSOR, and possible to get profiling data for each CPU.

In the current implementation, locks are acquired at the entrance of the mcount
internal function, so the higher the number of cores, the more lock conflict
occurs, making profiling performance in a MULTIPROCESSOR environment unusable
and slow. Profiling buffers has been changed to be reserved for each CPU,
improving profiling performance in MP by several to several dozen times.

- Eliminated cpu_simple_lock in mcount internal function, using per-CPU buffers.
- Add ci_gmon member to struct cpu_info of each MP arch.
- Add kern.profiling.percpu node in sysctl tree.
- Add new -c <cpuid> option to kgmon(8) to specify the cpuid, like openbsd.
For compatibility, if the -c option is not specified, the entire system can be
operated as before, and the -p option will get the total profiling data for
all CPUs.
 1.7 01-Dec-2019  ad Fix false sharing problems with cpu_info. Identified with tprof(8).
This was a very nice win in my tests on a 48 CPU box.

- Reorganise cpu_data slightly according to usage.
- Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc).
- On x86, put some items in their own cache lines according to usage, like
the IPI bitmask and ci_want_resched.
 1.6 21-Nov-2019  ad mi_userret(): take care of calling preempt(), set spc_curpriority directly,
and remove MD code that does the same.
 1.5 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.4 01-Apr-2015  matt branches: 1.4.16; 1.4.20;
_KMEMUSER only needs struct cpu_info
 1.3 31-Mar-2015  matt Define curcpu() as lwp_getcpu(curlwp) since curlwp is always in the "tp"
(thread pointer) register.
 1.2 28-Mar-2015  matt Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.4.20.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.4.20.1 10-Jun-2019  christos Sync with HEAD
 1.4.16.2 03-Dec-2017  jdolecek update from HEAD
 1.4.16.1 01-Apr-2015  jdolecek file cpu.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.15.2.1 02-Aug-2025  perseant Sync with HEAD
 1.3 15-Oct-2022  simonb Use __volatile so the compiler doesn't optimise out successive calls
to cpu_counter().
Add a 64-bit cycle counter on _LP64.
 1.2 15-Oct-2022  simonb #define<tab>
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file cpu_counter.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.13 25-Nov-2024  skrll risc-v: support crash(8)
 1.12 23-Nov-2024  skrll risc-v: don't include locore.h in db_machdep.h
 1.11 22-Nov-2024  skrll G/C
 1.10 19-Nov-2024  skrll Whitespace
 1.9 02-Sep-2023  skrll branches: 1.9.6;
Fix a comment and enable RISC-V ddb mach commands
 1.8 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.7 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.6 27-Sep-2022  skrll Basic ddb and backtrace support.

[ 1.0000000] panic: kernel diagnostic assertion "msgbufaddr != 0" failed: file "/home/nick/netbsd/nbcvs/src/sys/arch/riscv/riscv/riscv_machdep.c", line 564
[ 1.0000000] cpu0: Begin traceback...
[ 1.0000000] trace fp ffffffc000801dd0
[ 1.0000000] fp ffffffc000801e10 ?() at ffffffc0001eee98
[ 1.0000000] fp ffffffc000801e30 ?() at ffffffc0002ad984
[ 1.0000000] fp ffffffc000801ee0 ?() at ffffffc000005430
[ 1.0000000] cpu0: End traceback...
[ 1.0000000] Trapframe @ 0xffffffc000801cb0 (cause=3 (breakpoint), status=0x100, pc=0xffffffc0000007e4, va=0):
[ 1.0000000] ra =0xffffffc0001eee9c, sp =0xffffffc000801dd0, gp =0xffffffc0006a8f40, tp = 0
[ 1.0000000] s0 =0xffffffc000600ac0, s1 = 0x1000, s2 =0xffffffc000438df0, s3 =0xffffffc000801d80
[ 1.0000000] s4 =0xffffffc0001eed78, s5 =0xffffffc0006d55f8, s6 =0xffffffc000801d88, s7 =0xffffffc0006dfdb8
[ 1.0000000] s8 =0xffffffc000428c18, s9 =0xffffffc000801dd0, s10=0xffffffc0000a3822, s11=0xffffffc0006d55f8
[ 1.0000000] a0 = 0x17, a1 = 0xa, a2 = 0, a3 =0xffffffc00041f658
[ 1.0000000] a4 = 0, a5 = 0x1, a5 = 0, a7 = 0x1
[ 1.0000000] t0 =0xffffffc0006dfe30, t1 =0xffffffc000801bb8, t2 =0xffffffc000803000, t3 = 0x75
[ 1.0000000] t4 = 0, t5 = 0x63, t6 = 0x1
[ 1.0000000] kernel: breakpoint
Stopped in pid 0.0 (system) at ffffffc0000007e4: c.ebreak
db>
 1.5 18-May-2021  skrll Use #define<tab> in this file
 1.4 18-May-2021  skrll Remove argument names from function declaration prototypes.
Misc tidyup.
 1.3 14-Apr-2021  dholland branches: 1.3.2; 1.3.4;
Add a ddb disassembler for riscv.

builds, but not really tested yet.
 1.2 06-Nov-2017  christos branches: 1.2.2; 1.2.20;
Cleanup and clarify the ELFSIZE mess:

We now have 2 variables automatically set in elf_machdep.h:

ARCH_ELFSIZE: the size for userland binaries
KERN_ELFSIZE: the size for the kernel binaries

DB_ELFSIZE has been deleted and KERN_ELFSIZE should have always the
same values DB_ELFSIZE used to have.

In sys/exec_elf.h, if ELFSIZE is not set, it is set to KERN_ELFSIZE
for the kernel and ARCH_ELFSIZE for userland. These defaults should
eliminate the need for most manual ELFSIZE setting.
 1.1 19-Sep-2014  matt New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.2.20.1 17-Apr-2021  thorpej Sync with HEAD.
 1.2.2.2 03-Dec-2017  jdolecek update from HEAD
 1.2.2.1 06-Nov-2017  jdolecek file db_machdep.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.3.4.1 31-May-2021  cjep sync with head
 1.3.2.1 17-Jun-2021  thorpej Sync w/ HEAD.
 1.9.6.1 02-Aug-2025  perseant Sync with HEAD
 1.2 24-May-2022  andvar s/dosen't/doesn't/ in copy pasted comment.
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file disklabel.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.10 04-Aug-2024  skrll spaces to tabs
 1.9 03-Dec-2022  skrll branches: 1.9.8;
Correct some pre-existing relocations and add some new ones.
 1.8 14-Mar-2020  skrll Trailing whitespace
 1.7 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.6 06-Nov-2017  christos branches: 1.6.2; 1.6.6;
Cleanup and clarify the ELFSIZE mess:

We now have 2 variables automatically set in elf_machdep.h:

ARCH_ELFSIZE: the size for userland binaries
KERN_ELFSIZE: the size for the kernel binaries

DB_ELFSIZE has been deleted and KERN_ELFSIZE should have always the
same values DB_ELFSIZE used to have.

In sys/exec_elf.h, if ELFSIZE is not set, it is set to KERN_ELFSIZE
for the kernel and ARCH_ELFSIZE for userland. These defaults should
eliminate the need for most manual ELFSIZE setting.
 1.5 28-May-2015  matt add ELF64_MACHDEP_ID
 1.4 01-Apr-2015  matt Add two new relocs for compressed branches.
 1.3 27-Mar-2015  matt Fix one error and make life for ld.elf_so a little easier.
 1.2 27-Mar-2015  matt Switch to new ABI (return values now in a0/a1; v0/v1 are no more)
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.2 06-Jun-2015  skrll Sync with HEAD
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.6.6.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.6.6.1 10-Jun-2019  christos Sync with HEAD
 1.6.2.2 03-Dec-2017  jdolecek update from HEAD
 1.6.2.1 06-Nov-2017  jdolecek file elf_machdep.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.9.8.1 02-Aug-2025  perseant Sync with HEAD
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file endian.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file endian_machdep.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.5 12-May-2024  riastradh riscv fenv.h: Make sure FE_* exception constants have type int.

This may not be formally required by the standard, but the values
must be representable by int since that's the type that functions
like fetestexcept and feclearexcept traffic in. And this is less
work than changing all the printf %d users in tree.
 1.4 10-May-2024  skrll Use __BIT and fix FE_INEXACT
 1.3 14-Mar-2020  skrll Trailing whitespace
 1.2 22-Mar-2017  chs branches: 1.2.12; 1.2.16;
provide a common softfloat fenv implemenation and use it for softfloat builds.
restore ABI compatibility with previous releases for ieeefp.h on sh3.
add namespace.h protection for all the fenv interfaces.
use MKSOFTFLOAT on sh3 instead of assuming softfloat.
standardize on comparing MKSOFTFLOAT with "no".
remove the arm-specific softfloat fenv code (which also had several bugs).
fix logic errors in the arm hardfloat feraiseexcept() and feupdateenv().
 1.1 19-Sep-2014  matt branches: 1.1.2; 1.1.4; 1.1.6;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.6.1 21-Apr-2017  bouyer Sync with HEAD
 1.1.4.1 26-Apr-2017  pgoyette Sync with HEAD
 1.1.2.1 28-Aug-2017  skrll Sync with HEAD
 1.2.16.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.2.12.2 03-Dec-2017  jdolecek update from HEAD
 1.2.12.1 22-Mar-2017  jdolecek file fenv.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2 30-Oct-2024  riastradh Sprinkle <sys/featuretest.h> where _*_SOURCE macros are consulted.

Otherwise, the feature tests might come out wrong. For example,
header files that check for _NETBSD_SOURCE won't get the default when
no other _*_SOURCE macros are defined; header files that check for
_POSIX_C_SOURCE might miss _XOPEN_SOURCE, which is supposed to imply
a corresponding _POSIX_C_SOURCE.

PR lib/58752: various header files test _*_SOURCE macros but don't
include sys/featuretest.h
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.58;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.58.1 02-Aug-2025  perseant Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file float.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.6 23-Jun-2023  skrll Pad the trapframe so it's a multiple of 16 bytes so that when a trapframe
is created on the stack SP remains 16-byte aligned as per the ABI
requirements.

Patch from Rin with some updates from me.
 1.5 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.4 04-Nov-2020  skrll Fix some of the previous - I must have compile tested the wrong tree
 1.3 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.2 14-Mar-2020  skrll branches: 1.2.4;
Trailing whitespace
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file frame.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2.4.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.2 13-Apr-2019  maya Our current configuration is that long double is 128bit, so reflect
that in the relevant headers.

Taken from sparc64.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file ieee.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2 14-Mar-2020  skrll Trailing whitespace
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file ieeefp.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.5 02-Feb-2024  andvar fix various typos in comments.
 1.4 19-Apr-2021  dholland Make the riscv disassembler work, as best as I can test from amd64 userspace.
 1.3 14-Apr-2021  dholland Add a ddb disassembler for riscv.

builds, but not really tested yet.
 1.2 04-Nov-2020  skrll branches: 1.2.2;
RCSID and whitespace police...
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.34;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.34.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file insn.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2.2.1 17-Apr-2021  thorpej Sync with HEAD.
 1.3 12-Jan-2025  skrll risc-v: Fix UINT32_C.

PR port-riscv/58766 ntpd / ntpdate setting time on risc64 fails to work
 1.2 04-Jul-2023  riastradh branches: 1.2.6;
riscv: Fix (U)INT64_C suffix to match gcc's built-in idea of types.

XXX pullup-10
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file int_const.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2.6.1 02-Aug-2025  perseant Sync with HEAD
 1.4 17-Apr-2019  mrg fix for riscv32.
 1.3 16-Apr-2019  maya We're now using gcc netbsd-stdint.h instead of our own definitions, so
match those with the format types

XXX wrong for 32bit.
XXX unclear if changing the fast types was the right call
 1.2 13-Apr-2019  maya Provide defines for the 64bit case.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file int_fmtio.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file int_limits.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file int_mwgwtypes.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file int_types.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.7 19-Nov-2024  skrll risc-v: expose intr_establish_xname
 1.6 04-Aug-2024  skrll spaces to tabs
 1.5 03-Sep-2023  skrll branches: 1.5.6;
Fix and enable MULTIPROCESSOR
 1.4 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.3 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2 28-Mar-2015  matt branches: 1.2.16;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.2.16.2 03-Dec-2017  jdolecek update from HEAD
 1.2.16.1 28-Mar-2015  jdolecek file intr.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.5.6.1 02-Aug-2025  perseant Sync with HEAD
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file kcore.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file limits.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.1 05-May-2021  jmcneill branches: 1.1.4;
Add loadfile_machdep.h for riscv
 1.1.4.2 13-May-2021  thorpej Sync with HEAD.
 1.1.4.1 05-May-2021  thorpej file loadfile_machdep.h was added on branch thorpej-i2c-spi-conf on 2021-05-13 00:47:27 +0000
 1.4 26-Jun-2015  matt branches: 1.4.16;
Move the riscv lock.h which uses only compiler builtin atomic primitives
to a common location which can be used by others and make riscv's lock.h
use it.
 1.3 26-Jun-2015  matt Fix c&p error.
 1.2 29-Mar-2015  matt Use C11 atomic builtins instead of __asm.
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.2 22-Sep-2015  skrll Sync with HEAD
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.4.16.2 03-Dec-2017  jdolecek update from HEAD
 1.4.16.1 26-Jun-2015  jdolecek file lock.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.14 22-Nov-2024  skrll risc-v: split userret into its own header as per other ports

Helps with crash(8)
 1.13 02-May-2024  skrll branches: 1.13.2;
risc-v: fix the error code when uvm_fault fails with cpu_set_onfault

Return the error from uvm_fault instead of EFAULT unconditionally when
faulting with cpu_set_onfault to fix several atf tests.
 1.12 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.11 20-Sep-2022  skrll Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|

Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3

Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes

Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509
 1.10 05-Oct-2021  jmcneill #define<tab>
 1.9 05-Oct-2021  skrll Fix riscv32 GENERIC build
 1.8 01-May-2021  skrll Sprinkle #ifdef FPE for now
 1.7 04-Nov-2020  skrll branches: 1.7.4;
RCSID and whitespace police...
 1.6 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.5 14-Mar-2020  skrll branches: 1.5.4;
Trailing whitespace
 1.4 11-Apr-2019  kamil Fix a typo in a comment
 1.3 16-Mar-2017  chs branches: 1.3.12; 1.3.16;
allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.
 1.2 28-Mar-2015  matt branches: 1.2.2; 1.2.4;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.2 28-Aug-2017  skrll Sync with HEAD
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.2.4.1 21-Apr-2017  bouyer Sync with HEAD
 1.2.2.1 20-Mar-2017  pgoyette Sync with HEAD
 1.3.16.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.3.16.1 10-Jun-2019  christos Sync with HEAD
 1.3.12.2 03-Dec-2017  jdolecek update from HEAD
 1.3.12.1 16-Mar-2017  jdolecek file locore.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.5.4.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.7.4.1 13-May-2021  thorpej Sync with HEAD.
 1.13.2.1 02-Aug-2025  perseant Sync with HEAD
 1.2 04-Nov-2024  christos Undo previous lwp.h change.
 1.1 03-Nov-2024  christos Split __lwp_getprivate_fast and __lwp_*tcb from mcontext.h into a separate
lwp.h file.
 1.1 30-Nov-2024  christos branches: 1.1.4;
Create a new header lwp_private.h to contain _lwp_getprivate_fast,
_lwp_gettcb_fast, _lwp_settcb and remove them from mcontext.h, so that:
1. we don't need special hacks to hide them
2. we can include <lwp.h> where needed to get the necessary prototypes
without redefining them locally.
 1.1.4.2 02-Aug-2025  perseant Sync with HEAD
 1.1.4.1 30-Nov-2024  perseant file lwp_private.h was added on branch perseant-exfatfs on 2025-08-02 05:56:03 +0000
 1.6 02-Feb-2025  skrll KNF - sort includes.
 1.5 12-Jun-2023  skrll branches: 1.5.6;
risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.4 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.3 16-Oct-2022  skrll Map the DTB using VM_KERNEL_DTB_BASE and CONSADDR using VM_KERNEL_IO_BASE
 1.2 28-Sep-2022  skrll Use legacy SBI Console GetChar for earlycons. It works on qemu.
 1.1 20-Sep-2022  skrll Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|

Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3

Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes

Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509
 1.5.6.1 02-Aug-2025  perseant Sync with HEAD
 1.3 16-Apr-2019  maya RISC-V ELF psABI says ILP32 also defaults to 128bit long double.
 1.2 13-Apr-2019  maya Our current configuration is that long double is 128bit, so reflect
that in the relevant headers.

Taken from sparc64.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file math.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.12 30-Nov-2024  christos Create a new header lwp_private.h to contain _lwp_getprivate_fast,
_lwp_gettcb_fast, _lwp_settcb and remove them from mcontext.h, so that:
1. we don't need special hacks to hide them
2. we can include <lwp.h> where needed to get the necessary prototypes
without redefining them locally.
 1.11 04-Nov-2024  christos Undo previous lwp.h change.
 1.10 03-Nov-2024  christos Split __lwp_getprivate_fast and __lwp_*tcb from mcontext.h into a separate
lwp.h file.
 1.9 31-May-2024  skrll branches: 1.9.2;
Add more ABI register defines - should have been committed with previous
change.
 1.8 04-May-2024  skrll Fix the __greg_t typedef for riscv32
 1.7 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.6 14-Mar-2020  skrll Trailing whitespace
 1.5 15-Feb-2018  kamil branches: 1.5.4;
Introduce _UC_MACHINE_FP() as a macro

_UC_MACHINE_FP() is a helper macro to extract from mcontext a frame pointer.

Don't rely on this interface as a compiler might strip frame pointer or
optimize it making this interface unreliable.


For hppa assume a small frame context, for larger frames FP might be located
in a different register (4 instead of 3).

For ia64 there is no strict frame pointer, and registers might rotate.
Reuse 79 following:

./gcc/config/ia64/ia64.h:#define HARD_FRAME_POINTER_REGNUM LOC_REG (79)

Once ia64 will mature, this should be revisited.

A macro can encapsulate a real function for extracting Frame Pointer on
more complex CPUs / ABIs.


For the remaining CPUs, reuse standard register as defined in appropriate ABI.

The direct users of this macro are LLVM and GCC with Sanitizers.

Proposed on tech-userlevel@.

Sponsored by <The NetBSD Foundation>
 1.4 01-Apr-2015  matt branches: 1.4.10; 1.4.16;
Add _REG_S0
 1.3 27-Mar-2015  matt Switch to new ABI (return values now in a0/a1; v0/v1 are no more)
 1.2 24-Oct-2014  dennis branches: 1.2.2;
Fix a typo: the PC is likely in _REG_PC
 1.1 19-Sep-2014  matt New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.2.2.1 06-Apr-2015  skrll Sync with HEAD
 1.4.16.2 03-Dec-2017  jdolecek update from HEAD
 1.4.16.1 01-Apr-2015  jdolecek file mcontext.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.4.10.3 21-Mar-2018  martin Pull up the following, requested by kamil in ticket #552:

external/gpl3/gcc{.old}/dist/libsanitizer/asan/asan_linux.cc 1.4
sys/arch/aarch64/include/mcontext.h 1.2
sys/arch/alpha/include/mcontext.h 1.9
sys/arch/amd64/include/mcontext.h 1.19
sys/arch/arm/include/mcontext.h 1.19
sys/arch/hppa/include/mcontext.h 1.9
sys/arch/i386/include/mcontext.h 1.14
sys/arch/ia64/include/mcontext.h 1.6
sys/arch/m68k/include/mcontext.h 1.10
sys/arch/mips/include/mcontext.h 1.22
sys/arch/or1k/include/mcontext.h 1.2
sys/arch/powerpc/include/mcontext.h 1.18
sys/arch/riscv/include/mcontext.h 1.5
sys/arch/sh3/include/mcontext.h 1.11
sys/arch/sparc/include/mcontext.h 1.14-1.17
sys/arch/sparc64/include/mcontext.h 1.10
sys/arch/vax/include/mcontext.h 1.9
tests/lib/libc/sys/Makefile 1.50
tests/lib/libc/sys/t_ucontext.c 1.2-1.5
sys/arch/hppa/include/mcontext.h 1.10
sys/arch/ia64/include/mcontext.h 1.7

- Introduce _UC_MACHINE_FP(). _UC_MACHINE_FP() is a helper
macro to extract from mcontext a frame pointer.
- Add new tests in lib/libc/sys/t_ucontext:
* ucontext_sp (testing _UC_MACHINE_SP)
* ucontext_fp (testing _UC_MACHINE_FP)
* ucontext_pc (testing _UC_MACHINE_PC)
* ucontext_intrv (testing _UC_MACHINE_INTRV)

Add a dummy implementation of _UC_MACHINE_INTRV() for ia64.

Implement _UC_MACHINE_INTRV() for hppa.

Make the t_ucontext.c test more portable.

We now have _UC_MACHINE_FP.
 1.4.10.2 26-Feb-2018  snj revert ticket 552, which broke the build
 1.4.10.1 25-Feb-2018  snj Pull up following revision(s) (requested by kamil in ticket #552):
sys/arch/aarch64/include/mcontext.h: 1.2
sys/arch/alpha/include/mcontext.h: 1.9
sys/arch/amd64/include/mcontext.h: 1.19
sys/arch/arm/include/mcontext.h: 1.19
sys/arch/hppa/include/mcontext.h: 1.9
sys/arch/i386/include/mcontext.h: 1.14
sys/arch/ia64/include/mcontext.h: 1.6
sys/arch/m68k/include/mcontext.h: 1.10
sys/arch/mips/include/mcontext.h: 1.22
sys/arch/or1k/include/mcontext.h: 1.2
sys/arch/powerpc/include/mcontext.h: 1.18
sys/arch/riscv/include/mcontext.h: 1.5
sys/arch/sh3/include/mcontext.h: 1.11
sys/arch/sparc/include/mcontext.h: 1.14-1.17
sys/arch/sparc64/include/mcontext.h: 1.10
sys/arch/vax/include/mcontext.h: 1.9
tests/lib/libc/sys/Makefile: 1.50
tests/lib/libc/sys/t_ucontext.c: 1.2
Introduce _UC_MACHINE_FP() as a macro
_UC_MACHINE_FP() is a helper macro to extract from mcontext a frame pointer.
Don't rely on this interface as a compiler might strip frame pointer or
optimize it making this interface unreliable.
For hppa assume a small frame context, for larger frames FP might be located
in a different register (4 instead of 3).
For ia64 there is no strict frame pointer, and registers might rotate.
Reuse 79 following:
./gcc/config/ia64/ia64.h:#define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
Once ia64 will mature, this should be revisited.
A macro can encapsulate a real function for extracting Frame Pointer on
more complex CPUs / ABIs.
For the remaining CPUs, reuse standard register as defined in appropriate ABI.
The direct users of this macro are LLVM and GCC with Sanitizers.
Proposed on tech-userlevel@.
Sponsored by <The NetBSD Foundation>
--
Improve _UC_MACHINE_FP() for SPARC/SPARC64
Introduce a static inline function _uc_machine_fp() that contains improved
caluclation of a frame pointer.
Algorithm:
uptr *stk_ptr;
# if defined (__arch64__)
stk_ptr = (uptr *) (*sp + 2047);
# else
stk_ptr = (uptr *) *sp;
# endif
*bp = stk_ptr[15];
Noted by <mrg>
--
Make _UC_MACHINE_FP() compile again and fix it so that it does not add
the offset twice.
--
fix _UC_MACHINE32_FP() -- use 32 bit pointer value so that [15] is
the right offset. do this by using __greg32_t, which is only in
the sparc64 version, and these are only useful there, so move them.
--
Add new tests in lib/libc/sys/t_ucontext
New tests:
- ucontext_sp
- ucontext_fp
- ucontext_pc
- ucontext_intrv
They test respectively:
- _UC_MACHINE_SP
- _UC_MACHINE_FP
- _UC_MACHINE_PC
- _UC_MACHINE_INTRV
These tests attempt to access and print the values from ucontext, without
interpreting the values.
This is a follow up of the _UC_MACHINE_FP() introduction.
These tests use PRIxREGISTER, and require to be built with -D_KERNTYPES.
Sponsored by <The NetBSD Foundation>
 1.5.4.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.9.2.1 02-Aug-2025  perseant Sync with HEAD
 1.7 25-Nov-2024  skrll risc-v: support crash(8)
 1.6 12-Jul-2023  riastradh branches: 1.6.6;
machine/mutex.h: Sprinkle sys/types.h, omit machine/lock.h.

Turns out machine/lock.h is not needed for __cpu_simple_lock_t, which
always comes from sys/types.h. And, really, sys/types.h (or at least
sys/stdint.h) is needed for uintN_t and uintptr_t.
 1.5 09-Jul-2023  riastradh machine/mutex.h: Sprinkle includes so this can be used by crash(8).

XXX pullup-10
 1.4 25-Aug-2021  thorpej branches: 1.4.4;
- In kern_mutex.c, if MUTEX_CAS() is not defined, define it in terms of
atomic_cas_ulong().
- For arm, ia64, m68k, mips, or1k, riscv, vax: don't define our own
MUTEX_CAS(), as they either use atomic_cas_ulong() or equivalent
(atomic_cas_uint() on m68k).
- For alpha and sparc64, don't define MUTEX_CAS() in terms of their own
_lock_cas(), which has its own memory barriers; the call sites in
kern_mutex.c already have the appropriate memory barrier calls. Thus,
alpha and sparc64 can use default definition.
- For sh3, don't define MUTEX_CAS() in terms of its own _lock_cas();
atomic_cas_ulong() is strong-aliased to _lock_cas(), therefore defining
our own MUTEX_CAS() is redundant.

Per thread:
https://mail-index.netbsd.org/tech-kern/2021/07/25/msg027562.html
 1.3 29-Nov-2019  riastradh Nix now-unused definitions of MUTEX_GIVE/MUTEX_RECEIVE.
 1.2 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file mutex.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.4.4.1 09-Aug-2023  martin Pull up following revision(s) (requested by maya in ticket #316):

sys/arch/m68k/include/mutex.h: revision 1.13
sys/arch/arm/include/cpu.h: revision 1.125
sys/arch/sun68k/include/intr.h: revision 1.21
sys/arch/arm/include/mutex.h: revision 1.28
sys/sys/rwlock.h: revision 1.18
sys/arch/powerpc/include/mutex.h: revision 1.7
sys/arch/arm/include/mutex.h: revision 1.29
sys/arch/powerpc/include/mutex.h: revision 1.8
sys/uvm/uvm_param.h: revision 1.42
sys/sys/ksem.h: revision 1.16
sys/arch/x86/include/mutex.h: revision 1.10
sys/sys/proc.h: revision 1.372
sys/sys/ksem.h: revision 1.17
sys/arch/ia64/include/mutex.h: revision 1.8
sys/arch/evbarm/include/intr.h: revision 1.29
sys/sys/lua.h: revision 1.9
sys/arch/next68k/include/intr.h: revision 1.23
sys/arch/ia64/include/mutex.h: revision 1.9
sys/arch/hp300/include/intr.h: revision 1.35
sys/arch/hp300/include/intr.h: revision 1.36
sys/arch/sparc/include/cpu.h: revision 1.111
sys/arch/hppa/include/mutex.h: revision 1.16
sys/arch/vax/include/intr.h: revision 1.31
sys/arch/hppa/include/mutex.h: revision 1.17
sys/arch/news68k/include/intr.h: revision 1.28
sys/arch/hppa/include/mutex.h: revision 1.18
sys/arch/hppa/include/intr.h: revision 1.3
sys/arch/hppa/include/mutex.h: revision 1.19
sys/arch/hppa/include/intr.h: revision 1.4
sys/sys/sched.h: revision 1.92
sys/opencrypto/cryptodev.h: revision 1.51
sys/arch/vax/include/mutex.h: revision 1.20
sys/arch/sparc64/include/mutex.h: revision 1.10
sys/arch/ia64/include/sapicvar.h: revision 1.2
sys/arch/riscv/include/mutex.h: revision 1.5
sys/arch/amiga/dev/grfabs_cc.c: revision 1.39
sys/external/bsd/drm2/include/linux/idr.h: revision 1.11
sys/arch/riscv/include/mutex.h: revision 1.6
sys/ddb/files.ddb: revision 1.16
sys/arch/mac68k/include/intr.h: revision 1.32
share/man/man4/ddb.4: revision 1.203
sys/ddb/db_command.c: revision 1.183
sys/arch/mips/include/mutex.h: revision 1.10
sys/ddb/db_command.c: revision 1.184
sys/arch/x68k/include/intr.h: revision 1.22
sys/arch/sparc/include/psl.h: revision 1.51
sys/arch/or1k/include/mutex.h: revision 1.4
sys/arch/mips/include/mutex.h: revision 1.11
sys/arch/arm/xscale/pxa2x0_intr.h: revision 1.16
sys/arch/sparc64/include/cpu.h: revision 1.134
sys/arch/sparc/include/psl.h: revision 1.52
sys/arch/or1k/include/mutex.h: revision 1.5
sys/arch/mvme68k/include/intr.h: revision 1.22
sys/arch/luna68k/include/intr.h: revision 1.16
external/cddl/osnet/sys/sys/kcondvar.h: revision 1.6
sys/arch/sparc/include/mutex.h: revision 1.12
sys/arch/sparc/include/mutex.h: revision 1.13
sys/arch/usermode/include/mutex.h: revision 1.5
sys/arch/usermode/include/mutex.h: revision 1.6
sys/kern/kern_core.c: revision 1.38
usr.sbin/crash/Makefile: revision 1.49
sys/arch/amiga/include/intr.h: revision 1.23
sys/arch/alpha/include/mutex.h: revision 1.12
sys/arch/alpha/include/mutex.h: revision 1.13
sys/arch/evbarm/lubbock/sacc_obio.c: revision 1.16
sys/ddb/ddb.h: revision 1.6
sys/arch/sparc64/include/mutex.h: revision 1.8
sys/arch/sh3/include/mutex.h: revision 1.12
sys/arch/evbarm/lubbock/sacc_obio.c: revision 1.17
sys/ddb/db_syncobj.c: revision 1.1
sys/arch/vax/include/mutex.h: revision 1.18
sys/arch/sparc64/include/psl.h: revision 1.63
sys/arch/sparc64/include/mutex.h: revision 1.9
sys/arch/sh3/include/mutex.h: revision 1.13
sys/arch/evbarm/lubbock/obio.c: revision 1.13
sys/arch/atari/include/intr.h: revision 1.23
sys/ddb/db_syncobj.c: revision 1.2
sys/arch/vax/include/mutex.h: revision 1.19
sys/arch/evbarm/g42xxeb/obio.c: revision 1.14
sys/arch/evbarm/g42xxeb/obio.c: revision 1.15
sys/arch/cesfic/include/intr.h: revision 1.14
sys/ddb/db_syncobj.h: revision 1.1
sys/arch/x86/include/cpu.h: revision 1.134
sys/arch/evbarm/g42xxeb/obio.c: revision 1.16
sys/arch/cesfic/include/intr.h: revision 1.15
sys/arch/arm/xscale/pxa2x0_intr.c: revision 1.26
sys/sys/cpu_data.h: revision 1.54
sys/arch/m68k/include/mutex.h: revision 1.12
sys/arch/ia64/acpi/madt.c: revision 1.6

sys/rwlock.h: Make this more self-contained for bool.

machine/mutex.h: Sprinkle includes so this can be used by crash(8).

ddb: New `show all tstiles' command.
Shows who's waiting for which locks and what the owner is up to.

Include psl.h for ipl_cookie_t if __MUTEX_PRIVATE

sys: Rip <sys/resourcevar.h> out of <uvm/uvm_param.h>.

And thus out of <sys/param.h>, which is exceedingly overused and
fragile and delenda est.

Should fix (some) issues with the recent inclusion of machine/lock.h
in various machine/mutex.h files.

arm/mutex.h: Need machine/intr.h, machine/lock.h.

For ipl_cookie_t and __cpu_simple_lock_t.
evbarm/intr.h: Define ipl_cookie_t before including ARM_INTR_IMPL.

Otherwise arm/mutex.h doesn't work, due to a cyclic dependency which
should really be fixed.
opencrypto/cryptodev.h: Fix includes.
- Move sys/condvar.h under #ifdef _KERNEL.
- Add some other necessary includes and forward declarations.
- Sort.

hp300/intr.h: Fix missing includes.
linux/idr.h: Need <sys/mutex.h> for kmutex_t.
amiga/intr.h: Don't define spl*() functions if !_KERNEL.

This is used by crash(8) now, and what's important is ipl_cookie_t.
cesfic/intr.h: Expose ipl_cookie_t to userland for crash(8).
cesfic/intr.h: Expose ipl_cookie_t to userland only with _KMEMUSER.

Probably not necessary but let's be a little more cautious about
this.

atari/intr.h: Expose ipl_cookie_t with _KMEMUSER for crash(8).

arm/cpu.h: Need sys/param.h for COHERENCY_UNIT.

Nix machine/param.h -- not meant to be used directly, pulled in by
sys/param.h.

Move the definition of ipl_cookie_t out of the kernel-only sections,
some _KMEMUSER applications need it.

ddb: Cast pointer to uintptr_t first before db_expr_t.

hppa/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

luna68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

mvme68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

news68k/intr.h: Fix includes. Put some definitions under _KERNEL.

next68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

sys/ksem.h: Hack around fstat(8) abuse of _KERNEL.

sun68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

vax/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

x68k/intr.h: Put functions under _KERNEL so crash(8) can use this.

Make ipl_cookie_t visible for _KMEMUSER userland applications.

fix editor mishap in previous

Explicitly include <sys/mutex.h> for kmutex_t.

Replace kmutex_t * (which may be undefined here) with struct kmutex *,
suggested by Taylor.

hp300/intr.h: Put most of this under #ifdef _KERNEL.
Only ipl_cookie_t really needs to be exposed now, for crash(8).

mac68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).
Make inclusion of sys/intr.h explicit for spl*.

fix hppa and vax builds.

machine/lock.h isn't necessary for __cpu_simple_lock_t, it's in
sys/types.h. avoids cpu_data.h vs sched.h include order issues.

move the hppa ipl_t typedef with the moved usage of it.
machine/mutex.h: Sprinkle sys/types.h, omit machine/lock.h.

Turns out machine/lock.h is not needed for __cpu_simple_lock_t, which
always comes from sys/types.h. And, really, sys/types.h (or at least
sys/stdint.h) is needed for uintN_t and uintptr_t.

ddb: Cast pointer to uintptr_t, then to db_expr_t.
Avoids warnings about conversion between pointer and integer of
different size on some architectures.

re-fix hppa builds.

this file uses __cpu_simple_lock(), not just the underlying type,
so it does need machine/lock.h.

Break cycle by using `struct kmutex *' instead of `kmutex_t *'.
sys/sched.h included sys/mutex.h
which includes sys/intr.h
which includes machine/intr.h
which on cats includes arm/footbridge/footbridge_intr.h
which includes arm/cpu.h
which includes sys/cpu_data.h
which includes sys/sched.h

But there was never any real need for sys/mutex.h in sys/sched.h,
because it only uses pointers to the opaque struct kmutex. Cycle
broken by using `struct kmutex *' instead of pulling in sys/mutex.h
for the definition of kmutex_t.

Side effect: This revealed that sys/cpu_data.h needed sys/intr.h
(which was pulled in accidentally by sys/mutex.h via sys/sched.h) for
SOFTINT_COUNT. Also revealed some other machine/cpu.h header files
were missing includes of sys/mutex.h for kmutex_t.

ia64: Need sys/types.h for u_int, vaddr_t; sys/mutex.h for kmutex_t.

explicitly include no longer implicitly included sys/mutex.h.

arm/xscale: Use sys/bitops.h fls32 - 1 instead of 31 - __builtin_clz.
Sidesteps namespace collision with `#define bits ...' in net/zlib.c.

complete the previous - there were two calls to find_first_bit() to fix.

arm/xscale: Missed a spot with previous find_first_bit commit.

evbarm/g42xxeb: Fix off-by-one in previous.

The original find_first_bit(x) was 31 - __builtin_clz((uint32_t)x),
which is equivalent to fls32(x) - 1, not to fls32(x).

Note that fls32 is 1-based and returns 0 for x=0.
 1.6.6.1 02-Aug-2025  perseant Sync with HEAD
 1.2 28-May-2024  skrll Change MIPS to RISC-V.
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file netbsd32_machdep.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.8 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.7 12-Oct-2022  simonb NKMEMPAGES_MIN_DEFAULT is in pages not bytes (hint is in the name).
Also set NKMEMPAGES_MAX_UNLIMITED while we're here.
 1.6 19-Jul-2021  christos Remove definitions for CACHE_LINE_SIZE and COHERENCY_UNIT which are the same
as the default.
 1.5 31-May-2021  simonb Include "opt_param.h" (ifdef _KERNEL_OPT) everywhere that MSGBUFSIZE is
referenced since some sources include <machine/param.h>.
 1.4 01-May-2021  skrll Bump MSGBUFSIZE (if not defined)

Provide COHERENCY_UNIT and CACHE_LINE_SIZE

Also provide MAXCPUS
 1.3 01-Jun-2019  maxv branches: 1.3.14;
Misc changes in RISC-V. Start changing the memory layout, too.
 1.2 07-Jan-2019  jdolecek move DEV_BSIZE, DEV_BSHIFT out of MD param.h, they are same on all ports

also move BLKDEV_IOSIZE, MAXPHYS, but allow override since some ports
have different value (powerpc uses NBPG for BLKDEV_IOSIZE, sun2/sun3
have lower MAXPHYS)
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.20; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.20.1 18-Jan-2019  pgoyette Synch with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file param.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.3.14.3 01-Aug-2021  thorpej Sync with HEAD.
 1.3.14.2 17-Jun-2021  thorpej Sync w/ HEAD.
 1.3.14.1 13-May-2021  thorpej Sync with HEAD.
 1.3 04-Aug-2024  skrll spaces to tabs
 1.2 07-May-2023  skrll branches: 1.2.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file pcb.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2.6.1 02-Aug-2025  perseant Sync with HEAD
 1.1 01-Jan-2025  skrll branches: 1.1.4;
risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.
 1.1.4.2 02-Aug-2025  perseant Sync with HEAD
 1.1.4.1 01-Jan-2025  perseant file pci_machdep.h was added on branch perseant-exfatfs on 2025-08-02 05:56:03 +0000
 1.25 12-Oct-2025  thorpej Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/
 1.24 04-Aug-2024  skrll branches: 1.24.2;
spaces to tabs
 1.23 01-Jan-2024  skrll branches: 1.23.2;
risc-v: probe the number of supported ASIDs

Flush the entire TLB if no ASIDs are supported on pmap_activate.
 1.22 06-Oct-2023  skrll Not all RISC-V CPUs have ASIDs
 1.21 03-Sep-2023  skrll Fix and enable MULTIPROCESSOR
 1.20 12-Aug-2023  skrll risc-v: Use 'onproc' for 2nd arg of pmap_md_page_syncicache

Match other definitions of pmap_md_page_syncicache argument naming by
renaming the 2nd arg to 'onproc'
 1.19 26-Jul-2023  skrll G/C pmap_md_kernel_*
 1.18 12-Jun-2023  skrll risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
 1.17 08-May-2023  skrll Remove some #if 0'ed code
 1.16 08-May-2023  skrll KNF
 1.15 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.14 23-Dec-2022  skrll Fix RV builds
 1.13 20-Oct-2022  skrll Add the "memory" clobber in two places that it's needed.
 1.12 18-Oct-2022  skrll Correct XSEGSHIFT for RV32 case
 1.11 15-Oct-2022  simonb #define<tab>
 1.10 20-Sep-2022  skrll Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|

Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3

Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes

Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509
 1.9 01-May-2021  skrll Fixup some pmap / VM related #defines and code
 1.8 20-Dec-2020  skrll branches: 1.8.4;
Support __HAVE_PMAP_PV_TRACK in sys/uvm/pmap based pmaps (aka common pmap)
 1.7 15-Nov-2020  skrll This file is #define<space>
 1.6 10-Aug-2020  skrll branches: 1.6.2;
Whitespace
 1.5 07-Aug-2020  skrll Provide a pmap_segtab_deactivate for symmetry with pmap_segtab_activate
and use it in pmap_deactivate

Call pmap_md_xtab_{,de}activate from pmap_segtab_{,de}activate to be used
for PMAP_HWPAGEWALKER and any caches ops that might be required.

Provide empty (for now) pmap_md_xtab_{,de}activate functions on the
platforms that use sys/uvm/pmap
 1.4 11-Mar-2020  thorpej With DEBUG defined, it's possible to execute a TLB-vs-segmap consistency
check from a (soft) interrupt handler. But if a platform does not otherwise
require the pmap_tlb_miss_lock, then where will be a brief window of
inconsistency that, while harmless, will still fire an assertion in the
consistency check.

Fix this with the following changes:
1- Refactor the pmap_tlb_miss_lock into MI code and rename it from
pmap_tlb_miss_lock_{enter,exit}() to pmap_tlb_miss_lock_{enter,exit}().
MD code can still define the "md" hooks as necessary, and if so, will
override the common implementation.
2- Provde a pmap_bootstrap_common() function to perform common pmap bootstrap
operations, namely initializing the pmap_tlb_miss_lock if it's needed.
If MD code overrides the implementation, it's responsible for initializing
its own lock.
3- Call pmap_bootstrap_common() from the mips, powerpc booke, and riscv
pmap_bootstrap() routines. (This required adding one for riscv.)
4- Switch powerpc booke to the common pmap_tlb_miss_lock.
5- Enable pmap_tlb_miss_lock if DEBUG is defined, even if it's not otherwise
required.

PR port-mips/55062 (Failed assertion in pmap_md_tlb_check_entry())
 1.3 16-Jun-2019  maxv Misc changes in RISC-V.
 1.2 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.3 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.1.22.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file pmap.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.6.2.2 03-Jan-2021  thorpej Sync w/ HEAD.
 1.6.2.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.8.4.1 13-May-2021  thorpej Sync with HEAD.
 1.23.2.1 02-Aug-2025  perseant Sync with HEAD
 1.24.2.1 26-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #67):

sys/arch/riscv/include/sysreg.h: revision 1.34
sys/arch/riscv/include/pte.h: revision 1.15
sys/arch/riscv/include/pte.h: revision 1.16
sys/arch/riscv/riscv/genassym.cf: revision 1.17
sys/arch/riscv/riscv/locore.S: revision 1.47
sys/arch/riscv/riscv/bus_space.c: revision 1.3
sys/arch/riscv/include/pmap.h: revision 1.25
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.22
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.23
sys/arch/riscv/riscv/cpu.c: revision 1.10
sys/arch/riscv/riscv/riscv_machdep.c: revision 1.46

Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.

Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/


Fix RV32 build. Svpbmt and Memory Attribute Extension (XTheadMae) are
SV39 and above only.
 1.2 12-Jul-2018  maxv Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.20; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.20.1 28-Jul-2018  pgoyette Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file pmc.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.6 04-Aug-2024  skrll spaces to tabs
 1.5 08-May-2023  skrll branches: 1.5.6;
Don't expose vaddr_t or register_t to userland. The gdb configure script
needs this so it can detect struct lwp correctly.
 1.4 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.3 31-Mar-2015  matt branches: 1.3.16;
Optimize the exception handle a little bit more.
 1.2 31-Mar-2015  matt Add a md_tp member to mdlwp so that the exception handler can temporarily
store the user's thread pointer before saving it in the trapframe.
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.3.16.2 03-Dec-2017  jdolecek update from HEAD
 1.3.16.1 31-Mar-2015  jdolecek file proc.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.5.6.1 02-Aug-2025  perseant Sync with HEAD
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file profile.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.17 13-Oct-2025  skrll risc-v: pte_make_enter set PTE_D when page is known to be modified.

PR/59696: pte_make_enter() appears to have bug vis a vis already-modified managed pages
 1.16 12-Oct-2025  skrll Fix RV32 build. Svpbmt and Memory Attribute Extension (XTheadMae) are
SV39 and above only.
 1.15 12-Oct-2025  thorpej Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/
 1.14 12-Oct-2024  skrll branches: 1.14.2;
Install pte.h for libkvm
 1.13 07-May-2023  skrll branches: 1.13.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.12 22-Apr-2023  skrll G/C pte_index
 1.11 12-Nov-2022  skrll Note some SV39 PTE bits defined in extensions.

Fix pte_nv_entry for the kernel.

Fix pte_pde_ptpage. PTE.{X,W,R} must be zero for pointer to next level.
 1.10 18-Oct-2022  skrll Some fixes from Simon.
 1.9 15-Oct-2022  simonb #define<tab>
 1.8 30-Sep-2022  skrll Don't set A, D in page table pointers, but do set them in leaf entries.

Beagle-v now boots to the msgbufaddr panic same as qemu
 1.7 21-Sep-2022  skrll Use c99 types. NFC.
 1.6 01-May-2021  skrll Fixup some pmap / VM related #defines and code
 1.5 01-Nov-2020  skrll branches: 1.5.4;
Comments from zmcgrew@
 1.4 14-Mar-2020  skrll branches: 1.4.4;
Trailing whitespace
 1.3 16-Jun-2019  maxv Misc changes in RISC-V.
 1.2 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.3 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.1.22.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.22.1 10-Jun-2019  christos Sync with HEAD
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file pte.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.4.4.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.5.4.1 13-May-2021  thorpej Sync with HEAD.
 1.13.6.1 02-Aug-2025  perseant Sync with HEAD
 1.14.2.2 26-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #68):

sys/arch/riscv/include/pte.h: revision 1.17

risc-v: pte_make_enter set PTE_D when page is known to be modified.

PR/59696: pte_make_enter() appears to have bug vis a vis=20
already-modified managed pages
 1.14.2.1 26-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #67):

sys/arch/riscv/include/sysreg.h: revision 1.34
sys/arch/riscv/include/pte.h: revision 1.15
sys/arch/riscv/include/pte.h: revision 1.16
sys/arch/riscv/riscv/genassym.cf: revision 1.17
sys/arch/riscv/riscv/locore.S: revision 1.47
sys/arch/riscv/riscv/bus_space.c: revision 1.3
sys/arch/riscv/include/pmap.h: revision 1.25
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.22
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.23
sys/arch/riscv/riscv/cpu.c: revision 1.10
sys/arch/riscv/riscv/riscv_machdep.c: revision 1.46

Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.

Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/


Fix RV32 build. Svpbmt and Memory Attribute Extension (XTheadMae) are
SV39 and above only.
 1.6 03-May-2024  skrll Use the _X_FOO register macros instead of magic numbers.
 1.5 14-Sep-2023  rin riscv: ptrace: Add PTRACE_ILLEGAL_ASM for ATF

All related tests successfully pass.
 1.4 24-Aug-2023  rin riscv: Add PTRACE_BREAKPOINT and friends for ATF

Since its size must be determined a priori, explicitly use
c.ebreak for sure.

Now, related tests in ATF successfully pass for riscv64,
as far as I can see.
 1.3 18-Jun-2019  kamil Introduce PTRACE_REG_FP() a helper macro to retrieve the frame pointer

The macro is dummy for ia64 (the FP register is unknown and can change
freely) and sparc/sparc64 (not stored in struct reg).
 1.2 15-Sep-2015  christos branches: 1.2.16; 1.2.20;
Provide access to pc/sp/syscall-return registers like we have for mcontext
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.1 22-Sep-2015  skrll Sync with HEAD
 1.2.20.1 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.2.16.2 03-Dec-2017  jdolecek update from HEAD
 1.2.16.1 15-Sep-2015  jdolecek file ptrace.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.10 13-Dec-2022  skrll KNF
 1.9 12-Oct-2022  simonb Fix a tyop regname in a comment.
 1.8 07-Nov-2020  skrll Whitespace
 1.7 07-Nov-2020  skrll Indent and annotate FP registers much like the general registers
 1.6 07-Nov-2020  skrll Note if a register is Caller / Callee saved
 1.5 04-Nov-2020  skrll whitespace in comments
 1.4 04-Nov-2020  skrll typo in comment
 1.3 04-Nov-2020  skrll Remove incorrect comment
 1.2 27-Mar-2015  matt branches: 1.2.16; 1.2.32;
Switch to new ABI (return values now in a0/a1; v0/v1 are no more)
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.2.32.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.2.16.2 03-Dec-2017  jdolecek update from HEAD
 1.2.16.1 27-Mar-2015  jdolecek file reg.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.2 29-Nov-2019  riastradh Largely eliminate the MD rwlock.h header file.

This was full of definitions that have been obsolete for over a
decade. The file still remains for __HAVE_RW_STUBS but that's all.
Used only internally in kern_rwlock.c now, not by <sys/rwlock.h>.
 1.1 19-Sep-2014  matt branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.22.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file rwlock.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2 27-Mar-2015  matt branches: 1.2.16;
Switch to new ABI (return values now in a0/a1; v0/v1 are no more)
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.2.16.2 03-Dec-2017  jdolecek update from HEAD
 1.2.16.1 27-Mar-2015  jdolecek file setjmp.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file signal.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file sysarch.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.34 12-Oct-2025  thorpej Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/
 1.33 14-May-2024  riastradh branches: 1.33.4;
riscv: No volatile needed on asm to _read_ rounding mode, exceptions.

These instructions can be omitted if the return values are unused.
In contrast, _writes_ to the rounding mode or exceptions must not be
omitted (even if we ignore the return value, which is the old value
of the field).

I think "memory" is the wrong clobber on these asm blocks too; they
can't be reordered around _floating-point_ instructions, while
reordering around loads and stores is fine. But I don't know how to
spell the right thing in gcclish.
 1.32 14-May-2024  riastradh riscv: Fix reading and writing frm and fflags.

The FRRM/FSRM and FRFLAGS/FSFLAGS instructions do all the masking and
shifting needed -- __SHIFTIN/__SHIFTOUT is wrong.
 1.31 05-Feb-2024  andvar fix various typos in comments.
 1.30 25-Dec-2023  skrll G/C ununsed and incorrect SIE_IM
 1.29 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.28 03-Dec-2022  skrll leading whitespace... oops
 1.27 18-Nov-2022  skrll Fix SR_WPRI.

Tweak csr_cycle_read and csr_asid_write for code style, and add some
KNF whitespace.
 1.26 17-Nov-2022  simonb Document lots of bits.
Remove bits no longer in the RISC-V supervisor spec.
Update defines for the user-mode sstatus value.
 1.25 15-Nov-2022  simonb Use similar macro-magic to aarch64 armreg.h to add per-csr
read/write/set-bits/clear-bits inline functions. Keep the
open-coded 32-bit version of riscvreg_cycle_read() than reads
a 64-bit cycle counter values.

Added benefit of fixing these so that the inline asm uses __volatile
and aren't opmtimised to nops by the compiler.
 1.24 13-Nov-2022  skrll Comment fix
 1.23 12-Nov-2022  skrll Use uintptr_t consistently rather than register_t
 1.22 11-Nov-2022  simonb The supervisor status register is the native word width, not fixed
at 32 bits.
 1.21 08-Nov-2022  simonb Parentheses police.
 1.20 08-Nov-2022  simonb Add cause register trap types, and some macros to access cause register
fields.
 1.19 08-Nov-2022  skrll whitepsace nit
 1.18 15-Oct-2022  skrll Fix typo in SATP_MODE_SV64
 1.17 15-Oct-2022  simonb Consistency nit: use "__volatile" instead of "volatile" with asm()s.
 1.16 15-Oct-2022  simonb Add SATP modes for bare, SV57 and SV64.
 1.15 15-Oct-2022  simonb #define<tab>
 1.14 10-Sep-2022  skrll Remove unnecessary cast.
 1.13 01-May-2021  skrll Provide riscvreg_satp_{read,write}
 1.12 01-May-2021  skrll Indent the FCSR_FRM value #defines
 1.11 16-Dec-2020  christos branches: 1.11.4;
interupt -> interrupt
 1.10 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.9 04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.8 02-Nov-2020  skrll Add SATP_MODE values
 1.7 02-Nov-2020  skrll Whitespace
 1.6 01-Nov-2020  skrll Update CAUSE_* defines to reflect riscv-privileged-20190608.pdf
 1.5 14-Mar-2020  skrll branches: 1.5.4;
Trailing whitespace
 1.4 16-Jun-2019  maxv Misc changes in RISC-V.
 1.3 31-Mar-2015  matt branches: 1.3.16; 1.3.20;
No more fatc (replaced by sfence.vm instruction).
 1.2 28-Mar-2015  matt Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.3.20.2 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.3.20.1 08-Apr-2020  martin Merge changes from current as of 20200406
 1.3.16.2 03-Dec-2017  jdolecek update from HEAD
 1.3.16.1 31-Mar-2015  jdolecek file sysreg.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.5.4.2 03-Jan-2021  thorpej Sync w/ HEAD.
 1.5.4.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.11.4.1 13-May-2021  thorpej Sync with HEAD.
 1.33.4.1 26-Oct-2025  martin Pull up following revision(s) (requested by skrll in ticket #67):

sys/arch/riscv/include/sysreg.h: revision 1.34
sys/arch/riscv/include/pte.h: revision 1.15
sys/arch/riscv/include/pte.h: revision 1.16
sys/arch/riscv/riscv/genassym.cf: revision 1.17
sys/arch/riscv/riscv/locore.S: revision 1.47
sys/arch/riscv/riscv/bus_space.c: revision 1.3
sys/arch/riscv/include/pmap.h: revision 1.25
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.22
sys/arch/riscv/riscv/pmap_machdep.c: revision 1.23
sys/arch/riscv/riscv/cpu.c: revision 1.10
sys/arch/riscv/riscv/riscv_machdep.c: revision 1.46

Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.

Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/


Fix RV32 build. Svpbmt and Memory Attribute Extension (XTheadMae) are
SV39 and above only.
 1.19 23-Nov-2024  skrll risc-v: add __HAVE_MM_MD_KERNACC (basic) support.
 1.18 04-Aug-2024  skrll spaces to tabs
 1.17 06-Apr-2024  skrll branches: 1.17.2;
Provide and use _ucas_{32,64} implementations
 1.16 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.15 08-Nov-2022  simonb Add a #define for XLEN, the RISC-V native base integer ISA width.
 1.14 18-Oct-2022  skrll VSXLEN=64 supports 16-bit ASID space so change tlb_asid_t to be big
enough. Spotted by Simon.
 1.13 11-Sep-2022  skrll Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.
 1.12 03-May-2021  skrll Sort __HAVE_ #defines. NFCI.
 1.11 01-May-2021  skrll Make paddr_t/psize_t __uint64_t for both 32 and 64 bit ports
 1.10 01-Apr-2021  simonb branches: 1.10.2;
Whitespace: #define<tab>
 1.9 22-Mar-2020  ad branches: 1.9.4; 1.9.6;
Temporarily mark hppa, mips, powerpc and riscv with __HAVE_UNLOCKED_PMAP,
for the benefit of UVM.

These need some pmap changes to support concurrent faults on the same
object. I have changes to do just that, but they're a work in progress.
 1.8 14-Mar-2020  skrll Trailing whitespace
 1.7 12-Jul-2018  maxv Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.
 1.6 26-Jan-2017  christos branches: 1.6.12; 1.6.14; 1.6.16;
provide __HAVE_COMPAT_NETBSD32 and fix multiple include protection consistently.
 1.5 23-Jan-2016  christos branches: 1.5.2; 1.5.4;
expose the kernel types for standalone code.
 1.4 23-Jan-2016  christos Hide {p,v}{addr,size}_t and register_t (and a couple more types that
are machine-specific) from userland unless _KERNEL/_KMEMUSER and a
new _KERNTYPES variables is defined. The _KERNTYPES should be fixed
for many subsystems that should not be using it (rump)...
 1.3 27-Aug-2015  pooka Fix PTHREAD_FOO_INITIALIZER for C++ by not using volatile in the relevant
pthread types in C++ builds, attempt 2.

The problem with attempt 1 was making assumptions of what the MD
__cpu_simple_lock_t (declared volatile) looks like. To get a same type
except non-volatile, we change the MD type to __cpu_simple_lock_nv_t
and typedef __cpu_simple_lock_t as a volatile __cpu_simple_lock_nv_t.
IMO, __cpu_simple_lock_t should not be volatile at all, but changing it
now is too risky.

Fixes at least Rumprun w/ gcc 5.1/5.2. Furthermore, the mpd application
(and possibly others) will no longer require NetBSD-specific patches.

Tested: build.sh for i386, Rumprun for x86_64 w/ gcc 5.2.

Based on the patch from Christos in lib/49989.
 1.2 28-Mar-2015  matt Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1 19-Sep-2014  matt branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.2.4 05-Feb-2017  skrll Sync with HEAD
 1.1.2.3 19-Mar-2016  skrll Sync with HEAD
 1.1.2.2 22-Sep-2015  skrll Sync with HEAD
 1.1.2.1 06-Apr-2015  skrll Sync with HEAD
 1.5.4.1 21-Apr-2017  bouyer Sync with HEAD
 1.5.2.1 20-Mar-2017  pgoyette Sync with HEAD
 1.6.16.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.6.16.1 10-Jun-2019  christos Sync with HEAD
 1.6.14.1 28-Jul-2018  pgoyette Sync with HEAD
 1.6.12.2 03-Dec-2017  jdolecek update from HEAD
 1.6.12.1 26-Jan-2017  jdolecek file types.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.9.6.1 03-Apr-2021  thorpej Sync with HEAD.
 1.9.4.1 03-Apr-2021  thorpej Sync with HEAD.
 1.10.2.1 13-May-2021  thorpej Sync with HEAD.
 1.17.2.1 02-Aug-2025  perseant Sync with HEAD
 1.1 22-Nov-2024  skrll branches: 1.1.4;
risc-v: split userret into its own header as per other ports

Helps with crash(8)
 1.1.4.2 02-Aug-2025  perseant Sync with HEAD
 1.1.4.1 22-Nov-2024  perseant file userret.h was added on branch perseant-exfatfs on 2025-08-02 05:56:04 +0000
 1.14 07-May-2023  skrll RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.13 16-Oct-2022  skrll Map the DTB using VM_KERNEL_DTB_BASE and CONSADDR using VM_KERNEL_IO_BASE
 1.12 15-Oct-2022  skrll Update a comment
 1.11 12-Oct-2022  simonb Set RISCV_DIRECTMAP_SIZE to 2^64-PAGESIZE, since 2^64 is effectively 0
for a 64bit constant.
Bump VM_PHYSSEG_MAX from 1 to 16.
 1.10 20-Sep-2022  skrll Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|

Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3

Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes

Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509
 1.9 01-May-2021  skrll Fixup some pmap / VM related #defines and code
 1.8 26-Feb-2021  simonb branches: 1.8.4;
Drop 64-bit default stack sizes back to 4MB.
 1.7 07-Nov-2020  skrll Use lower case for hex constants
 1.6 06-Oct-2020  christos branches: 1.6.2;
GC unused MAXTSIZ32
 1.5 01-Jun-2019  maxv Misc changes in RISC-V. Start changing the memory layout, too.
 1.4 31-May-2018  mrg branches: 1.4.2;
it's called VM_MAXUSER_ADDRESS32 not VM_MAXUSER32_ADDRESS.

fixes mips64 builds, and likely fixes riscv when it happens again.
 1.3 24-Jun-2017  joerg branches: 1.3.4; 1.3.6;
Update VM_DEFAULT_ADDRESS32_TOPDOWN to include guard area.
 1.2 23-Jun-2017  joerg Recommit exec_subr.c revision 1.79:
Always include a 1MB guard area beyond the end of stack. While ASLR will
normally create a guard area as well, this provides a deterministic area
for all binaries.

Mitigates the rest of CVE-2017-1000374 and CVE-2017-1000375 from
Qualys.

Additionally, change VM_DEFAULT_ADDRESS_TOPDOWN to include
user_stack_guard_size in the size reservation.
 1.1 19-Sep-2014  matt branches: 1.1.2; 1.1.12;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.12.1 31-Aug-2017  bouyer Pull up following revision(s) (requested by joerg in ticket #234):
sys/arch/amd64/include/vmparam.h: revision 1.43
sys/kern/exec_subr.c: revision 1.79
lib/libpthread/pthread_int.h: revision 1.94
sys/arch/mips/include/vmparam.h: revision 1.58
sys/arch/mips/include/vmparam.h: revision 1.59
lib/libpthread/TODO: revision 1.19
sys/arch/powerpc/include/vmparam.h: revision 1.20
sys/arch/riscv/include/vmparam.h: revision 1.2
sys/arch/riscv/include/vmparam.h: revision 1.3
sys/arch/i386/include/vmparam.h: revision 1.85
tests/lib/libpthread/t_join.c: revision 1.9
sys/uvm/uvm_meter.c: revision 1.66
sys/uvm/uvm_param.h: revision 1.36
sys/kern/exec_subr.c: revision 1.80
sys/uvm/uvm_param.h: revision 1.37
sys/kern/exec_subr.c: revision 1.81
sys/kern/exec_subr.c: revision 1.82
lib/libpthread/pthread_attr_getguardsize.3: revision 1.4
lib/libpthread/pthread.c: revision 1.148
lib/libpthread/pthread_attr.c: revision 1.17
sys/arch/amd64/include/vmparam.h: revision 1.42
Always include a 1MB guard area beyond the end of stack. While ASLR will
normally create a guard area as well, this provides a deterministic area
for all binaries.
Mitigates the rest of CVE-2017-1000374 and CVE-2017-1000375 from
Qualys.
Revert for the moment, creates problems on i386.
Recommit exec_subr.c revision 1.79:
Always include a 1MB guard area beyond the end of stack. While ASLR will
normally create a guard area as well, this provides a deterministic area
for all binaries.
Mitigates the rest of CVE-2017-1000374 and CVE-2017-1000375 from
Qualys.
Additionally, change VM_DEFAULT_ADDRESS_TOPDOWN to include
user_stack_guard_size in the size reservation.
Update VM_DEFAULT_ADDRESS32_TOPDOWN to include guard area.
Export the guard size of the main thread via vm.guard_size. Add a
complementary writable sysctl for the initial guard size of threads
created via pthread_create. Let the existing attribut accessors do the
right thing. Raise the default guard size for threads to 64KB.
 1.1.2.1 28-Aug-2017  skrll Sync with HEAD
 1.3.6.1 25-Jun-2018  pgoyette Sync with HEAD
 1.3.4.2 03-Dec-2017  jdolecek update from HEAD
 1.3.4.1 24-Jun-2017  jdolecek file vmparam.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.4.2.1 10-Jun-2019  christos Sync with HEAD
 1.6.2.2 03-Apr-2021  thorpej Sync with HEAD.
 1.6.2.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.8.4.1 13-May-2021  thorpej Sync with HEAD.
 1.1 19-Sep-2014  matt branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
 1.1.18.2 03-Dec-2017  jdolecek update from HEAD
 1.1.18.1 19-Sep-2014  jdolecek file wchar_limits.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000

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