Create a new header lwp_private.h to contain _lwp_getprivate_fast,
_lwp_gettcb_fast, _lwp_settcb and remove them from mcontext.h, so that:
1. we don't need special hacks to hide them
2. we can include <lwp.h> where needed to get the necessary prototypes
without redefining them locally.

Undo previous lwp.h change.

Split __lwp_getprivate_fast and __lwp_*tcb from mcontext.h into a separate
lwp.h file.

Install pte.h for libkvm

branches: 1.2.36;
Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.

branches: 1.1.18; 1.1.20; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

PR 58960: fix misunderstanding in semantic and provide both the original
id string as well as _NETBSD_REVISIONID.
Do not rely on string concatenation in the inline assembler, use .ascii
and .asciz for individual string parts instead.

fix copy&pasto in previous

PR 58960: riscv/asm.h: Respect NETBSD_REVISIONID.

spaces to tabs

branches: 1.7.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Provide __CONCAT, __STRING and ___CONCAT

branches: 1.5.6;
Mark the .ident section as mergable string section to avoid redundant
entries.

branches: 1.4.2;
Trailing whitespace

Handle changes since the gcc riscv toolchain was upstreamed

branches: 1.2.16; 1.2.20;
Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

spaces to tabs

branches: 1.1.18; 1.1.58;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.

Provide PRIxBUSADDR, PRIxBUSSIZE, PRIuBUSSIZE, and PRIxBSH for all arches
to follow arm and (generic) mips.

Reviewed by christos.

branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

spaces to tabs

branches: 1.3.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Fix some types

Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.

Whitespace

branches: 1.3.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Fix some types

Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.

Eliminate recursive dependency on <sys/bswap.h> in MD <byte_swap.h>

On certain NetBSD archs, it isn't possible to include <sys/bswap.h>
directly without including <sys/endian.h> first. This has been
broken since at least before netbsd-10, but recent changes elsewhere
have made this problem more visible for some reason.

Fix this by not including <sys/types.h>, eliminating recursive
inclusion - <sys/types.h> includes <machine/endian.h>. It would
be nice to remove that line from types.h, since it's no longer
necessary, but currently the kernel assumes that <sys/endian.h> is
included from <sys/types.h> in various places (and possibly userspace
software does too).

For now we can take the less dangerous option by avoiding
including <sys/types.h> from these bswap headers. They don't need the
full header, and applications that assume transclusion aren't portable
anyway, since architectures like sparc64 don't include <sys/types.h>
via <sys/bswap.h>.

PR pkg/59839 palemoon, firefox, etc., don't build on arm64 any more

branches: 1.5.30;
silence lint.

Avoid -Wconversion warnings

branches: 1.3.18; 1.3.22;
Shave an instruction from the generated code for the 32 bit byte
swap inline. Prune 5 or 9 instructions (depending on what you count)
from the 64 bit byte swap inline.

Correct 32 and 64 bit byte swap inlines.

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

spaces to tabs

branches: 1.15.2;
Count interrupts across harts and their local interrupt controllers
correctly.

Fix and enable MULTIPROCESSOR

Slight reformatting. NFCI.

risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.

Fix CLKF_INTR so that not all time is shown as being spent in interrupts.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Use better types and struct member names in the clockframe.
Avoid a magic number in CLKF_USERMODE().

Improved the performance of kernel profiling on MULTIPROCESSOR, and possible to get profiling data for each CPU.

In the current implementation, locks are acquired at the entrance of the mcount
internal function, so the higher the number of cores, the more lock conflict
occurs, making profiling performance in a MULTIPROCESSOR environment unusable
and slow. Profiling buffers has been changed to be reserved for each CPU,
improving profiling performance in MP by several to several dozen times.

- Eliminated cpu_simple_lock in mcount internal function, using per-CPU buffers.
- Add ci_gmon member to struct cpu_info of each MP arch.
- Add kern.profiling.percpu node in sysctl tree.
- Add new -c <cpuid> option to kgmon(8) to specify the cpuid, like openbsd.
For compatibility, if the -c option is not specified, the entire system can be
operated as before, and the -p option will get the total profiling data for
all CPUs.

Fix false sharing problems with cpu_info. Identified with tprof(8).
This was a very nice win in my tests on a 48 CPU box.

- Reorganise cpu_data slightly according to usage.
- Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc).
- On x86, put some items in their own cache lines according to usage, like
the IPI bitmask and ci_want_resched.

mi_userret(): take care of calling preempt(), set spc_curpriority directly,
and remove MD code that does the same.

Misc changes in RISC-V. Start changing the memory layout, too.

branches: 1.4.16; 1.4.20;
_KMEMUSER only needs struct cpu_info

Define curcpu() as lwp_getcpu(curlwp) since curlwp is always in the "tp"
(thread pointer) register.

Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.

branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Use __volatile so the compiler doesn't optimise out successive calls
to cpu_counter().
Add a 64-bit cycle counter on _LP64.

#define<tab>

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

risc-v: support crash(8)

risc-v: don't include locore.h in db_machdep.h

G/C

Whitespace

branches: 1.9.6;
Fix a comment and enable RISC-V ddb mach commands

risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Basic ddb and backtrace support.

[ 1.0000000] panic: kernel diagnostic assertion "msgbufaddr != 0" failed: file "/home/nick/netbsd/nbcvs/src/sys/arch/riscv/riscv/riscv_machdep.c", line 564
[ 1.0000000] cpu0: Begin traceback...
[ 1.0000000] trace fp ffffffc000801dd0
[ 1.0000000] fp ffffffc000801e10 ?() at ffffffc0001eee98
[ 1.0000000] fp ffffffc000801e30 ?() at ffffffc0002ad984
[ 1.0000000] fp ffffffc000801ee0 ?() at ffffffc000005430
[ 1.0000000] cpu0: End traceback...
[ 1.0000000] Trapframe @ 0xffffffc000801cb0 (cause=3 (breakpoint), status=0x100, pc=0xffffffc0000007e4, va=0):
[ 1.0000000] ra =0xffffffc0001eee9c, sp =0xffffffc000801dd0, gp =0xffffffc0006a8f40, tp = 0
[ 1.0000000] s0 =0xffffffc000600ac0, s1 = 0x1000, s2 =0xffffffc000438df0, s3 =0xffffffc000801d80
[ 1.0000000] s4 =0xffffffc0001eed78, s5 =0xffffffc0006d55f8, s6 =0xffffffc000801d88, s7 =0xffffffc0006dfdb8
[ 1.0000000] s8 =0xffffffc000428c18, s9 =0xffffffc000801dd0, s10=0xffffffc0000a3822, s11=0xffffffc0006d55f8
[ 1.0000000] a0 = 0x17, a1 = 0xa, a2 = 0, a3 =0xffffffc00041f658
[ 1.0000000] a4 = 0, a5 = 0x1, a5 = 0, a7 = 0x1
[ 1.0000000] t0 =0xffffffc0006dfe30, t1 =0xffffffc000801bb8, t2 =0xffffffc000803000, t3 = 0x75
[ 1.0000000] t4 = 0, t5 = 0x63, t6 = 0x1
[ 1.0000000] kernel: breakpoint
Stopped in pid 0.0 (system) at ffffffc0000007e4: c.ebreak
db>

Use #define<tab> in this file

Remove argument names from function declaration prototypes.
Misc tidyup.

branches: 1.3.2; 1.3.4;
Add a ddb disassembler for riscv.

builds, but not really tested yet.

branches: 1.2.2; 1.2.20;
Cleanup and clarify the ELFSIZE mess:

We now have 2 variables automatically set in elf_machdep.h:

ARCH_ELFSIZE: the size for userland binaries
KERN_ELFSIZE: the size for the kernel binaries

DB_ELFSIZE has been deleted and KERN_ELFSIZE should have always the
same values DB_ELFSIZE used to have.

In sys/exec_elf.h, if ELFSIZE is not set, it is set to KERN_ELFSIZE
for the kernel and ARCH_ELFSIZE for userland. These defaults should
eliminate the need for most manual ELFSIZE setting.

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

s/dosen't/doesn't/ in copy pasted comment.

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

riscv/elf_machdep.h: organize symbols into psABI & local groups.

Allow this file to be used with <sys/elfdefinitions.h>.

PR lib/59564

spaces to tabs

branches: 1.9.8;
Correct some pre-existing relocations and add some new ones.

Trailing whitespace

Misc changes in RISC-V. Start changing the memory layout, too.

branches: 1.6.2; 1.6.6;
Cleanup and clarify the ELFSIZE mess:

We now have 2 variables automatically set in elf_machdep.h:

ARCH_ELFSIZE: the size for userland binaries
KERN_ELFSIZE: the size for the kernel binaries

DB_ELFSIZE has been deleted and KERN_ELFSIZE should have always the
same values DB_ELFSIZE used to have.

In sys/exec_elf.h, if ELFSIZE is not set, it is set to KERN_ELFSIZE
for the kernel and ARCH_ELFSIZE for userland. These defaults should
eliminate the need for most manual ELFSIZE setting.

add ELF64_MACHDEP_ID

Add two new relocs for compressed branches.

Fix one error and make life for ld.elf_so a little easier.

Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

riscv fenv.h: Make sure FE_* exception constants have type int.

This may not be formally required by the standard, but the values
must be representable by int since that's the type that functions
like fetestexcept and feclearexcept traffic in. And this is less
work than changing all the printf %d users in tree.

Use __BIT and fix FE_INEXACT

Trailing whitespace

branches: 1.2.12; 1.2.16;
provide a common softfloat fenv implemenation and use it for softfloat builds.
restore ABI compatibility with previous releases for ieeefp.h on sh3.
add namespace.h protection for all the fenv interfaces.
use MKSOFTFLOAT on sh3 instead of assuming softfloat.
standardize on comparing MKSOFTFLOAT with "no".
remove the arm-specific softfloat fenv code (which also had several bugs).
fix logic errors in the arm hardfloat feraiseexcept() and feupdateenv().

branches: 1.1.2; 1.1.4; 1.1.6;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Sprinkle <sys/featuretest.h> where _*_SOURCE macros are consulted.

Otherwise, the feature tests might come out wrong. For example,
header files that check for _NETBSD_SOURCE won't get the default when
no other _*_SOURCE macros are defined; header files that check for
_POSIX_C_SOURCE might miss _XOPEN_SOURCE, which is supposed to imply
a corresponding _POSIX_C_SOURCE.

PR lib/58752: various header files test _*_SOURCE macros but don't
include sys/featuretest.h

branches: 1.1.18; 1.1.58;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Pad the trapframe so it's a multiple of 16 bytes so that when a trapframe
is created on the stack SP remains 16-byte aligned as per the ABI
requirements.

Patch from Rin with some updates from me.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Fix some of the previous - I must have compile tested the wrong tree

Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@

branches: 1.2.4;
Trailing whitespace

branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Our current configuration is that long double is 128bit, so reflect
that in the relevant headers.

Taken from sparc64.

branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Trailing whitespace

branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

fix various typos in comments.

Make the riscv disassembler work, as best as I can test from amd64 userspace.

Add a ddb disassembler for riscv.

builds, but not really tested yet.

branches: 1.2.2;
RCSID and whitespace police...

branches: 1.1.18; 1.1.34;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

risc-v: Fix UINT32_C.

PR port-riscv/58766 ntpd / ntpdate setting time on risc64 fails to work

branches: 1.2.6;
riscv: Fix (U)INT64_C suffix to match gcc's built-in idea of types.

XXX pullup-10

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

fix for riscv32.

We're now using gcc netbsd-stdint.h instead of our own definitions, so
match those with the format types

XXX wrong for 32bit.
XXX unclear if changing the fast types was the right call

Provide defines for the 64bit case.

branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

risc-v: expose intr_establish_xname

spaces to tabs

branches: 1.5.6;
Fix and enable MULTIPROCESSOR

risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

branches: 1.2.16;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.

branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

branches: 1.1.4;
Add loadfile_machdep.h for riscv

branches: 1.4.16;
Move the riscv lock.h which uses only compiler builtin atomic primitives
to a common location which can be used by others and make riscv's lock.h
use it.

Fix c&p error.

Use C11 atomic builtins instead of __asm.

branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

risc-v: split userret into its own header as per other ports

Helps with crash(8)

branches: 1.13.2;
risc-v: fix the error code when uvm_fault fails with cpu_set_onfault

Return the error from uvm_fault instead of EFAULT unconditionally when
faulting with cpu_set_onfault to fix several atf tests.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|

Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3

Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes

Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509

#define<tab>

Fix riscv32 GENERIC build

Sprinkle #ifdef FPE for now

branches: 1.7.4;
RCSID and whitespace police...

Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@

branches: 1.5.4;
Trailing whitespace

Fix a typo in a comment

branches: 1.3.12; 1.3.16;
allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.

branches: 1.2.2; 1.2.4;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.

branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Undo previous lwp.h change.

Split __lwp_getprivate_fast and __lwp_*tcb from mcontext.h into a separate
lwp.h file.

branches: 1.1.4;
Create a new header lwp_private.h to contain _lwp_getprivate_fast,
_lwp_gettcb_fast, _lwp_settcb and remove them from mcontext.h, so that:
1. we don't need special hacks to hide them
2. we can include <lwp.h> where needed to get the necessary prototypes
without redefining them locally.

KNF - sort includes.

branches: 1.5.6;
risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Map the DTB using VM_KERNEL_DTB_BASE and CONSADDR using VM_KERNEL_IO_BASE

Use legacy SBI Console GetChar for earlycons. It works on qemu.

Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|

Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3

Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes

Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509

RISC-V ELF psABI says ILP32 also defaults to 128bit long double.

Our current configuration is that long double is 128bit, so reflect
that in the relevant headers.

Taken from sparc64.

branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Create a new header lwp_private.h to contain _lwp_getprivate_fast,
_lwp_gettcb_fast, _lwp_settcb and remove them from mcontext.h, so that:
1. we don't need special hacks to hide them
2. we can include <lwp.h> where needed to get the necessary prototypes
without redefining them locally.

Undo previous lwp.h change.

Split __lwp_getprivate_fast and __lwp_*tcb from mcontext.h into a separate
lwp.h file.

branches: 1.9.2;
Add more ABI register defines - should have been committed with previous
change.

Fix the __greg_t typedef for riscv32

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Trailing whitespace

branches: 1.5.4;
Introduce _UC_MACHINE_FP() as a macro

_UC_MACHINE_FP() is a helper macro to extract from mcontext a frame pointer.

Don't rely on this interface as a compiler might strip frame pointer or
optimize it making this interface unreliable.


For hppa assume a small frame context, for larger frames FP might be located
in a different register (4 instead of 3).

For ia64 there is no strict frame pointer, and registers might rotate.
Reuse 79 following:

./gcc/config/ia64/ia64.h:#define HARD_FRAME_POINTER_REGNUM LOC_REG (79)

Once ia64 will mature, this should be revisited.

A macro can encapsulate a real function for extracting Frame Pointer on
more complex CPUs / ABIs.


For the remaining CPUs, reuse standard register as defined in appropriate ABI.

The direct users of this macro are LLVM and GCC with Sanitizers.

Proposed on tech-userlevel@.

Sponsored by <The NetBSD Foundation>

branches: 1.4.10; 1.4.16;
Add _REG_S0

Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

branches: 1.2.2;
Fix a typo: the PC is likely in _REG_PC

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

risc-v: support crash(8)

branches: 1.6.6;
machine/mutex.h: Sprinkle sys/types.h, omit machine/lock.h.

Turns out machine/lock.h is not needed for __cpu_simple_lock_t, which
always comes from sys/types.h. And, really, sys/types.h (or at least
sys/stdint.h) is needed for uintN_t and uintptr_t.

machine/mutex.h: Sprinkle includes so this can be used by crash(8).

XXX pullup-10

branches: 1.4.4;
- In kern_mutex.c, if MUTEX_CAS() is not defined, define it in terms of
atomic_cas_ulong().
- For arm, ia64, m68k, mips, or1k, riscv, vax: don't define our own
MUTEX_CAS(), as they either use atomic_cas_ulong() or equivalent
(atomic_cas_uint() on m68k).
- For alpha and sparc64, don't define MUTEX_CAS() in terms of their own
_lock_cas(), which has its own memory barriers; the call sites in
kern_mutex.c already have the appropriate memory barrier calls. Thus,
alpha and sparc64 can use default definition.
- For sh3, don't define MUTEX_CAS() in terms of its own _lock_cas();
atomic_cas_ulong() is strong-aliased to _lock_cas(), therefore defining
our own MUTEX_CAS() is redundant.

Per thread:
https://mail-index.netbsd.org/tech-kern/2021/07/25/msg027562.html

Nix now-unused definitions of MUTEX_GIVE/MUTEX_RECEIVE.

Misc changes in RISC-V. Start changing the memory layout, too.

branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Change MIPS to RISC-V.

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

NKMEMPAGES_MIN_DEFAULT is in pages not bytes (hint is in the name).
Also set NKMEMPAGES_MAX_UNLIMITED while we're here.

Remove definitions for CACHE_LINE_SIZE and COHERENCY_UNIT which are the same
as the default.

Include "opt_param.h" (ifdef _KERNEL_OPT) everywhere that MSGBUFSIZE is
referenced since some sources include <machine/param.h>.

Bump MSGBUFSIZE (if not defined)

Provide COHERENCY_UNIT and CACHE_LINE_SIZE

Also provide MAXCPUS

branches: 1.3.14;
Misc changes in RISC-V. Start changing the memory layout, too.

move DEV_BSIZE, DEV_BSHIFT out of MD param.h, they are same on all ports

also move BLKDEV_IOSIZE, MAXPHYS, but allow override since some ports
have different value (powerpc uses NBPG for BLKDEV_IOSIZE, sun2/sun3
have lower MAXPHYS)

branches: 1.1.18; 1.1.20; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

spaces to tabs

branches: 1.2.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

branches: 1.1.4;
risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.

Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/

branches: 1.24.2;
spaces to tabs

branches: 1.23.2;
risc-v: probe the number of supported ASIDs

Flush the entire TLB if no ASIDs are supported on pmap_activate.

Not all RISC-V CPUs have ASIDs

Fix and enable MULTIPROCESSOR

risc-v: Use 'onproc' for 2nd arg of pmap_md_page_syncicache

Match other definitions of pmap_md_page_syncicache argument naming by
renaming the 2nd arg to 'onproc'

G/C pmap_md_kernel_*

risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.

Remove some #if 0'ed code

KNF

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Fix RV builds

Add the "memory" clobber in two places that it's needed.

Correct XSEGSHIFT for RV32 case

#define<tab>

Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|

Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3

Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes

Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509

Fixup some pmap / VM related #defines and code

branches: 1.8.4;
Support __HAVE_PMAP_PV_TRACK in sys/uvm/pmap based pmaps (aka common pmap)

This file is #define<space>

branches: 1.6.2;
Whitespace

Provide a pmap_segtab_deactivate for symmetry with pmap_segtab_activate
and use it in pmap_deactivate

Call pmap_md_xtab_{,de}activate from pmap_segtab_{,de}activate to be used
for PMAP_HWPAGEWALKER and any caches ops that might be required.

Provide empty (for now) pmap_md_xtab_{,de}activate functions on the
platforms that use sys/uvm/pmap

With DEBUG defined, it's possible to execute a TLB-vs-segmap consistency
check from a (soft) interrupt handler. But if a platform does not otherwise
require the pmap_tlb_miss_lock, then where will be a brief window of
inconsistency that, while harmless, will still fire an assertion in the
consistency check.

Fix this with the following changes:
1- Refactor the pmap_tlb_miss_lock into MI code and rename it from
pmap_tlb_miss_lock_{enter,exit}() to pmap_tlb_miss_lock_{enter,exit}().
MD code can still define the "md" hooks as necessary, and if so, will
override the common implementation.
2- Provde a pmap_bootstrap_common() function to perform common pmap bootstrap
operations, namely initializing the pmap_tlb_miss_lock if it's needed.
If MD code overrides the implementation, it's responsible for initializing
its own lock.
3- Call pmap_bootstrap_common() from the mips, powerpc booke, and riscv
pmap_bootstrap() routines. (This required adding one for riscv.)
4- Switch powerpc booke to the common pmap_tlb_miss_lock.
5- Enable pmap_tlb_miss_lock if DEBUG is defined, even if it's not otherwise
required.

PR port-mips/55062 (Failed assertion in pmap_md_tlb_check_entry())

Misc changes in RISC-V.

Misc changes in RISC-V. Start changing the memory layout, too.

branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.

branches: 1.1.18; 1.1.20; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

spaces to tabs

branches: 1.5.6;
Don't expose vaddr_t or register_t to userland. The gdb configure script
needs this so it can detect struct lwp correctly.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

branches: 1.3.16;
Optimize the exception handle a little bit more.

Add a md_tp member to mdlwp so that the exception handler can temporarily
store the user's thread pointer before saving it in the trapframe.

branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

risc-v: pte_make_enter set PTE_D when page is known to be modified.

PR/59696: pte_make_enter() appears to have bug vis a vis already-modified managed pages

Fix RV32 build. Svpbmt and Memory Attribute Extension (XTheadMae) are
SV39 and above only.

Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/

branches: 1.14.2;
Install pte.h for libkvm

branches: 1.13.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

G/C pte_index

Note some SV39 PTE bits defined in extensions.

Fix pte_nv_entry for the kernel.

Fix pte_pde_ptpage. PTE.{X,W,R} must be zero for pointer to next level.

Some fixes from Simon.

#define<tab>

Don't set A, D in page table pointers, but do set them in leaf entries.

Beagle-v now boots to the msgbufaddr panic same as qemu

Use c99 types. NFC.

Fixup some pmap / VM related #defines and code

branches: 1.5.4;
Comments from zmcgrew@

branches: 1.4.4;
Trailing whitespace

Misc changes in RISC-V.

Misc changes in RISC-V. Start changing the memory layout, too.

branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Use the _X_FOO register macros instead of magic numbers.

riscv: ptrace: Add PTRACE_ILLEGAL_ASM for ATF

All related tests successfully pass.

riscv: Add PTRACE_BREAKPOINT and friends for ATF

Since its size must be determined a priori, explicitly use
c.ebreak for sure.

Now, related tests in ATF successfully pass for riscv64,
as far as I can see.

Introduce PTRACE_REG_FP() a helper macro to retrieve the frame pointer

The macro is dummy for ia64 (the FP register is unknown and can change
freely) and sparc/sparc64 (not stored in struct reg).

branches: 1.2.16; 1.2.20;
Provide access to pc/sp/syscall-return registers like we have for mcontext

branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

KNF

Fix a tyop regname in a comment.

Whitespace

Indent and annotate FP registers much like the general registers

Note if a register is Caller / Callee saved

whitespace in comments

typo in comment

Remove incorrect comment

branches: 1.2.16; 1.2.32;
Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Largely eliminate the MD rwlock.h header file.

This was full of definitions that have been obsolete for over a
decade. The file still remains for __HAVE_RW_STUBS but that's all.
Used only internally in kern_rwlock.c now, not by <sys/rwlock.h>.

branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

riscv: fix the SBI version 0.3 PMU FID define names

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

branches: 1.2.16;
Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.

This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.

So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.

With this, my D1 Nezha board boots to the root device prompt. \o/

branches: 1.33.4;
riscv: No volatile needed on asm to _read_ rounding mode, exceptions.

These instructions can be omitted if the return values are unused.
In contrast, _writes_ to the rounding mode or exceptions must not be
omitted (even if we ignore the return value, which is the old value
of the field).

I think "memory" is the wrong clobber on these asm blocks too; they
can't be reordered around _floating-point_ instructions, while
reordering around loads and stores is fine. But I don't know how to
spell the right thing in gcclish.

riscv: Fix reading and writing frm and fflags.

The FRRM/FSRM and FRFLAGS/FSFLAGS instructions do all the masking and
shifting needed -- __SHIFTIN/__SHIFTOUT is wrong.

fix various typos in comments.

G/C ununsed and incorrect SIE_IM

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

leading whitespace... oops

Fix SR_WPRI.

Tweak csr_cycle_read and csr_asid_write for code style, and add some
KNF whitespace.

Document lots of bits.
Remove bits no longer in the RISC-V supervisor spec.
Update defines for the user-mode sstatus value.

Use similar macro-magic to aarch64 armreg.h to add per-csr
read/write/set-bits/clear-bits inline functions. Keep the
open-coded 32-bit version of riscvreg_cycle_read() than reads
a 64-bit cycle counter values.

Added benefit of fixing these so that the inline asm uses __volatile
and aren't opmtimised to nops by the compiler.

Comment fix

Use uintptr_t consistently rather than register_t

The supervisor status register is the native word width, not fixed
at 32 bits.

Parentheses police.

Add cause register trap types, and some macros to access cause register
fields.

whitepsace nit

Fix typo in SATP_MODE_SV64

Consistency nit: use "__volatile" instead of "volatile" with asm()s.

Add SATP modes for bare, SV57 and SV64.

#define<tab>

Remove unnecessary cast.

Provide riscvreg_satp_{read,write}

Indent the FCSR_FRM value #defines

branches: 1.11.4;
interupt -> interrupt

Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@

Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@

Add SATP_MODE values

Whitespace

Update CAUSE_* defines to reflect riscv-privileged-20190608.pdf

branches: 1.5.4;
Trailing whitespace

Misc changes in RISC-V.

branches: 1.3.16; 1.3.20;
No more fatc (replaced by sfence.vm instruction).

Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.

branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

risc-v: add __HAVE_MM_MD_KERNACC (basic) support.

spaces to tabs

branches: 1.17.2;
Provide and use _ucas_{32,64} implementations

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Add a #define for XLEN, the RISC-V native base integer ISA width.

VSXLEN=64 supports 16-bit ASID space so change tlb_asid_t to be big
enough. Spotted by Simon.

Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.

Remove the RISC-V Host Target Interface (HTIF) Emulation code.

Sort __HAVE_ #defines. NFCI.

Make paddr_t/psize_t __uint64_t for both 32 and 64 bit ports

branches: 1.10.2;
Whitespace: #define<tab>

branches: 1.9.4; 1.9.6;
Temporarily mark hppa, mips, powerpc and riscv with __HAVE_UNLOCKED_PMAP,
for the benefit of UVM.

These need some pmap changes to support concurrent faults on the same
object. I have changes to do just that, but they're a work in progress.

Trailing whitespace

Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.

branches: 1.6.12; 1.6.14; 1.6.16;
provide __HAVE_COMPAT_NETBSD32 and fix multiple include protection consistently.

branches: 1.5.2; 1.5.4;
expose the kernel types for standalone code.

Hide {p,v}{addr,size}_t and register_t (and a couple more types that
are machine-specific) from userland unless _KERNEL/_KMEMUSER and a
new _KERNTYPES variables is defined. The _KERNTYPES should be fixed
for many subsystems that should not be using it (rump)...

Fix PTHREAD_FOO_INITIALIZER for C++ by not using volatile in the relevant
pthread types in C++ builds, attempt 2.

The problem with attempt 1 was making assumptions of what the MD
__cpu_simple_lock_t (declared volatile) looks like. To get a same type
except non-volatile, we change the MD type to __cpu_simple_lock_nv_t
and typedef __cpu_simple_lock_t as a volatile __cpu_simple_lock_nv_t.
IMO, __cpu_simple_lock_t should not be volatile at all, but changing it
now is too risky.

Fixes at least Rumprun w/ gcc 5.1/5.2. Furthermore, the mpd application
(and possibly others) will no longer require NetBSD-specific patches.

Tested: build.sh for i386, Rumprun for x86_64 w/ gcc 5.2.

Based on the patch from Christos in lib/49989.

Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.

branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

branches: 1.1.4;
risc-v: split userret into its own header as per other ports

Helps with crash(8)

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Map the DTB using VM_KERNEL_DTB_BASE and CONSADDR using VM_KERNEL_IO_BASE

Update a comment

Set RISCV_DIRECTMAP_SIZE to 2^64-PAGESIZE, since 2^64 is effectively 0
for a 64bit constant.
Bump VM_PHYSSEG_MAX from 1 to 16.

Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|

Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3

Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes

Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509

Fixup some pmap / VM related #defines and code

branches: 1.8.4;
Drop 64-bit default stack sizes back to 4MB.

Use lower case for hex constants

branches: 1.6.2;
GC unused MAXTSIZ32

Misc changes in RISC-V. Start changing the memory layout, too.

branches: 1.4.2;
it's called VM_MAXUSER_ADDRESS32 not VM_MAXUSER32_ADDRESS.

fixes mips64 builds, and likely fixes riscv when it happens again.

branches: 1.3.4; 1.3.6;
Update VM_DEFAULT_ADDRESS32_TOPDOWN to include guard area.

Recommit exec_subr.c revision 1.79:
Always include a 1MB guard area beyond the end of stack. While ASLR will
normally create a guard area as well, this provides a deterministic area
for all binaries.

Mitigates the rest of CVE-2017-1000374 and CVE-2017-1000375 from
Qualys.

Additionally, change VM_DEFAULT_ADDRESS_TOPDOWN to include
user_stack_guard_size in the size reservation.

branches: 1.1.2; 1.1.12;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

branches: 1.1.18;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)