| History log of /src/sys/arch/riscv/include/pmap.h |
| Revision | | Date | Author | Comments |
| 1.25 |
| 12-Oct-2025 |
thorpej | Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.
This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.
So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.
With this, my D1 Nezha board boots to the root device prompt. \o/
|
| 1.24 |
| 04-Aug-2024 |
skrll | spaces to tabs
|
| 1.23 |
| 01-Jan-2024 |
skrll | branches: 1.23.2;
risc-v: probe the number of supported ASIDs
Flush the entire TLB if no ASIDs are supported on pmap_activate.
|
| 1.22 |
| 06-Oct-2023 |
skrll | Not all RISC-V CPUs have ASIDs
|
| 1.21 |
| 03-Sep-2023 |
skrll | Fix and enable MULTIPROCESSOR
|
| 1.20 |
| 12-Aug-2023 |
skrll | risc-v: Use 'onproc' for 2nd arg of pmap_md_page_syncicache
Match other definitions of pmap_md_page_syncicache argument naming by
renaming the 2nd arg to 'onproc'
|
| 1.19 |
| 26-Jul-2023 |
skrll | G/C pmap_md_kernel_*
|
| 1.18 |
| 12-Jun-2023 |
skrll | risc-v: MULTIPROCESSOR support
Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.
Some other improvements to spl and cpu identification / reporting.
|
| 1.17 |
| 08-May-2023 |
skrll | Remove some #if 0'ed code
|
| 1.16 |
| 08-May-2023 |
skrll | KNF
|
| 1.15 |
| 07-May-2023 |
skrll | RISC-V support that works on QEMU with a single hart.
Thanks for Simon Burge for plic(4).
|
| 1.14 |
| 23-Dec-2022 |
skrll | Fix RV builds
|
| 1.13 |
| 20-Oct-2022 |
skrll | Add the "memory" clobber in two places that it's needed.
|
| 1.12 |
| 18-Oct-2022 |
skrll | Correct XSEGSHIFT for RV32 case
|
| 1.11 |
| 15-Oct-2022 |
simonb | #define<tab>
|
| 1.10 |
| 20-Sep-2022 |
skrll | Checkpoint WIP.
QEMU RV64 virt can boot into virtual mode
OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|
Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3
Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes
Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509
|
| 1.9 |
| 01-May-2021 |
skrll | Fixup some pmap / VM related #defines and code
|
| 1.8 |
| 20-Dec-2020 |
skrll | branches: 1.8.4;
Support __HAVE_PMAP_PV_TRACK in sys/uvm/pmap based pmaps (aka common pmap)
|
| 1.7 |
| 15-Nov-2020 |
skrll | This file is #define<space>
|
| 1.6 |
| 10-Aug-2020 |
skrll | branches: 1.6.2;
Whitespace
|
| 1.5 |
| 07-Aug-2020 |
skrll | Provide a pmap_segtab_deactivate for symmetry with pmap_segtab_activate
and use it in pmap_deactivate
Call pmap_md_xtab_{,de}activate from pmap_segtab_{,de}activate to be used
for PMAP_HWPAGEWALKER and any caches ops that might be required.
Provide empty (for now) pmap_md_xtab_{,de}activate functions on the
platforms that use sys/uvm/pmap
|
| 1.4 |
| 11-Mar-2020 |
thorpej | With DEBUG defined, it's possible to execute a TLB-vs-segmap consistency
check from a (soft) interrupt handler. But if a platform does not otherwise
require the pmap_tlb_miss_lock, then where will be a brief window of
inconsistency that, while harmless, will still fire an assertion in the
consistency check.
Fix this with the following changes:
1- Refactor the pmap_tlb_miss_lock into MI code and rename it from
pmap_tlb_miss_lock_{enter,exit}() to pmap_tlb_miss_lock_{enter,exit}().
MD code can still define the "md" hooks as necessary, and if so, will
override the common implementation.
2- Provde a pmap_bootstrap_common() function to perform common pmap bootstrap
operations, namely initializing the pmap_tlb_miss_lock if it's needed.
If MD code overrides the implementation, it's responsible for initializing
its own lock.
3- Call pmap_bootstrap_common() from the mips, powerpc booke, and riscv
pmap_bootstrap() routines. (This required adding one for riscv.)
4- Switch powerpc booke to the common pmap_tlb_miss_lock.
5- Enable pmap_tlb_miss_lock if DEBUG is defined, even if it's not otherwise
required.
PR port-mips/55062 (Failed assertion in pmap_md_tlb_check_entry())
|
| 1.3 |
| 16-Jun-2019 |
maxv | Misc changes in RISC-V.
|
| 1.2 |
| 01-Jun-2019 |
maxv | Misc changes in RISC-V. Start changing the memory layout, too.
|
| 1.1 |
| 19-Sep-2014 |
matt | branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
|
| 1.1.22.3 |
| 13-Apr-2020 |
martin | Mostly merge changes from HEAD upto 20200411
|
| 1.1.22.2 |
| 08-Apr-2020 |
martin | Merge changes from current as of 20200406
|
| 1.1.22.1 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.1.18.2 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.1.18.1 |
| 19-Sep-2014 |
jdolecek | file pmap.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
|
| 1.6.2.2 |
| 03-Jan-2021 |
thorpej | Sync w/ HEAD.
|
| 1.6.2.1 |
| 14-Dec-2020 |
thorpej | Sync w/ HEAD.
|
| 1.8.4.1 |
| 13-May-2021 |
thorpej | Sync with HEAD.
|
| 1.23.2.1 |
| 02-Aug-2025 |
perseant | Sync with HEAD
|
