| History log of /src/sys/arch/riscv/include/sysreg.h |
| Revision | | Date | Author | Comments |
| 1.34 |
| 12-Oct-2025 |
thorpej | Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.
This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.
So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.
With this, my D1 Nezha board boots to the root device prompt. \o/
|
| 1.33 |
| 14-May-2024 |
riastradh | riscv: No volatile needed on asm to _read_ rounding mode, exceptions.
These instructions can be omitted if the return values are unused.
In contrast, _writes_ to the rounding mode or exceptions must not be
omitted (even if we ignore the return value, which is the old value
of the field).
I think "memory" is the wrong clobber on these asm blocks too; they
can't be reordered around _floating-point_ instructions, while
reordering around loads and stores is fine. But I don't know how to
spell the right thing in gcclish.
|
| 1.32 |
| 14-May-2024 |
riastradh | riscv: Fix reading and writing frm and fflags.
The FRRM/FSRM and FRFLAGS/FSFLAGS instructions do all the masking and
shifting needed -- __SHIFTIN/__SHIFTOUT is wrong.
|
| 1.31 |
| 05-Feb-2024 |
andvar | fix various typos in comments.
|
| 1.30 |
| 25-Dec-2023 |
skrll | G/C ununsed and incorrect SIE_IM
|
| 1.29 |
| 07-May-2023 |
skrll | RISC-V support that works on QEMU with a single hart.
Thanks for Simon Burge for plic(4).
|
| 1.28 |
| 03-Dec-2022 |
skrll | leading whitespace... oops
|
| 1.27 |
| 18-Nov-2022 |
skrll | Fix SR_WPRI.
Tweak csr_cycle_read and csr_asid_write for code style, and add some
KNF whitespace.
|
| 1.26 |
| 17-Nov-2022 |
simonb | Document lots of bits.
Remove bits no longer in the RISC-V supervisor spec.
Update defines for the user-mode sstatus value.
|
| 1.25 |
| 15-Nov-2022 |
simonb | Use similar macro-magic to aarch64 armreg.h to add per-csr
read/write/set-bits/clear-bits inline functions. Keep the
open-coded 32-bit version of riscvreg_cycle_read() than reads
a 64-bit cycle counter values.
Added benefit of fixing these so that the inline asm uses __volatile
and aren't opmtimised to nops by the compiler.
|
| 1.24 |
| 13-Nov-2022 |
skrll | Comment fix
|
| 1.23 |
| 12-Nov-2022 |
skrll | Use uintptr_t consistently rather than register_t
|
| 1.22 |
| 11-Nov-2022 |
simonb | The supervisor status register is the native word width, not fixed
at 32 bits.
|
| 1.21 |
| 08-Nov-2022 |
simonb | Parentheses police.
|
| 1.20 |
| 08-Nov-2022 |
simonb | Add cause register trap types, and some macros to access cause register
fields.
|
| 1.19 |
| 08-Nov-2022 |
skrll | whitepsace nit
|
| 1.18 |
| 15-Oct-2022 |
skrll | Fix typo in SATP_MODE_SV64
|
| 1.17 |
| 15-Oct-2022 |
simonb | Consistency nit: use "__volatile" instead of "volatile" with asm()s.
|
| 1.16 |
| 15-Oct-2022 |
simonb | Add SATP modes for bare, SV57 and SV64.
|
| 1.15 |
| 15-Oct-2022 |
simonb | #define<tab>
|
| 1.14 |
| 10-Sep-2022 |
skrll | Remove unnecessary cast.
|
| 1.13 |
| 01-May-2021 |
skrll | Provide riscvreg_satp_{read,write}
|
| 1.12 |
| 01-May-2021 |
skrll | Indent the FCSR_FRM value #defines
|
| 1.11 |
| 16-Dec-2020 |
christos | branches: 1.11.4;
interupt -> interrupt
|
| 1.10 |
| 04-Nov-2020 |
skrll | Miscellaneous updates to reflect riscv-privileged-20190608.pdf
Some from zmcgrew@
|
| 1.9 |
| 04-Nov-2020 |
skrll | Miscellaneous updates to reflect riscv-privileged-20190608.pdf
Some from zmcgrew@
|
| 1.8 |
| 02-Nov-2020 |
skrll | Add SATP_MODE values
|
| 1.7 |
| 02-Nov-2020 |
skrll | Whitespace
|
| 1.6 |
| 01-Nov-2020 |
skrll | Update CAUSE_* defines to reflect riscv-privileged-20190608.pdf
|
| 1.5 |
| 14-Mar-2020 |
skrll | branches: 1.5.4;
Trailing whitespace
|
| 1.4 |
| 16-Jun-2019 |
maxv | Misc changes in RISC-V.
|
| 1.3 |
| 31-Mar-2015 |
matt | branches: 1.3.16; 1.3.20;
No more fatc (replaced by sfence.vm instruction).
|
| 1.2 |
| 28-Mar-2015 |
matt | Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
|
| 1.1 |
| 19-Sep-2014 |
matt | branches: 1.1.2;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
|
| 1.1.2.1 |
| 06-Apr-2015 |
skrll | Sync with HEAD
|
| 1.3.20.2 |
| 13-Apr-2020 |
martin | Mostly merge changes from HEAD upto 20200411
|
| 1.3.20.1 |
| 08-Apr-2020 |
martin | Merge changes from current as of 20200406
|
| 1.3.16.2 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.3.16.1 |
| 31-Mar-2015 |
jdolecek | file sysreg.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
|
| 1.5.4.2 |
| 03-Jan-2021 |
thorpej | Sync w/ HEAD.
|
| 1.5.4.1 |
| 14-Dec-2020 |
thorpej | Sync w/ HEAD.
|
| 1.11.4.1 |
| 13-May-2021 |
thorpej | Sync with HEAD.
|
