| History log of /src/sys/arch/riscv/include/vmparam.h |
| Revision | | Date | Author | Comments |
| 1.14 |
| 07-May-2023 |
skrll | RISC-V support that works on QEMU with a single hart.
Thanks for Simon Burge for plic(4).
|
| 1.13 |
| 16-Oct-2022 |
skrll | Map the DTB using VM_KERNEL_DTB_BASE and CONSADDR using VM_KERNEL_IO_BASE
|
| 1.12 |
| 15-Oct-2022 |
skrll | Update a comment
|
| 1.11 |
| 12-Oct-2022 |
simonb | Set RISCV_DIRECTMAP_SIZE to 2^64-PAGESIZE, since 2^64 is effectively 0
for a 64bit constant.
Bump VM_PHYSSEG_MAX from 1 to 16.
|
| 1.10 |
| 20-Sep-2022 |
skrll | Checkpoint WIP.
QEMU RV64 virt can boot into virtual mode
OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|
Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3
Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes
Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509
|
| 1.9 |
| 01-May-2021 |
skrll | Fixup some pmap / VM related #defines and code
|
| 1.8 |
| 26-Feb-2021 |
simonb | branches: 1.8.4;
Drop 64-bit default stack sizes back to 4MB.
|
| 1.7 |
| 07-Nov-2020 |
skrll | Use lower case for hex constants
|
| 1.6 |
| 06-Oct-2020 |
christos | branches: 1.6.2;
GC unused MAXTSIZ32
|
| 1.5 |
| 01-Jun-2019 |
maxv | Misc changes in RISC-V. Start changing the memory layout, too.
|
| 1.4 |
| 31-May-2018 |
mrg | branches: 1.4.2;
it's called VM_MAXUSER_ADDRESS32 not VM_MAXUSER32_ADDRESS.
fixes mips64 builds, and likely fixes riscv when it happens again.
|
| 1.3 |
| 24-Jun-2017 |
joerg | branches: 1.3.4; 1.3.6;
Update VM_DEFAULT_ADDRESS32_TOPDOWN to include guard area.
|
| 1.2 |
| 23-Jun-2017 |
joerg | Recommit exec_subr.c revision 1.79:
Always include a 1MB guard area beyond the end of stack. While ASLR will
normally create a guard area as well, this provides a deterministic area
for all binaries.
Mitigates the rest of CVE-2017-1000374 and CVE-2017-1000375 from
Qualys.
Additionally, change VM_DEFAULT_ADDRESS_TOPDOWN to include
user_stack_guard_size in the size reservation.
|
| 1.1 |
| 19-Sep-2014 |
matt | branches: 1.1.2; 1.1.12;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
|
| 1.1.12.1 |
| 31-Aug-2017 |
bouyer | Pull up following revision(s) (requested by joerg in ticket #234):
sys/arch/amd64/include/vmparam.h: revision 1.43
sys/kern/exec_subr.c: revision 1.79
lib/libpthread/pthread_int.h: revision 1.94
sys/arch/mips/include/vmparam.h: revision 1.58
sys/arch/mips/include/vmparam.h: revision 1.59
lib/libpthread/TODO: revision 1.19
sys/arch/powerpc/include/vmparam.h: revision 1.20
sys/arch/riscv/include/vmparam.h: revision 1.2
sys/arch/riscv/include/vmparam.h: revision 1.3
sys/arch/i386/include/vmparam.h: revision 1.85
tests/lib/libpthread/t_join.c: revision 1.9
sys/uvm/uvm_meter.c: revision 1.66
sys/uvm/uvm_param.h: revision 1.36
sys/kern/exec_subr.c: revision 1.80
sys/uvm/uvm_param.h: revision 1.37
sys/kern/exec_subr.c: revision 1.81
sys/kern/exec_subr.c: revision 1.82
lib/libpthread/pthread_attr_getguardsize.3: revision 1.4
lib/libpthread/pthread.c: revision 1.148
lib/libpthread/pthread_attr.c: revision 1.17
sys/arch/amd64/include/vmparam.h: revision 1.42
Always include a 1MB guard area beyond the end of stack. While ASLR will
normally create a guard area as well, this provides a deterministic area
for all binaries.
Mitigates the rest of CVE-2017-1000374 and CVE-2017-1000375 from
Qualys.
Revert for the moment, creates problems on i386.
Recommit exec_subr.c revision 1.79:
Always include a 1MB guard area beyond the end of stack. While ASLR will
normally create a guard area as well, this provides a deterministic area
for all binaries.
Mitigates the rest of CVE-2017-1000374 and CVE-2017-1000375 from
Qualys.
Additionally, change VM_DEFAULT_ADDRESS_TOPDOWN to include
user_stack_guard_size in the size reservation.
Update VM_DEFAULT_ADDRESS32_TOPDOWN to include guard area.
Export the guard size of the main thread via vm.guard_size. Add a
complementary writable sysctl for the initial guard size of threads
created via pthread_create. Let the existing attribut accessors do the
right thing. Raise the default guard size for threads to 64KB.
|
| 1.1.2.1 |
| 28-Aug-2017 |
skrll | Sync with HEAD
|
| 1.3.6.1 |
| 25-Jun-2018 |
pgoyette | Sync with HEAD
|
| 1.3.4.2 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.3.4.1 |
| 24-Jun-2017 |
jdolecek | file vmparam.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
|
| 1.4.2.1 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.6.2.2 |
| 03-Apr-2021 |
thorpej | Sync with HEAD.
|
| 1.6.2.1 |
| 14-Dec-2020 |
thorpej | Sync w/ HEAD.
|
| 1.8.4.1 |
| 13-May-2021 |
thorpej | Sync with HEAD.
|
