| History log of /src/sys/arch/riscv/riscv/bus_dma.c |
| Revision | | Date | Author | Comments |
| 1.11 |
| 26-Sep-2025 |
skrll | risc-v: Adjust barriers issued in bus_dmamap_sync for the coherent case.
PR/59653
This change adjusts the memory barriers issued by bus_dmamap_sync for
the coherent case. In the non-coherent case the CPU cache operations
are expected to provide any, and all required barriers.
These barriers are emitted after bouncing for PREWRITE and before
bouncing for POSTREAD.
Net change:
op old new
|
| 1.10 |
| 02-Mar-2025 |
riastradh | branches: 1.10.2;
riscv/bus_dma: Handle pmap_extract failure.
That is, when the va is not mapped in the pmap.
Otherwise this trips over uninitialized memory, e.g.:
[ 1.0000000] panic: kernel diagnostic assertion "(vaddr & PAGE_MASK) == (curaddr & PAGE_MASK)" failed: file "/tmp/build/2025.02.22.19.09.05-riscv-riscv64/src/sys/arch/riscv/riscv/bus_dma.c", line 1568 va 0xffffffc000a01718 curaddr 0x1
https://releng.netbsd.org/b5reports/riscv-riscv64/2025/2025.02.22.19.09.05/install.log
Perhaps the caller should guarantee that the va is valid, but
(a) for some reason this doesn't work when the va is on the stack,
(b) this is not documented in bus_dma(9), and
(c) if pmap_extract failure should lead to panic then it should do so
intentionally instead of accidentally tripping over a subsequent
assertion.
XXX Do this consistently across bus_dma implementations.
|
| 1.9 |
| 10-Dec-2024 |
skrll | risc-v: bus_dma: Sprinkle error check with __predict_{true,false}.
Apply the same sprinkling of __predict_{true,false} to bus_dmamap_load*(),
and bus_dmamap_sync() that the arm version got to improve performance.
|
| 1.8 |
| 21-Oct-2024 |
skrll | Sync a comment with the arm version.
XXX need to fix the copy pasta
|
| 1.7 |
| 20-Oct-2024 |
skrll | Revert previous - I misread the code.
|
| 1.6 |
| 20-Oct-2024 |
skrll | G/C an unused event counter.
|
| 1.5 |
| 20-Oct-2024 |
skrll | More KNF
|
| 1.4 |
| 20-Oct-2024 |
skrll | Apply the same fix that was applied to the arm version of this.
_bus_dmatag_subregion is always EOPNOTSUPP for !_RISCV_NEED_BUS_DMA_BOUNCE
No need to check {min,max}_addr. Compiler did the right thing, but...
|
| 1.3 |
| 20-Oct-2024 |
skrll | KNF
|
| 1.2 |
| 08-Feb-2024 |
skrll | branches: 1.2.2;
Define _RISCV_NEED_BUS_DMA_BOUNCE.
Pointed out as being needed by jmcneill. Thanks!
|
| 1.1 |
| 07-May-2023 |
skrll | RISC-V support that works on QEMU with a single hart.
Thanks for Simon Burge for plic(4).
|
| 1.2.2.1 |
| 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.10.2.1 |
| 01-Oct-2025 |
martin | Pull up following revision(s) (requested by skrll in ticket #38):
sys/arch/riscv/riscv/bus_dma.c: revision 1.11
risc-v: Adjust barriers issued in bus_dmamap_sync for the coherent case.
PR/59653
This change adjusts the memory barriers issued by bus_dmamap_sync for
the coherent case. In the non-coherent case the CPU cache operations
are expected to provide any, and all required barriers.
These barriers are emitted after bouncing for PREWRITE and before
bouncing for POSTREAD.
Net change:
op old new
|
