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History log of /src/sys/arch/riscv/riscv/vm_machdep.c
RevisionDateAuthorComments
 1.9  04-Aug-2024  skrll spaces to tabs
 1.8  07-May-2023  skrll branches: 1.8.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.7  04-Dec-2022  skrll ASSERT that md_astpending it zero for the new lwp.
 1.6  15-Nov-2022  simonb Use similar macro-magic to aarch64 armreg.h to add per-csr
read/write/set-bits/clear-bits inline functions. Keep the
open-coded 32-bit version of riscvreg_cycle_read() than reads
a 64-bit cycle counter values.

Added benefit of fixing these so that the inline asm uses __volatile
and aren't opmtimised to nops by the compiler.
 1.5  29-Sep-2022  skrll Remove unnecessary include of <sys/malloc.h>.
 1.4  04-Nov-2020  skrll Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@
 1.3  14-Mar-2020  skrll branches: 1.3.4;
Trailing whitespace
 1.2  13-Nov-2019  pgoyette Clean-up unnecessary inclusions of opt_coredump.h
 1.1  28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.22;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.22.2  13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.1.22.1  08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.18.2  03-Dec-2017  jdolecek update from HEAD
 1.1.18.1  28-Mar-2015  jdolecek file vm_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
 1.1.2.2  06-Apr-2015  skrll Sync with HEAD
 1.1.2.1  28-Mar-2015  skrll file vm_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.3.4.1  14-Dec-2020  thorpej Sync w/ HEAD.
 1.8.6.1  02-Aug-2025  perseant Sync with HEAD

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