Cross Reference: /src/sys/arch/riscv/sifive

History log of /src/sys/arch/riscv/sifive
Revision	Date	Author	Comments
1.4	06-Sep-2025	thorpej	Step towards modularizing the Flattened Device Tree code. Define attributes for each of the specific device bindings: clock, dai, dma, gpio, i2c, iommu, mbox, mmc_pwrseq, phy, power, power domain, pwm, regulator, reset controller, spi, system controller, pin controller. Include these support files only if either a provider or consumer with one of these attributes is present in the kernel config. Add the necessary attributes to the device / attach declarations for each provider and consumer. There are some bindings that are consumed by generic code (iommu, pinctrl, power, power domain). Provide weak stubs for these routines to handle situations where there is no provider. No actual code changed; NFCI.
1.3	13-Jan-2024	skrll	risc-v: add a SiFive FU[57]40/ L2 Cache controller driver
1.2	03-Dec-2022	skrll	Trailing whitespace
1.1	25-Nov-2022	jmcneill	Add driver for SiFive FU540 PRCI clock controller.
1.2	14-Jan-2024	skrll	risc-v: the SiFive FU[57]40 cache controller is present in the JH71x0 SoCs.
1.1	13-Jan-2024	skrll	risc-v: add a SiFive FU[57]40/ L2 Cache controller driver
1.1	25-Nov-2022	jmcneill	Add driver for SiFive FU540 PRCI clock controller.

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