| History log of /src/sys/arch/riscv/starfive |
| Revision | Date | Author | Comments |
| 1.12 | 06-Sep-2025 |
thorpej | Step towards modularizing the Flattened Device Tree code.
Define attributes for each of the specific device bindings: clock,
dai, dma, gpio, i2c, iommu, mbox, mmc_pwrseq, phy, power, power domain,
pwm, regulator, reset controller, spi, system controller, pin
controller. Include these support files only if either a provider
or consumer with one of these attributes is present in the kernel
config.
Add the necessary attributes to the device / attach declarations for
each provider and consumer.
There are some bindings that are consumed by generic code (iommu, pinctrl,
power, power domain). Provide weak stubs for these routines to handle
situations where there is no provider.
No actual code changed; NFCI.
|
| 1.11 | 08-Feb-2025 |
skrll | risc-v: add a JH7110 TRNG driver
|
| 1.10 | 03-Jan-2025 |
skrll | risc-v: add a StarFive JH71[01]0 temperature sensor driver
|
| 1.9 | 01-Jan-2025 |
skrll | risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.
Testing as working with xhci and nvme on VisionFive2.
Uses legacy PCI interrupts currently. MSIs to be added later.
pcihost_fdt code is 99% the same as the Arm version and should be shared.
|
| 1.8 | 11-Nov-2024 |
skrll | risc-v: add a specific driver for the JH7110 STG system controller
|
| 1.7 | 11-Nov-2024 |
skrll | risc-v: add a JH7110 PCIe PHY driver
|
| 1.6 | 11-Nov-2024 |
skrll | risc-v: Add initial JH7110 pin controller driver
|
| 1.5 | 26-Oct-2024 |
skrll | risc-v: add ethernet support on JH71[01]0 support
At present only the JH7110 EQOS support is enabled as it work.
The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.
|
| 1.4 | 27-Jul-2024 |
skrll | risc-v: split the jh7100 clock controller driver
In preparation for the JH7110 clock driver split the clock definition
and attachment code from the clock handling macros / methods.
|
| 1.3 | 07-Feb-2024 |
skrll | branches: 1.3.2;
risc-v: add a driver the JH7100 pin controller
|
| 1.2 | 18-Jan-2024 |
skrll | risc-v: attach the Cadence XHCI usb controller on the JH7100 SoC
|
| 1.1 | 16-Jan-2024 |
skrll | risc-v: add a StarTech JH7100 SoC clock driver
The JH7100 is seen in the Beagle-V board.
|
| 1.3.2.1 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.6 | 18-Jan-2025 |
skrll | risc-v: StarFive JH7100: add the temperature sensor clocks to the clock driver
|
| 1.5 | 18-Jan-2025 |
skrll | risc-v: add support for the StarFive JH7100 audio clocks
|
| 1.4 | 18-Sep-2024 |
skrll | #define<space> consistency
|
| 1.3 | 27-Jul-2024 |
skrll | risc-v: split the jh7100 clock controller driver
In preparation for the JH7110 clock driver split the clock definition
and attachment code from the clock handling macros / methods.
|
| 1.2 | 17-Jan-2024 |
skrll | branches: 1.2.2;
Implement jh7100_clkc_fracdiv_get_rate
|
| 1.1 | 16-Jan-2024 |
skrll | risc-v: add a StarTech JH7100 SoC clock driver
The JH7100 is seen in the Beagle-V board.
|
| 1.2.2.1 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.3 | 27-Jul-2024 |
skrll | risc-v: split the jh7100 clock controller driver
In preparation for the JH7110 clock driver split the clock definition
and attachment code from the clock handling macros / methods.
|
| 1.2 | 17-Jan-2024 |
skrll | branches: 1.2.2;
Fix types of constants
|
| 1.1 | 16-Jan-2024 |
skrll | risc-v: add a StarTech JH7100 SoC clock driver
The JH7100 is seen in the Beagle-V board.
|
| 1.2.2.1 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.1 | 26-Oct-2024 |
skrll | branches: 1.1.4;
risc-v: add ethernet support on JH71[01]0 support
At present only the JH7110 EQOS support is enabled as it work.
The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.
|
| 1.1.4.2 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.1.4.1 | 26-Oct-2024 |
perseant | file jh7100_gmac.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
|
| 1.3 | 18-Sep-2024 |
skrll | #define<space> consistency
|
| 1.2 | 08-Feb-2024 |
skrll | branches: 1.2.2;
Some fixes from Roland Illig
- fix a locking bug
- '\n' at the end of error messages
|
| 1.1 | 07-Feb-2024 |
skrll | risc-v: add a driver the JH7100 pin controller
|
| 1.2.2.1 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.8 | 17-Jan-2025 |
skrll | branches: 1.8.4;
risc-v: Don't attach the JH7110 ISP clock controller
Something isn't quite right with the ISP clock controller and it causes
problems with sysctl -A. As it's not currently used don't attach it.
|
| 1.7 | 17-Jan-2025 |
skrll | Order the clock controllers consistently. NFC.
|
| 1.6 | 20-Sep-2024 |
rin | riscv/jh7110_clkc: Missing <sys/kmem.h> include
|
| 1.5 | 18-Sep-2024 |
skrll | risc-v: add reset support to the JH7110 SOC clock controller driver
|
| 1.4 | 18-Sep-2024 |
skrll | Match "Image-Signal-Process" clock controller and only aprint_debug the
state of "System" and "Always-On" clocks.
|
| 1.3 | 18-Sep-2024 |
skrll | #define<space> consistency
|
| 1.2 | 09-Sep-2024 |
skrll | Whitespace
|
| 1.1 | 19-Aug-2024 |
skrll | Add a clock driver for the JH7110 SoC found in the StarFive VisionFive 2
SBC.
It's not fully functional as something is wrong for the
Image-Signal-Process controller which is why it's #if 0'd out.
|
| 1.8.4.2 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.8.4.1 | 17-Jan-2025 |
perseant | file jh7110_clkc.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
|
| 1.2 | 17-Nov-2024 |
skrll | branches: 1.2.4;
Miscellaneous cleanup.
|
| 1.1 | 26-Oct-2024 |
skrll | risc-v: add ethernet support on JH71[01]0 support
At present only the JH7110 EQOS support is enabled as it work.
The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.
|
| 1.2.4.2 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.2.4.1 | 17-Nov-2024 |
perseant | file jh7110_eqos.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
|
| 1.2 | 09-Jan-2025 |
skrll | branches: 1.2.4;
Fix error reporting to not include two ": "
|
| 1.1 | 01-Jan-2025 |
skrll | risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.
Testing as working with xhci and nvme on VisionFive2.
Uses legacy PCI interrupts currently. MSIs to be added later.
pcihost_fdt code is 99% the same as the Arm version and should be shared.
|
| 1.2.4.2 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.2.4.1 | 09-Jan-2025 |
perseant | file jh7110_pcie.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
|
| 1.3 | 01-Jan-2025 |
skrll | branches: 1.3.4;
spaces to tab
|
| 1.2 | 12-Nov-2024 |
skrll | Remove #if 0 / #endif blocks
|
| 1.1 | 11-Nov-2024 |
skrll | risc-v: add a JH7110 PCIe PHY driver
|
| 1.3.4.2 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.3.4.1 | 01-Jan-2025 |
perseant | file jh7110_pciephy.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
|
| 1.1 | 11-Nov-2024 |
skrll | branches: 1.1.4;
risc-v: Add initial JH7110 pin controller driver
|
| 1.1.4.2 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.1.4.1 | 11-Nov-2024 |
perseant | file jh7110_pinctrl.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
|
| 1.1 | 11-Nov-2024 |
skrll | branches: 1.1.4;
risc-v: add a specific driver for the JH7110 STG system controller
|
| 1.1.4.2 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.1.4.1 | 11-Nov-2024 |
perseant | file jh7110_syscon.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
|
| 1.2 | 09-Feb-2025 |
skrll | branches: 1.2.4;
risc-v: JH7110 TRNG aprint_verbose the features and build conf registers
|
| 1.1 | 08-Feb-2025 |
skrll | risc-v: add a JH7110 TRNG driver
|
| 1.2.4.2 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.2.4.1 | 09-Feb-2025 |
perseant | file jh7110_trng.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
|
| 1.4 | 18-Sep-2024 |
skrll | branches: 1.4.4;
#define<space> consistency
|
| 1.3 | 19-Aug-2024 |
skrll | Add a clock driver for the JH7110 SoC found in the StarFive VisionFive 2
SBC.
It's not fully functional as something is wrong for the
Image-Signal-Process controller which is why it's #if 0'd out.
|
| 1.2 | 04-Aug-2024 |
skrll | spaces to tabs
|
| 1.1 | 27-Jul-2024 |
skrll | risc-v: split the jh7100 clock controller driver
In preparation for the JH7110 clock driver split the clock definition
and attachment code from the clock handling macros / methods.
|
| 1.4.4.2 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.4.4.1 | 18-Sep-2024 |
perseant | file jh71x0_clkc.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
|
| 1.5 | 12-Oct-2024 |
skrll | branches: 1.5.4;
Consistency of #define<space>
|
| 1.4 | 18-Sep-2024 |
skrll | risc-v: add reset support to the JH7110 SOC clock controller driver
|
| 1.3 | 25-Aug-2024 |
skrll | Whitespace
|
| 1.2 | 19-Aug-2024 |
skrll | Add a clock driver for the JH7110 SoC found in the StarFive VisionFive 2
SBC.
It's not fully functional as something is wrong for the
Image-Signal-Process controller which is why it's #if 0'd out.
|
| 1.1 | 27-Jul-2024 |
skrll | risc-v: split the jh7100 clock controller driver
In preparation for the JH7110 clock driver split the clock definition
and attachment code from the clock handling macros / methods.
|
| 1.5.4.2 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.5.4.1 | 12-Oct-2024 |
perseant | file jh71x0_clkc.h was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
|
| 1.1 | 26-Oct-2024 |
skrll | branches: 1.1.4;
risc-v: add ethernet support on JH71[01]0 support
At present only the JH7110 EQOS support is enabled as it work.
The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.
|
| 1.1.4.2 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.1.4.1 | 26-Oct-2024 |
perseant | file jh71x0_eth.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
|
| 1.1 | 26-Oct-2024 |
skrll | branches: 1.1.4;
risc-v: add ethernet support on JH71[01]0 support
At present only the JH7110 EQOS support is enabled as it work.
The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.
|
| 1.1.4.2 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.1.4.1 | 26-Oct-2024 |
perseant | file jh71x0_eth.h was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
|
| 1.1 | 03-Jan-2025 |
skrll | branches: 1.1.4;
risc-v: add a StarFive JH71[01]0 temperature sensor driver
|
| 1.1.4.2 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.1.4.1 | 03-Jan-2025 |
perseant | file jh71x0_temp.c was added on branch perseant-exfatfs on 2025-08-02 05:56:05 +0000
|
| 1.3 | 18-Sep-2024 |
skrll | #define<space> consistency
|
| 1.2 | 25-Aug-2024 |
skrll | spaces to tab
|
| 1.1 | 18-Jan-2024 |
skrll | branches: 1.1.2;
risc-v: attach the Cadence XHCI usb controller on the JH7100 SoC
|
| 1.1.2.1 | 02-Aug-2025 |
perseant | Sync with HEAD
|
