Step towards modularizing the Flattened Device Tree code.

Define attributes for each of the specific device bindings: clock,
dai, dma, gpio, i2c, iommu, mbox, mmc_pwrseq, phy, power, power domain,
pwm, regulator, reset controller, spi, system controller, pin
controller. Include these support files only if either a provider
or consumer with one of these attributes is present in the kernel
config.

Add the necessary attributes to the device / attach declarations for
each provider and consumer.

There are some bindings that are consumed by generic code (iommu, pinctrl,
power, power domain). Provide weak stubs for these routines to handle
situations where there is no provider.

No actual code changed; NFCI.

risc-v: add a JH7110 TRNG driver

risc-v: add a StarFive JH71[01]0 temperature sensor driver

risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.

risc-v: add a specific driver for the JH7110 STG system controller

risc-v: add a JH7110 PCIe PHY driver

risc-v: Add initial JH7110 pin controller driver

risc-v: add ethernet support on JH71[01]0 support

At present only the JH7110 EQOS support is enabled as it work.

The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.

risc-v: split the jh7100 clock controller driver

In preparation for the JH7110 clock driver split the clock definition
and attachment code from the clock handling macros / methods.

branches: 1.3.2;
risc-v: add a driver the JH7100 pin controller

risc-v: attach the Cadence XHCI usb controller on the JH7100 SoC

risc-v: add a StarTech JH7100 SoC clock driver

The JH7100 is seen in the Beagle-V board.

risc-v: StarFive JH7100: add the temperature sensor clocks to the clock driver

risc-v: add support for the StarFive JH7100 audio clocks

#define<space> consistency

risc-v: split the jh7100 clock controller driver

In preparation for the JH7110 clock driver split the clock definition
and attachment code from the clock handling macros / methods.

branches: 1.2.2;
Implement jh7100_clkc_fracdiv_get_rate

risc-v: add a StarTech JH7100 SoC clock driver

The JH7100 is seen in the Beagle-V board.

risc-v: split the jh7100 clock controller driver

In preparation for the JH7110 clock driver split the clock definition
and attachment code from the clock handling macros / methods.

branches: 1.2.2;
Fix types of constants

risc-v: add a StarTech JH7100 SoC clock driver

The JH7100 is seen in the Beagle-V board.

branches: 1.1.4;
risc-v: add ethernet support on JH71[01]0 support

At present only the JH7110 EQOS support is enabled as it work.

The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.

#define<space> consistency

branches: 1.2.2;
Some fixes from Roland Illig
- fix a locking bug
- '\n' at the end of error messages

risc-v: add a driver the JH7100 pin controller

branches: 1.8.4;
risc-v: Don't attach the JH7110 ISP clock controller

Something isn't quite right with the ISP clock controller and it causes
problems with sysctl -A. As it's not currently used don't attach it.

Order the clock controllers consistently. NFC.

riscv/jh7110_clkc: Missing <sys/kmem.h> include

risc-v: add reset support to the JH7110 SOC clock controller driver

Match "Image-Signal-Process" clock controller and only aprint_debug the
state of "System" and "Always-On" clocks.

#define<space> consistency

Whitespace

Add a clock driver for the JH7110 SoC found in the StarFive VisionFive 2
SBC.

It's not fully functional as something is wrong for the
Image-Signal-Process controller which is why it's #if 0'd out.

branches: 1.2.4;
Miscellaneous cleanup.

risc-v: add ethernet support on JH71[01]0 support

At present only the JH7110 EQOS support is enabled as it work.

The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.

branches: 1.2.4;
Fix error reporting to not include two ": "

risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.

branches: 1.3.4;
spaces to tab

Remove #if 0 / #endif blocks

risc-v: add a JH7110 PCIe PHY driver

branches: 1.1.4;
risc-v: Add initial JH7110 pin controller driver

branches: 1.1.4;
risc-v: add a specific driver for the JH7110 STG system controller

branches: 1.2.4;
risc-v: JH7110 TRNG aprint_verbose the features and build conf registers

risc-v: add a JH7110 TRNG driver

branches: 1.4.4;
#define<space> consistency

Add a clock driver for the JH7110 SoC found in the StarFive VisionFive 2
SBC.

It's not fully functional as something is wrong for the
Image-Signal-Process controller which is why it's #if 0'd out.

spaces to tabs

risc-v: split the jh7100 clock controller driver

In preparation for the JH7110 clock driver split the clock definition
and attachment code from the clock handling macros / methods.

branches: 1.5.4;
Consistency of #define<space>

risc-v: add reset support to the JH7110 SOC clock controller driver

Whitespace

Add a clock driver for the JH7110 SoC found in the StarFive VisionFive 2
SBC.

It's not fully functional as something is wrong for the
Image-Signal-Process controller which is why it's #if 0'd out.

risc-v: split the jh7100 clock controller driver

In preparation for the JH7110 clock driver split the clock definition
and attachment code from the clock handling macros / methods.

branches: 1.1.4;
risc-v: add ethernet support on JH71[01]0 support

At present only the JH7110 EQOS support is enabled as it work.

The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.

branches: 1.1.4;
risc-v: add ethernet support on JH71[01]0 support

At present only the JH7110 EQOS support is enabled as it work.

The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.

branches: 1.1.4;
risc-v: add a StarFive JH71[01]0 temperature sensor driver

#define<space> consistency

spaces to tab

branches: 1.1.2;
risc-v: attach the Cadence XHCI usb controller on the JH7100 SoC