Cross Reference: /src/sys/arch/riscv/starfive/jh71x0

History log of /src/sys/arch/riscv/starfive/jh71x0_clkc.h
Revision	Date	Author	Comments
1.5	12-Oct-2024	skrll	Consistency of #define<space>
1.4	18-Sep-2024	skrll	risc-v: add reset support to the JH7110 SOC clock controller driver
1.3	25-Aug-2024	skrll	Whitespace
1.2	19-Aug-2024	skrll	Add a clock driver for the JH7110 SoC found in the StarFive VisionFive 2 SBC. It's not fully functional as something is wrong for the Image-Signal-Process controller which is why it's #if 0'd out.
1.1	27-Jul-2024	skrll	risc-v: split the jh7100 clock controller driver In preparation for the JH7110 clock driver split the clock definition and attachment code from the clock handling macros / methods.

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