Reduce amount of -no-integrated-as on x86 as .code16 is now supported by
LLVM.

branches: 1.8.2; 1.8.12; 1.8.16;
fix typo, revert to previous version

revert previous; bug was in the position of the inclusion of the file.

Don't depend on the .d file here; since this is the only rule, acpi_wakeup.d
will never be build!

LLVM's assembler parser doesn't support .code32 yet, so disable it as
needed.

branches: 1.4.2; 1.4.6; 1.4.8;
Use sed, awk and hexdump from tools to make this work on Solaris. Ok by apb.

branches: 1.3.4; 1.3.6; 1.3.16; 1.3.24; 1.3.26;
MAKEVERBOSE support

branches: 1.2.2;
How did these get lost?

branches: 1.1.2; 1.1.8; 1.1.10; 1.1.12;
file Makefile.wakecode.inc was initially added on branch jmcneill-pm.

Normalize some machine dependent CPU frequenct sysctl variables.

This moves machdep.*.frequency.* to machdep.cpu.frequency.*.

This was proposed on tech-kern some time ago. The intention is to allow
third-party tools such as estd and conky to more easily and reliably
fetch or modify the current CPU frequency without iterating through
various machine-dependent variables to check their presence.

PR kern/55080: current does not boot

Back out previous. To be addressed differently.

Put ACPI idle under ACPICPU_ENABLE_C3 until the wrinkles are ironed out.
This seems well written and basically all good, but currently doesn't enter
a low power state, and imposes a big performance penalty. Proposed on
port-i386 & port-amd64.

Add the __nocsan attribute on this function. Races on ci_want_resched are
accepted (part of the design).

xc_barrier - convenience function to xc_broadcast() a nop.

Make the intent more clear and also avoid a bunch of (xcfunc_t)nullop
casts that gcc 8 -Wcast-function-type is not happy about.

Remove unused cpu_msr.h includes.

branches: 1.78.14; 1.78.16;
Add a synthesized pc beeper and keyboard bell for platforms with an audio
device.

branches: 1.77.4; 1.77.8;
CID/1203191: Out of bounds read

branches: 1.76.2;
correct/add protection against snprintf overflow.

Make new function named tsc_is_invariant() to avoid code duplication.
The behavior of acpicpu_md_flags() will change on some CPUs because
the detecting code of invariant TSC is replaced with newer code.

Allow 4-bit range for MSR_THERM_CONTROL.

Modify some macros and add some new macros for CPU family and model
to reduce code duplication and to avoid bug.

CPUID_TO_STEPPING(cpuid) (not changed)

CPUID_TO_FAMILY(cpuid) (new)
CPUID_TO_MODEL(cpuid) (new)

Return the display family and the display model.
The macro names are the same as FreeBSD.

CPUID_TO_BASEFAMILY(cpuid) (The old name was CPUID2FAMILY)
CPUID_TO_BASEMODEL(cpuid) (The old name was CPUID2MODEL)

Only for the base field.

CPUID_TO_EXTFAMILY(cpuid) (The old name was CPUID2EXTFAMILY)
CPUID_TO_EXTMODEL(cpuid) (The old name was CPUID2EXTMODEL)

Only for the extended field.

See http://mail-index.netbsd.org/port-amd64/2013/11/12/msg001978.html

branches: 1.72.2;
Disable C1E also on K8, if present. From Imre Vadasz <imre@vdsz.com>
in PR install/47224.

branches: 1.71.2; 1.71.6; 1.71.8;
Fix missing case for AMD 0x15.

Add non-XPSS support for AMD family 15h a.k.a. "Bulldozer". Ok releng@.

branches: 1.69.4;
Add support for AMD family 12h. Also revert revision 1.67, as it implies
maintenance burden for limited value. XXX: Need to add family 15h too.

branches: 1.68.2;
Convert to use cpufreq(9).

Try to obtain reliable MHz values for AMD familiesi 10h and 11h.

Be more intelligent; read the MSR_CMPHALT with rdmsr_safe() and set the
C1E-flag based on this. Pointed out by jmcneill@.

As the detection of C1E is not entirely clear-cut, use rdmsr_safe()
when reading the AMD "interrupt pending and CMP-halt register".

Do not disable interrupts at machine-level in the MI idle-loop entry.

Fix bug pointed out by njoly@.

Get rid of RUN_ONCE(9). Should fix PR # kern/44043.

Move the evaluation of the _PDC control method out from the acpicpu(4)
driver to the main acpi(4) stack. Follow Linux and evaluate it early.
Should fix PR port-amd64/42895, possibly also PR kern/42583, and many
other comparable bugs.

A common sense explanation is that Intel supplies additional CPU tables to
OEMs. BIOS writers do not bother to modify their DSDTs, but instead load
these extra tables dynamically as secondary SSDT tables. The actual Load()
happens when the _PDC method is invoked, and thus namespace errors occur
when the CPU-specific ACPI methods are not yet present but referenced in the
AML by various drivers, including, but not limited to, acpitz(4).

When getting the frequency, use APERF/MPERF as a fallback method.

branches: 1.59.2;
Remove the sanity check that tested the internal consistency of the "FID/VID
algorithm" used by K8. Tested by cegger@. The check is still included in the
original powernow(4) (where possible failures have probably gone unnoticed
because the driver is less noisy).

Neither pci_dma64_available(), pci_probe_device(), pci_mapreg_map(9),
pci_find_rom(), pci_intr_map(9), pci_enumerate_bus(), nor the match
predicate passed to pciide_compat_intr_establish() should ever modify
their pci_attach_args argument, so make their pci_attach_args arguments
const and deal with the fallout throughout the kernel.

For the most part, these changes add a 'const' where there was no
'const' before, however, some drivers and MD code used to modify
pci_attach_args. Now those drivers either copy their pci_attach_args
and modify the copy, or refrain from modifying pci_attach_args:

Xen: according to Manuel Bouyer, writing to pci_attach_args in
pci_intr_map() was a leftover from Xen 2. Probably a bug. I
stopped writing it. I have not tested this change.

siside(4): sis_hostbr_match() needlessly wrote to pci_attach_args.
Probably a bug. I use a temporary variable. I have not tested this
change.

slide(4): sl82c105_chip_map() overwrote the caller's pci_attach_args.
Probably a bug. Use a local pci_attach_args. I have not tested
this change.

viaide(4): via_sata_chip_map() and via_sata_chip_map_new() overwrote the
caller's pci_attach_args. Probably a bug. Make a local copy of the
caller's pci_attach_args and modify the copy. I have not tested
this change.

While I'm here, make pci_mapreg_submap() static.

With these changes in place, I have tested the compilation of these
kernels:

alpha GENERIC
amd64 GENERIC XEN3_DOM0
arc GENERIC
atari HADES MILAN-PCIIDE
bebox GENERIC
cats GENERIC
cobalt GENERIC
evbarm-eb NSLU2
evbarm-el ADI_BRH ARMADILLO9 CP3100 GEMINI GEMINI_MASTER GEMINI_SLAVE GUMSTIX
HDL_G IMX31LITE INTEGRATOR IQ31244 IQ80310 IQ80321 IXDP425 IXM1200
KUROBOX_PRO LUBBOCK MARVELL_NAS NAPPI SHEEVAPLUG SMDK2800 TEAMASA_NPWR
TEAMASA_NPWR_FC TS7200 TWINTAIL ZAO425
evbmips-el AP30 DBAU1500 DBAU1550 MALTA MERAKI MTX-1 OMSAL400 RB153 WGT624V3
evbmips64-el XLSATX
evbppc EV64260 MPC8536DS MPC8548CDS OPENBLOCKS200 OPENBLOCKS266
OPENBLOCKS266_OPT P2020RDB PMPPC RB800 WALNUT
hp700 GENERIC
i386 ALL XEN3_DOM0 XEN3_DOMU
ibmnws GENERIC
macppc GENERIC
mvmeppc GENERIC
netwinder GENERIC
ofppc GENERIC
prep GENERIC
sandpoint GENERIC
sgimips GENERIC32_IP2x
sparc GENERIC_SUN4U KRUPS
sparc64 GENERIC

As of Sun Apr 3 15:26:26 CDT 2011, I could not compile these kernels
with or without my patches in place:

### evbmips-el GDIUM

nbmake: nbmake: don't know how to make /home/dyoung/pristine-nbsd/src/sys/arch/mips/mips/softintr.c. Stop

### evbarm-el MPCSA_GENERIC
src/sys/arch/evbarm/conf/MPCSA_GENERIC:318: ds1672rtc*: unknown device `ds1672rtc'

### ia64 GENERIC

/tmp/genassym.28085/assym.c: In function 'f111':
/tmp/genassym.28085/assym.c:67: error: invalid application of 'sizeof' to incomplete type 'struct pcb'
/tmp/genassym.28085/assym.c:76: error: dereferencing pointer to incomplete type

### sgimips GENERIC32_IP3x

crmfb.o: In function `crmfb_attach':
crmfb.c:(.text+0x2304): undefined reference to `ddc_read_edid'
crmfb.c:(.text+0x2304): relocation truncated to fit: R_MIPS_26 against `ddc_read_edid'
crmfb.c:(.text+0x234c): undefined reference to `edid_parse'
crmfb.c:(.text+0x234c): relocation truncated to fit: R_MIPS_26 against `edid_parse'
crmfb.c:(.text+0x2354): undefined reference to `edid_print'
crmfb.c:(.text+0x2354): relocation truncated to fit: R_MIPS_26 against `edid_print'

Reset APERF and MPERF only after interrupts have been enabled.

Remove the "simple CPU lock" that was unnecessary.
Thanks to rmind@ for clarifications.

branches: 1.55.2;
Add __cpu_simple_lock_t. Use it, x86_read_psl(), and x86_disable_intr() to
disable interrupts locally and protect the access to APERF and MPERF. Also
rationalize the MD initialization sequence.

If the P-state control mask is set, do a proper read-modify-write.

Rename a badly named constant. Make it correspond with <x86/specialreg.h>.

Adjust the detection of Turbo Boost to prevent a theoretical array OOB access.

Append Intel's Turbo Boost to the debug printfs if we detect it.

Remove the cross-call from the APERF/MPERF -function.

Move the xcall(9) that does the P- and T-state transformations from the MD
layer to the main code. Makes the caches coherent and provides consistent
vmstat(1) output. This is still not quite right, given that most of the
cross-calls are typically unnecessary with the dependency coordination.

Provide MD wrappers for match and attach.

Claim to support the dependency coordination during the _PDC/_OSC query.
(Although we do not actually support it.) Only after these bits are set,
many Intel-based BIOSes are willing to relinquish the necessary information.

Fix an oversight; the APERF and MPERF counters are per-CPU, so also reset
these by broadcasting to all CPUs with x86_msr_xcall(9).

Add couple of comments.

Also declare support for APERF/MPERF during the BIOS _PDC/_OSC query.

Rename couple of badly named functions for consistency. No functional change.

Add support for APERF and MPERF on AMD processors.

Add preliminary support for the IA32_APERF and IA32_MPERF frequency counters.
These are not yet used for anything and only Intel is supported at the moment.

add support for Family 14h (AMD Fusion)

Fix and add comments.

branches: 1.38.2; 1.38.4;
Move the function that counts the CPUs from acpicpu(4) to the MD layer.

Add an additional assertion for the control MSR address.

Fix boolean brain freeze.

Add AMD C1E quirk. Tested by cegger@.

(a) This should be removed once C-states are supported.

(b) As there seems to be no reliable way to detect whether C1E is present,
the quirk blindly assumes that C1E is used on families 10h and 11h.

branches: 1.34.2;
Add definitions for Intel Digital Thermal Sensor and Power Management, at
CPUID Fn0000_0006, %eax, %ecx. Use these instead of magic numbers.

As all reported P-state failures so far have centered around the status-
check (today it was christos@' laptop), follow Linux and disable this rather
expensive sanity-check for the time being. A hypothesis about the cause of
the failures relates to the absence of cross-CPU coordination in the current
implementation.

Add native support for AMD family 0Fh processors. This is the furthest we
will go backwards; K7 will not be supported already due doubts about
availability and reliability of ACPI during that era. Some unfortunate code
duplication is present (but not overly much). Thanks to cegger@ and jakllsch@
for patiently testing this.

Other entry points beyond x86_cpu_idle_halt() may use HLT as the
idle-mechanism. Send an IPI also for these in cpu_need_resched().

Still DELAY(9) a little even when we do not do the status-check.

After discussion with jakllsch@ and jmcneill@, revert the previous and only
do the status-check when the comparison value reported by BIOS is not zero.
The uncertainty noted in the previous commit still applies. But if we ever
see a timeout again, it will likely be either a firmware bug or a special
case like the Intel Turbo Boost.

When we do the sanity check that a P- or T-state transition was successful,
compare also against the control-field. There appears to be many BIOSes in
the field that report a zero value in the status-field. It is unclear whether
this should be taken as a hint that the status-check is not necessary also
during P-state transitions. If we still see timeouts (EAGAIN), this should
be reverted and the status-check should be bypassed if ps->ps_status is 0.

Use an inverse logic when filling the (X)PSS structures -- if we know
the addresses, we trust ourselves more than a random BIOS in the field.

Add a comment.

Check from CPUID 0x06 %eax (on Intel) whether we might actually have an
invariant APIC timer or an "ARAT" ("always running APIC timer"). This means
that the APIC timer may keep ticking at the same rate also in deep C-states
with some new or forthcoming Intel CPUs.

Add a quirk for Turbo Boost.

It was observed that at least Sverre Froyen's ThinkPad T500 reports values
that do not match readings from the IA32_PERF_STATUS register. This only
applied to the P0-state. Thus, for now, skip the status check if Turbo
Boost has been detected and the requested state is P0.

This needs to be revisited once Turbo Boost actually works in NetBSD. It is
unclear whether this is a BIOS flaw or not; these values may well be what we
get from IA32_PERF_STATUS once the CPU actually uses the +133.33 MHz boost.

Detect Intel's Turbo Boost and presence of IA32_APERF/IA32_MPERF. The former
is required for a quirk, and the latter is needed for hardware P-state
coordination (once acpicpu(4) will support fine-grained coordination).

Detect whether TSC is invariant, which may be the case on both new AMD and
Intel processors. The invariance means that TSC runs at a constant rate
during all ACPI state changes. If it is variant, skew may occur and TSC is
generally unsuitable for wall clock services. This is especially relevant
with C-states; with variant TSC, the whole counter may be stopped with states
larger than C1. All x86 CPUs before circa mid-2000s can be assumed to have a
variant time stamp counter.

Properly detect AMD hardware P-state support. Also detect "core boost" (only
present in some models of family 10h).

Check if SpeedStep is enabled. If it is disabled, try to enable it.

Revert all previous changes that were made naively believing that the
existing CPU power management implementations could peacefully coexist with
the acpicpu(4) driver. The following options can not be used with acpicpu(4):
ENHANCED_SPEEDSTEP, INTEL_ONDEMAND_CLOCKMOD, POWERNOW_K7, and POWERNOW_K8.

Properly calculate the AMD CPU family.

Add native P-state support for AMD family 10h and 11h processors. Both are
supported irrespective of XPSS. Family 10h tested by jakllsch@.

VIA CPUs can have EST as well, so treat them the same as Intel

Use the idea from cegger@ and fill the (X)PSS structure during initialization.

Check the status of P- and T-state transformations on all CPUs. This is
still not ideal, as ACPI gives us information about "cross logical processor
dependencies". For instance, a single MSR call on one CPU may cause all other
CPUs in the same domain to follow the state shift. Thus, rather than using
xc_broadcast(9), we should xc_unicast(9) on per-domain or per-CPU-set basis.

Add MD support for the vendor-independent extended PSS. Some conforming AMD
systems are known to work. Alas, not all of them. We still need to deal with
the variety of different PowerNow! revisions.

branches: 1.12.2;
Move the PIIX4-quirk to the MD file and disable T-states for PIIX4.

Remove some unnecessary locking. Mainly a leftover from previous revisions
where the dynamic maximum/minimum was used also when retrieving the current
state. The state-array itself changes only in C-states.

Merge T-state a.k.a. throttling support for acpicpu(4).

Remarks:

1. Native instructions are supported only on Intel. Native support for
other x86 vendors will be investigated. By assumption, AMD and others
use the I/O based approach.

2. The existing code, INTEL_ONDEMAND_CLOCKMOD, must be disabled in
order to use acpicpu(4). Otherwise fatal MSR races may occur.
Unlike with P-states, no attempt is done to disable the existing
implementation.

3. There is no rationale to export controls to user land.

4. Throttling is an artefact from the past. T-states will not be used for
power management per se. For CPU frequency management, P-states are
preferred in all circumstances. No noticeable additional power savings
were observed in various experiments. When the system has been scaled
to the highest (i.e. lowest power) P-state, it is preferable to move
from C0 to deeper C-states than it is to actively throttle the CPU.

5. But T-states need to be implemented for passive cooling via acpitz(4).
As specified by ACPI and Intel documents, these can be used as the
last line of defence against critical thermal conditions. Support
for this will be added later.

branches: 1.9.2;
Revert the previous changes to EST. The used hack had an obvious flaw:
the acpicpu(4) driver should attach even if the existing frequency management
code fails to attach, mainly because ACPI is the only proper way to deal
with EST on new Intel system.

Use a more drastic hack to deal with this: when acpicpu(4) attachs, it tears
down any existing sysctl(8) controls and installs identical ones in place.
Upon detachment, the initialization function of the existing EST is called.

Remove a redundant function.

When retrieving the current frequency, scan all available P-states.
Only use the dynamic maximum when setting a frequency.

Move the sysctl function pointers used by acpicpu(4) to x86/cpu.c.
Rename these so that the same pointers may be used in other parts.

Merge P-state support for acpicpu(4).

Remarks:

1. All processors (x86 or not) for which the vendor has implemented
ACPI I/O access routines are supported. Native instructions are
currently supported only for Intel's "Enhanced Speedstep". Code for
"PowerNow!" (AMD) will be merged later. Native support for VIA's
"PowerSaver" will be investigated.

2. Backwards compatibility with existing userland code is maintained.
Comparable to the case with cpu_idle(9), the ACPI CPU driver
installs alternative functions for the existing sysctl(8) controls.
The "native" behavior (if any) is restored upon detachment.

3. The dynamic nature of ACPI-provided P-states needs more investigation.
The maximum frequency induced (but not forced) by the firmware may
change dynamically. Currently, the sysctl(8) controls error out with
a value larger than the dynamic maximum. The code itself does not
however yet react to the notifications from the firmware by changing
the frequencies in-place. Presumably the system administrator should
be able to choose whether to use dynamic or static frequencies.

Run a xcall(9) to ensure that all CPUs are out from the ACPI idle-loop
before detachment.

Make sure we use MWAIT with MONITOR.

Also clarify when we have interrupts disabled.

Add missing CVS identifiers.

Merge a driver for ACPI CPUs with basic support for processor power states,
also known as C-states. The code is modular and provides an easy way to add
the remaining functionality later (namely throttling and P-states).

Remarks:

1. Commented out in the GENERICs; more testing exposure is needed.

2. The C3-state is disabled for the time being because it turns off
timers, among them the local APIC timer. This may not be universally
true on all x86 processors; define ACPICPU_ENABLE_C3 to test.

3. The algorithm used to choose a power state may need tuning. When
evaluating the appropriate state, the implementation uses the
previous sleep time as an indicator. Additional hints would include
for example the system load.

Also bus master activity is evaluated when choosing a state. The
usb(4) stack is notorious for such activity even when unused.
Typically it must be disabled in order to reach the C3-state,
but it may also prevent the use of C2.

4. While no extensive empirical measurements have been carried out, the
power savings are somewhere between 1-2 W with C1 and C2, depending
on the processor, firmware, and load. With C3 even up to 4 W can be
saved. The less something ticks, the more power is saved.

ok jmcneill@, joerg@, and discussed with various people.

x86: Wire up PCI resource manager if enabled.

Enable in your kernel config with `options PCI_RESOURCE'.

Adapted from a patch by mlelstv@.

PR port-amd64/59118: Thinkpad T495s - iwm PCI BAR is zero

branches: 1.39.2;
Introduce pvh_boot boolean to identify the real hypervisor when booting in PVH
mode.

As of now, sys/arch/x86/x86/identcpu.c / identify_hypervisor() returns in the
case of vm_guest being VM_GUEST_GENPVH, yet this VM type is not an actual
hypervisor but an information recorded in locore.S to drive boot method.
We need to investigate what type of hypervisor is really running the VM in
order to apply specifics, so instead of relying on vm_guest_is_pvh() which only
checks for VM_GUEST_XENPVH || VM_GUEST_GENPVH, pvh_boot informs on the boot
method while allowing to identify the real hypervisor.

Idea ok'd by bouyer@, tested on Xen domU, Xen dom0 with GENERIC PVH and
qemu GENERIC PVH boot.

Introduce vm_guest_is_pvh() and use it in place of
(vm_guest == VM_GUEST_XENPVH || vm_guest == VM_GUEST_GENPVH)

Add support for non-Xen PVH guests to amd64. Patch from
Emile 'iMil' Heitor in PR kern/57813, with some cosmetic tweaks by me.
Tested on bare metal, Xen PV and Xen PVH by me.

branches: 1.36.6;
Declare
int acpi_md_vesa_modenum;
int acpi_md_vbios_reset;
struct vcons_screen x86_genfb_console_screen;

in genfb_machdep.h instead of locally as extern in various .c files.

x86/acpi/acpi_machdep.c: Nix trailing whitespace.

No functional change intended.

branches: 1.34.2;
x86/acpi: Mark acpica interrupt handlers MP-safe.

acpica has its own internal locking, and the interrupt handlers we
install with AcpiInstall*Handler (gpe, notify, &c.) also have their
own locking.

x86: Split most of pmap.h into pmap_private.h or vmparam.h.

This way pmap.h only contains the MD definition of the MI pmap(9)
API, which loads of things in the kernel rely on, so changing x86
pmap internals no longer requires recompiling the entire kernel every
time.

Callers needing these internals must now use machine/pmap_private.h.
Note: This is not x86/pmap_private.h because it contains three parts:

1. CPU-specific (different for i386/amd64) definitions used by...

2. common definitions, including Xenisms like xpmap_ptetomach,
further used by...

3. more CPU-specific inlines for pmap_pte_* operations

So {amd64,i386}/pmap_private.h defines 1, includes x86/pmap_private.h
for 2, and then defines 3. Maybe we should split that out into a new
pmap_pte.h to reduce this trouble.

No functional change intended, other than that some .c files must
include machine/pmap_private.h when previously uvm/uvm_pmap.h
polluted the namespace with pmap internals.

Note: This migrates part of i386/pmap.h into i386/vmparam.h --
specifically the parts that are needed for several constants defined
in vmparam.h:

VM_MAXUSER_ADDRESS
VM_MAX_ADDRESS
VM_MAX_KERNEL_ADDRESS
VM_MIN_KERNEL_ADDRESS

Since i386 needs PDP_SIZE in vmparam.h, I added it there on amd64
too, just to keep things parallel.

- Define a device call for PCI bus instances to fetch a direct child's
device handle given the device's device/function #s (extracted from
a pcitag_t). Use it to associate the handle with the child device
at config_found() time.
- Implement this device call for ACPI and OpenFirmware.
- Enable the OpenFirmware variant for evbarm FDT, macppc, ofppc, sparc64.
- Obsolete acpi_device_register(); it is no longer needed.
- Obsolete setting the OpenFirmware handle in PCI devices in the
sparc64 device_register(); it is no longer needed.

branches: 1.31.4; 1.31.6;
Call acpi_device_register() as appropriate.

branches: 1.30.2;
Introduce Xen PVH support in GENERIC.
This is compiled in with
options XENPVHVM
x86 changes:
- add Xen section and xen pvh entry points to locore.S. Set vm_guest
to VM_GUEST_XENPVH in this entry point.
Most of the boot procedure (especially page table setup and switch to
paged mode) is shared with native.
- change some x86_delay() to delay_func(), which points to x86_delay() for
native/HVM, and xen_delay() for PVH

Xen changes:
- remove Xen bits from init_x86_64_ksyms() and init386_ksyms()
and move to xen_init_ksyms(), used for both PV and PVH
- set ISA no-legacy-devices property for PVH
- factor out code from Xen's cpu_bootconf() to xen_bootconf()
in xen_machdep.c
- set up a specific pvh_consinit() which starts with printk()
(which uses a simple hypercall that is available early) and switch to
xencons when we can use pmap_kenter_pa().

Add acpi_intr_mask() and acpi_intr_unmask() which, following the pre-existing
ACPI software layering model, are wrappers around acpi_md_intr_mask() and
acpi_md_intr_unmask(), which in turn are wrappers around intr_mask() and
intr_unmask().

XXX ARM and IA64 implementations of acpi_md_intr_mask() and
acpi_md_intr_unmask() are just stubs for now.

Cast physical addresses via uintptr_t to ACPI_PHYSICAL_ADDRESS to deal
with all size variants of the types used here in different builds.
Patch from manu@.

Attempt to obtain ACPI RSDP from the hypervisor for Xen PV

There are three possible way of obtaining the ACPI RSDP
- From Extended BIOS Data Area (EBDA) when kernel or Xen was booted from
BIOS bootstrap
- From EFI SystemTable when kernel is booted from EFI bootstrap
- When Xen is booted from EFI bootstrap, EBDA is not mapped, and EFI
SystemTable is not passed to the kernel. The only way to go is to
obtain ACPI RSDP trhough an hypercall.

Note: EFI bootstrap support for booting Xen has not yet been committed.

branches: 1.26.2;
Handle ISA/EISA interrupts like isa_machdep.c.

In acpi_md_OsRemoveInterruptHandler() redir and mpflags are only
relevant to the NIOAPIC > 0 case (not used without that). Rearrange
#if's slightly to make that happen (avoid "set but not used" warnings
(aka errors) when NIOAPIC == 0 (or undefined)).

Start replacing the x86 PTE bits.

Fix bug, PG_W is 'wired', not 'writable'.

We reorganise definitions for XEN source support as follows:

XEN - common sources required for baseline XEN support.
XENPV - sources required for support of XEN in PV mode.
XENPVHVM - sources required for support for XEN in HVM mode.
XENPVH - sources required for support for XEN in PVH mode.

Apply MADT interrupt source overrides to interrupts established via
acpi_md_intr_establish.

Add MD functions for establishing and disestablishing interrupt handlers.

branches: 1.19.2;
Allow registering ACPI interrupt handlers with a xname.
AcpiOsInstallInterruptHandler(), part of ACPICA API, doesn't allow passing
the xname. I extend the API with AcpiOsInstallInterruptHandler_xname()
for this purpose, and change acpi_md_OsInstallInterruptHandler() to
accept and use the xname (ia64 doens't use it).
The xname was hardcoded to "acpi SCI" in the
x86 acpi_md_OsInstallInterruptHandler(), so I make
AcpiOsInstallInterruptHandler() call
AcpiOsInstallInterruptHandler_xname with xname = "acpi SCI".

Now 'vmstat -i' shows the device's name instead of "acpi SCI" for for i2c HID
interrupts.

Proposed on tech-kern@ on Dec 29.

branches: 1.18.6; 1.18.12;
Handle persistent memory. Currently only debug output.

x86: make btinfo_memmap from btinfo_efimemmap for to reduce mem_cluster_cnt.

should fix PR/51953.

efi_md::md_virt always uses uint64_t.

Initial commit of native amd64 EFI boot loader.

branches: 1.14.2;
provide intr xname

Set hw.acpi.sleep.vbios when a non-HW accelerated VGA driver attaches.
If the VGA_POST option is present in the kernel the default value is 2,
otherwise 1. PR kern/50781

Reviewed by: agc, mrg

branches: 1.12.2;
Fix build break.

Add support for grub to find the ACPI root table pointer via a bootinfo entry
from grub.
From: https://mail-index.netbsd.org/tech-kern/2014/05/22/msg017119.html

CID/1325751: Avoid possible 32 bit overflow.

PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific

branches: 1.8.4;
acpi_md_findoverride is only used when NIOAPIC > 0, so don't provide it
otherwise.

branches: 1.7.2;
Correct acpi_md_OsWritable() logic so that it can return TRUE.
From Masanori Kanaoka in PR 47571.

branches: 1.6.4;
yet more fixes for PR 47648 / PR 47016:
when using a temporary mp_intr_map, initialize the "flags" field
as well as "redir" since apic_set_redir() uses both. fix how
the flags field is change when applying an override, the trigger
and polarity sub-fields aren't just one bit like they are in redir.

redo the ACPI interrupt handler setup again, this time handling
MADT overrides that change the pin as well as the polarity.
fixes PR 47648.

locate PCI buses and determine their bus numbers using the info
previously extracted from ACPICA rather than trying to figure it out again.
allow PCI buses that don't have a _PRT method.

branches: 1.3.2; 1.3.6;
acpi_md_ncpus: use kcpuset_attached instead.

branches: 1.2.2; 1.2.4; 1.2.8;
#include <sys/bus.h> instead of <machine/bus.h>.

branches: 1.1.2;
Follow IA-64 with the x86-specific ACPI MD functions and move these where
they belong to. Remove an unused function. Minor KNF. No functional change.

branches: 1.2.2; 1.2.4;
Use acpi_match_cpu_handle() from acpi_util.c and only evaluate
the _PDC control method for CPUs that are enabled in the MADT.

Move the evaluation of the _PDC control method out from the acpicpu(4)
driver to the main acpi(4) stack. Follow Linux and evaluate it early.
Should fix PR port-amd64/42895, possibly also PR kern/42583, and many
other comparable bugs.

A common sense explanation is that Intel supplies additional CPU tables to
OEMs. BIOS writers do not bother to modify their DSDTs, but instead load
these extra tables dynamically as secondary SSDT tables. The actual Load()
happens when the _PDC method is invoked, and thus namespace errors occur
when the CPU-specific ACPI methods are not yet present but referenced in the
AML by various drivers, including, but not limited to, acpitz(4).

Move definition of acpi_md_vesa_modenum to acpi_wakeup.c; allows building
kernels without framebuffer devices.
Problem reported by John D. Baker on current-users@

Declare
int acpi_md_vesa_modenum;
int acpi_md_vbios_reset;
struct vcons_screen x86_genfb_console_screen;

in genfb_machdep.h instead of locally as extern in various .c files.

xen: Provide definitions or ifdefs to make drm build in XEN3_DOM0.

No idea if it works, but it builds now.

PR port-xen/49330

branches: 1.54.12;
x86: Reset cached tsc in every lwp to 0 on suspend/resume.

This avoids spuriously warning about tsc going backwards, which is to
be expected after a suspend/resume cycle.

branches: 1.53.6;
- Recalibrate the APIC timer using the TSC, once the TSC has in turn been
recalibrated using the HPET. This gets the clock interrupt firing more
closely to HZ.

- Undo change with recent Xen merge and go back to starting the clocks in
initclocks() on the boot CPU, and in cpu_hatch() on secondary CPUs.

- On reflection don't use HPET delay any more, it works very well but means
going over the bus. It's enough to use HPET to calibrate the TSC and
APIC.

Tested on amd64 native, xen and xen PVH.

remove some unnecessary includes of internal UVM headers.

branches: 1.51.2;
Rewrite the FPU code on x86. This greatly simplifies the logic and removes
the dependency on IPL_HIGH. NVMM is updated accordingly. Posted on
port-amd64 a week ago.

Bump the kernel version to 9.99.16.

The second parameter to AcpiSetFirmwareWakingVector sets the
X_Firmware_Waking_Vector field (where supported), which will cause firmware
to resume in protected mode. Since our wake code assumes real mode, always
set X_Firmware_Waking_Vector to 0.

branches: 1.49.4;
Initialize the errata MSRs when waking up, otherwise they are clear and
we're re-enabling certain CPU bugs.

Reinitialize the PAT MSR when waking up, otherwise the write-combined
pages become write-through.

Remove unused macro

Save and restore xcr0 when doing ACPI sleeps. Should fix PR/49174.

branches: 1.45.8;
There is a huge fpu synchronization issue here.

When the remote CPUs receive the ACPI sleep IPI, they do not save the fpu
state of the lwp they are executing. The problem is, when waking up they
reinitialize the registers of their local fpu and go back to their lwp
directly. Therefore, if an lwp is interrupted while storing data in an fpu
register, that data gets overwritten, which basically means the lwp is
likely to go crazy when resuming execution.

Fix this by simply saving the fpu state correctly. This way when going to
sleep the state is stored in the lwp's pcb and CR0_TS is set, so the next
time the lwp wants to use the fpu we'll get a dna, and the state will be
restored as expected.

While here, don't forget to reenable interrupts (and the spl) if an error
occurs.

Reload the MSRs on the original cpu on i386 - looks like I forgot this part
in my rev1.41. Technically it does not change anything, since the only MSR
is NOX and it is already reloaded in the trampoline.

Don't include sys/cdefs.h and __KERNEL_RSCID twice... once is enough.

use a value of hw.acpi.sleep.vbios that might actually
work for any real hardware suspend.

stop dragging feet through the ground in PR kern/50781

Call cpu_init_msrs on i386 when waking up. Currently it does not change
anything, since MSR_EFER is already enabled earlier. But if we add new
MSRs in the future, we will want them when waking up as well.

The MSR EFER state is not saved and restored when sleeping on i386. On PAE,
the CPU crashes right after waking up, since it needs to access NOX-ed
pages, which are to be enabled in an MSR.

Fix this by properly saving and restoring the EFER MSR. It's a little
tricky since the wakeup code uses %edx, but rdmsr overwrites it. We just
save it in %esi.

Now, the CPU sleeps properly on PAE kernels.

branches: 1.39.2;
dup the argument of the wakeup vector. XXX: is that correct?

branches: 1.38.6;
Ensure that the top level sysctl nodes (kern, vfs, net, ...) exist before
the sysctl link sets are processed, and remove redundancy.

Shaves >13kB off of an amd64 GENERIC, not to mention >1k duplicate
lines of code.

Add explicit #include <x86/fpu.h> instead of relying on pcb.h including it.

Move sys/arch/amd64/amd64/fpu.c and sys/arch/amd64/include/fpu.h
into sys/arch/x86 in preparation for using the same code for i386.

Remove support for 'external' floating point units and the MS-DOS
compatible method of handling floating point exceptions.
Make kernel support for teh fpu non-optional (486SX should still work).
Only 386 cpus support external fpu, and i386 support was removed years ago.
This means that the npx code no longer uses port 0xf0 or interupt 13.
All the "npx at isa" lines go from the configs, arch/i386/isa/npx.c
is now mandatory for all i386 kernels.
I've renamed npxinit() to fpuinit() and npxinit_cpu() to fpuinit_cpu()
to match the very similar amd64 functions.
The fpu of the boot cpu is now initialised by a direct call from
cpu_configure(), this enables FP emulation for a 486SX.
(for amd64 the cr0 values are set in locore.S and similar).
This fixes a long-standing bug in linux_setregs() - which did not
save the fpu regsiters if they were active.
I've test booted a single cpu i386 kernel (using anita).
amd64 builds - none of teh changes should affect it.
The i386 XEN kernels build, but I'm not sure where they set cr0, and
it might have got lost!

revert fpu/pcu changes until we figure out what's wrong; they cause random
freezes

Use the MI "pcu" framework for bookkeeping of npx/fpu states on x86.
This reduces the amount of MD code enormously, and makes it easier
to implement support for newer CPU features which require more fpu
state, or for fpu usage by the kernel.
For access to FPU state across CPUs, an xcall kthread is used now
rather than a dedicated IPI.
No user visible changes intended.

branches: 1.32.2; 1.32.4;
It turns out we're actually waiting for other processors to be unbusy, not busy.
Unbreaks ACPI suspend on uniprocessor. Probably fixes unnoticed bugs on MP.
Needs pullup to netbsd-6.

- Convert x86 MD code, mainly pmap(9) e.g. TLB shootdown code, to use
kcpuset(9) and thus replace hardcoded CPU bitmasks. This removes the
limitation of maximum CPUs.

- Support up to 256 CPUs on amd64 architecture by default.

Bug fixes, improvements, completion of Xen part and testing on 64-core
AMD Opteron(tm) Processor 6282 SE (also, as Xen HVM domU with 128 CPUs)
by Manuel Bouyer.

Now that 6.0 is branched, remove the ACPI-related sysctl nodes in machdep.

branches: 1.29.2; 1.29.6; 1.29.8;
#include <sys/bus.h> instead of <machine/bus.h>.

Explicitly re-enable the SCI interrupt when the wakeup starts (and before
interrupts are enabled). A workaround for a BIOS bug. Fixes the interrupt
storm reported by Taylor R. Campbell in PR # 44581.

branches: 1.27.2; 1.27.4;
Add a comment.

Move the ACPI sleep-specific sysctl variables to hw.acpi.sleep. The old
machdep-variables are provided for backwards compatibility (eventually these
should be removed). All ACPI sysctl variables are now under hw.acpi.

Remove the custom enter_s4_with_bios(). Use ACPICA's native
AcpiEnterSleepStateS4bios() instead. Minimum functional change.

ok jmcneill@

Use acpi_eval_set_integer(), KNF. No functional change.

UINT32 -> uint32_t; UINT8 -> uint8_t.

Use CTLTYPE_BOOL.

branches: 1.21.2;
Use native functions instead of polluting the namespace with ACPICA-macros.

branches: 1.20.2;
Add a flags argument to pmap_kenter_pa(9).
Patch showed on tech-kern@ http://mail-index.netbsd.org/tech-kern/2009/11/04/msg006434.html
No objections.

kill extra whitespaces
reviewed by tsutsui@

Be a bit more noisy by telling the user VGA_POST is missing in the
kernel config when trying machdep.acpi_vbios_reset=2.

Don't allow machdep.acpi_vbios_reset=2 if option VGA_POST is missing.

Pass the VBE mode number from the bootloader to the kernel, and then
make the ACPI wakecode aware of it. Restore the desired VBE mode on resume
when acpi_vbios_reset=1, so suspend/resume with genfb console will work.

Switch to ACPICA 20090730, and update for API changes.

Rearrange TSC inter-CPU synchronization code so that the gory details
are dealt with in x86/tsc.c and callers don't have to care that much.
Also add some comments and make some variables static.
approved by ad (a while ago)

bcopy -> memcpy

sync TSC on resume (because CPUs were switched off in the meantime),
otherwise we get diverging timecounters leading to eg the monotonic
clock jump backwards
(pullup candidate)

branches: 1.11.4;
On resum-from-RAM explicitly restore PCI link device state before
reenabling interrupts. At least one BIOS doesn't do this automatically
as reported by Christoph Egger.

branches: 1.10.2; 1.10.4;
Explicitly disable all GPEs and clear fixed events before enabling
interrupts. This is the first part of PR 38683.

Revert previous.

PR# 38683 - T61 cannot suspend with recent kernels

Don't restore spl until after AcpiLeaveSleepState.

machdep.acpi_vbios_reset = 2 --> vga_pci_resume will use x86emu to do a
POST when options VGA_POST is present.

branches: 1.6.4;
Share cpu.h between the x86 ports.

branches: 1.5.2;
Remove clause 3 and 4 from TNF licenses

branches: 1.4.2; 1.4.4;
Disable machdep.acpi_beep_on_reset by default.

branches: 1.3.6;
splhigh == splipi

branches: 1.2.2;
Introduce optional cpu_offline_md to execute MD actions at the end of
cpu_offline. Use this on amd64/i386 to force a FPU save. As this was
triggered by npxsave_cpu/fpusave_cpu not working for a different CPU,
remove the cpu_info argument and adjust npxsave_*/fpusave_* to use bool
for the save.

OK ad@

branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8;
Add new IPI for saving CPU state explicitly, share high-level part of
ACPI wakeup code and teach it how to start the APs again. As a side
effect the CPU_START interface allows choosing between different
bootstrap codes more easily now.

Use sed, awk and hexdump from tools to make this work on Solaris. Ok by apb.

branches: 1.2.6; 1.2.8; 1.2.18; 1.2.26; 1.2.28;
How did these get lost?

branches: 1.1.2; 1.1.8; 1.1.10; 1.1.12;
file genwakecode.sh was initially added on branch jmcneill-pm.

PR 59568: Disable viogpu in MICROVM kernel configuration as it is not
supported for now.

branches: 1.3.2; 1.3.4;
Rename BOOTCYCLETIME kernel option and subsequent files to BOOT_DURATION

Add BOOTCYCLETIME option to print kernel boot time

Introduce a new kernel option, BOOTCYCLETIME, which will print
the time taken for the kernel to boot on (for now) amd64 and i386
architectures.

x86: consolidate MICROVM kernel configurations

Move common configuration options from amd64/conf/MICROVM and
i386/conf/MICROVM into a shared x86/conf/MICROVM.common file.

Make PCI_ADDR_FIXUP depended on PCI_BUS_FIXUP.
It is no-op if PCI_BUS_FIXUP is missing.

MI PMAP EFI_RUNTIME support

x86: Support EFI runtime services.

This creates a special pmap, efi_runtime_pmap, which avoids setting
PTE_U but allows mappings to lie in what would normally be user VM --
this way we don't fall afoul of SMAP/SMEP when executing EFI runtime
services from CPL 0. SVS does not apply to the EFI runtime pmap.

The mechanism is intended to work with either physical addressing or
virtual addressing; currently the bootloader does physical addressing
but in principle it could be modified to do virtual addressing
instead, if it allocated virtual pages, assigned them in the memory
map, and issued RT->SetVirtualAddressMap.

Not sure pmap_activate_sync and pmap_deactivate_sync are correct,
need more review from an x86 wizard.

If this causes fallout, it can be disabled temporarily without
reverting anything by just making efi_runtime_init return immediately
without doing anything, or by removing options EFI_RUNTIME.

amd64-only for now pending type fixes and testing on i386.

x86: Rename x86/efi.c -> x86/efi_machdep.c.

Avoid collision with dev/efi.c.

x86's platform.c no longer has any x86 specific code in it, so move it to
dev/smbios_platform.c to let other ports use it

Separate MI smbios interface from MD specific code.

branches: 1.120.6;
move vmt(4) from MD to MI, and add support vmt on aarch64. tested on ESXi-Arm Fling

- move from sys/arch/x86/x86/{vmt.c,vmtreg.h,vmtvar.h} to sys/dev/vmt/{vmt_subr.c,vmtreg.h,vmtvar.h},
and split the attach part of the cpufeaturebus and fdt
- add aarch64 vmware backdoor op
- add include guard to vmt{reg,var}.h
- Yet there is still some little-endian dependency. it needs to be fixed in order to work properly on aarch64eb

defflag NO_PCI_MSI_MSIX

Implement ChaCha with SSE2 on x86 machines.

Slightly disappointed that it only doubles, rather than quadruples,
throughput on my Ivy Bridge laptop. Worth investigating.

Introduce per-cpu IDTs

This is realized by following modifications:
- Add IDT pages and its allocation maps for each cpu in "struct cpu_info"
- Load per-cpu IDTs at cpu_init_idt(struct cpu_info*)
- Copy the IDT entries for cpu0 to other CPUs at attach
- These are, for example, exceptions, db, system calls, etc.

And, added a kernel option named PCPU_IDT to enable the feature.

New permutation-based AES implementation using SSSE3.

This covers a lot of CPUs -- particularly lower-end CPUs over the
past decade which lack AES-NI.

Derived from Mike Hamburg's public domain vpaes software; see
<https://crypto.stanford.edu/vpaes/> for details.

New SSE2-based bitsliced AES implementation.

This should work on essentially all x86 CPUs of the last two decades,
and may improve throughput over the portable C aes_ct implementation
from BearSSL by

(a) reducing the number of vector operations in sequence, and
(b) batching four rather than two blocks in parallel.

Derived from BearSSL'S aes_ct64 implementation adjusted so that where
aes_ct64 uses 64-bit q[0],...,q[7], aes_sse2 uses (q[0], q[4]), ...,
(q[3], q[7]), each tuple representing a pair of 64-bit quantities
stacked in a single 128-bit register. This translation was done very
naively, and mostly reduces the cost of ShiftRows and data movement
without doing anything to address the S-box or (Inv)MixColumns, which
spread all 64-bit quantities across separate registers and ignore the
upper halves.

Unfortunately, SSE2 -- which is all that is guaranteed on all amd64
CPUs -- doesn't have PSHUFB, which would help out a lot more. For
example, vpaes relies on that. Perhaps there are enough CPUs out
there with PSHUFB but not AES-NI to make it worthwhile to import or
adapt vpaes too.

Note: This includes local definitions of various Intel compiler
intrinsics for gcc and clang in terms of their __builtin_* &c.,
because the necessary header files are not available during the
kernel build. This is a kludge -- we should fix it properly; the
present approach is expedient but not ideal.

Add AES implementation with VIA ACE.

padlock(4): Remove legacy rijndael API use.

This doesn't actually need to compute AES -- it just needs the
standard AES key schedule, so use the BearSSL constant-time key
schedule implementation.

XXX Compile-tested only.
XXX The byte-order business here seems highly questionable.

Add x86 AES-NI support.

Limited to amd64 for now. In principle, AES-NI should work in 32-bit
mode, and there may even be some 32-bit-only CPUs that support
AES-NI, but that requires work to adapt the assembly.

x86/x86/ipi.c should not be built for XENPV, even if dom0ops is defined.

Merge the bouyer-xenpvh branch, bringing in Xen PV drivers support under HVM
guests in GENERIC.
Xen support can be disabled at runtime with
boot -c
disable hypervisor

Make crypto/rijindael optional again as cprng_strong does no longer
depend on it. Dependency is explicitly declared in files.foo if a
component requires it.

Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.

- If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors
can take TSC/core crystal clock ratio but core crystal clock frequency
can't be taken. Intel SDM give us the values for some processors.
- It also required to change lapic_per_second to make LAPIC timer correctly.
- Add new file x86/x86/identcpu_subr.c to share common subroutines between
kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c
will be moved to this file in future.
- Add comment to clarify.

branches: 1.107.4; 1.107.10;
Added Microsoft Hyper-V support. It ported from OpenBSD and FreeBSD.

graphical console is not work on Gen.2 VM yet. To use the serial console,
enter "consdev com,0x3f8,115200" on efiboot.

Make ipmi driver available to other platforms.
Add ACPI attachment.

Enable 'options NO_PCI_MSI_MSIX' to DTRT in x86 builds.

Document 'options NO_PCI_MSI_MSIX' in options(4).

Add an option to have a static kernel memory layout. This option is
disabled by default - that is to say, KASLR remains enabled by default.

Move
arch/x86/x86/tprof_pmi.c
arch/x86/x86/tprof_amdpmi.c
into
dev/tprof/tprof_x86_intel.c
dev/tprof/tprof_x86_amd.c

Remove the X86PMC code I had written, replaced by tprof. Many defines
become unused in specialreg.h, so remove them. We don't want to add
defines all the time, there are countless PMCs on many generations, and
it's better to just inline the event/unit values.

branches: 1.101.2;
Mmh, don't compile spectre.c on Xen.

Make MPVERBOSE a defparam rather than defflag. It has multiple
non-zero usages within mpacpi.c

Move the SpectreV2 mitigation code into a dedicated spectre.c file. The
content of the file is taken from the end of cpu.c, and is copied as-is.

Separate the compat code in its own file to facilitate module building.

branches: 1.97.2;
move the imc code into x86/pci/files.pci so that pci is defined in time.

Move the imc(4) and imcsmb(4) sources into architecture-specific
directory (for previous CVS history see the sys/dev/pci/imcsmb/
Attic)

Replace spaces with tabs (xterm copy-&-pasto)

Move the imc and imcsmb stuff out of general files.pci and into the
architecture-specific files.x86

Should unbreak the sgimips build.

Move SVS into x86/svs.c

rename sys/arch/x86/x86/pmap_tlb.c to sys/arch/x86/x86/x86_tlb.c, so that
x86 can eventually use uvm/pmap/pmap_tlb.c; step to future PCID support

Make things compile again.

Merge into x86/.

Merge into x86/.

branches: 1.88.6;
Move pmc.c into x86/, it can be shared with amd64.

branches: 1.87.2; 1.87.4;
Add cpu_rng, a framework for simple on-CPU random number generators.

Add support for grub to find the ACPI root table pointer via a bootinfo entry
from grub.
From: https://mail-index.netbsd.org/tech-kern/2014/05/22/msg017119.html

Split out the pmap_pv_track stuff for use by others.

Discussed with riastradh@

add x86 MD MSI/MSI-X support code.

branches: 1.83.2;
Normalize: acpicpu depends on acpi.

Define "machdep" attribute and mark files (in amd64 and x86).

Merge riastradh-drm2 to HEAD.

A few "isa" files are so tightly integrated into the x86 platform code
as to not really be part of the optional isa bus autoconf machinery.

Allows configuring a kernel like so:

include "arch/amd64/conf/GENERIC"
no isa

branches: 1.79.2; 1.79.4; 1.79.10;
Extend the CPU microcode update framework to support Intel x86 CPUs.
Contrary to the AMD implementation, it doesn't use xcalls to distribute
the update to all CPUs but relies on cpuctl(8) to bind itself to the
right CPU -- to keep it simple and avoid possible problems with
hyperthreading.
Also, it doesn't parse the vendor supplied file to pick the right
part for the present CPU model but relies on userland to prepare
files with specific filenames. I'll commit a pkg for this in a minute
(pkgsrc/sysutils/intel-microcode).
The ioctl interface changed; compatibility is provided (should be
limited to COMPAT_NETBSD6 as soon as this is available).

Merge i386 and amd64 version of db_memrw.c.

Use this opportunity to skip calculating the VA of the page. Let the CPU
deal with the invalidation itself through invlpg + destination address to
avoid converting between canonical/non canonical forms.

Make option CPU_UCODE global

Support CPU microcode loading via cpuctl(8).
Implemented and enabled via CPU_UCODE kernel config option
for x86 and Xen Dom0.
Tested on different AMD machines with different
CPU families.

ok wiz@ for the manpages
ok releng@
ok core@ via releng@

branches: 1.75.2; 1.75.6;
Don't link pci_ranges.c with x86 kernels for now, it's using a
pcibus_attach_args member that I haven't added, yet.

vmt needs sysmon_taskq

add a port of the VMware Tools driver vmt(4) from OpenBSD

Add pci_ranges.c to the set of files compiled when 'pci' is configured.

Follow IA-64 with the x86-specific ACPI MD functions and move these where
they belong to. Remove an unused function. Minor KNF. No functional change.

Move the evaluation of the _PDC control method out from the acpicpu(4)
driver to the main acpi(4) stack. Follow Linux and evaluate it early.
Should fix PR port-amd64/42895, possibly also PR kern/42583, and many
other comparable bugs.

A common sense explanation is that Intel supplies additional CPU tables to
OEMs. BIOS writers do not bother to modify their DSDTs, but instead load
these extra tables dynamically as secondary SSDT tables. The actual Load()
happens when the _PDC method is invoked, and thus namespace errors occur
when the CPU-specific ACPI methods are not yet present but referenced in the
AML by various drivers, including, but not limited to, acpitz(4).

Welcome to 5.99.53! Merge rmind-uvmplock branch:

- Reorganize locking in UVM and provide extra serialisation for pmap(9).
New lock order: [vmpage-owner-lock] -> pmap-lock.

- Simplify locking in some pmap(9) modules by removing P->V locking.

- Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share
the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs).

- Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner.
Add TLBSTATS option for x86 to collect statistics about TLB shootdowns.

- Unify /dev/mem et al in MI code and provide required locking (removes
kernel-lock on some ports). Also, avoid cache-aliasing issues.

Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches
formed the core changes of this branch.

branches: 1.68.2;
Don't use the C preprocessor to configure USERCONF. Instead, either do
or do not link in subr_userconf.c and x86_userconf.c.

Provide no-op stubs for userconf_bootinfo(), userconf_init(), and
userconf_prompt().

Delete all occurrences of #include "opt_userconf.h" as well as USERCONF
and __HAVE_USERCONF_BOOTINFO #ifdef'age.

Merge db_trace for x86. From: Vladimir Kirillov proger at wilab dot org dot ua

As pointed out by Manuel Bouyer and Taylor R Campbell, I forgot to
commit the change to files.x86 that adds x86_stub.c, so do that.

sys/arch/x86/x86/iclockmod.c has been removed.

Move INTEL_ONDEMAND_CLOCKMOD -- or odcm(4) -- to the cpufeaturebus.

Move acpicpu(4) from "acpinodebus" to "cpufeaturebus".

Move VIA_C7TEMP to the cpufeaturebus.

Move PowerNow! to the cpufeaturebus.

Move ENHANCED_SPEEDSTEP, or henceforth est(4), to the cpufeaturebus.

Modularize coretemp(4). Ok jmcneill@.

modularize VIA PadLock support
- retire options VIA_PADLOCK, replace with 'padlock0 at cpu0'
- driver supports attach & detach
- support building as a module

decouple tprof and its backends.

branches: 1.56.2; 1.56.4;
Merge a driver for ACPI CPUs with basic support for processor power states,
also known as C-states. The code is modular and provides an easy way to add
the remaining functionality later (namely throttling and P-states).

Remarks:

1. Commented out in the GENERICs; more testing exposure is needed.

2. The C3-state is disabled for the time being because it turns off
timers, among them the local APIC timer. This may not be universally
true on all x86 processors; define ACPICPU_ENABLE_C3 to test.

3. The algorithm used to choose a power state may need tuning. When
evaluating the appropriate state, the implementation uses the
previous sleep time as an indicator. Additional hints would include
for example the system load.

Also bus master activity is evaluated when choosing a state. The
usb(4) stack is notorious for such activity even when unused.
Typically it must be disabled in order to reach the C3-state,
but it may also prevent the use of C2.

4. While no extensive empirical measurements have been carried out, the
power savings are somewhere between 1-2 W with C1 and C2, depending
on the processor, firmware, and load. With C3 even up to 4 W can be
saved. The less something ticks, the more power is saved.

ok jmcneill@, joerg@, and discussed with various people.

Unify i386 and amd64 procfs MD code into x86.

branches: 1.54.2; 1.54.4;
Remove X86_IPI_WRITE_MSR (and msr_ipifuncs.c), replace all uses in drivers
with xc_broadcast(). AMD K8 PowerNow driver tested by <jakllsch>, thanks!

Closes PR/37665.

Add support for VIA C7 temperature sensors (options VIA_C7TEMP)

Move x86 CPU topology detection code into the separate file (as it was originally).
OK by <yamt>.

Introduce sys/arch/x86/x86/mp.c for common x86 MP configuration code.
mpacpi_scan_pci() and mpbios_scan_pci() are identical code, so replace
them with mp_pci_scan().

Introduce mp_pci_childdetached(), which helps us to detach root PCI
buses that were enumerated either by MP BIOS or by ACPI.

Let us detach and re-attach PCI buses from mainbus0 on i386. This is
necessarily a work-in-progress, because testing detach and re-attach
is very difficult: to detach and re-attach the entire PCI tree on most
x86 computers that I own is not possible because some essential device
attaches under the PCI subtree: the console, com0, NIC, or storage
controller always attaches in the PCI tree.

- Add macros to handle (some) trapframe registers for common x86 code.
- Merge i386 and amd64 syscall.c into x86. No functional changes intended.

Proposed on (port-i386 & port-amd64). Unfortunately, I cannot merge these
lists into the single port-x86. :(

Add opt_intrdebug.h for the INTRDEBUG option, and #include it here and
there. Fixes GENERIC/i386 compilation with 'options INTRDEBUG'.

Merge i386 and amd64 vm_machdep.c into x86. No functional changes intended.
Note: some #ifdefs will be removed with macros.

Merge/move core_machdep.c into x86, no difference between i386 and amd64.

- rewrite x86 nmi dispatcher so that establish and disesablish are safe
on a running system.
- adapt existing users of the api. (elan)
- adapt tprof_pmi driver to use the api.

PR# port-i386/37026: userconf(4) doesn't work with vesafb(4)

Add early console support for x86 genfb.

branches: 1.44.2; 1.44.4; 1.44.8; 1.44.12;
Move some MD declarations from x86/pci/files.pci to x86/conf/files.x86,
so that Xen can use the former.

Drop Xen's pcib.c in favor of the x86 code and thereby unbreak ichlpcib.

branches: 1.43.4;
Simplify x86 identcpu code, and share between i386/amd64.

Make cpu_idle a macro calling a function pointer on x86.
Select the Xen idle routine for Xen, mwait if supported by the CPU and
it is not AMD and halt otherwise. As reported by Christoph Egger,
AMD Barcelona keeps the CPU in C0 state with MWAIT, contrary to HLT,
which uses C1 and therefore much less power.

branches: 1.41.2; 1.41.4;
Include null IPI functions if !MULTIPROCESSOR.

branches: 1.40.6; 1.40.8;
try to detect processor resource sharing topologies. ie. package/core/smt IDs.

- share idt entry allocation code among x86.
- introduce a function to reserve an idt entry and use it instead of
manipulating idt_allocmap directly.
- rename idt to xen_idt for amd64 xen. add missing #ifdef XEN.

Add initial version of calling VGA POST from vga_resume. This is the
equivalent to "vbetool post" using x86emu in the kernel.

Add new IPI for saving CPU state explicitly, share high-level part of
ACPI wakeup code and teach it how to start the APs again. As a side
effect the CPU_START interface allows choosing between different
bootstrap codes more easily now.

branches: 1.36.2;
Merge jmcneill-pm branch.

branches: 1.35.2; 1.35.4;
Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

__cpu_simple_locks really should be simple, otherwise they can cause
problems for e.g. profiling.

branches: 1.33.2;
Add coretemp(4). A new driver for Intel Core's on-die thermal sensor,
available on Intel Core or newer CPUs.

Ported from FreeBSD. Tested by rmind on i386 and joerg on amd64.

Enabled with "options INTEL_CORETEMP".

- Share pchb(4) between i386 and amd64; one copy is enough for both.
- Move some of the x86 PCI devices into x86/pci/files.pci.
- Add more x86 stuff into x86/conf/files.x86.

ok joerg.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.30.8; 1.30.10; 1.30.14;
Make the Enhanced Speedstep driver available for i386 and amd64.
To use it on EM64T CPUs supporting the EST CPUID feature. Note that
some CPUs still don't work with this driver, like Xeon or Pentium 4.

Move the p[34]_get_bus_clock functions into its own file,
intel_busclock.c and remove this code from i386/identcpu.c.

Tested on i386 by myself and amd64 by Tonerre.

branches: 1.29.2;
Share the sysarch stuff between the x86 ports. PR kern/36046.

Driver for Intel Thermal Monitor (feature TM) On-Demand Clock
Modulation.

This works by changing the duty cycle of the clock modulation,
and saves power and helps to not increase the temperature by
software.

Adapted from OpenBSD/FreeBSD's p4tcc.

To enable it one must use "options INTEL_ONDEMAND_CLOCKMOD".

Tested by me in UP and SMP, ok'ed by Matthew R. Green.

MSR read and write IPI handlers for x86. A MSR will be read or written
in all CPUs available in the system. This adds another member
to struct cpu_info, ci_msr_rvalue; it will contain the value of the MSR
in a previous operation.

Tested with clockmod in UP and SMP by me, tested with est in SMP
by Daniel Carosone and Michael Van Elst.

Ok'ed by Andrew Doran and Matthew R. Green.

Ok... there were people really angry with this, backing it out.

Add a driver for the Pentium 4 and later models with feature TM
(Thermal Monitor).

This driver will throttle the CPU clock modulation, saving some
power, also known as ODMC (On Demand Modulation Clock).

The processor can change from 12.5% to 100% (there are two erratas,
so two levels might be skipped in the worst case).

If supported, you'll see the following sysctl sub-tree:

machdep.p4tcc.throttling.target: CPU Clock throttling state (0 = lowest, 7 highest)
machdep.p4tcc.throttling.current: current CPU throttling state
machdep.p4tcc.throttling.available: list of CPU Clock throttling states

machdep.p4tcc.throttling.target = 2
machdep.p4tcc.throttling.current = 2
machdep.p4tcc.throttling.available = 7 6 5 4 3 2

Adapted from OpenBSD/FreeBSD.

branches: 1.24.2; 1.24.4; 1.24.6;
clean up how cpus and ioapics are attached at the mainbus:
Seperate "cpubus" and "ioapicbus" -- while they share a common "address
space" (the apic id), the kernel doesn't use this fact. There are different
data passed to cpus and apics, which caused some ugly polymorphism. This
also saves the special "submatch" functions needed to distingush cpus
and ioapics for autoconf. (And it makes that "apid" locators wired
in the kernel configuration are honored now; this allows one to dumb down
an mp box to singleprocessor by userconfig.)
Print "apid" locators in the buses "print" function "as everyone does",
so the per-port cpu drivers don't need to do it.
Being here, constify "struct cpu_functions" and g/c the unused MP_PICMODE
flag.

branches: 1.23.2;
Add an opencrypto provider for the AES xcrypt instructions found on VIA
C5P and later cores (also known as 'ACE', which is part of the VIA PadLock
security engine). Ported from OpenBSD.

Reviewed on tech-crypto and port-i386, no objections to commiting this.

Merge newlock2 to head.

Report on and where possible, try to work around some of the known errata
for Athlon 64 and Opteron processors. Tested briefly by cube@ and elad@.

branches: 1.20.2;
Add ipmi(4) driver, from OpenBSD. This requires SMBios support, so add
SMBios detection and mapping to bios32.c, also from OpenBSD (for now this
is only compiled in if ipmi(4) is configured). The sensors and watchdog are
accessible though envsys(4).
Works on i386; some work is needed on amd64 to access the BIOS. It would
eventually work on Xen if the SMBios is accessible (to be tested).

branches: 1.19.4; 1.19.6;
* Do not change struct powernow_pst_s (I added another member in my
previous patch) and this MUST be of that size, otherwise the tables
won't be found.

* powernow_k8.c moved into x86/x86, it should work both i386 and amd64.

* Added more DPRINTFs needed to found the first problem.

* Create "machdep.powernow.frequency" again, I can't remember why I
removed frequency... it should work with estd now.

* Do not try to call k[78]_powernow_init() if cpu is not AMD (thanks
to christos).

And more things I can't remember, but this time it will work in
Athlon 64 cpus and it won't crash in EM64T cpus.

AMD PowerNow!/Cool`n'Quiet driver for NetBSD/amd64,
adapted from OpenBSD.

Tested on a few machines:

http://bigbird.dohd.org:3021/NetBSD/dmesg
http://www.bsd.org.il/netbsd/acpi/dmesg

Thanks to cube, elad and others for testing and fixes.

Enabled by default on GENERIC.

Apply fvdl's acpi pci interrupt configuration code.
- MPACPI is no more.
- MPACPI_SCANPCI -> ACPI_SCANPCI

branches: 1.16.4; 1.16.12;
Split move interrupt-related PCI functions from pci_machdep.c to
pci_intr_machdep.c. In Xen-3 registers access is done the normal way but
interrupts need custom setup. Proposed on port-amd64, port-i386 and
port-xen a week ago.

branches: 1.15.2; 1.15.4;
Add a 'struct bootinfo' to represent the bootinfo structure used in the
kernel by x86 platforms (instead of a simple char *). This way, the code
in, e.g., lookup_bootinfo, is a bit easier to understand.

While here, move the lookup_bootinfo function used in x86 platforms (amd64,
i386 and xen) to a common file (x86/x86_machdep.c), as it was exactly the
same in all of them.

merge ktrace-lwp.

branches: 1.13.2;
Move definitions for PCI_*_FIXUP to files.x86 so that ACPI compiles for
amd64...

branches: 1.12.10;
Move boot device detection code from i386 and amd64 ports to x86_autoconf.c.
Rename i386_alldisks and x86_64_alldisks to x86_alldisks, adjust other
references to compensate.

Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

pciide_machdep.c depends on pciide_common, not pciide.
Pointed out and fix tested by Marc Recht.

Move the bulk of pci_intr_string into a seperate intr_string function. Use
that new function to print the pciide compat interrupt in pciide_machdep.c.
Share pciide_machdep.c between amd64 and i386.

branches: 1.8.2;
Add the options MPBIOS_SCANPCI and MPACPI_SCANPCI to configure PCI roots
with the MPBIOS/ACPI bus information, by walking through the buses, and
descending down every bus that hasn't been marked configured yet.

Update for acpi file move to sys/arch/x86/x86.

Share some common cache info cpuid code between i386 and x86_64.

Split bus_space and bus_dma into separate files.

lock_machdep.c moved here from arch/i386/i386.

Add consinit.c

Catch up with isa_machdep.c and pci_machdep.c move.

Move some files out of i386 into x86, so that they can be shared with
other ports.

Create a new header lwp_private.h to contain _lwp_getprivate_fast,
_lwp_gettcb_fast, _lwp_settcb and remove them from mcontext.h, so that:
1. we don't need special hacks to hide them
2. we can include <lwp.h> where needed to get the necessary prototypes
without redefining them locally.

branches: 1.25.20;
Merge the x86 gdt function and constant definitions

branches: 1.24.14;
Undo previous, fixed in userland.

expose the {rd,wr}msr functions to userland and install the header for
the benefit of cpuctl (fix the build).

branches: 1.22.4;
Stop installing dbregs.h

This is now kernel-only header. The behavior is well specified by the CPU
documents and we don't introduce changes to it.

Noted by <wiz>

branches: 1.21.8;
Add support for hardware assisted watchpoints/breakpoints API in ptrace(2)

Add new ptrace(2) calls:
- PT_COUNT_WATCHPOINTS - count the number of available hardware watchpoints
- PT_READ_WATCHPOINT - read struct ptrace_watchpoint from the kernel state
- PT_WRITE_WATCHPOINT - write new struct ptrace_watchpoint state, this
includes enabling and disabling watchpoints

The ptrace_watchpoint structure contains MI and MD parts:

typedef struct ptrace_watchpoint {
int pw_index; /* HW Watchpoint ID (count from 0) */
lwpid_t pw_lwpid; /* LWP described */
struct mdpw pw_md; /* MD fields */
} ptrace_watchpoint_t;

For example amd64 defines MD as follows:
struct mdpw {
void *md_address;
int md_condition;
int md_length;
};

These calls are protected with the __HAVE_PTRACE_WATCHPOINTS guard.

Tested on amd64, initial support added for i386 and XEN.

Sponsored by <The NetBSD Foundation>

branches: 1.20.2;
Add cpu_rng, a framework for simple on-CPU random number generators.

branches: 1.19.6;
Move sys/arch/amd64/amd64/fpu.c and sys/arch/amd64/include/fpu.h
into sys/arch/x86 in preparation for using the same code for i386.

Userspace (especially libkvm) build better is cpu_extended_state.h
is exported.

branches: 1.17.2; 1.17.4;
Extend the CPU microcode update framework to support Intel x86 CPUs.
Contrary to the AMD implementation, it doesn't use xcalls to distribute
the update to all CPUs but relies on cpuctl(8) to bind itself to the
right CPU -- to keep it simple and avoid possible problems with
hyperthreading.
Also, it doesn't parse the vendor supplied file to pick the right
part for the present CPU model but relies on userland to prepare
files with specific filenames. I'll commit a pkg for this in a minute
(pkgsrc/sysutils/intel-microcode).
The ioctl interface changed; compatibility is provided (should be
limited to COMPAT_NETBSD6 as soon as this is available).

branches: 1.16.2;
Good-bye bus.h. Don't install <machine/bus.h>.

To use x86/cpu.h struct cpu_info from userland, we need via_padlock.h installed.

Install x86/pte.h

branches: 1.13.12; 1.13.18; 1.13.20;
Share cpu.h between the x86 ports.

branches: 1.12.6; 1.12.8; 1.12.10; 1.12.12;
- rewrite P->V tracking.
- use a hash rather than SPLAY trees.
SPLAY tree is a wrong algorithm to use here.
will be revisited if it slows down anything other than
micro-benchmarks.
- optimize the single mapping case (it's a common case) by
embedding an entry into mdpage.
- don't keep a pmap pointer as it can be obtained from ptp.
(discussed on port-i386 some years ago.)
ideally, a single paddr_t should be enough to describe a pte.
but it needs some more thoughts as it can increase computational
costs.
- pmap_enter: simplify and fix races with pmap_sync_pv.
- don't bother to lock pm_obj[i] where i > 0, unless DIAGNOSTIC.
- kill mp_link to save space.
- add many KASSERTs.

branches: 1.11.2; 1.11.8;
merge yamt-x86pmap branch.

- reduce differences between amd64 and i386. notably, share pmap.c
between them. it makes several i386 pmap improvements available to
amd64, including tlb shootdown reduction and bug fixes from Stephan Uphoff.
- implement deferred pmap switching for amd64.
- remove LARGEPAGES option. always use large pages if available.
also, make it work on amd64.

branches: 1.10.10; 1.10.12; 1.10.14; 1.10.16;
+ x86/sysarch.h

branches: 1.9.2; 1.9.6; 1.9.8;
Merge newlock2 to head.

Report on and where possible, try to work around some of the known errata
for Athlon 64 and Opteron processors. Tested briefly by cube@ and elad@.

branches: 1.7.14;
Revert yesterday's change that attempted to fix the detection of the
boot device when using a Multiboot boot loader. It couldn't work because
these boot loaders do not pass a checksum of the disk so matchbiosdisk()
cannot really find any matches. I should have gone to sleep before
commiting...

Found by xtraeme@.

branches: 1.6.2;
When booting an i386 kernel with Multiboot, properly detect the boot device
by looking it up in the x86_alldisks table (instead of trying to match it
to 'wd*' manually).

In order to do this, move the cpu_rootconf function from x86 common code
to amd64 and i386 specific one. This way, i386 can do an extra step (call
the appropriate Multiboot code) in the appropriate place (after
x86_matchbiosdisks and before findroot()).

branches: 1.5.16; 1.5.30;
Use a common <machine/math.h> for amd64 and i386.

branches: 1.4.2;
Install cacheinfo.h

Install cpuvar.h

Move a few more files to x86/include. Trim the list of files to install
in /usr/include a bit.

Install header files.

Add acpi_intr_mask() and acpi_intr_unmask() which, following the pre-existing
ACPI software layering model, are wrappers around acpi_md_intr_mask() and
acpi_md_intr_unmask(), which in turn are wrappers around intr_mask() and
intr_unmask().

XXX ARM and IA64 implementations of acpi_md_intr_mask() and
acpi_md_intr_unmask() are just stubs for now.

Add MD functions for establishing and disestablishing interrupt handlers.

branches: 1.12.2;
Allow registering ACPI interrupt handlers with a xname.
AcpiOsInstallInterruptHandler(), part of ACPICA API, doesn't allow passing
the xname. I extend the API with AcpiOsInstallInterruptHandler_xname()
for this purpose, and change acpi_md_OsInstallInterruptHandler() to
accept and use the xname (ia64 doens't use it).
The xname was hardcoded to "acpi SCI" in the
x86 acpi_md_OsInstallInterruptHandler(), so I make
AcpiOsInstallInterruptHandler() call
AcpiOsInstallInterruptHandler_xname with xname = "acpi SCI".

Now 'vmstat -i' shows the device's name instead of "acpi SCI" for for i2c HID
interrupts.

Proposed on tech-kern@ on Dec 29.

branches: 1.11.36;
locate PCI buses and determine their bus numbers using the info
previously extracted from ACPICA rather than trying to figure it out again.
allow PCI buses that don't have a _PRT method.

branches: 1.10.2; 1.10.8; 1.10.12;
Follow IA-64 with the x86-specific ACPI MD functions and move these where
they belong to. Remove an unused function. Minor KNF. No functional change.

Move the evaluation of the _PDC control method out from the acpicpu(4)
driver to the main acpi(4) stack. Follow Linux and evaluate it early.
Should fix PR port-amd64/42895, possibly also PR kern/42583, and many
other comparable bugs.

A common sense explanation is that Intel supplies additional CPU tables to
OEMs. BIOS writers do not bother to modify their DSDTs, but instead load
these extra tables dynamically as secondary SSDT tables. The actual Load()
happens when the _PDC method is invoked, and thus namespace errors occur
when the CPU-specific ACPI methods are not yet present but referenced in the
AML by various drivers, including, but not limited to, acpitz(4).

branches: 1.8.6;
Move the function that counts the CPUs from acpicpu(4) to the MD layer.

Revert the previous partially for the time being.

Move ACPI_FLUSH_CPU_CACHE() (a.k.a. WBINVD on x86) to MD headers where it
belongs to. Let IA-64 define its own function/instruction instead of
requiring a dummy wbinvd() to satisfy the definition in a MI header.

branches: 1.5.2; 1.5.4;
Add acpi_md_OsEnableInterrupt, to go with acpi_md_OsDisableInterrupt

branches: 1.4.10; 1.4.18; 1.4.24;
Move mapping of the real mode location for the ACPI wakeup code into a
separate function called from acpi_md_callback.

branches: 1.3.2;
Merge jmcneill-pm branch.

branches: 1.2.2; 1.2.56; 1.2.58; 1.2.68; 1.2.70;
Merge changes for ACPI-CA 20050408.

branches: 1.1.2;
Moved here from sys/arch/i386/include.

Move some files out of i386 into x86, so that they can be shared with
other ports.

Add support for CPUID leaf 0x40000010 to detect TSC and LAPIC frequency on
hypervisors implementing the VMware-defined interface

This change enables virtual machines to obtain TSC and LAPIC frequency
information directly from the hypervisor via CPUID leaf 0x40000010, avoiding
the need for runtime calibration, thus reducing boot speed in supported
environments.

Tested on GENERIC and MICROVM kernels, QEMU/KVM and QEMU/NVMM (current and
10.1), Intel and AMD CPUs, NetBSD/amd64 and i386.

Revert VMware-compatible TSC and LAPIC frequency detection.

Add support for CPUID leaf 0x40000010, which enables VMware-compatible TSC
and LAPIC frequency detection for virtual machines.

branches: 1.8.26;
Merge the bouyer-xenpvh branch, bringing in Xen PV drivers support under HVM
guests in GENERIC.
Xen support can be disabled at runtime with
boot -c
disable hypervisor

Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.

- If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors
can take TSC/core crystal clock ratio but core crystal clock frequency
can't be taken. Intel SDM give us the values for some processors.
- It also required to change lapic_per_second to make LAPIC timer correctly.
- Add new file x86/x86/identcpu_subr.c to share common subroutines between
kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c
will be moved to this file in future.
- Add comment to clarify.

branches: 1.6.2; 1.6.8;
- Dump LAPIC and I/O APIC correctly.
- Don't print redirect target on LAPIC.
- Fix DEST_MASK:
- DEST_MASK is not 1 bit but 2 bit.
- Add missing "\0"s to print decoded name correctly.
- Support both LAPIC and I/O APIC correctly in apic_format_redir().
- Improve output of some bits using with snprintb()'s "F\B\1" and ":\V".

branches: 1.5.80; 1.5.88;
Remove clause 3 and 4 from TNF licenses

branches: 1.4.40; 1.4.42; 1.4.44;
clean up how cpus and ioapics are attached at the mainbus:
Seperate "cpubus" and "ioapicbus" -- while they share a common "address
space" (the apic id), the kernel doesn't use this fact. There are different
data passed to cpus and apics, which caused some ugly polymorphism. This
also saves the special "submatch" functions needed to distingush cpus
and ioapics for autoconf. (And it makes that "apid" locators wired
in the kernel configuration are honored now; this allows one to dumb down
an mp box to singleprocessor by userconfig.)
Print "apid" locators in the buses "print" function "as everyone does",
so the per-port cpu drivers don't need to do it.
Being here, constify "struct cpu_functions" and g/c the unused MP_PICMODE
flag.

branches: 1.3.2; 1.3.34;
Sprinkle const.

Nuke __P().

branches: 1.1.2;
Move some files out of i386 into x86, so that they can be shared with
other ports.

Added drivers for Hyper-V Synthetic Keyboard and Video device.

This change modifies the mainbus(4) entry point for all x86 sub-archs
in the following way:

i) It provides a unified entry point in
x86/x86/mainbus.c:mainbus_attach()
ii) It carves out the preliminary bus attachment sequence that is
common to all sub-archs into
x86/x86/mainbus.c: x86_cpubus_attach()
iii) It consolidates the remaining pathways as internal callee
functions so that these may be called piecemeal if required. A
special usecase of this is XEN PVHVM which may need to call the
native configure path, the xen configure path, or both.
iv) It moves the driver private data structures from
i386/i386_mainbus.c to an x86/ level one. This allows for other
sub-arch's to do similar, if needed. (They do not at the moment).
v) For dom0 kernels, it enables 'acpi0 at mainbus?' and
'acpi0 at hypervisorbus'. This serves two purposes:
a) To demonstrate the possibility of dynamic configuration tree
traversal ordering changes.
b) To allow for the common acpi_check(self, "acpibus") call in
x86/mainbus.c to not barf when it is called from the dom0 attach
path. We allow for the acpi0 device to be a child of mainbus with
the changes to amd64/conf/XEN3_DOM0 and i386/conf/XEN3PAE_DOM0
without actually probing further in the code. This path will later
be pursued in a PVHVM boot codepath.

There should be no operative changes with this change. If there are,
please complain loudly.

branches: 1.4.8; 1.4.14; 1.4.16;
Set hw.acpi.sleep.vbios when a non-HW accelerated VGA driver attaches.
If the VGA_POST option is present in the kernel the default value is 2,
otherwise 1. PR kern/50781

Reviewed by: agc, mrg

branches: 1.3.12; 1.3.30; 1.3.34;
Define some optional routines that will help device_register() to
register ISA & PCI devices. Add stub implementations of the routines.

Revert yesterday's change that attempted to fix the detection of the
boot device when using a Multiboot boot loader. It couldn't work because
these boot loaders do not pass a checksum of the disk so matchbiosdisk()
cannot really find any matches. I should have gone to sleep before
commiting...

Found by xtraeme@.

branches: 1.1.2;
When booting an i386 kernel with Multiboot, properly detect the boot device
by looking it up in the x86_alldisks table (instead of trying to match it
to 'wd*' manually).

In order to do this, move the cpu_rootconf function from x86 common code
to amd64 and i386 specific one. This way, i386 can do an extra step (call
the appropriate Multiboot code) in the appropriate place (after
x86_matchbiosdisks and before findroot()).

Remove clause 3 and 4 from TNF licenses

branches: 1.4.6; 1.4.8; 1.4.10;
Convert many of the uses of __attribute__ to equivalent
__packed, __unused and __dead macros from cdefs.h

branches: 1.3.20; 1.3.26; 1.3.28; 1.3.32;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.2.16; 1.2.54;
Nuke __P().

branches: 1.1.2;
Move some files out of i386 into x86, so that they can be shared with
other ports.

Introduce pvh_boot boolean to identify the real hypervisor when booting in PVH
mode.

As of now, sys/arch/x86/x86/identcpu.c / identify_hypervisor() returns in the
case of vm_guest being VM_GUEST_GENPVH, yet this VM type is not an actual
hypervisor but an information recorded in locore.S to drive boot method.
We need to investigate what type of hypervisor is really running the VM in
order to apply specifics, so instead of relying on vm_guest_is_pvh() which only
checks for VM_GUEST_XENPVH || VM_GUEST_GENPVH, pvh_boot informs on the boot
method while allowing to identify the real hypervisor.

Idea ok'd by bouyer@, tested on Xen domU, Xen dom0 with GENERIC PVH and
qemu GENERIC PVH boot.

branches: 1.31.10;
x86/bootinfo.h: Add include guard.

PR/54147: Increase BOOTINFO_MAXSIZE to 16Kib.

Some systems require a larger bootinfo size for memory descriptors.

branches: 1.29.2;
x86: Increase BOOTINFO_MAXSIZE to 8Kib.

Proposed on port-i386 and port-amd64 with no objections:
http://mail-index.netbsd.org/port-i386/2018/04/11/msg003692.html
http://mail-index.netbsd.org/port-amd64/2018/04/11/msg002697.html

branches: 1.28.2;
add "prekern" to the string list.

Add a new option in libsa, to load dynamic binaries. A separate function
is used, and it does not break in any way the generic static loader. Then,
add a new "pkboot" command in the x86 bootloader, which boots a
GENERIC_KASLR kernel via the prekern. (See thread on tech-kern@.)

branches: 1.26.6;
x86: add e820 memory type.

Initial commit of native amd64 EFI boot loader.

branches: 1.24.2; 1.24.4;
Add support for grub to find the ACPI root table pointer via a bootinfo entry
from grub.
From: https://mail-index.netbsd.org/tech-kern/2014/05/22/msg017119.html

branches: 1.23.6;
Add support for using a raw file-system image as memory disk root with
the x86 bootloader.

branches: 1.22.2;
Complete the dosparts -> mbrparts conversion. Only x86k new uses dosparts
because it also uses struct dos_partition.

Complete the dosparts -> mbrparts conversion. Only x86k new uses dosparts
because it also uses struct dos_partition.

Complete the dosparts -> mbrparts conversion. Only x86k new uses dosparts
because it also uses struct dos_partition.

branches: 1.19.8;

Add support for passing saved entropy (random seed file) to the kernel
from the bootloader. This can fix the problem of poor quality keys
for other kernel modules which call arc4random() early in kernel startup
(NFS startup, in particular, causes this).

We continue to rely on the etc/rc.d/random_seed script to save entropy
to the seed file at shutdown and erase the seed file at startup.

Boot loader support implemented only for i386 and amd64 ports for now but
it should be easy for other ports to do the same or similar.

branches: 1.18.4;
Support userconf(4) command in boot(8)/boot.cfg(5) on i386/amd64.

From jmmv@, no objections seen in the proposed thread:

http://mail-index.netbsd.org/tech-kern/2009/01/22/msg004081.html

add BI_MODULE_IMAGE boot module type

branches: 1.16.4; 1.16.6; 1.16.8;
Pass the VBE mode number from the bootloader to the kernel, and then
make the ACPI wakecode aware of it. Restore the desired VBE mode on resume
when acpi_vbios_reset=1, so suspend/resume with genfb console will work.

Kernel-side modifications for framebuffer console support on i386 and amd64.

* New BTINFO_FRAMEBUFFER kernel parameter to pass screen configuration
* Early attach support for framebuffer console
* Pass BTINFO_FRAMEBUFFER parameters to genfb in device_register
* Provide hooks to genfb to set VGA DAC palette in 8bpp mode

branches: 1.14.2; 1.14.8;
Remove duplicate definition of "bootinfo" structure.
Patch provided by Juan RP in PR kern/39495.

branches: 1.13.2; 1.13.6;
- Give x86 BIOS boot the ability to load new style modules and pass them
into the kernel. Based on a patch by jmcneill@, with many fixes and
improvements by me.

- Put MEMORY_DISK_DYNAMIC and MODULAR into the GENERIC kernels, so that
you can load miniroot.kmod from the boot blocks and boot into the
installer!

branches: 1.12.6; 1.12.8; 1.12.10;
Convert many of the uses of __attribute__ to equivalent
__packed, __unused and __dead macros from cdefs.h

branches: 1.11.46; 1.11.52; 1.11.56; 1.11.60;
Implement support for 'The Multiboot Specification' so that i386 kernels
can be booted directly from Multiboot-compliant boot loaders (e.g. GRUB).
See the added multiboot(8) manual page for more information.

No objections in tech-kern@; only positive comments.

branches: 1.10.2; 1.10.4;
Add a 'struct bootinfo' to represent the bootinfo structure used in the
kernel by x86 platforms (instead of a simple char *). This way, the code
in, e.g., lookup_bootinfo, is a bit easier to understand.

While here, move the lookup_bootinfo function used in x86 platforms (amd64,
i386 and xen) to a common file (x86/x86_machdep.c), as it was exactly the
same in all of them.

branches: 1.9.2;
BIOSDISK_EXT13INFO_V3 -> BIOSDISK_EXTINFO_V3
u_intNN_t -> uintNN_t
u_int -> unsigned int
Remove trailing spaces

Make disklabel(8) and fdisk(8) into "host tools " last step: build
and install ${TOOLDIR}/bin/${MACHINE_GNU_PLATFORM}-disklabel,
${TOOLDIR}/bin/${MACHINE_GNU_PLATFORM}-fdisk by "reaching over" to
the sources in ${NETBSDSRCDIR}/sbin/{disklabel fdisk}/.

To avoid clashes with a build-host's header files, especially on
*BSD, the host-tools versions of fdisk and disklabel search for
#includes such as disklabel.h, disklabel_acorn.h, disklabel_gpt.h,
and bootinfo.h in a new #includes namespace, nbinclude/. That is,
they #include <nbinclude/sys/disklabel.h>, <nbinclude/machine/disklabel.h>,
<nbinclude/sparc64/disklabel.h>, instead of <sys/disklabel.h> and
such. I have also updated the system headers to #include from
nbinclude/-space when HAVE_NBTOOL_CONFIG_H is #defined.

The bootinfo_wedge structure must be packed, or the 32bit alignments
used by the bootloader don't match the amd64 kernel.

branches: 1.6.4; 1.6.6;
Add support for passing booted wedge information to the kernel.

remove license clauses 3 and 4 from my cpoyright notices

Nuke __P().

Overhaul MBR handling (part 1):

<sys/bootblock.h>:
* Added definitions for the Master Boot Record (MBR) used by
a variety of systems (primarily i386), including the format
of the BIOS Parameter Block (BPB).
This information was cribbed from a variety of sources
including <sys/disklabel_mbr.h> which this is a superset of.

As part of this, some data structure elements and #defines
were renamed to be more "namespace friendly" and consistent
with other bootblocks and MBR documentation.
Update all uses of the old names to the new names.

<sys/disklabel_mbr.h>:
* Deprecated in favor of <sys/bootblock.h> (the latter is more
"host tool" friendly).

amd64 & i386:
* Renamed /usr/mdec/bootxx_dosfs to /usr/mdec/bootxx_msdos, to
be consistent with the naming convention of the msdosfs tools.

* Removed /usr/mdec/bootxx_ufs, as it's equivalent to bootxx_ffsv1
and it's confusing to have two functionally equivalent bootblocks,
especially given that "ufs" has multiple meanings (it could be
a synonym for "ffs", or the group of ffs/lfs/ext2fs file systems).

* Rework pbr.S (the first sector of bootxx_*):
+ Ensure that BPB (bytes 11..89) and the partition table
(bytes 446..509) do not contain code.
+ Add support for booting from FAT partitions if BOOT_FROM_FAT
is defined. (Only set for bootxx_msdos).
+ Remove "dummy" partition 3; if people want to installboot(8)
these to the start of the disk they can use fdisk(8) to
create a real MBR partition table...
+ Compile with TERSE_ERROR so it fits because of the above.
Whilst this is less user friendly, I feel it's important
to have a valid partition table and BPB in the MBR/PBR.

* Renamed /usr/mdec/biosboot to /usr/mdec/boot, to be consistent
with other platforms.

* Enable SUPPORT_DOSFS in /usr/mdec/boot (stage2), so that
we can boot off FAT partitions.

* Crank version of /usr/mdec/boot to 3.1, and fix some of the other
entries in the version file.

installboot(8) (i386):
* Read the existing MBR of the filesystem and retain the BIOS
Parameter Block (BPB) in bytes 11..89 and the MBR partition
table in bytes 446..509. (Previously installboot(8) would
trash those two sections of the MBR.)

mbrlabel(8):
* Use sys/lib/libkern/xlat_mbr_fstype.c instead of homegrown code
to map the MBR partition type to the NetBSD disklabel type.


Test built "make release" for i386, and new bootblocks verified to work
(even off FAT!).

branches: 1.2.2;
Add definitions (#defined out) to pass the result of the v3.x bios
extended disk information request to the kernel.
Binary compatible with the existing code, disabled because I don't
have a system with a bios that supports the request.

Move some files out of i386 into x86, so that they can be shared with
other ports.

x86: Split bootspace out of x86/pmap.h into new x86/bootspace.h.

Good-bye bus.h. Don't install <machine/bus.h>.

On x86, change the bus_space_tag_t to a pointer to a struct
bus_space_tag. For now, bus_space_tag's only member is
bst_type, the type of space, which is either X86_BUS_SPACE_IO
or X86_BUS_SPACE_MEM. In the future, new bus_space_tag members
will refer to override-functions installed by a new function,
bus_space_tag_create(9).

Add pointers to constant struct bus_space_tag, x86_bus_space_io and
x86_bus_space_mem. Use them to replace most uses of X86_BUS_SPACE_IO
and X86_BUS_SPACE_MEM.

Add an x86-specific bus_space_is_equal(9) implementation that compares
the two tags' bst_type.

branches: 1.19.2; 1.19.4;
Change bus_size_t from paddr_t to size_t. It doens't make sense to have
a 64bit bus_size_t on i386 as the address space is 32bits anyway.
With a 64bit bus_size_t we need a different bus_space.S for PAE and non-PAE.

branches: 1.18.2;
Apply patch proposed on port-amd64/port-i386, allowing to use a 64bit
bus_addr_t on i386PAE kernels:
change bus_addr_t to be a paddr_t (so its size follows paddr_t depending
on options PAE)
remplace bus_addr_t with vaddr_t where the value is used as a virtual address.

Difference with the proposed patch: cast to uintmax_t and use %jx in
printf() as suggested by Joerg.

Use NULL instead of (bus_dma_tag_t)0.

branches: 1.16.6; 1.16.8; 1.16.10; 1.16.14;
Remove clause 3 and 4 from TNF licenses

branches: 1.15.16; 1.15.18; 1.15.20;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

x86 changes for pcc and LKMs.

- Replace most inline assembly with proper functions. As a side effect
this reduces the size of amd64 GENERIC by about 120kB, and i386 by a
smaller amount. Nearly all of the inlines did something slow, or something
that does not need to be fast.
- Make curcpu() and curlwp functions proper, unless __GNUC__ && _KERNEL.
In that case make them inlines. Makes curlwp LKM and preemption safe.
- Make bus_space and bus_dma more LKM friendly.
- Share a few more files between the ports.
- Other minor changes.

branches: 1.13.2; 1.13.10; 1.13.18; 1.13.20; 1.13.22;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

add a pair of new bus_dma(9) functions:
int _bus_dmatag_subregion(bus_dma_tag_t tag,
bus_addr_t min_addr,
bus_addr_t max_addr,
bus_dma_tag_t *newtag,
int flags)
void _bus_dmatag_destroy(bus_dma_tag_t tag)

that allow a (normally broken/limited) device to restrict the bus address
range it can talk to. this is used by bce(4) to limit DMA addresses to
1GB range, the maximum the chip can address.

all this is from Yorick Hardy <yhardy@uj.ac.za> with input from several
people on tech-kern.

XXX: bus_dma(9) needs an update still.

branches: 1.11.20;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.

branches: 1.10.2; 1.10.4; 1.10.6;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

branches: 1.9.2;
tweak x86 bus_dma code so that it can be used by xen port.

- distinguish paddr_t and bus_addr_t.
for xen, use bus_addr_t in the sense of machine address.
- move _X86_BUS_DMA_PRIVATE part of bus.h into bus_private.h.
- remove special handling of xen_shm. we can always grab
machine address from pte.

branches: 1.8.2;
Add a dm_maxsegsz public member to bus_dmamap_t. This allows a user of the API
to select the maximum segment size for each bus_dmamap_load (up to the maxsegsz
supplied to bus_dmamap_create). dm_maxsegsz is reset to the value supplied to
bus_dmamap_create when the dmamap is unloaded.

branches: 1.7.4; 1.7.6;
Remove the "ID" component of the x86 bus_dma flags, since these are no
longer "ISA DMA" specific flags.

unexport following x86 bus_dma internal functions.
_bus_dma_alloc_bouncebuf
_bus_dma_free_bouncebuf
_bus_dmamap_load_buffer

issue memory read barrier for BUS_DMASYNC_POSTREAD operation.
PR/21665 from Stephan Uphoff.

Nuke __P().

branches: 1.3.2;
Handle 64bit DMA addresses on PCI for platforms that can (currently only
enabled on amd64). Add a dmat64 field to various PCI attach structures,
and pass it down where needed. Implement a simple new function called
pci_dma64_available(pa) to test if 64bit DMA addresses may be used.
This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>,
and there is more than 4G of memory.

Generalize bounce buffers, and use them for 32 bit PCI if needed.
Make ALLOCNOW the default iff bouncing might be needed (this has
no effect on i386 because ISA DMA devices already had to use
ALLOCNOW, and PCI isn't bounced (yet), since we don't do > 4G
at this point for i386.

Move some files out of i386 into x86, so that they can be shared with
other ports.

PRIxXXXX (etc) definitions should not include the %

Will fix anything this ends up breaking later.

branches: 1.5.8;
Add support for Kernel Memory Sanitizer (kMSan). It detects uninitialized
memory used by the kernel at run time, and just like kASan and kCSan, it
is an excellent feature. It has already detected 38 uninitialized variables
in the kernel during my testing, which I have since discreetly fixed.

We use two shadows:
- "shad", to track uninitialized memory with a bit granularity (1:1).
Each bit set to 1 in the shad corresponds to one uninitialized bit of
real kernel memory.
- "orig", to track the origin of the memory with a 4-byte granularity
(1:1). Each uint32_t cell in the orig indicates the origin of the
associated uint32_t of real kernel memory.

The memory consumption of these shadows is consequent, so at least 4GB of
RAM is recommended to run kMSan.

The compiler inserts calls to specific __msan_* functions on each memory
access, to manage both the shad and the orig and detect uninitialized
memory accesses that change the execution flow (like an "if" on an
uninitialized variable).

We mark as uninit several types of memory buffers (stack, pools, kmem,
malloc, uvm_km), and check each buffer passed to copyout, copyoutstr,
bwrite, if_transmit_lock and DMA operations, to detect uninitialized memory
that leaves the system. This allows us to detect kernel info leaks in a way
that is more efficient and also more user-friendly than KLEAK.

Contrary to kASan, kMSan requires comprehensive coverage, ie we cannot
tolerate having one non-instrumented function, because this could cause
false positives. kMSan cannot instrument ASM functions, so I converted
most of them to __asm__ inlines, which kMSan is able to instrument. Those
that remain receive special treatment.

Contrary to kASan again, kMSan uses a TLS, so we must context-switch this
TLS during interrupts. We use different contexts depending on the interrupt
level.

The orig tracks precisely the origin of a buffer. We use a special encoding
for the orig values, and pack together in each uint32_t cell of the orig:
- a code designating the type of memory (Stack, Pool, etc), and
- a compressed pointer, which points either (1) to a string containing
the name of the variable associated with the cell, or (2) to an area
in the kernel .text section which we resolve to a symbol name + offset.

This encoding allows us not to consume extra memory for associating
information with each cell, and produces a precise output, that can tell
for example the name of an uninitialized variable on the stack, the
function in which it was pushed on the stack, and the function where we
accessed this uninitialized variable.

kMSan is available with LLVM, but not with GCC.

The code is organized in a way that is similar to kASan and kCSan, so it
means that other architectures than amd64 can be supported.

Add DMA instrumentation in KASAN. We note the original buffer and length in
the map, and check the buffer on each bus_dmamap_sync. This allows us to
find DMA buffer overflows and UAFs, which couldn't be found before because
the device accesses to memory are outside of KASAN's control.

Provide PRIxBUSADDR, PRIxBUSSIZE, PRIuBUSSIZE, and PRIxBSH for all arches
to follow arm and (generic) mips.

Reviewed by christos.

branches: 1.2.2; 1.2.56;
Add to x86 bus_space_tag_t a member, bst_exists, that tells whether a
routine is overridden by this tag or by any ancestral tag.

Per discussion at
<http://mail-index.netbsd.org/tech-kern/2010/04/02/msg007941.html>,
divide each machine's bus.h into bus_defs.h (constants & data types)
and bus_funcs.h (macro implementations of bus_space(9) routines and MD
prototypes).

Note that some bus_space(9) routines' implementation will move to .c
files from inline subroutines or macros in .h files.

I've only made the split for machine architectures where there is PCI.
All of the non-PCI-having architectures will require a similar split.

These #include files are not referenced by any (committed) Makefiles or
header files, yet. Changes to Makefiles, to <sys/bus.h>, and to some
more machine-dependent files will dribble in before I throw the switch.

branches: 1.1.2;
Per discussion at
<http://mail-index.netbsd.org/tech-kern/2010/04/02/msg007941.html>,
divide each machine's bus.h into bus_defs.h (constants & data types)
and bus_funcs.h (macro implementations of bus_space(9) routines and MD
prototypes).

Note that some bus_space(9) routines' implementation will move to .c
files from inline subroutines or macros in .h files.

I've only made the split for machine architectures where there is PCI.
All of the non-PCI-having architectures will require a similar split.

These #include files are not referenced by any (committed) Makefiles or
header files, yet. Changes to Makefiles, to <sys/bus.h>, and to some
more machine-dependent files will dribble in before I throw the switch.

Ensure bus_dmatag_subregion is called with an inclusive max_addr
everywhere.

remove some unnecessary includes of internal UVM headers.

branches: 1.14.54; 1.14.60;
Add bus_dma overrides. From dyoung

Add override members to x86_bus_dma_tag.

Pull in uvm/uvm.h for VM_PAGE_TO_PHYS().

branches: 1.11.14; 1.11.22;
Remove clause 3 and 4 from TNF licenses

branches: 1.10.16; 1.10.18; 1.10.20;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

x86 changes for pcc and LKMs.

- Replace most inline assembly with proper functions. As a side effect
this reduces the size of amd64 GENERIC by about 120kB, and i386 by a
smaller amount. Nearly all of the inlines did something slow, or something
that does not need to be fast.
- Make curcpu() and curlwp functions proper, unless __GNUC__ && _KERNEL.
In that case make them inlines. Makes curlwp LKM and preemption safe.
- Make bus_space and bus_dma more LKM friendly.
- Share a few more files between the ports.
- Other minor changes.

branches: 1.8.2; 1.8.10; 1.8.18; 1.8.20; 1.8.22;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

add a pair of new bus_dma(9) functions:
int _bus_dmatag_subregion(bus_dma_tag_t tag,
bus_addr_t min_addr,
bus_addr_t max_addr,
bus_dma_tag_t *newtag,
int flags)
void _bus_dmatag_destroy(bus_dma_tag_t tag)

that allow a (normally broken/limited) device to restrict the bus address
range it can talk to. this is used by bce(4) to limit DMA addresses to
1GB range, the maximum the chip can address.

all this is from Yorick Hardy <yhardy@uj.ac.za> with input from several
people on tech-kern.

XXX: bus_dma(9) needs an update still.

branches: 1.6.8;
Some bus_dma(9) fixes for Xen:
- Attempt to gracefully recover from a failed decrease_reservation or
increase_reservation, by avoiding physical memory loss.
- always store a machine address in ds_addr; this avoids some mistakes
where machine address would in some case be freed at physical address, or
mapped as physical address.

branches: 1.5.2; 1.5.12;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.

branches: 1.4.2; 1.4.4; 1.4.6;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

branches: 1.3.6;
Rename _PRIVATE_BUS_DMAMEM_ALLOC_RANGE to _BUS_DMAMEM_ALLOC_RANGE for
consistency with other macros defined in bus_private.h. Pointed out by
YAMAMOTO Takashi.

More adjustements to deal with Xen's physical <=> machine addresses mappings:
- Allow _bus_dmamem_alloc_range to be provided from external source:
Use a _PRIVATE_BUS_DMAMEM_ALLOC_RANGE macro, defined to
_bus_dmamem_alloc_range by default.
- avail_end is the end of the physical address range. Define a macro
_BUS_AVAIL_END (defined by default to avail_end) and use it instead.

branches: 1.1.2; 1.1.4; 1.1.6;
add files which i forgot to add with arch/x86/x86/bus_dma.c rev.1.21.

Remove clause 3 and 4 from TNF licenses

branches: 1.1.2; 1.1.4; 1.1.6; 1.1.10; 1.1.14; 1.1.28; 1.1.30; 1.1.32;
x86 changes for pcc and LKMs.

- Replace most inline assembly with proper functions. As a side effect
this reduces the size of amd64 GENERIC by about 120kB, and i386 by a
smaller amount. Nearly all of the inlines did something slow, or something
that does not need to be fast.
- Make curcpu() and curlwp functions proper, unless __GNUC__ && _KERNEL.
In that case make them inlines. Makes curlwp LKM and preemption safe.
- Make bus_space and bus_dma more LKM friendly.
- Share a few more files between the ports.
- Other minor changes.

Print TLB message consistently to improve readability.

Example:
cpu0: L2 cache: 256KB 64B/line 4-way
cpu0: L3 cache: 4MB 64B/line 16-way
cpu0: 64B prefetching
-cpu0: ITLB: 64 4KB entries 8-way, 2M/4M: 8 entries
+cpu0: ITLB: 64 4KB entries 8-way, 8 2M/4M entries
cpu0: DTLB: 64 4KB entries 4-way, 4 1GB entries 4-way
cpu0: L2 STLB: 1536 4KB entries 6-way
cpu0: Initial APIC ID 0

Move some common functions into x86/identcpu_subr.c. No functional change.

Add Load Only TLB and Store Only TLB.

branches: 1.28.2;
- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
Intel Deterministic Cache Parameter Leaf(0x04), so make new
cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
common definition.
- KNF.

XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?

It seems that AMD zen2's CPUID 0x80000006 leaf's spec has changed.
The EDX register's acsociativity field has 9. In the latest available document,
it's a reserved value. I have no access to zen2's document, but many websites
say that the acsociativity is 16. Add it.

branches: 1.26.2;
AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.

Add 3way and 6way of L2 cache or TLB on AMD CPU.

Add yet another Shared L2 TLB (2M/4M pages).

XXX need redesign.

branches: 1.23.2;
Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.

branches: 1.22.10;
Add new desc 0x64 and 0xc4.

Index 0x6c is not 126 entries but 128 entries. The old value was from
previous SDM.

Add some TLB entries from the latest Intel SDM. This change might be incorrect
because the document itself is very strange.

branches: 1.19.2;
Add new cache descriptor (0xc3) from the latest Intel SDM.

branches: 1.18.2;
Fix some entries:
- Desc 0x55 and 0xb1 are Instruction TLB but not fixed to 4K.
- Desc 0x5a and 0xc0 are Data TLB but not fixed to 4K.
- Desc 0x57 and 0x59 are 4K fixed DTLB.
- Fix string of desc 0xc2 and it's not fixed to 4K.
- Desc 0xca is 4K fixed L2 shared TLB.
- Add desc 0xa0.

BUG: A lot of CPUs have multiple CAI_DTLB and/or CAI_DTLB2 entries. Currently
TLB info is indexed in ci_cinfo[CAI_COUNT], so some info is overwritten.

Nowadays CPUs have very complexed TLBs. It's hard to manage with CAI_* index.
We should think to separate TLB info structure from ci_cinfo[CAI_COUNT]
in struct cpu_info.

branches: 1.17.2;
Support prefetch size.

Add Shared L2 TLB and some cache and tlb entries from the latest document.

Add some new TLB and cache entries from document (Table 3-22 Encoding of CPUID
Leaf 2 Descriptors, Intel 64 and IA-32 Architectures Software Developer's
Manual Vol. 2A.)

Fix 0x0d's DCACHE entry and 0xeb's L3CACHE entry from the document
(Table 3-22 Encoding of CPUID Leaf 2 Descriptors, Intel 64 and IA-32
Architectures Software Developer's Manual Vol. 2A.)

branches: 1.13.2; 1.13.6; 1.13.10;
add info on L2 TLBs and 1GB pages.

branches: 1.12.12; 1.12.16;
Fix toyp in previous. Pointed out by snj@

1. Extend CPU probe of Intel processors to handle extended-models. This
allows us to properly identify new Intel 45nm processors, Core i7,
Atom, and the 45nm Xeon MP.

2. Properly decode several new Intel cache descriptors, as listed in the
most recent (March 2009) edition of Intel's Application Note 485.

3. Convert decode of the various features masks to use the newly added
snprintb_m(3) routine.

Addresses my PR bin/41289
Addresses my PR bin/41290

Constify a userland-only member.

branches: 1.9.6; 1.9.8; 1.9.12; 1.9.16;
don't undef __CI_TBL before we use it :-)

- fix an amd cache entry.
- merge tables
- support phenom
from Paul Goyette

PR/38722: Paul Goyette: Share cacheinfo information

print L3 and TLB cache information for AMD Barcelona/Phenom

Simplify x86 identcpu code, and share between i386/amd64.