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History log of /src/sys/arch/x86/include/cacheinfo.h
RevisionDateAuthorComments
 1.31  09-Dec-2021  msaitoh Print TLB message consistently to improve readability.

Example:
cpu0: L2 cache: 256KB 64B/line 4-way
cpu0: L3 cache: 4MB 64B/line 16-way
cpu0: 64B prefetching
-cpu0: ITLB: 64 4KB entries 8-way, 2M/4M: 8 entries
+cpu0: ITLB: 64 4KB entries 8-way, 8 2M/4M entries
cpu0: DTLB: 64 4KB entries 4-way, 4 1GB entries 4-way
cpu0: L2 STLB: 1536 4KB entries 6-way
cpu0: Initial APIC ID 0
 1.30  07-Oct-2021  msaitoh Move some common functions into x86/identcpu_subr.c. No functional change.
 1.29  27-Sep-2021  msaitoh Add Load Only TLB and Store Only TLB.
 1.28  26-Jul-2019  msaitoh branches: 1.28.2;
- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
Intel Deterministic Cache Parameter Leaf(0x04), so make new
cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
common definition.
- KNF.

XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?
 1.27  24-Jul-2019  msaitoh It seems that AMD zen2's CPUID 0x80000006 leaf's spec has changed.
The EDX register's acsociativity field has 9. In the latest available document,
it's a reserved value. I have no access to zen2's document, but many websites
say that the acsociativity is 16. Add it.
 1.26  12-Mar-2018  msaitoh branches: 1.26.2;
AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.
 1.25  12-Mar-2018  msaitoh Add 3way and 6way of L2 cache or TLB on AMD CPU.
 1.24  09-Mar-2018  msaitoh Add yet another Shared L2 TLB (2M/4M pages).

XXX need redesign.
 1.23  05-Mar-2018  msaitoh branches: 1.23.2;
Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.
 1.22  27-Apr-2016  msaitoh branches: 1.22.10;
Add new desc 0x64 and 0xc4.
 1.21  08-Jan-2016  msaitoh Index 0x6c is not 126 entries but 128 entries. The old value was from
previous SDM.
 1.20  19-Oct-2015  msaitoh Add some TLB entries from the latest Intel SDM. This change might be incorrect
because the document itself is very strange.
 1.19  09-Sep-2014  msaitoh branches: 1.19.2;
Add new cache descriptor (0xc3) from the latest Intel SDM.
 1.18  03-Jul-2014  msaitoh branches: 1.18.2;
Fix some entries:
- Desc 0x55 and 0xb1 are Instruction TLB but not fixed to 4K.
- Desc 0x5a and 0xc0 are Data TLB but not fixed to 4K.
- Desc 0x57 and 0x59 are 4K fixed DTLB.
- Fix string of desc 0xc2 and it's not fixed to 4K.
- Desc 0xca is 4K fixed L2 shared TLB.
- Add desc 0xa0.

BUG: A lot of CPUs have multiple CAI_DTLB and/or CAI_DTLB2 entries. Currently
TLB info is indexed in ci_cinfo[CAI_COUNT], so some info is overwritten.

Nowadays CPUs have very complexed TLBs. It's hard to manage with CAI_* index.
We should think to separate TLB info structure from ci_cinfo[CAI_COUNT]
in struct cpu_info.
 1.17  28-Oct-2013  msaitoh branches: 1.17.2;
Support prefetch size.
 1.16  14-Sep-2013  msaitoh Add Shared L2 TLB and some cache and tlb entries from the latest document.
 1.15  17-Jul-2013  msaitoh Add some new TLB and cache entries from document (Table 3-22 Encoding of CPUID
Leaf 2 Descriptors, Intel 64 and IA-32 Architectures Software Developer's
Manual Vol. 2A.)
 1.14  17-Jul-2013  msaitoh Fix 0x0d's DCACHE entry and 0xeb's L3CACHE entry from the document
(Table 3-22 Encoding of CPUID Leaf 2 Descriptors, Intel 64 and IA-32
Architectures Software Developer's Manual Vol. 2A.)
 1.13  04-Dec-2011  chs branches: 1.13.2; 1.13.6; 1.13.10;
add info on L2 TLBs and 1GB pages.
 1.12  13-May-2009  pgoyette branches: 1.12.12; 1.12.16;
Fix toyp in previous. Pointed out by snj@
 1.11  13-May-2009  pgoyette 1. Extend CPU probe of Intel processors to handle extended-models. This
allows us to properly identify new Intel 45nm processors, Core i7,
Atom, and the 45nm Xeon MP.

2. Properly decode several new Intel cache descriptors, as listed in the
most recent (March 2009) edition of Intel's Application Note 485.

3. Convert decode of the various features masks to use the newly added
snprintb_m(3) routine.

Addresses my PR bin/41289
Addresses my PR bin/41290
 1.10  15-Apr-2009  lukem Constify a userland-only member.
 1.9  30-May-2008  christos branches: 1.9.6; 1.9.8; 1.9.12; 1.9.16;
don't undef __CI_TBL before we use it :-)
 1.8  30-May-2008  christos - fix an amd cache entry.
- merge tables
- support phenom
from Paul Goyette
 1.7  30-May-2008  christos PR/38722: Paul Goyette: Share cacheinfo information
 1.6  11-May-2008  cegger print L3 and TLB cache information for AMD Barcelona/Phenom
 1.5  11-May-2008  ad Simplify x86 identcpu code, and share between i386/amd64.
 1.4  16-Apr-2005  yamt branches: 1.4.82; 1.4.84; 1.4.86; 1.4.88;
make multi inclusion protection macros consistent.
 1.3  17-Aug-2004  briggs branches: 1.3.4; 1.3.10;
Get correct cache information for earlier VIA C3 models.
Mostly from PR kern/26689 submitted by Michael van Elst.
 1.2  08-Aug-2004  briggs VIA C3 cache info.
 1.1  25-Apr-2003  fvdl branches: 1.1.2; 1.1.4;
Share some common cache info cpuid code between i386 and x86_64.
 1.1.4.2  22-Aug-2004  tron Pull up revision 1.3 (requested by briggs in ticket #770):
Get correct cache information for earlier VIA C3 models.
Mostly from PR kern/26689 submitted by Michael van Elst.
 1.1.4.1  12-Aug-2004  jmc Pullup rev 1.2 (requested by briggs in ticket #742)

Enable VIA C3 CPU support
 1.1.2.5  10-Nov-2005  skrll Sync with HEAD. Here we go again...
 1.1.2.4  21-Sep-2004  skrll Fix the sync with head I botched.
 1.1.2.3  18-Sep-2004  skrll Sync with HEAD.
 1.1.2.2  25-Aug-2004  skrll Sync with HEAD.
 1.1.2.1  12-Aug-2004  skrll Sync with HEAD.
 1.3.10.1  21-Apr-2005  tron Pull up revision 1.4 (requested by yamt in ticket #174):
make multi inclusion protection macros consistent.
 1.3.4.1  29-Apr-2005  kent sync with -current
 1.4.88.1  23-Jun-2008  wrstuden Sync w/ -current. 34 merge conflicts to follow.
 1.4.86.3  16-May-2009  yamt sync with head
 1.4.86.2  04-May-2009  yamt sync with head.
 1.4.86.1  16-May-2008  yamt sync with head.
 1.4.84.2  04-Jun-2008  yamt sync with head
 1.4.84.1  18-May-2008  yamt sync with head.
 1.4.82.1  02-Jun-2008  mjf Sync with HEAD.
 1.9.16.1  21-Apr-2010  matt sync to netbsd-5
 1.9.12.3  01-Nov-2009  jym Sync with HEAD.
 1.9.12.2  31-May-2009  jym Sync with HEAD.
 1.9.12.1  13-May-2009  jym Sync with HEAD.

Commit is split, to avoid a "too many arguments" protocol error.
 1.9.8.1  18-May-2009  bouyer Pull up following revision(s) (requested by pgoyette in ticket #761):
sys/arch/x86/include/cacheinfo.h: revisions 1.11, 1.12
usr.sbin/cpuctl/arch/i386.c: revisions 1.18, 1.19 via patch
1. Extend CPU probe of Intel processors to handle extended-models. This
allows us to properly identify new Intel 45nm processors, Core i7,
Atom, and the 45nm Xeon MP.
2. Properly decode several new Intel cache descriptors, as listed in the
most recent (March 2009) edition of Intel's Application Note 485.
Addresses my PR bin/41289
Addresses my PR bin/41290
 1.9.6.1  28-Apr-2009  skrll Sync with HEAD.
 1.12.16.1  18-Feb-2012  mrg merge to -current.
 1.12.12.2  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.12.12.1  17-Apr-2012  yamt sync with head
 1.13.10.2  18-May-2014  rmind sync with head
 1.13.10.1  28-Aug-2013  rmind sync with head
 1.13.6.2  03-Dec-2017  jdolecek update from HEAD
 1.13.6.1  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.13.2.1  29-Dec-2014  martin Pullup the following revisions, requested by msaitoh in #1219:

sys/arch/x86/include/cacheinfo.h 1.14-1.19

Update Intel's cache and TLB descripotr table. This changes the number
of page coloring on some CPUs.
- Add Shared L2 TLB.
- Support prefetch size.
- Add some new TLB and cache entries from the document.
- Fix some entries:
- Fix 0x0d's DCACHE entry and 0xeb's L3CACHE entry.
- Desc 0x55 and 0xb1 are Instruction TLB but not fixed to 4K.
- Desc 0x5a and 0xc0 are Data TLB but not fixed to 4K.
- Desc 0x57 and 0x59 are 4K fixed DTLB.
- Fix string of desc 0xc2 and it's not fixed to 4K.
- Desc 0xca is 4K fixed L2 shared TLB.
 1.17.2.1  10-Aug-2014  tls Rebase.
 1.18.2.4  09-Oct-2018  snj Pull up following revision(s) (requested by msaitoh in ticket #1636):
sys/arch/x86/include/cacheinfo.h: 1.23-1.26
sys/arch/x86/include/cpu.h: 1.70
sys/arch/x86/include/specialreg.h: 1.91-1.93,1.98,1.100,1.102-1.124,1.126,1.130 via patch
sys/arch/x86/x86/cpu_topology.c: 1.10
sys/arch/x86/x86/identcpu.c: 1.56-1.57,1.70 via patch
usr.sbin/cpuctl/arch/i386.c: 1.71,1.75-1.79,1.81-1.85 via patch
Add some register definitions for x86:
- Add CLWB bit.
- Fix a few (unused) MSR values, and add some bit definitions of
MSR_EFER from Murray Armfield in PR#42861.
- CPUID_CFLUSH bit is not for CFLUSH insn but CLFLUSH insn, so modify
comments and snprintb() string.
- Define CPUID Fn00000001 %ebx bits and use them.
No functional change.
- Add Structured Extended Flags Enumeration Leaf's bit definitions:
AVX512_{IFMA,VBMI2,VNNI,BITALG,VPOPCNTDQ,4VNNIW,4FMAPS},GFNI&VAES.
- Add Turbo Boost Max Technology 3.0 bit.
- Add AMD SVM features definitions.
- Add Intel cpuid 7 %edx IBRS and STIBP bit definitions.
- Fix swapped comments for EFER LME and LMA
- Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
- Add MSR_IA32_ARCH_CAPABILITIES definition.
- Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR.
- Add Intel Deterministic Address Translation Parameter Leaf(0x18)
definitions.
- s/CLFUSH/CLFLUSH/
- Add AMD's Disable Indirect Branch Predictor bit definition.
- Add the MSR bits definitions for IBRS, STIBP and IBPB.
- Add Intel Fn0000_0006 %eax new bit 14-20 (HWP stuff).
- Intel Fn0000_0007 %ecx bit 22 is for both RDPID and IA32_TSC_AUX.
- Add AMD's CPUID Fn80000001 %edx MMX and FXSR bit definitions.
- Add RDCL_NO and IBRS_ALL.
- Add SSBD and RSBA bit definitions.
- Add AMD's SSB bit definitions for F15H, F16H and F17H.
- Add cpuid 7 edx L1D_FLUSH bit.
- Add IA32_ARCH_SKIP_L1DFL_VMENTRY bit.
- Add IA32_FLUSH_CMD MSR.
- Add yet another Shared L2 TLB (2M/4M pages).
- Add 3way and 6way of L2 cache or TLB on AMD CPU.
- AMD L3 cache association bitfield is not 8bit but 4bit like others
association bitfields.
- Sort entries. No functional change.
- Modify comment, fix typo in comment and add comment.
cpuctl(8):
- Add detection for Quark X1000, Xeon E5 v4, E7 v4,
Core i7-69xx Extreme Edition, Xeon Scalable (Skylake),
Xeon Phi [357]200 (Knights Landing), Atom (Goldmont),
Atom (Denverton), Future Core (Cannon Lake), Atom (Goldmont Plus),
Xeon Phi 7215, 7285 and 7295 (Knights Mill) and
7th or 8th gen Core (Kaby Lake, Coffee Lake).
- Print Structured Extended Feature leaf Fn0000_0007 %ebx on AMD,too.
- Print Fn0000_0007 %ecx on Intel.
- Print Intel cpuid 7 %edx.
- Parse the TLB info from `cpuid leaf 18H' on Intel processor.
- Use aprint_error_dev() for error output.
 1.18.2.3  08-Dec-2016  snj Pull up following revision(s) (requested by msaitoh in ticket #1285):
sys/arch/x86/include/cacheinfo.h: revision 1.22
sys/arch/x86/include/specialreg.h: revisions 1.87 and 1.90
usr.sbin/cpuctl/arch/i386.c: revisions 1.72-1.74
Changes for x86's cpuctl(8):
- Add Quark X1000, Xeon E[57] v4, Core i7-69xx Extreme, 7th gen Core,
Denverton, Xeon Phi [357]200, Future Xeon and Future Xeon Phi.
- Add SGX, UMIP, RDPID, SGXLC, AVX512DQ, AVX512BW and AVX512VL bit.
- Fix the bit location of CLFLUSHOPT.
- Add new TLB descriptor 0x64 and 0xc4.
 1.18.2.2  06-Mar-2016  martin branches: 1.18.2.2.2;
Pull up the following changes, requested by msaitoh in #1117:

sys/arch/x86/include/cacheinfo.h 1.20-1.21
sys/arch/x86/include/specialreg.h 1.83-1.86
usr.sbin/cpuctl/arch/i386.c 1.67-1.70

Changes for x86's cpuctl(8):
- Add some TLB information (index 0x6a-0x6d).
- Add Hardware-Controlled Performance States (HWP) bits, FPU Data
Pointer Updated Only bit and CLFLUSHOPT bit.
- Add some AMD's bit definitions from "BIOS and Kernel Developer(BKDG)
for AMD Family 15h Models 60h-6Fh Processors".
- Add Xeon E5-4600 v3,
- Add Xeon E3-1200 v4 and v5.
- Add 6th gen Core, Xeon E3-1500 v5 and Xeon D-1500.
- Change CPU family 0x1c from "Atom Family" to "45nm Atom Family"
 1.18.2.1  12-Dec-2014  martin Pull up following revision(s) (requested by msaitoh in ticket #310):
sys/arch/x86/include/specialreg.h: revision 1.79-1.80
usr.sbin/cpuctl/arch/i386.c: revision 1.59
sys/arch/x86/include/cacheinfo.h: revision 1.19

Update some cpuid related values:
- Add XSAVECC, XGETBV, XSAVES, SMAP and PQE
- Change XINUSE to XGETBV
- Add new cache descripter value (0xc3)
- Update signatures for the follwing CPUs:
- Core M-5xxx
- Core i7 Extreme
- Future Core (0x4e)
- Future Xeon (0x56)
 1.18.2.2.2.1  18-Jan-2017  skrll Sync with netbsd-5
 1.19.2.3  29-May-2016  skrll Sync with HEAD
 1.19.2.2  19-Mar-2016  skrll Sync with HEAD
 1.19.2.1  27-Dec-2015  skrll Sync with HEAD (as of 26th Dec)
 1.22.10.5  24-Dec-2021  martin Pull up the following (all via patch), requested by msaitoh in ticket #1721:

usr.sbin/cpuctl/arch/i386.c 1.118-1.119, 1.121-1.122
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.6
sys/arch/x86/x86/identcpu_subr.c 1.8-1.9
sys/arch/x86/x86/identcpu.c 1.123
sys/arch/x86/include/cacheinfo.h 1.30
sys/arch/x86/include/cpu.h 1.132

- Fix a bug that some TLB related lines were not printed.
- Fix a bug that STLB is printed as DTLB.
- If a TLB is variable sized, print the max size instead of error message.
- Cosmetic changes to improve readability.
 1.22.10.4  16-Aug-2019  martin Pull up following revision(s) (requested by msaitoh in ticket #1338):

usr.sbin/cpuctl/arch/i386.c: revision 1.104
sys/arch/x86/x86/identcpu.c: revision 1.93
sys/arch/x86/include/cacheinfo.h: revision 1.28
sys/arch/x86/include/specialreg.h: revision 1.150

- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
Intel Deterministic Cache Parameter Leaf(0x04), so make new
cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
common definition.
- KNF.

XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?
 1.22.10.3  16-Aug-2019  martin Pull up following revision(s) (requested by msaitoh in ticket #1338):

sys/arch/x86/include/cacheinfo.h: revision 1.27
sys/arch/x86/x86/identcpu.c: revision 1.74

Handle more Vortex CPU's from Andrius V.
While here refactor the code to make it smaller.

-

It seems that AMD zen2's CPUID 0x80000006 leaf's spec has changed.
The EDX register's acsociativity field has 9. In the latest available document,
it's a reserved value. I have no access to zen2's document, but many websites
say that the acsociativity is 16. Add it.

-

- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
Intel Deterministic Cache Parameter Leaf(0x04), so make new
cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
common definition.
- KNF.

XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?
 1.22.10.2  09-Apr-2018  martin Pull up following revision(s) (requested by msaitoh in ticket #715):

sys/arch/x86/include/cacheinfo.h: revision 1.24-1.26
usr.sbin/cpuctl/arch/i386.c: revision 1.81-1.84

- Parse the TLB info from `cpuid leaf 18H' on Intel processor. Currently,
this change doesn't decode perfectly. Tested with Gemini Lake. It has
two L2 Shared TLB. One is 4MB and another is 2MB/4MB but former isn't
printed yet:
cpu0: ITLB 1 4KB entries 48-way
cpu0: DTLB 1 4KB entries 32-way
cpu0: L2 STLB 8 4MB entries 4-way
Need some rework for struct x86_cache_info.
- Use aprint_error_dev() for error output.
Calculate way and number of entries correctly from CPUID leaf 18H.
Add yet another Shared L2 TLB (2M/4M pages).
XXX need redesign.

Add 3way and 6way of L2 cache or TLB on AMD CPU.
AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.

From the latest Intel SDM:
- Add Xeon Phi 7215, 7285 and 7295
- Add Coffee Lake
 1.22.10.1  16-Mar-2018  martin Pull up following revision(s) (requested by msaitoh in ticket #633):
sys/arch/x86/include/specialreg.h: revision 1.107
sys/arch/x86/include/specialreg.h: revision 1.108
sys/arch/x86/include/specialreg.h: revision 1.109
sys/arch/x86/include/cacheinfo.h: revision 1.23
sys/arch/x86/include/specialreg.h: revision 1.110
sys/arch/x86/include/specialreg.h: revision 1.111
sys/arch/x86/include/specialreg.h: revision 1.112
sys/arch/x86/include/specialreg.h: revision 1.113
sys/arch/x86/include/specialreg.h: revision 1.114
usr.sbin/cpuctl/arch/i386.c: revision 1.79
sys/arch/x86/x86/identcpu.c: revision 1.70
sys/arch/x86/include/specialreg.h: revision 1.106

Add comment.

Add Intel cpuid 7 %edx IBRS(IBPB Speculation Control) and
STIBP(STIBP Speculation Control) from OpenBSD.

Print Intel cpuid 7 %edx.

Example output of cpuctl -v identify 0:
+cpu0: 00000007: 00000000 000027ab 00000000 0c000000
(snip)
+cpu0: SEF edx 0xc000000<IBRS,STIBP>

fix swapped comments for EFER LME and LMA

- Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
- Add comment.
Add MSR_IA32_ARCH_CAPABILITIES definition.

Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR.

Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.

Sort entries. No functional change.

s/CLFUSH/CLFLUSH/
No functional change.
 1.23.2.1  15-Mar-2018  pgoyette Synch with HEAD
 1.26.2.1  13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.28.2.1  24-Dec-2021  martin Pull up the following (all via patch), requested by msaitoh in ticket #1396:

usr.sbin/cpuctl/arch/i386.c 1.118-1.119, 1.121-1.122
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.6
sys/arch/x86/x86/identcpu_subr.c 1.8-1.9
sys/arch/x86/x86/identcpu.c 1.123
sys/arch/x86/include/cacheinfo.h 1.30
sys/arch/x86/include/cpu.h 1.132

- Fix a bug that some TLB related lines were not printed.
- Fix a bug that STLB is printed as DTLB.
- If a TLB is variable sized, print the max size instead of error message.
- Cosmetic changes to improve readability.

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