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History log of /src/sys/arch/x86/pci/msipic.c
RevisionDateAuthorComments
 1.27  24-May-2022  bouyer - msipic_construct_msix_pic(): set mp_table_base to memaddr (without
table_offset), this is what Xen wants
while there use pci_conf_write16() in msi_set_msictl_enablebit() too,
for consistency (it seems that Xen accepts the 32bit write at this point,
but this may change).

- xen_map_msix_pirq(): don't forget to set map_irq.table_base in the
MSI-X case, otherwise Xen maps it as MSI
- call pic_hwunmask() after pirq_establish() in msi/msix case, to make sure
the msi-x vector is unmasked.

Now MSI-X works with Xen so stop disabling it in pci_attach_hook().
 1.26  23-May-2022  bouyer Work in progress on MSI/MSI-X on Xen (MSI works on my hardware, more work
needed for MSI-X):
- Xen silently rejects 32 bits writes to MSI configuration registers
(especially when setting PCI_MSI_CTL_MSI_ENABLE/PCI_MSIX_CTL_ENABLE),
it expects 16 bits writes. So introduce a pci_conf_write16(),
only available on XENPV (and working only for mode 1 without
PCI_OVERRIDE_CONF_WRITE) and use it to enable MSI or MSI-X on XENPV.
- for multi-MSI vectors, Xen allocates all of them in a single hypercall,
so it's not convenient to do it at intr_establish() time.
So do it at alloc() time and register the pirqs in the msipic structure.
xen_pic_to_gsi() now just returns the values cached in the msipic.
As a bonus, if the PHYSDEVOP_map_pirq hypercall fails we can fail
the alloc() and we don't need the xen_pci_msi*_probe() hacks.

options NO_PCI_MSI_MSIX still on by default for XEN3_DOM0.
 1.25  11-Dec-2020  knakahara Fix build failure when XNEPV is defined.
 1.24  11-Dec-2020  knakahara Not pic->pic_addroute but pic->pic_hwunmask should enable interrupts for MSI-X.

pic->pic_addroute should not enable interrupt, because callers expect
interrupts have been disabled until they call pic->pic_hwunmask.

By the way, the old implement writes zero to Vector Control for MSI-X Table
Entries, howerver it must be read and updated. Because, there are not only
Mask Bit but also ST lower and ST upper.
 1.23  04-May-2020  jdolecek branches: 1.23.2;
add support for using MSI for XenPV Dom0

use PHYSDEVOP_map_pirq to get the pirq/gsi for MSI/MSI-X, switch also INTx
to use it instead of PHYSDEVOP_alloc_irq_vector

MSI confirmed working with single-vector MSI for wm(4), ahcisata(4), bge(4)

XXX added some provision for MSI-X, but it doesn't actually work (no interrupts
delivered), needs some further investigation; disable MSI-X for XENPV
via flag in x86/pci/pci_machdep.c
 1.22  04-May-2020  jdolecek constify the pic templates
 1.21  25-Apr-2020  bouyer Merge the bouyer-xenpvh branch, bringing in Xen PV drivers support under HVM
guests in GENERIC.
Xen support can be disabled at runtime with
boot -c
disable hypervisor
 1.20  02-Dec-2019  msaitoh branches: 1.20.6;
Use PCI_MSIX_"TBL"BIR_MASK instead of PCI_MSIX_"PBA"BIR_MASK for MSI-X table.
This is not a real bug because both macros have the same value.
 1.19  13-Nov-2019  hikaru Disable MSI-X before writing the MSI-X table.

That fixes MSI-X interrupt lost on VMware ESXi 6.7 PCI passthrough devices.

ok knakahara@
 1.18  03-Oct-2019  tnn change bus_space_map to _x86_memio_map

Resolves bus space reservation conflict between MI and MD code.
Discussion:
http://mail-index.netbsd.org/port-amd64/2019/09/28/msg003014.html
 1.17  26-Jun-2019  knakahara branches: 1.17.2;
Fix updating "Multiple Message Enable" field for MSI multiple vectors. Pointed out by jmcneill@n.o, thanks.

I tested ahcisata for MSI single vector regression.
 1.16  18-Jun-2019  msaitoh Add note about the case of PCI_MSI_MDATA[64] is 16bit.
 1.15  17-Jun-2019  msaitoh KNF. No functional change.
 1.14  17-Jun-2019  msaitoh Fix comma with semicolon. No functional change.
 1.13  14-Jun-2019  msaitoh No functional change:
- Rename macros:
- ICR, LVT and MSIDATA can share the bit definitions. Remove redundant
definitions and use the common macros.
- Consistently use LAPIC_LVT_ for all local vector table's macro names.
- Use __BITS().
- Add definition for TSC-deadline (LAPIC_LVT_TMM_TSCDLT).
 1.12  01-Apr-2019  msaitoh Fix typo in comment (s/numer/number/).
 1.11  28-Jul-2017  maxv branches: 1.11.2; 1.11.6;
Don't include malloc.h.
 1.10  01-Jun-2017  chs branches: 1.10.2;
remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.
 1.9  23-May-2017  nonaka x86: Add preliminary x2APIC support.

x2APIC is used only when x2APIC is enabled in BIOS/UEFI.
LAPIC ID is not supported above 256.
 1.8  17-Nov-2015  msaitoh No functional change:
- Add comments.
- Remove obsolete comment.
- Move definitions to better location.
- Rename bit definition.
- KNF.
- Indent.
 1.7  13-Aug-2015  msaitoh Add workaround for PCI prefetchable bit in msipic_construct_msix_pic().
Some chips (e.g. Intel 82599) report SERR and MSI-X interrupt doesn't work.
This problem might not be the driver's bug but our PCI common part or VMs'
bug. See fxp(4), bge(4) and ixgbe(4). All of them has the same workaround
related to prefetchable bit. For the MSI-X table area, it should not have side
effect by prefetching. Until we find a real reason, we ignore the prefetchable
bit.
 1.6  13-Aug-2015  msaitoh - Don't take pci_attach_args as an argument in pci_msi[x]_count().
- Move prototypes of pci_msi[x]_count() from x86/x86/pci_machdep_common to
sys/dev/pci/pcivar.h.
- Move pci_msi[x]_count() from x86/pci/pci_msi_machdep.c to sys/dev/pci/pci.c
 1.5  11-Aug-2015  msaitoh Add missing opt_intrdebug.h.
 1.4  08-May-2015  knakahara branches: 1.4.2;
add a const qualifier to struct pci_attach_args *pa argument
 1.3  28-Apr-2015  martin Make this compilable in non-DIAGNOSTIC kernels.
 1.2  28-Apr-2015  knakahara fix debug message.
 1.1  27-Apr-2015  knakahara add x86 MD MSI/MSI-X support code.
 1.4.2.5  28-Aug-2017  skrll Sync with HEAD
 1.4.2.4  27-Dec-2015  skrll Sync with HEAD (as of 26th Dec)
 1.4.2.3  22-Sep-2015  skrll Sync with HEAD
 1.4.2.2  06-Jun-2015  skrll Sync with HEAD
 1.4.2.1  08-May-2015  skrll file msipic.c was added on branch nick-nhusb on 2015-06-06 14:40:04 +0000
 1.10.2.1  20-Nov-2019  martin Pull up following revision(s) (requested by hikaru in ticket #1453):

sys/arch/x86/pci/msipic.c: revision 1.19

Disable MSI-X before writing the MSI-X table.

That fixes MSI-X interrupt lost on VMware ESXi 6.7 PCI passthrough devices.

ok knakahara@
 1.11.6.2  13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.11.6.1  10-Jun-2019  christos Sync with HEAD
 1.11.2.2  03-Dec-2017  jdolecek update from HEAD
 1.11.2.1  28-Jul-2017  jdolecek file msipic.c was added on branch tls-maxphys on 2017-12-03 11:36:50 +0000
 1.17.2.2  16-Nov-2019  martin Pull up following revision(s) (requested by hikaru in ticket #429):

sys/arch/x86/pci/msipic.c: revision 1.19

Disable MSI-X before writing the MSI-X table.

That fixes MSI-X interrupt lost on VMware ESXi 6.7 PCI passthrough devices.

ok knakahara@
 1.17.2.1  15-Oct-2019  martin Pull up following revision(s) (requested by tnn in ticket #305):

sys/arch/x86/pci/msipic.c: revision 1.18

change bus_space_map to _x86_memio_map

Resolves bus space reservation conflict between MI and MD code.

Discussion:
http://mail-index.netbsd.org/port-amd64/2019/09/28/msg003014.html
 1.20.6.1  19-Apr-2020  bouyer Add per-PIC callbacks for interrupt_get_devname(), interrupt_get_assigned()
and interrupt_get_count(). Implement Xen-specific callbacks for
PIC_XEN and use the x86 one for others.
In event_set_handler(), call intr_allocate_io_intrsource() so that
events appears in interrupt list (intrctl list).
 1.23.2.1  14-Dec-2020  thorpej Sync w/ HEAD.

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