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History log of /src/sys/dev/i2c/gttwsivar.h
RevisionDateAuthorComments
 1.6  12-Jan-2020  thorpej Clean up gttwsi's register access stuff:
- Garbage-collect the obsolete GTTWSI_ALLWINNER option; it hasn't been
needed since FDT'ization of the Allwinner support code.
- Redefine thw "TWSI_*" register definitions to clearly call out:
-> The Marvell flavor of the offsets
-> The Allwinner flavor of the offsets
...and make the regular definitions indices into a register map.
- Pass the appropriate register map from the front-end to the core.
- Remove the customer register read/write callbacks -- they are no longer
needed now that each front-end passes an appropriate register map to
the core.
 1.5  25-Dec-2019  thorpej branches: 1.5.2;
Remove assertions that no longer make sense now that the bus acquire / release
logic is handled by the upper layer.
 1.4  07-May-2018  jmcneill branches: 1.4.2;
Don't sleep with IPL_VM lock held.
 1.3  29-Oct-2017  jmcneill branches: 1.3.2;
Allow drivers to provide their own read/write register functions. While
here, sprinkle KASSERTs to verify that the i2c lock is held where it
should be.
 1.2  23-Nov-2014  jmcneill branches: 1.2.12;
On Allwinner A31 you need to set the CONTROL_IFLG bit to clear it. Add
a "iflg-rwc" property to enable this behaviour.
 1.1  06-Sep-2013  matt branches: 1.1.2; 1.1.6; 1.1.8; 1.1.10; 1.1.12;
Make gttswi MI and usuable from non-Marvell SoCs.
(should rename to mvi2c but ...)
 1.1.12.3  03-Dec-2017  jdolecek update from HEAD
 1.1.12.2  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.1.12.1  06-Sep-2013  tls file gttwsivar.h was added on branch tls-maxphys on 2014-08-20 00:03:37 +0000
 1.1.10.1  25-Nov-2014  snj Pull up following revision(s) (requested by jmcneill in ticket #257):
sys/arch/arm/allwinner/awin_twi.c: revision 1.5
sys/arch/arm/allwinner/awin_reg.h: revision 1.53
sys/arch/evbarm/conf/HUMMINGBIRD_A31: revision 1.20
sys/dev/i2c/gttwsi_core.c: revision 1.2
sys/dev/i2c/gttwsivar.h: revision 1.2
On Allwinner A31 you need to set the CONTROL_IFLG bit to clear it. Add
a "iflg-rwc" property to enable this behaviour.
--
Don't assume that U-Boot has enabled the TWI clock. Also, for A31, set
the "iflg-rwc" device property for gttwsi.
--
The SoC RTC works on this board but does not seem to be hooked up to the
battery. Thankfully, there is a PCF8563 attached to TWI2 at address 51h,
so use that instead.
 1.1.8.2  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.1.8.1  06-Sep-2013  yamt file gttwsivar.h was added on branch yamt-pagecache on 2014-05-22 11:40:21 +0000
 1.1.6.2  18-May-2014  rmind sync with head
 1.1.6.1  06-Sep-2013  rmind file gttwsivar.h was added on branch rmind-smpnet on 2014-05-18 17:45:37 +0000
 1.1.2.2  24-Mar-2014  matt Merge mvi2c from HEAD
 1.1.2.1  06-Sep-2013  matt file gttwsivar.h was added on branch matt-nb5-mips64 on 2014-03-24 18:48:52 +0000
 1.2.12.1  15-Oct-2018  snj Pull up following revision(s) (requested by bouyer in ticket #1061):
sys/dev/i2c/gttwsi_core.c: revision 1.4-1.8 via patch
sys/dev/i2c/gttwsivar.h: revision 1.4 via patch
Use IPL_VM for bus lock so we can do i2c xfers from interrupt context
Don't sleep with IPL_VM lock held.
When initiating a transfer, if a device isn't present, we won't
get an ACK after sending the address. Check for this alternate
state and suppress the error message when it occurs.
Fixes PR kern/53356.
Bail early if gttwsi_send_start() fails in gttwsi_initiate_xfer() to
avoid unexpected state error message later (on Allwinner H5).
Expand code covered by sc->sc_mtx, to make sure an interrupt would not be
handled before the cv_timedwait_sig() call, or while polling.
Seems to fix "sunxitwi0: send STOP failed" messages frequently seen related
to axp20x0 sensors.
 1.3.2.1  21-May-2018  pgoyette Sync with HEAD
 1.4.2.1  08-Apr-2020  martin Merge changes from current as of 20200406
 1.5.2.1  17-Jan-2020  ad Sync with head.

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