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History log of /src/sys/dev/ic/ns16550reg.h
RevisionDateAuthorComments
 1.14  06-Oct-2022  riastradh com(4): Add include guards.
 1.13  11-Jan-2019  thorpej Simplify regmap initialization, and fix an regmap issue that
affected TI OMAP (LCR register would get clobbered due to
using the wrong offset for the MDR1 register) reported by Lwazi Dube
(who also found the root cause).
 1.12  29-Oct-2017  jmcneill branches: 1.12.2; 1.12.4;
Make all of the COM_xxx type options runtime selectable. Kernel configs
with the existing options (COM_16650, COM_16750, COM_AWIN, COM_HAYESP, and
COM_PXA2X0) will select the correct type in com_attach_subr. New code
should specify the com type by passing COM_TYPE_xxx to comcnattach and/or
setting sc_type.
 1.11  27-May-2016  bouyer The UART in the allwiner SoCs is not full-compatible with the 16550, and
it's not a 16750 either. Like the 16750 it has the IIR_BUSY interrupt,
which is triggered when writing to LCR while the chip
can't accept it. But unlike the 16750, it has a specific register,
HALT, to allow writing to the LCR and divisor registers, and then
commit the changes.
Tested on an A20 SoC, changing the baud rate while keeping the
tty device open and incoming data.
 1.10  03-Oct-2013  kiyohara branches: 1.10.4; 1.10.6;
Revirt 'Move the Marvell extension to com_mv.c' at Sun Sep 1 04:51:24 UTC 2013.
build test only.
 1.9  01-Sep-2013  kiyohara Move the Marvell extension to com_mv.c.
 1.8  20-Apr-2013  rkujawa Add support for 16750 style UARTs. Activated by defining COM_16750.

Obtained from Marvell, Semihalf.
 1.7  11-Dec-2005  christos branches: 1.7.110; 1.7.120;
merge ktrace-lwp.
 1.6  07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.5  16-May-2000  thorpej branches: 1.5.28;
Whitespace glitch.
 1.4  27-Oct-1994  cgd branches: 1.4.32;
new RCS ID format.
 1.3  30-Jun-1993  andrew Added com_scratch entry.
 1.2  22-May-1993  cgd add rcsids to everything and clean up headers
 1.1  21-Mar-1993  cgd branches: 1.1.1;
Initial revision
 1.1.1.1  21-Mar-1993  cgd initial import of 386bsd-0.1 sources
 1.4.32.1  20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.5.28.3  21-Sep-2004  skrll Fix the sync with head I botched.
 1.5.28.2  18-Sep-2004  skrll Sync with HEAD.
 1.5.28.1  03-Aug-2004  skrll Sync with HEAD
 1.7.120.2  03-Dec-2017  jdolecek update from HEAD
 1.7.120.1  23-Jun-2013  tls resync from head
 1.7.110.1  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.10.6.1  29-May-2016  skrll Sync with HEAD
 1.10.4.1  22-Jun-2016  snj Pull up following revision(s) (requested by bouyer in ticket #1178):
sys/arch/arm/allwinner/files.awin: revision 1.36
sys/conf/files: revision 1.1159
sys/dev/ic/com.c: revision 1.339
sys/dev/ic/comreg.h: revision 1.25
sys/dev/ic/comvar.h: revision 1.82
sys/dev/ic/ns16550reg.h: revision 1.11
The UART in the allwiner SoCs is not full-compatible with the 16550, and
it's not a 16750 either. Like the 16750 it has the IIR_BUSY interrupt,
which is triggered when writing to LCR while the chip
can't accept it. But unlike the 16750, it has a specific register,
HALT, to allow writing to the LCR and divisor registers, and then
commit the changes.
Tested on an A20 SoC, changing the baud rate while keeping the
tty device open and incoming data.
 1.12.4.1  10-Jun-2019  christos Sync with HEAD
 1.12.2.1  18-Jan-2019  pgoyette Synch with HEAD

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