| History log of /src/sys/dev/pci/agp_i810var.h |
| Revision | | Date | Author | Comments |
| 1.7 |
| 27-Aug-2018 |
riastradh | Restore gtt page table control register on resume.
Additional subroutine agp_i810_reset is used by i915drmkms to make
sure it happens early enough, since i915drmkms resumes before agp.
XXX pullup-7
XXX pullup-8
|
| 1.6 |
| 06-Mar-2015 |
riastradh | branches: 1.6.10; 1.6.16; 1.6.18;
Pass cache-related flags through to the GTT on pre-SNB devices.
I had assumed for ages this would increase the amount of caching and
thereby increase the chance of stale caches leading to rendering
glitches. But apparently I was wrong, and failing to pass these
through was causing all sorts of problems!
|
| 1.5 |
| 10-Jun-2014 |
riastradh | branches: 1.5.2; 1.5.4; 1.5.6;
Another round of weed-whacking for agp_i810.
- Make struct agp_i810_softc::gatt specific to i810 chipsets; use other
members of struct agp_i810_softc for non-i810 chipsets.
- agp_i810_init detects and sets isc->gtt_size.
- Map GTT based on the GTT size detected by agp_i810_init.
- Sprinkle some comments particularly about questionable calculations.
|
| 1.4 |
| 27-May-2014 |
riastradh | Rework agp_i810 attachment code a little.
- Fix up error branches in agp_i810_attach.
- Use a separate bus space handle for the GTT, whether it is in a
separate BAR or a subregion of the MMIO device registers, so that
(a) agp_i810_write_gtt_entry and agp_i810_post_gtt_entry are easier to
follow, and
(b) we can map the GTT prefetchable eventually.
|
| 1.3 |
| 23-May-2014 |
riastradh | Implement Intel AGP chipset flush.
While here, fix the use of the I915 PCI MSAC register: it lies on the
bridge device (bus 0 dev 0 func 0), not the graphics device (bus 0
dev 2 func 0). I'm not sure we ever need to consult this register,
really -- the PCI BARs should be sized. But I'll leave a rototill of
this mess for another day.
|
| 1.2 |
| 18-Mar-2014 |
riastradh | branches: 1.2.2; 1.2.4; 1.2.6;
Merge riastradh-drm2 to HEAD.
|
| 1.1 |
| 05-Mar-2014 |
riastradh | branches: 1.1.2;
file agp_i810var.h was initially added on branch riastradh-drm2.
|
| 1.1.2.2 |
| 05-Mar-2014 |
riastradh | Expose agp_i810_write_gtt_entry for drm2.
Also add an agp_i810_post_gtt_entry to do a posting read for that GTT
entry.
|
| 1.1.2.1 |
| 05-Mar-2014 |
riastradh | Expose the agp_i810 softc.
This is an Intel-specific kludge so that i915drmkms can get at the
GTT, graphics translation table, for pre-Sandy Bridge Intel graphics
devices.
|
| 1.2.6.2 |
| 22-May-2014 |
yamt | sync with head.
for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.
this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
|
| 1.2.6.1 |
| 18-Mar-2014 |
yamt | file agp_i810var.h was added on branch yamt-pagecache on 2014-05-22 11:40:24 +0000
|
| 1.2.4.2 |
| 18-May-2014 |
rmind | sync with head
|
| 1.2.4.1 |
| 18-Mar-2014 |
rmind | file agp_i810var.h was added on branch rmind-smpnet on 2014-05-18 17:45:39 +0000
|
| 1.2.2.1 |
| 10-Aug-2014 |
tls | Rebase.
|
| 1.5.6.1 |
| 06-Apr-2015 |
skrll | Sync with HEAD
|
| 1.5.4.3 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.5.4.2 |
| 20-Aug-2014 |
tls | Rebase to HEAD as of a few days ago.
|
| 1.5.4.1 |
| 10-Jun-2014 |
tls | file agp_i810var.h was added on branch tls-maxphys on 2014-08-20 00:03:41 +0000
|
| 1.5.2.1 |
| 17-Mar-2015 |
riz | Pull up following revision(s) (requested by snj in ticket #590):
sys/external/bsd/drm2/i915drm/intel_gtt.c: revision 1.5
sys/external/bsd/drm2/drm/drm_drv.c: revision 1.15
sys/external/bsd/drm2/dist/drm/i915/i915_gem.c: revision 1.28
sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_nv50.c: revision 1.3
sys/dev/pci/agp_i810.c: revision 1.115
sys/dev/pci/agp_i810.c: revision 1.116
sys/external/bsd/drm2/include/drm/intel-gtt.h: revision 1.5
sys/dev/pci/agp_i810.c: revision 1.117
sys/external/bsd/drm2/drm/drm_gem_vm.c: revision 1.6
sys/dev/pci/agp_i810var.h: revision 1.6
Issue a write barrier after updating the GTT.
Linux never used to do this...until a month:
<a rel="nofollow" href="https://bugs.freedesktop.org/show_bug.cgi?id=88191">https://bugs.freedesktop.org/show_bug.cgi?id=88191</a>
commit 983d308cb8f602d1920a8c40196eb2ab6cc07bd2
Author: Chris Wilson <chris%chris-wilson.co.uk@localhost>
Date: Mon Jan 26 10:47:10 2015 +0000
agp/intel: Serialise after GTT updates
Include <sys/atomic.h> for membar_producer.
(Why didn't this fail in my build?)
Pass cache-related flags through to the GTT on pre-SNB devices.
I had assumed for ages this would increase the amount of caching and
thereby increase the chance of stale caches leading to rendering
glitches. But apparently I was wrong, and failing to pass these
through was causing all sorts of problems!
Dedup the NetBSD portion of the code (ok Riastradh), no functional change.
Don't return events that are too large and leave them in the list.
Apply access control to gem mmap.
fix gcc is stupid.
|
| 1.6.18.1 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.6.16.1 |
| 06-Sep-2018 |
pgoyette | Sync with HEAD
Resolve a couple of conflicts (result of the uimin/uimax changes)
|
| 1.6.10.1 |
| 31-Aug-2018 |
martin | Pull up following revision(s) (requested by riastradh in ticket #998):
sys/dev/pci/agp_i810var.h: revision 1.7
sys/external/bsd/drm2/i915drm/intel_gtt.c: revision 1.7
sys/dev/pci/agp_i810.c: revision 1.123
Restore gtt page table control register on resume.
Additional subroutine agp_i810_reset is used by i915drmkms to make
sure it happens early enough, since i915drmkms resumes before agp.
XXX pullup-7
XXX pullup-8
|
