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History log of /src/sys/dev/pci/pcireg.h
RevisionDateAuthorComments
 1.172  31-Dec-2024  skrll Use C99 types
 1.171  14-Jun-2024  msaitoh branches: 1.171.2;
PCI_CLASS_MASK: Use unsigned to avoid undefined behavior. Found by kUBSan.
 1.170  19-Apr-2024  andvar s/Resorce/Resource/ in comment and log message.
 1.169  02-Feb-2024  andvar s/Staus/Status/ in comments.
 1.168  17-Oct-2022  mrg branches: 1.168.2;
add pcie capability and read request size linux compat, some pci root support

implement support for:
- pcie_capability_read_dword()
- pcie_capability_read_word()
- pcie_capability_write_dword()
- pcie_capability_write_word()
- pcie_get_readrq()
- pcie_set_readrq()

implement the "struct pci_dev" bus->self member by creating a minimal fake
"struct pci_dev" for the pci bus itself. this is kind of gross. it checks
that the current device's parent is a netbsd "pci" device, and that it has
a (grand) parent "ppb" device, and then fills in the fake device based upon
the pci and ppb devices.

add some PCIE_LCSR2_TGT_LSPEED encodings, and map them to linux names.
map several other PCIE_LCSR and PCIE_LCAP names.

uncomment several pcie code segments in radeon and amdgpu. (not sure that
we can test the amdgpu_si.c change, as we use the radeon version and the
amdgpu version hangs on the one machine i have.)

tested on amdgpu (RX550) and radeon (7750 & 3650).


ok @riastradh
 1.167  01-Oct-2022  rin No need to mangle argument of macro.
 1.166  20-Sep-2022  mrg fill out more of the linux pci API compat

- implement pcie_get_speed_cap(), pcie_bandwidth_available(), and
pci_is_root_bus().
- expand "enum pci_bus_speed" to add PCIe 5.x and 6.x speeds.
- add "enum pcie_link_width".
- add defines for PCIE_LCSR_LINKSPEED (PCIe generation) and PCIE_LCSR_NLW
(negotiated lane width) to pcireg.h
- enable amdgpu_device_get_pcie_info() code now it works.

ok riastradh@
 1.165  31-Jan-2022  msaitoh Decode SCSI programming interface. Whitespace fix.
 1.164  31-Jan-2022  msaitoh Add three new extended capabilities:

- Physical Layer 32.0 GT/s
- Alternate Protocol
- System Firmware Intermediary
 1.163  01-Jan-2022  msaitoh Print Physical Layer 16.0 GT/s and Lane Margining at the Receiver extended cap.

- Decode Physical Layer 16.0 GT/s extended capability.
- Decode Lane Margining at the Receiver extended capability.
- Rename pcie_link_compliance_preset_deemphasis to
pcie_link_preset_preshoot_deemphasis because the table is referenced from
multiple places.
- Print "reserved" instead of "unknown" when printing equalization preset.
One of them is known to be the default value.
- Rename PCI_EXTCAP_PYSLAY_16GT to PCI_EXTCAP_PL16G.
 1.162  28-Dec-2021  msaitoh Decode link control2's Compliance Preset/De-emphasis more. Fix typo.
 1.161  10-Oct-2021  msaitoh Use PCI-SIG official acronyms:

- RP stands for Root Port.
- RC stands for Root Complex.
- RCIEP stands for Root Complex Integrated End Point.
 1.160  10-Oct-2021  msaitoh Add Some PCI config information:

- Lane Margining at the Receiver
- NVME admin interface
- UFSHCI
- InfiniBand
- Host fabric
- HDA 1.0 with vendor ext
- USB4 HCI
- MIPI I3C
- Cellular controller/modem (+ Ethernet)
 1.159  10-Oct-2021  msaitoh Whitespace fix. No functional change.
 1.158  09-Sep-2021  mrg fix part of the previous: Link Capability Max Speed is a value not
a bitmask. pointed out by msaitoh@.
 1.157  09-Sep-2021  mrg add some bits in the pci Link Capabilities Register, and also the similar
set in the Link Capabilities 2 Register.
 1.156  17-Aug-2021  andvar fix multiplei repetitive typos in comments, messages and documentation. mainly because copy paste code big amount of files are affected.
 1.155  24-Jun-2021  thorpej From the "Should have been done years ago" department, add some macros
describing the format of PCI Type 0 and Type 1 Configuration Cycle
addresses.
 1.154  15-May-2021  jakllsch Change PCI_VENDOR_MASK and PCI_PRODUCT_MASK to unsigned values, to prevent
sign extension of product ID when shifted up into place in PCI_ID_CODE()

Should fix PR 56176.
 1.153  28-Dec-2020  skrll branches: 1.153.4; 1.153.6;
Add second space indentation for bit field values for Enhanced Allocation
capabilities. From thorpej.
 1.152  28-Dec-2020  skrll Trailing whitespace
 1.151  18-Feb-2020  msaitoh branches: 1.151.6;
Add comment.
 1.150  25-Jan-2020  msaitoh Add PCIe 4.0 stuff a little:

- 10-bit Tag Requester/Completer.
- Add Data link Feature extended capability.
- Add Physical Layer 16.0 GT/s extended capability. Not decode yet.
 1.149  22-Jan-2020  msaitoh Remove unused shift and mask definitions.
 1.148  11-Dec-2019  msaitoh branches: 1.148.2;
s/enalbe/enable/
 1.147  01-Mar-2019  msaitoh branches: 1.147.4;
- Almost all ppbreg.h's definitions are also in pcireg.h. Remove duplicated
definitions from ppbreg.h and move some definitions from ppbreg.h to
pcireg.h.
- Change fast back-to-back "capable" to "enable" in pci_subr.c.
- Print Primary Discard Timer, Secondary Discard Timer, Discard Timer Status
and Discard Timer SERR# Enable bit in pci_subr.c.
- PCI_BRIDGE_PREFETCHBASE32_REG and PCI_BRIDGE_PREFETCHLIMIT32_REG are
"upper" 32bit registers, rename to *UP32_REG to avoid confusion.
- Use macro.
 1.146  30-Nov-2018  msaitoh Add new PCIE_HAS_LINKREGS(pcie_devtype) and use it. No functional change.
 1.145  30-Nov-2018  msaitoh Add new macro PCIE_HAS_ROOTREGS(pcie_devtype) and use it. No functional
change.
 1.144  28-Nov-2018  msaitoh The register offset of the mask and pending register is depend on the 64bit
address capable bit, so fix the definition of PCI MSI vector mask and pending
register. This problem was not a real bug because PCI_MSI{MASK,PENDING} were
not used from anywhere.
 1.143  05-Nov-2018  msaitoh Decode PCI Enhanced Allocation.
 1.142  03-Oct-2018  msaitoh - Don't print TPH requester's ST Table Size if the ST table location field
is not PCI_TPH_REQ_STTBLLOC_TPHREQ because the size field is only applicaple
for PCI_TPH_REQ_STTBLLOC_TPHREQ case.
- Add comment.
 1.141  27-Sep-2018  msaitoh Root Complex Event Collector Bus Number Association ECN.
- If capability version is 2 (or greater), decode RCEC Associated Bus Numbers
register.
 1.140  12-Sep-2018  msaitoh Add ATS Relaxed Ordering supported bit described in Address Translation
Relaxed Ordering ECN.
 1.139  02-Jul-2018  msaitoh VGA 16 bit decode bit is not bit 3 but bit 4.
 1.138  09-May-2018  msaitoh branches: 1.138.2;
Fix typo. s/TPL/TLP/
 1.137  01-Feb-2018  msaitoh branches: 1.137.2;
- Add PCie Link Activation ECN.
- Use macro.
- KNF.
 1.136  18-Dec-2017  msaitoh Add VGA 16bit decode bit into the PCI bridge control register. This bit is
defined in PCI-to-PCI Bridge Architecture Specification Revision 1.2. This
bit has meaning if the VGA enable bit or the VGA Palette Snoop Enable bit is
set.

NOTE: sys/arch/x86/pci/pci_ranges.c::mmio_range_extend_by_vga_enable() and/or
some other functions should be modified.
 1.135  19-Oct-2017  msaitoh Fix a bug that the TPH ST table is decoded even if it's not in the TPH
Requester extended capability structure.
 1.134  10-Oct-2017  msaitoh Decode IOMMU capability of PCI secure device capability. From "AMD I/O
Virtualization Technology(IOMMU) Specification (#48882) Revision 3.00".
 1.133  05-Oct-2017  msaitoh - Add PCI_MAPREG_ROM_ADDR_MASK macro and PCI_MAPREG_ROM_ADDR() macro.
- print PCI_MAPREG_ROM_ENABLE bit.
- Decode Expansion ROM Validation ECN.
- Add Native PCIe Enclosure Management ECN's extended capability type.
Not decoded yet.
 1.132  13-Jul-2017  msaitoh - Official shortname of LN Requester is LNR, so change PCI_EXTCAP_LN_REQ
to PCI_EXTCAP_LNR
- Use macro.
 1.131  15-Jun-2017  msaitoh Fix a bug that LTR's latency in L1 PM Substates capability and Latency
Tolerance Reporting capability isn't printed correctly.
 1.130  29-May-2017  msaitoh branches: 1.130.2;
Print MSI Message data in 32bits when the Extended Message Data Capable bit
is set.
 1.129  24-May-2017  msaitoh Decode TPH Requester Control register.
 1.128  21-Apr-2017  msaitoh Add Flattening Portal Bridge capability ID and Hierarchy ID extended
capability ID.
 1.127  20-Apr-2017  msaitoh Add Downstream Port Containment (DPC) ECN and Enhanced DPC(eDPC) ECN.
 1.126  17-Apr-2017  msaitoh Use macro. No functional change.
 1.125  28-Mar-2017  msaitoh Sort & indent. No functional change.
 1.124  28-Mar-2017  msaitoh Indent. No functional change.
 1.123  28-Mar-2017  msaitoh Lowercase for consistency. No functional change.
 1.122  14-Mar-2017  msaitoh Add two new PCI classes:
- processing accelerators
- non-essential instrumentation
 1.121  27-Feb-2017  msaitoh Decode AGP capability.
 1.120  15-Feb-2017  msaitoh - Print Data Select and Data Scale in pci_conf_print_pcipm_cap().
- The Message Data register of MSI cap is not 32bit but 16bit.
- When the PCIE_LCAP_MAX_SPEED bitfiled is 0, it means it supports 2.5GT/s only.
- Print link de-emphasis value by "-X dB".
- Print Completion Timeout Ranges Supported filed with alphabets.
- Print TPH Completer Supported fileld's meaning.
- Print PCIE_DCAP2_MAX_EETLP correctly. 0 means 4 End-End TLP Prefixes.
- If the Supported Link Speed Vector is 0, the Link Capability 2 register is not
implemented. Don't decode LCAP2 when the vector is 0.
- The ACS's Egress Control Vector is 32bit, so print with 0x%08x.
- Print SR-IOV's device ID.
- Use __SHIFTOUT() to avoid using magic number.
- Prefix "0x" for hexadecimal value.
 1.119  28-Dec-2016  msaitoh branches: 1.119.2;
The Power Controller Control bit (PCIE_SLCSR_PCC) in the Slot Control & Status
Register is 0 on power on. Print "Power <on|off>" instead of "<on|off>".
 1.118  27-Dec-2016  msaitoh Fix PASID Control Register.
 1.117  31-Oct-2016  msaitoh Decode Resizable BAR.
 1.116  20-Oct-2016  msaitoh - pci_conf_print_pwrbdgt_base_power(): From 0xf3 to 0xff of the Base power are
reserved above 300W (PCI 3.0 Errata).
- Emergency Power Reduction mechanism with PWRBRK signal ECN.
- Extended Message Data for MSI ECN.
- Fix typo in comment.
 1.115  19-Oct-2016  msaitoh Add VF Resizable BARs ECN.
 1.114  17-Aug-2016  msaitoh Add Dynamic Power Allocation (DPA) ECN support.
 1.113  11-May-2016  msaitoh branches: 1.113.2;
Add Precision Time Management (PTM) ECN.
 1.112  18-Nov-2015  msaitoh - Add the Auto Slot Power Limit Disable bit in Slot Control register and
the Completion Timeout Prefix/Header Log Capable bit in the AER capability
and control register (ECN: Downstream Port Containment (DPC)).
- Add the Poisoned TLP Egress Block bit (ECN: Enhanced DPC).
- Update Link Capabilities 2 register and Link Control 3 register (ECN:
Separate Refclk Independent SSC Architecture (SRIS))
- ECN: Readiness Notifications (RN)
- Add the Retimer Presence Detect Supported bit in the Link Capabilities 2
register and the Retimer Presence Detected bit in the Link Status 2 register
(ECN: Extension Devices)
 1.111  17-Nov-2015  msaitoh - ARI's function group is not bit 32-24 but 22-20.
- Add the Structure Length field in AF capability register.
- Add Enhanced Allocation extended capability ID (ECN: Enhanced Allocation (EA)
for Memory and I/O Resources).
- Add LN System CLS (ECN: Lightweight Notification (LN) Protocol).
- Add ST Upper and Lower bit definitions (ECN: TLP Processiong Hints).
- Add the Global Invalidate bit in the ATS capability register and the PRG
Response PASID Required bit in the Page Request status register (ECN: PASID
Translation)
- Decode ASPM support bit more (ECN: ASPM Optionally)
- Use __BITS()
 1.110  17-Nov-2015  msaitoh No functional change:
- Add comments.
- Remove obsolete comment.
- Move definitions to better location.
- Rename bit definition.
- KNF.
- Indent.
 1.109  16-Nov-2015  msaitoh Define PCIE_XCAP_{VER,TYPE}(x) and use them.
 1.108  12-Nov-2015  msaitoh - Restore pci_subr.c rev. 1.135's change in pci_conf_print_caplist().
As wrote in the comment, HyperTransport capability appears multiple times.
pci_conf_cap() reruns only the first entry, so it can't be used here.
- Try to decode HyperTransport capability. Currently, the capability type
of each HyperTransport capability is printed and only the MSI Mapping
capability is decoded.
- Style change.
 1.107  12-Nov-2015  msaitoh PCI_HT_CAP() is right shifted value, so PCI_HT_CAP_* should not use
__SHIFTIN(). This change fixes a bug that HyperTransport system misunderstand
whether MSI/MSI-X can be used or not.
 1.106  30-Oct-2015  msaitoh - Move PCI_INTRSTR_LEN from pcireg.h to pcivar.h.
- In PCI-X cap, print 2nd bus's PCI-X mode, error protection type, Max clock
frequency and Max clock period.
- In SATA cap, print register location correctly.
- In Virtual Channel cap, print reference clock with "ns".
- In Root Complex Link Declaration, print Link Entry number.
 1.105  21-Oct-2015  msaitoh Decode SATA Capability and Multicast Extendeded Capability.
 1.104  02-Oct-2015  msaitoh PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific
 1.103  27-Jul-2015  msaitoh Add NVMe.
 1.102  27-Apr-2015  knakahara add x86 MD MSI/MSI-X support code.
 1.101  23-Feb-2015  knakahara - add macros to calculate MSI MME and MMC.
- add MSI-X table offset macros.
- fix MSI-X table entry name.
 1.100  24-Nov-2014  msaitoh branches: 1.100.2;
Add PCIe CRS Software Visibility bit.
 1.99  23-Oct-2014  msaitoh Add some HyperTransport related defines. It's required for the MSI.
 1.98  23-Oct-2014  msaitoh Add comment.
 1.97  06-Oct-2014  msaitoh - Add some PCI subclass and interfaces.
- The interface of PCI_SUBCLASS_BRIDGE_RACEWAY is not decoded yet.
- Fix typo in a message.
- Add comment.
- Modify comment.
 1.96  24-Sep-2014  msaitoh Rename PCIE_XCAP_VER_* macros to avoid confusion.
 1.95  09-Jun-2014  msaitoh branches: 1.95.2;
Add IOMMU and the Root Complex Event Collector.
 1.94  30-May-2014  msaitoh - Add PCI-X capability stuff.
- remove extra ':' in pci_conf_print_pcie_cap()
- Add comments.
 1.93  27-May-2014  msaitoh - Add some register definition for MSI and MSI-X
- print MSI-X capability
 1.92  27-May-2014  msaitoh - Fix incorrect calculation in PCI_MSIX_CTL_TBLSIZE().
- The PCI_MSIX_CTL_TBLSIZE bit field is in N-1, so add +1.
 1.91  24-May-2014  msaitoh Print some PCI Capabilities:
- Vendor specific (ID:0x09)
- Debugport (ID:0x0a)
- Subsystem (ID:0x0d)
- PCI Advanced Features (ID:0x13)
 1.90  24-May-2014  msaitoh - Decode the programming interface field in the Class Code register and print
it.
- Print the cache line size in bytes.
- Print the Link Status 2 register itself.
- Some bits were not printed if the bit is 0. Always print them using with
onoff() macro.
- Print more bits.
- KNF.
- Use macro.
- Add comments.
 1.89  23-May-2014  msaitoh - Add some register definitions (subclass, power management, etc.)
- Print some information (subclass, power management)
- Use macro.
 1.88  23-May-2014  msaitoh PME# clock is not bit 2 but bit 3. Use the macro!
 1.87  23-May-2014  msaitoh No functional change:
- sort in PCI capability ID order.
- add comments.
 1.86  09-May-2014  msaitoh Print the CRS Software Visibility Enable bit and the Crosslink Supported bit.
 1.85  29-Mar-2014  christos branches: 1.85.2;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.
 1.84  21-Apr-2013  msaitoh branches: 1.84.4;
- Add some PCIe 2.0 or higher capability register definitions.
- Rename some registers.
- Add comments.
- Indent.
 1.83  21-Apr-2013  msaitoh Delete "PCI_" from PCIX and PICE capability registers.
 1.82  17-Apr-2013  msaitoh - Add slot related registers
- Add root port related registers
- Fix the definition of PCI_PCIE_SLCAP_PSN
- Cleanup
 1.81  17-Apr-2013  msaitoh Add PCI_CAP_SUBVENDOR (= 0x0d).
 1.80  16-Apr-2013  msaitoh Decode some PCIe capability register bits.
 1.79  16-Apr-2013  msaitoh Fix a bug that IRQ(MSI) bits in PCIe capability register is incorrectly
decoded. The bit field is not 0x4e000000 but 0x3e000000.
 1.78  15-Apr-2013  msaitoh Add some PCIE capability register bit definitions from FreeBSD.
 1.77  12-Apr-2013  msaitoh Add comments for some PCI Express Capability registers.
 1.76  03-Mar-2013  msaitoh Add PCI Express's relax ordering bit.
 1.75  20-Oct-2012  matt Add PCI_SUBCLASS_MASS_STORAGE_NVM
 1.74  02-Sep-2012  matt branches: 1.74.2;
Finish devices the bits in PCIE capability LCSR field.
 1.73  17-Aug-2011  dyoung branches: 1.73.2; 1.73.8; 1.73.10;
Redefine PCI_MSI_* and PCI_PCIE_* constants in terms of bits(3).

Use named constants and more conventional variable names in
pci_msi_establish() and pci_msi_disestablish(). Fix a couple of bugs:
pci_msi_establish() returned a pointer to the struct intrhand instead of
to the struct msi_hdl as it was intended to, and pci_msi_disestablish()
did not free(9) the msi_hdl.
 1.72  06-Jun-2011  msaitoh Add two new capabilities(PCI_CAP_SATA and PCI_CAP_PCIAF).
 1.71  05-Apr-2011  dyoung branches: 1.71.2;
Use PCI_MAPREG_START instead of the anonymous constant 0x10.
 1.70  26-Jan-2011  dyoung Define masks for subsystem vendor and subsystem ID fields, plus a couple
of macros for extracting them.
 1.69  10-Jan-2011  jmcneill branches: 1.69.2; 1.69.4;
ppb_fix_pcix changes:
- rename to ppb_fix_pcie
- support version PCI-E 2.0
- print version and device/port type information
- use constants from pcireg.h instead of magic numbers

changes:

ppb2 at pci0 dev 21 function 0: vendor 0x15ad product 0x07a0 (rev. 0x01)
ppb2: unsupported PCI Express version

to:

ppb2 at pci0 dev 21 function 0: vendor 0x15ad product 0x07a0 (rev. 0x01)
ppb2: PCI Express 2.0 <Root Port of PCI-E Root Complex>
 1.68  11-Dec-2010  matt Add some PCI Express definitions, MSI, MSIX, etc.
 1.67  20-Mar-2010  dyoung Add PCI_BAR(n) for the nth Base Address Register.
 1.66  26-Feb-2010  dyoung branches: 1.66.2;
Move the definitions for PCI_BAR0, PCI_BAR1, PCI_BAR2, PCI_BAR3,
PCI_BAR4, and PCI_BAR5 to pcireg.h for re-use.
 1.65  23-Feb-2010  dyoung Remove unused functions pci_disable_retry() and cardbus_disable_retry().
 1.64  12-Feb-2010  msaitoh - Add some PCIe config registers.
- The register at 0x1c is not Control Status register. It contains Control
bits only. Rename it.
 1.63  01-Feb-2010  msaitoh branches: 1.63.2;
Fix the bug that unaligned access occurs on amd64. It also fixes the bug
that error bits aren't cleard because these bits are W2C (in other word, W1C).

Reported by Michael van Elst.
 1.62  28-Jan-2010  msaitoh Add some register definitions.
 1.61  11-Sep-2009  christos Add support for the 5100 and newer firmware. Tested also with the 4900.
Thanks to everyone for helping and testing.
 1.60  17-Aug-2009  jakllsch A few new PCI register #defines:
- size of config and extended config space
- EFI ROM code type number
- extended capability list register bits
 1.59  16-Jan-2009  cegger rename PCI_PMCSR_PME to PCI_PMCSR_PME_STS.
Per request from jmcneill
 1.58  16-Jan-2009  cegger add Power Management flag. From FreeBSD.
 1.57  25-Dec-2007  perry branches: 1.57.6; 1.57.10; 1.57.18; 1.57.20; 1.57.26;
Convert many of the uses of __attribute__ to equivalent
__packed, __unused and __dead macros from cdefs.h
 1.56  28-Nov-2007  briggs branches: 1.56.2; 1.56.6;
Correct a typo. To create the command/status word, shift the components
left, not right.
 1.55  12-Nov-2007  joerg Merge pci_disable_retry function from jmcneill-pm as it is found in
various drivers.
 1.54  13-May-2007  kent branches: 1.54.6; 1.54.8; 1.54.12; 1.54.14;
Add PCI_SUBCLASS_MULTIMEDIA_HDAUDIO to pcireg.h
and azalia(4) uses it
 1.53  26-Jan-2007  dyoung branches: 1.53.2; 1.53.6; 1.53.8;
#Define PCI_PMCSR_PME_EN.
 1.52  08-Nov-2006  drochner branches: 1.52.2; 1.52.4;
avoid magic number
 1.51  17-Jun-2006  christos branches: 1.51.4; 1.51.6;
re-factor the pci powestate api. reviewed by gimpy
 1.50  31-May-2006  drochner branches: 1.50.2;
-add 2 subclasses new in rev. 3.0 of the spec, and fix a pasto in another
-get power management rev printing right
 1.49  01-Mar-2006  gdamore branches: 1.49.2; 1.49.8;
Add pci_find_rom() API as discussed on tech-kern.
 1.48  27-Feb-2006  gdamore Add PCI_MAPREG_TYPE_ROM and allow it to be used with pci_mapreg_map().
Fix to configure (but do not enable) BARs for expansion ROMs.
Reviewed by briggs@
 1.47  11-Dec-2005  christos branches: 1.47.2; 1.47.4; 1.47.6;
merge ktrace-lwp.
 1.46  02-Aug-2004  joda branches: 1.46.12;
bridge memory and lower prefetch memory ranges are only 12 bits wide
 1.45  04-Feb-2004  soren Use the right bits for the AGP version.
 1.44  02-Dec-2003  briggs Configure PCI-Cardbus bridges, too.
Patch from KIYOHARA Takashi on current-users.
 1.43  21-Oct-2003  thorpej - Since we access PCI config space as 32-bit words, redefine the PCI-X
command register bits offset and shifted appropriatly (PCI-X command
makes up the upper 16 bits of the register that holds the PCI-X cap ID
and next-cap-pointer).
- Define shift counts for max memory read byte count in the command
and status registers.
 1.42  05-May-2003  fvdl branches: 1.42.2;
Define PCI32_DMA_BOUNCE_THRESHOLD
 1.41  20-Apr-2003  fvdl Add register definitions for the PCI-X capability.
 1.40  25-Mar-2003  thorpej Add PCI VPD access routines. From psi.cz!freza, PR kern/20889.
 1.39  21-Sep-2002  drochner -correct the "MSI" capability
-add some new subclasses and capability IDs
 1.38  18-Jun-2002  tshiozak add support for the per-device power management capability.

int pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, int newstate)
set power state of the device to newstate.
int pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag)
get current power state of the device.

In the future, these functions will be used for ACPI support.
 1.37  22-Mar-2002  drochner branches: 1.37.2;
iadd subclass codes from the 2.3 spec
 1.36  30-Aug-2001  briggs Rename PCI_MAPREG_TYPE_ROM to PCI_MAPREG_ROM_ENABLE to keep up with pciconf.?
 1.35  06-Jul-2001  thorpej branches: 1.35.2;
Add a bunch of Vital Product Data definitions.
 1.34  12-Feb-2001  briggs branches: 1.34.2;
Deal with a lack of the proper type of memory. For example, if a bridge
only supports 16-bit I/O addresses, do not configure it with addresses
having the upper 16-bits non-zero.
 1.33  09-Feb-2001  briggs Add an option (defopt) PCI_NETBSD_CONFIGURE that provides PCI bus
configuration (assignment of bus numbers, BARs, timer values,
interrupt lines, etc.).
The interface must be called from m.d. code prior to probing the bus.
It is meant to be called once for each primary (bus == 0) PCI bus in
the system. It will configure any busses behind PCI-PCI bridges.
Section 9 man page for pci_configure_bus() will come soon.
In the meantime, sample usage is in arch/sandpoint/sandpoint/mainbus.c.
[ Reviewed by thorpej ]
 1.32  07-Oct-2000  cgd Update for current PCI device class/subclass and capability codes.
(also, tweak the I2O subclass string to be "standard" -- the removal
of version info didn't extend that far.)
 1.31  02-Oct-2000  ad I2O subclasses currently have nothing to do with the protocol version.
 1.30  21-Aug-2000  castor Add a bunch of macros of the form PCI_<regname>_CODE similar to
existing PCI_ID_CODE to create the PCI appropriate register from
parameters.

Avoid use of 'class' in macro -- it's a C++ reserved keyword.
 1.29  18-Jul-2000  soda add "#define PCI_INTERRUPT_PIN_MAX 0x04"
 1.28  09-Jun-2000  soda branches: 1.28.2;
long long constant needs "LL" suffix.
 1.27  12-May-2000  jhawk branches: 1.27.2;
Define some PCI power management CSR constants.
 1.26  10-May-2000  thorpej Add support for mapping 64-bit PCI memory space. If the region
is mapped in a way that is inaccessible by a 32-bit bus_addr_t, then
print a message to that effect and return failure.

Original patches by Bill Studenmund, with a few small changes by me.
 1.25  08-May-2000  kleink Add a register offset for the Capability List Pointer in header type 2.

XXX Ideally the PCI-Cardbus Bridge header should be restructured to just
XXX present standard register definitions, making it ~safe to be included.
 1.24  28-Apr-2000  uch add PCI_MAPREG_PPB_END (PCI-PCI bridge) PCI_MAPREG_PCB_END (PCI-Cardbus bridge)
 1.23  25-Jan-2000  drochner use BUS_SPACE_MAP_PREFETCHABLE instead BUS_SPACE_MAP_CACHEABLE where the
PCI BAR bit is referred to
 1.22  16-Nov-1999  enami Make this file compile again; terminate the continuation line with backslash.
 1.21  15-Nov-1999  thorpej Add a macro to generate a class code given class, subclass, and interface.

From UCHIYAMA Yasushi's PCI BIOS patches.
 1.20  27-Sep-1999  cgd branches: 1.20.2; 1.20.8;
add classes/subclasses new in PCI 2.2. Needs a bit of cleanup, but then,
so does everything involving configuration space headers and if i don't
get this out of my source tree i'll go insane.
 1.19  21-Dec-1998  drochner add two of the newer register definitions
 1.18  07-Nov-1998  drochner add support for "extended capabilities" (new in PCI spec 2.2)
 1.17  15-Aug-1998  mycroft Make copyright notices with my name consistent.
 1.16  01-Jun-1998  cgd according to the PCI 2.1 spec, the low _two_ bits of I/O BARs have
defined meaning/value other than specifying the address of the region.
(lowest bit is 1, meaning I/O space. second-lowest bit is reserved.)
 1.15  18-May-1998  cgd add a PCI_HDRTYPE_TYPE() macro, to get the 'type' portion of the
headertype register (i.e., not including the 'multifunction' bit).
 1.14  14-Apr-1998  thorpej Add UDF and 66MHz capable bit definitions for the PCI status register.
From Zubin D. Dittia <zubin@clouseau.arl.wustl.edu>, PR #4249.
 1.13  11-Apr-1997  cgd clean up some constants ([A-F]->[a-f] in hex constants
 1.12  19-Mar-1997  cgd fix multi-function device support, add new known classes/subclasses,
and clean up class/subclass printing. From brb@brig.com via PR 3359.
 1.11  10-Aug-1996  mycroft Change PCI_MAPREG_{MEM,IO}_SIZE() to use the standard `x & -x' trick to select
the lowest bit set. This isn't any more or less valid according to the PCI
spec, but it deals with lame devices that don't implement all of the top
bits.
 1.10  06-Aug-1996  cgd revert PCI_MAPREG_IO_ADDR_MASK and PCI_MAPREG_IO_SIZE_MASK to their old
values, i.e. 0xfffffffe and 0xffffffff respectively. The changed
definitions were incorrect, according to the PCI Local Bus Specification
(Revision 2.0). Further rationale and a workaround for the broken
devices that instigated the change provided in a message to
current-users@netbsd.org, dated Mon, 05 Aug 1996 22:06:58 -0400,
message ID 16773.839297218@ux2.sp.cs.cmu.edu>.
 1.9  26-Jul-1996  mycroft Add PCI_MAPREG_{IO,MEM}_SIZE(), and use them.
 1.8  26-Jul-1996  mycroft Changes PCI_MAPREG_IO_ADDR_MASK to 0xfffe.
 1.7  27-Mar-1996  cgd branches: 1.7.4;
modify these to provide a new, better-specified PCI interface
(soon to be documented on mailing lists; eventually in section 9 manual
pages), most importantly:
(1) support interrupt pin swizzling on non-i386 systems with
PCI-PCI bridges (per PPB spec; done, but meaningless, on i386).
(2) provide pci_{io,mem}_find(), to determine what I/O or memory
space is described by a given PCI configuration space
mapping register.
(3) provide pci_intr_map(), pci_intr_string(), and
pci_intr_{,dis}establish() to manipulate and print info about
PCI interrupts.
(4) make pci functions take as an argument a machine-dependent
cookie, to allow more flexibility in implementation.
 1.6  27-Mar-1996  cgd add definitions for the BIST/Header Type/Latency Timer/Cache Line Size
configuration space register, and use it to determine whether or not
a given PCI device uses multiple functions.
 1.5  04-Mar-1996  cgd reorganize mapping register definitions
 1.4  27-Jul-1995  mycroft Add stuff for I/O mapping.
 1.3  18-Jun-1995  cgd macros to split out various parts of PCI registers, adjust constants
to match. (now, comparisons are comparisons, code doing them doesn't
have to mask.) define types for the various parts of the registers'
contents, where practical.
 1.2  27-Oct-1994  cgd new RCS ID format.
 1.1  09-Aug-1994  mycroft Add PCI autoconfiguration support.
 1.7.4.1  10-Dec-1996  mycroft From trunk:
Deal with devices that do not allow allow of the I/O address bits to be set.
 1.20.8.1  27-Dec-1999  wrstuden Pull up to last week's -current.
 1.20.2.3  12-Mar-2001  bouyer Sync with HEAD.
 1.20.2.2  11-Feb-2001  bouyer Sync with HEAD.
 1.20.2.1  20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.27.2.1  22-Jun-2000  minoura Sync w/ netbsd-1-5-base.
 1.28.2.2  25-Oct-2001  he Pull up revisions 1.31-1.32 (requested by ad):
Add Mylex DACC960, CAC-EISA, and I2O block/SCSI drivers.
 1.28.2.1  10-Aug-2000  soda Pull up to netbsd-1-5 branch
Approved by: thorpej

- define PCI_INTERRUPT_PIN_MAX and use it instead of magic number.
- define I386_PCI_INTERRUPT_LINE_NO_CONNECTION and use it instead of
magic number.

Revisions pulled up:
> cvs rdiff -r1.28 -r1.29 syssrc/sys/dev/pci/pcireg.h
> cvs rdiff -r1.14 -r1.15 syssrc/sys/arch/i386/include/pci_machdep.h
> cvs rdiff -r1.38 -r1.39 syssrc/sys/arch/i386/pci/pci_machdep.c
> cvs rdiff -r1.1 -r1.2 syssrc/sys/arch/i386/pci/opti82c558.c \
> syssrc/sys/arch/i386/pci/sis85c503.c \
> syssrc/sys/arch/i386/pci/via82c586.c
 1.34.2.5  18-Oct-2002  nathanw Catch up to -current.
 1.34.2.4  20-Jun-2002  nathanw Catch up to -current.
 1.34.2.3  01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.34.2.2  21-Sep-2001  nathanw Catch up to -current.
 1.34.2.1  24-Aug-2001  nathanw Catch up with -current.
 1.35.2.4  10-Oct-2002  jdolecek sync kqueue with -current; this includes merge of gehenna-devsw branch,
merge of i386 MP branch, and part of autoconf rototil work
 1.35.2.3  06-Sep-2002  jdolecek sync kqueue branch with HEAD
 1.35.2.2  23-Jun-2002  jdolecek catch up with -current on kqueue branch
 1.35.2.1  13-Sep-2001  thorpej Update the kqueue branch to HEAD.
 1.37.2.1  15-Jul-2002  gehenna catch up with -current.
 1.42.2.3  21-Sep-2004  skrll Fix the sync with head I botched.
 1.42.2.2  18-Sep-2004  skrll Sync with HEAD.
 1.42.2.1  03-Aug-2004  skrll Sync with HEAD
 1.46.12.7  21-Jan-2008  yamt sync with head
 1.46.12.6  07-Dec-2007  yamt sync with head
 1.46.12.5  15-Nov-2007  yamt sync with head.
 1.46.12.4  03-Sep-2007  yamt sync with head.
 1.46.12.3  26-Feb-2007  yamt sync with head.
 1.46.12.2  30-Dec-2006  yamt sync with head.
 1.46.12.1  21-Jun-2006  yamt sync with head.
 1.47.6.2  01-Jun-2006  kardel Sync with head.
 1.47.6.1  22-Apr-2006  simonb Sync with head.
 1.47.4.1  09-Sep-2006  rpaulo sync with head
 1.47.2.1  01-Mar-2006  yamt sync with head.
 1.49.8.1  19-Jun-2006  chap Sync with head.
 1.49.2.1  26-Jun-2006  yamt sync with head.
 1.50.2.1  13-Jul-2006  gdamore Merge from HEAD.
 1.51.6.1  10-Dec-2006  yamt sync with head.
 1.51.4.2  01-Feb-2007  ad Sync with head.
 1.51.4.1  18-Nov-2006  ad Sync with head.
 1.52.4.1  03-Sep-2007  wrstuden Sync w/ NetBSD-4-RC_1
 1.52.2.1  30-Jul-2007  liamjfoy Pull up following revision(s) (requested by dyoung in ticket #739):
sys/dev/pci/pccbb.c: revision 1.140
sys/dev/pci/pccbb.c: revision 1.141
sys/dev/pci/pccbb.c: revision 1.142
sys/dev/pci/pccbb.c: revision 1.143
sys/dev/pci/pccbb.c: revision 1.144
sys/dev/pci/pccbbvar.h: revision 1.28
sys/dev/pci/pcireg.h: revision 1.53
sys/dev/pci/pccbb.c: revision 1.139
Name magic numbers PCI_PMCSR_PME_EN and PCI_PMCSR.

Fix grammar in comment. From Patrick Welche.

Use the right subroutine name for the debug message.

Convert the rather long and backslash-ridden DELAY_MS macro to a
much shorter static subroutine, delay_ms().

Cosmetic: KNF indentation, curly braces, and argument declarations.

sc_pwrcycle is shared between the interrupt handler and Cardbus
event thread, so make it volatile.

Fix a bug in Cardbus power activation.

Most Cardbus bridges supported by pccbb(4) fire a power-cycle
interrupt when the power state of a cardslot changes from 'off' to
'on'. TI bridges fire a power-cycle interrupt on both on->off and
off->on changes.

When pccbb_power() powered-down a cardslot, it did not wait around
for the power-cycle interrupt. When pccbb_power() powered-up a
cardslot, it did wait for the interrupt. If a pccbb_power(UP)
followed a pccbb_power(DOWN) very closely, pccbb_power() used to
interpret the power-cycle interrupt for the up->down transition as
"power-up complete," read the power-state bit and, finding that
power had NOT been activated, complain, "cbb0: power on failed?"
Then pccbb_power() exited before power-activation was complete,
falsely indicating that the power-activation *was* complete. After
that, a driver attach/enable routine would blithely configure a
card that was not fully powered-up. An operator who ran a command
such as 'ifconfig rtw0 down up' or 'ifconfig ath0 down up' would
read 'cbb0: power on failed?' in the system log, and their NIC
would misbehave.

This excerpt from a comment in the source should suffice to explain
how I fixed the bug,

/*
* Wait as long as 200ms for a power-cycle interrupt. If
* interrupts are enabled, but the socket has already
* changed to the desired status, keep waiting for the
* interrupt. "Consuming" the interrupt in this way keeps
* the interrupt from prematurely waking some subsequent
* pccbb_power call.

And this explains why this patch will work for Ricoh bridges that
do not fire an interrupt on the on->off transition:

* XXX Not every bridge interrupts on the ->OFF transition.
* XXX That's ok, we will time-out after 200ms.
*
* XXX The power cycle event will never happen when attaching
* XXX a 16-bit card. That's ok, we will time-out after
* XXX 200ms.
*/

M. Warner Losh and Charles M. Hannum provided valuable input on
this patch.
 1.53.8.1  11-Jul-2007  mjf Sync with head.
 1.53.6.1  27-May-2007  ad Sync with head.
 1.53.2.1  17-May-2007  yamt sync with head.
 1.54.14.3  18-Feb-2008  mjf Sync with HEAD.
 1.54.14.2  08-Dec-2007  mjf Sync with HEAD.
 1.54.14.1  19-Nov-2007  mjf Sync with HEAD.
 1.54.12.1  13-Nov-2007  bouyer Sync with HEAD
 1.54.8.1  09-Jan-2008  matt sync with HEAD
 1.54.6.3  03-Dec-2007  joerg Sync with HEAD.
 1.54.6.2  14-Nov-2007  joerg Sync with HEAD.
 1.54.6.1  01-Oct-2007  joerg Extend device API by device_power_private and device_power_set_private.
The latter is a temporary mean until the pnp_register API itself is
overhault. This functions allow a generic power handler to store its
state independent of the driver.

Use this and revamp the PCI power handling. Pretty much all PCI devices
had power handlers that did the same thing, generalize this in
pci_generic_power_register/deregister and the handler. This interface
offers callbacks for the drivers to save and restore state on
transistions. After a long discussion with jmcneill@ it was considered
to be powerful enough until evidence is shown that devices can handle
D1/D2 with less code and higher speed than without the full
save/restore. The generic code is carefully written to handle device
without PCI-PM support and ensure that the correct registers are written
to when D3 loses all state.

Reimplement the generic PCI network device handling on
top of PCI generic power handling.

Introduce pci_disable_retry as used and implemented locally at least by
ath(4) and iwi(4). Use it in this drivers to restore behaviour from
before the introduction of generic PCI network handling.

Convert all PCI drivers that were using pnp_register to the new
framework. The only exception is vga(4) as it is commonly used as
console device. Add a note therein that this should be fixed later.
 1.56.6.1  02-Jan-2008  bouyer Sync with HEAD
 1.56.2.1  26-Dec-2007  ad Sync with head.
 1.57.26.2  15-Feb-2014  matt sync pcireg.h with HEAD.
update if_wm.c and ppb.c accordingly.
 1.57.26.1  24-Dec-2011  matt Pull down latest from -HEAD.
 1.57.20.3  09-Nov-2015  sborrill Pull up the following revisions(s) (requested by msaitoh in ticket #1983):
sys/dev/pci/pcidevs: revisions 1.1079, 1.1134, 1.1148-1.1149, 1.1151
sys/dev/pci/pcidevs.h: regen
sys/dev/pci/pcidevs_data.h: regen
sys/dev/pci/if_bge.c: revisions 1.183-1.185, 1.187, 1.189-1.193, 1.195-1.199, 1.202-1.226, 1.228-1.237, 1.240-1.264, 1.267-1.276, 1.278-1.280, 1.283-1.287 via patch
sys/dev/pci/if_bgereg.h: revisions 1.57-1.74, 1.76-1.90 via patch
sys/dev/pci/if_bgevar.h: revisions 1.6, 1.10-1.13, 1.15-1.17 via patch
sys/dev/pci/if_bnx.c: revisions 1.32, 1.34-1.43, 1.48-1.49, 1.52
sys/dev/pci/if_bnxreg.h: revisions 1.8, 1.11-1.14
sys/dev/pci/if_bnxvar.h: revisions 1.1-1.3
sys/dev/mii/brgphy.c: revisions 1.53-1.63, 1.65-69, 1.72-1.74 via patch
sys/dev/mii/brgphyreg.h: revisions 1.5-1.8
sys/dev/mii/miivar.h: revisions 1.61
sys/dev/pci/pcireg.h: patch

Sync bge(4) up to if_bge.c rev. 1.287. Sync brgphy(4) up to 1.74.
Fix some bugs on bnx(4).

Common:
- Add device IDs for Broadcom BCM57710, BCM57711(E), BCM57712(E) and
BCM57766 (pcidevs only).
- Fix BCM5709 PHY detection.
- Fix detection of BGEPHYF_FIBER_{MII|TBI}
- Add BCM5708S support in brgphy(4).
- Don't use the WIRESPEED function for fiber devices.
bge(4):
- Add some Fujitsu's device support from Michael Moll.
- Add BCM57762 support (PR#46961 from Ryo Onodera).
- Add Altima AC1003, APPLE BCM5701, Broadcom BCM5785F. BCM5785G,
BCM5787F, BCM5719, BCM5720, BCM57766, BCM57782 and BCM57786.
- Fix DMA setting for read/write on conventional PCI bus devices.
This bug was added in rev. 1.166.
- Fix printing "discarding oversize frame (len=-4)" message and
crash by NULL pointer dereferencing.
- The BCM5785 is a PCIe chip but does not report PCIe capabilities.
Check for this chip explicitely and enable PCIe. Fixes
'firmware handshake timeout'.
- Allow disabling interrupt mitigation.
- Workaround for BCM5906 silicon bug. When auto-negotiation results
in half-duplex operation, excess collision on the ethernet link may
cause internal chip delays that may result in subsequent valid
frames being dropped due to insufficient receive buffer resources.
(FreeBSD: r214219, r214251, r214292).
- Allow write DMA to request larger DMA burst size to get better
performance on BCM5785. (FreeBSD r213333: OpenBSD 1.294)
- Enable TX MAC state machine lockup fix for both BCM5755 or higher
and BCM5906. Publicly available data sheet just says it may happen
due to corrupted TxMbuf. (FreeBSD r214216)
- Follow Broadcom datasheet:
Delay 100 microseconds after enabling transmit MAC.
Delay 10 microseconds after enabling receive MAC. (FreeBSD
r241220)
- Insert the completion barrier between register write and the
consecutive delay(). It will fix some device timeout problems we have
seen before.
- Add DELAY(40) after turning on write DMA state machine.
- Add some workarounds for 5717 A0 and 5776[56] to be stable.
- Check BGE_RXBDFLAG_IPV6 flag for 5717_PLUS case. Note that
{tcp,udp}6csum flag is currently not added in the capability.
- Add delay after clearing BGE_MACMODE_TBI_SEND_CFGS for the link
checking.
- Do not touch the jumbo replenish threshold register on chips that do
not have jumbo support.
- Wait for the bootcode to complete initialization for 5717 and newer
devices.
- 5718 and 57785 document say we should wait 100us in init.
- Fix a bug that chips which have BCM5906 ASIC touch GPIO wrongly.
- Fix the setting of Tx Random Backoff Register.
- Check the hardware config words and print them.
- Set BGE_MISC_CTL's byte/word swap options before using
bge_readmem_ind(). Fixes PR#47716.
- For BGE_IS_575X_PLUS() devices, don't set
BGE_RXLPSTATCONTROL_DACK_FIX bits because these bits are reserved.
- Document says 5717 and newer chips have no
BGE_PCISTATE_INTR_NOT_ACTIVE bit, so don't use the bit on those
chips. Same as OpenBSD.
- Fix a bug that the PHY address bits in MI_MODE register is wrongly
cleard. Set the PHY address correctly.
- Use BGE_SETBIT() instead of CSR_WRITE_4() for the BGE_MISC_LOCAL_CTL
register to not to modify some GPIO bits.
- Set DMA watermark depend on the PCI max payload size.
- Set BGE_JUMBO_CAPABLE correctly.
- Fix a link detect bug on non-autopoll systems.
- Change the TX ring size for 5717 series and 57764 series.
- Set maximum read byte count to 2048 for PCI-X BCM5703/5704 devices.
- For PCI-X BCM5704, set maximum outstanding split transactions to 0.
- Add 40bit DMA bug workaround(BGEF_40BIT_BUG) from FreeBSD.
This workaround is for 5714/5715 controllers and is not actually a
MAC controller bug but an issue with the embedded PCIe to PCI-X
bridge in the device. This change uses bus_dmatag_subregion(),
so this workaround won't work on some archs which doesn't support
bus_dmatag_subregion().
- Add 2500SX support (not tested).
- Don't use the PHY Auto Poll Mode on many chips. This fixes a bug
that MII Fiber NIC drop packet about 50%. Tested on HP Moonshot.
- Add workaround for PR#48451. Some BCM5717-5720 based systems getNMI
on boot. This problem doesn't occur when we don't use prefetchable
memory in the APE area. Tested with HP MicroServer Gen8.
- In the BCM5703, the DMA read watermark should be set to less than
or equal to the maximum memory read byte count of the PCI-X command
register.
- Fix a bug that BGE_PHY_TEST_CTRL_REG isn't set correctly on some
PCIe devices.
- Use another firmware command in bge_asf_driver_up(). Same as Linux.
This change fixes a bug that watchdog timeout occurs every 25-30
minutes on HP ML110 G6 reported enami@ in PR#49657.
- Fix mbuf leak on failure.
- Remove PCI_PRODUCT_BROADCOM_BCM5724 and
PCI_PRODUCT_BROADCOM_BCM5750M. These devices have not released to
public.
- Add some workaround code for BGE_ASICREV_BCM5784 from Linux.
- Change some printf() to aprint_*().
- Fix typo in comments.
- Cleanup.
brgphy(4):
- Fix bit definition of BRGPHY_MRBE_MSG_PG5_NP_T2 from FreeBSD.
- Add BCM5481, BCM5709S, BCM5756, BCM5717C, BCM5720C, BCM5785,
BCM57765(PR#46961), BCM57780
- In brgphyattach(), set sc_isbge, sc_isbnx and sc_phyflags before
PHY_RESET() because brgphy_reset() refers those flags.
- Call brgpy specific autonego function in MII_TICK. Before this
commit, only MII_MEDIACHG calls brgphy_mii_phy_auto() and MII_TICK
calls MI mii_phy_auto(). That was not intended.
- Remove extra delay in brgphy_mii_phy_auto. Same as {Free,Open}BSD.
bnx(4):
- Add missing ifmedia_delete_instance() in bnx_detach().
- Fix a bug that BNX_NO_WOL_FLAG isn't correctly set on some chips.
Reported by From Henning Petersen in PR#44151.
- Fix SERDES initialization.
- Get out of the interrupt handler early if !IFF_RUNNING.
 1.57.20.2  11-May-2013  riz Applied patch (requested by msaitoh in ticket #1844):

sys/dev/pci/pcireg.h 1.69
sys/dev/pci/ppb.c 1.44-1.45

Support PCI Express 2.0.
Print version and device/port type information
[msaitoh, ticket #1844]
 1.57.20.1  19-Nov-2010  riz branches: 1.57.20.1.2;
Pull up revisions (requested by msaitoh in ticket #1358):
sys/dev/pci/if_wm.c 1.196-1.199,1.202,1.205
sys/dev/pci/if_wmvar.h 1.9
sys/dev/pci/if_wmreg.h 1.36-1.39
sys/dev/pci/pcireg.h 1.61-1.64
sys/dev/pci/pcidevs 1.1023
sys/dev/pci/pcidevs.h regen
sys/dev/pci/pcidevs_data.h regen
mii/igphy.c 1.21
mii/igphyvar.h 1.1
mii/inbmphyreg.h 1.2

- Count Receive error, CRC error, Alignment error, Symbol error, Sequence
error, Carrier extension error and Receive length error into ierror.
Fixes PR#30349 reported by UMEZAWA Takeshi.
- Add support for 82575, 82576 and 82580(ER).
- Apply the patch for 82575 from Wolfgang Stukenbrock (PR#42422). We use
only one RX ring and with the legacy mode.
- Add support for 82576.
- Partial support for 82580.
- Partial support for the serdes systems.
- Add two workarounds for ICH8 with igp3.
- Workaround for 82566 Kumeran PCS lock loss.
- WOL from S5 stops working.
- (pcireg.h) Add PCIe config register definitions.
- Note that the changes to count Missed packet (rx fifo overflow) and Receive
no buffers (rx ring full) into iqdrops in rev. 1.196 of if_wm.c is not
pulled up.
 1.57.20.1.2.1  07-Jan-2011  matt Add/define some MSI support
 1.57.18.1  19-Jan-2009  skrll Sync with HEAD.
 1.57.10.5  11-Aug-2010  yamt sync with head.
 1.57.10.4  11-Mar-2010  yamt sync with head
 1.57.10.3  16-Sep-2009  yamt sync with head
 1.57.10.2  19-Aug-2009  yamt sync with head.
 1.57.10.1  04-May-2009  yamt sync with head.
 1.57.6.1  17-Jan-2009  mjf Sync with HEAD.
 1.63.2.1  30-Apr-2010  uebayasi Sync with HEAD.
 1.66.2.4  12-Jun-2011  rmind sync with head
 1.66.2.3  21-Apr-2011  rmind sync with head
 1.66.2.2  05-Mar-2011  rmind sync with head
 1.66.2.1  30-May-2010  rmind sync with head
 1.69.4.1  08-Feb-2011  bouyer Sync with HEAD
 1.69.2.1  06-Jun-2011  jruoho Sync with HEAD.
 1.71.2.1  23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.73.10.1  28-Nov-2012  matt Add LCSR definitions and NVM storage subclass.
 1.73.8.1  05-Aug-2013  martin Pullup

sys/dev/pci/pcireg.h 1.74-1.82 and 1.84 via patch
sys/dev/pci/pci_subr.c 1.92-1.102, 1.104-1.105 via patch

Add some PCI(e) register and bit definitions in pcireg.h.
Fix the definition of PCI_PCIE_SLCAP_PSN.
Fix a bug that IRQ(MSI) bits in PCIe capability register is incorrectly
decoded.
Print more registers in "pcictl dump".
Fix bug in comment.

Requested by msaitoh in ticket #928
 1.73.2.2  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.73.2.1  30-Oct-2012  yamt sync with head
 1.74.2.4  03-Dec-2017  jdolecek update from HEAD
 1.74.2.3  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.74.2.2  23-Jun-2013  tls resync from head
 1.74.2.1  20-Nov-2012  tls Resync to 2012-11-19 00:00:00 UTC
 1.84.4.1  18-May-2014  rmind sync with head
 1.85.2.1  10-Aug-2014  tls Rebase.
 1.95.2.4  11-Aug-2018  martin Pull up the following, requested by msaitoh in ticket #1628:

share/man/man4/wm.4 1.40 via patch
sys/dev/mii/ihphyreg.h 1.2
sys/dev/mii/inbmphyreg.h 1.10
sys/dev/pci/if_wm.c 1.504, 1.506, 1.510-1.535, 1.539-1.540, 1.546, 1.548, 1.551-1.552, 1.558, 1.565-1.573, 1.575, 1.579, 1.582, 1.584 via patch
sys/dev/pci/if_wmreg.h 1.99-1.103, 1.106-1.107 via patch
sys/dev/pci/if_wmvar.h 1.34-1.39 via patch
sys/dev/pci/pcidevs 1.1327 via patch
sys/dev/pci/pcidevs.h regen
sys/dev/pci/pcidevs_data.h regen
sys/dev/pci/pcireg.h patch

Sync wm(4) up to 2018/08/08 except MSI/MSI-X and NET_MPSAFE:
- remove extra "+"
- Fix a bug that non-GMII devices don't send a routing message when
the link status is changed.
- Set WMREG_KABGTXD not in wm_init_locked() but in wm_reset(). Same as
other OSes.
- If a interrupt is a spurious interrupt, don't print debug message.
- Don't print the Image Unique ID if an NVM is iNVM (i210 and I211).
- Print sc_flags with snprintb().
- Fix a bug that a RAL was written at incorrect address when the index
number is more than 16 on 82544 and newer.
- The layout of RAL on PCH* are different from others. Fix it.
- Flush every MTA write. Same as Linux.
- Move the location of calling wm_set_filter. Same as some other OSes.
- Add CSR_WRITE_FLUSH() after writing WMREG_CTRL in
wm_gmii_mediachange().
- Add missing "else" in wm_nvm_release().
- Make new wm_phy_post_reset() and use this function at all location
after resetting phy.
- Move the location of calling wm_get_hw_control. Same as Linux.
- Add I219 specific wokaround for legacy interrupt. From OpenBSD.
- Move the location of calling wm_lplu_d0_disable().
- Fix latency calculation in wm_platform_pm_pch_lpt().
- Set OBFF water mark and enable OBFF on PCH_LPT and newer.
- Disable D0 LPLU on 8257[12356], 82580, I350 and I21[01], too. Before
this commit, above devices and non-PCIe devices accessed wrong
register.
- Use device_printf() instead of aprint_error_dev() for PHY read/write
functions because those are used not only in device attach.
- Fix a bug that wm_gmii_i82544_{read,write}reg() didn't take care of
page select. PHY access from igphy() automatically did it, but
accessing from wm(4) for wrokaround didn't work correctly. This
change affects 8254[17], 8257[12] ICH8, ICH9 and ICH10.
- Call wm_kmrn_lock_loss_workaround_ich8lan() before any PHY access in
wm_linkintr_gmii().
- Register access in wm_kmrn_lock_loss_workaround_ich8lan() now works
correctly. Enable this function.
- Configure the LCD with the extended configuration region in NVM if
it's required.
- If TX is not required to flush, RX is also not required to flush
in wm_flush_desc_rings(). Same as other OSes.
- Remove wrong semaphore access in wm_nvm_{read,write}_{ich8,spt} to
prevent hangup. A semaphore is get/put in wm_nvm_{read,write}.
- Move some initialization stuff in wm_attach() before wm_reset(). Some
flags and callback function are required to set correctly before
wm_reset() because wm_reset() and some helper functions refer them.
- Add wm_write_smbus_addr() to set SMBus address by software.
- Modify wm_gmii_hv_{read,write}reg_locked() to make them access
HV_SMB_ADDR correctly.
- Use new nvm.{acquire,release}() for semaphore.
- Our MII readreg/writereg API has not way to detect an error.
kmrn_{read,write}reg() are not used for MII API, so it's not required
for these functions to use the same API. So,
- Change return value as error code.
- Change register value from int to uint16_t.
- read: pass pointer for uint16_t as an argument.
- Check return value on caller side.
- Check whether it's required to use MDIC workaround for 80003 or not
in wm_reset(). If the workaround isn't required, don't use the
workaround code in wm_gmii_i80003_{read,write}reg.
- Add WM_F_WA_I210_CLSEM flag for a workaround. FreeBSD/Linux drivers
say "In rare circumstances, the SW semaphore may already be held
unintentionally on I21[01]". PXE boot is one of the case.
- Qemu's e1000e emulation (82574L)'s SPI has only 64 words. I've never
seen on real 82574 hardware with such small SPI ROM. Check
sc->sc_nvm_wordsize before accessing higher address words to prevent
timeout.
- Check some wm_nvm_read()'s return vale.
- Print NVM offset and word count when EERD polling failed.
- On I219, drop TARC0 bit 28 for DMA hang workaround (from Linux).
- 82583 supports jumbo frame. Fixes PR#52773 reported by
Shinichi Doyashiki.
- Fix typo in comment. Reported by Shinichi Doyashiki in PR#52885.
- Add ASPM workaround for 8257[1234] and 82583 to prevent device
timeout or hangup. Fixes PR#52818 reported by Shinichi Doyashiki.
- CID-1427779: Fix uninitialized variables.
- Fix a bug that wm_pll_workaround_i210() is not called when
a) Chip is I211 or b) Chip is I210 and it uses iNVM (not FLASH).
- Do wm_reset_mdicnfg_82580() on 82580 only.
- Fix FLASH access on PCH_SPT and newer. Their FLASH access should be
done by 32bit. Especially for ICH_FLASH_HSFCTL register, it's located
at 0x0006, so it must be accessed via ICH_FLASH_HSFSTS(0x0004) and
use shift or mask.
- Make wm_nvm_valid_bank_detect_ich8lan() the same as other OSes.
- If the extended configuration size in the EXTCNFSIZE register is 0,
don't continue in wm_init_lcd_from_nvm().
- Add PCH_CNP support (I219 with Intel 300 series chipset).
- Enable I219 support.
- I354 uses an external PHY, so don't use wm_set_eee_i350().
- Fix a bug that the link can't detect in link interrupt function for
non-SERDES fiber.
- Fix a bug that 82542 misunderstand fiber's signal detection.
- Add debug printf()s.
- Update comment.
- Rename functions and variables.
- Add diagnostic code.
- Sort registers.
- Lowercase hexadecimal values.
- KNF.
 1.95.2.3  14-Dec-2014  martin Pull up following revision(s) (requested by msaitoh in ticket #325):
sys/dev/pci/pcireg.h: revision 1.100
sys/dev/pci/pci_subr.c: revision 1.133
Add PCIe CRS Software Visibility bit.
 1.95.2.2  12-Dec-2014  martin Pull up following revision(s) (requested by msaitoh in ticket #312):
sys/dev/pci/pci_subr.c: revision 1.130
sys/dev/pci/pci_subr.c: revision 1.131
sys/dev/pci/pci_subr.c: revision 1.132
sys/dev/pci/pcireg.h: revision 1.97
sys/dev/pci/pcireg.h: revision 1.98
sys/dev/pci/pcireg.h: revision 1.99
sys/dev/pci/pci_subr.c: revision 1.127
sys/dev/pci/pci_subr.c: revision 1.128
sys/dev/pci/pci_subr.c: revision 1.129
Always print the Slot implemented bit in the PCIe Capabilities
Register using with onoff().
- Add some PCI subclass and interfaces.
- The interface of PCI_SUBCLASS_BRIDGE_RACEWAY is not decoded yet.
- Fix typo in a message.
- Add comment.
- Modify comment.
s/genric/generic/
Add comment.
Fix typo in comment.
Fix a bug that the specification revision of the Power Management function
was incorrectly printed in the output of capability "list".
The value is also printed in the detail output and it has no bug.
- Cleanup pci_conf_print_caplist. Use table. The reason why it loops twice
is that some capabilities appear multiple times (e.g. HyperTransport cap).
- Print the specification revision of Power Management and AGP not in
the capability list part but in the detail part.
Add some HyperTransport related defines. It's required for the MSI.
 1.95.2.1  12-Dec-2014  martin Pull up following revision(s) (requested by msaitoh in ticket #311):
sys/dev/pci/ppb.c: revision 1.53
sys/dev/pci/ppb.c: revision 1.54
sys/dev/pci/pcireg.h: revision 1.96
- Modify message of PCIe capability version. This field (PCIE_XCAP_VER_MASK)
is not specification's version number but the capability structure's version
number. To avoid confusion, print "PCI Express capability version x".
- The max number of PCIe lane is not 16 but 32. Fix the bug using with macro.
- Use macro instead of magic number.
- Gb/s -> GT/s
Rename PCIE_XCAP_VER_* macros to avoid confusion.
 1.100.2.9  28-Aug-2017  skrll Sync with HEAD
 1.100.2.8  05-Feb-2017  skrll Sync with HEAD
 1.100.2.7  05-Dec-2016  skrll Sync with HEAD
 1.100.2.6  05-Oct-2016  skrll Sync with HEAD
 1.100.2.5  29-May-2016  skrll Sync with HEAD
 1.100.2.4  27-Dec-2015  skrll Sync with HEAD (as of 26th Dec)
 1.100.2.3  22-Sep-2015  skrll Sync with HEAD
 1.100.2.2  06-Jun-2015  skrll Sync with HEAD
 1.100.2.1  06-Apr-2015  skrll Sync with HEAD
 1.113.2.4  26-Apr-2017  pgoyette Sync with HEAD
 1.113.2.3  20-Mar-2017  pgoyette Sync with HEAD
 1.113.2.2  07-Jan-2017  pgoyette Sync with HEAD. (Note that most of these changes are simply $NetBSD$
tag issues.)
 1.113.2.1  04-Nov-2016  pgoyette Sync with HEAD
 1.119.2.1  21-Apr-2017  bouyer Sync with HEAD
 1.130.2.11  29-Jan-2022  martin Pull up the following revisions, requested by msaitoh in ticket #1728:

sys/dev/pci/pci_subr.c 1.232-1.239 via patch
sys/dev/pci/pcireg.h 1.62-1.63

- Decode link control2's Compliance Preset/De-emphasis more.
- Decode Physical Layer 16.0 GT/s extended capability.
- Decode Lane Margining at the Receiver extended capability.
- Print "reserved" instead of "unknown" when printing equalization
preset. One of them is known to be the default value.
- Fix typo.
 1.130.2.10  03-Dec-2021  martin Pull up the following revisions, requested by msaitoh in ticket #1714:

sys/dev/pci/pcireg.h 1.148-1.154, 1.156-1.161
sys/dev/pci/pci_subr.c 1.217-1.222, 1.224, 1.227-1.232
via patch
sys/dev/pci/nvme_pci.c 1.31
sys/dev/pci/pci.c 1.158
sys/dev/pci/ppb.c 1.74

- Print Bridge Config Retry Enable bit and Retimer Presence Detect
Supported bit.
- Add PCIe 4.0 stuff a little:
- 10-bit Tag Requester/Completer.
- Add Data link Feature extended capability.
- Add Physical Layer 16.0 GT/s extended capability. Not decode yet.
- Change pci_conf_print() to allocate memory for the regs dynamically
instead of on-stack.
- Print some DPC register values not with %04x but with %08x because
those are 32bit.
- Fix a bug that the virtual channel extended configuration's
arbitration phase register can't be decoded correctly.
- When parsing Enhanced Allocation entries, use the correct calculation
for finding the next entry.
- Add 32.0GT/s to the list of pcie speeds (PCIe 5.x.).
- Add Some PCI config information:
- Lane Margining at the Receiver
- NVME admin interface
- UFSHCI
- InfiniBand
- Host fabric
- HDA 1.0 with vendor ext
- USB4 HCI
- MIPI I3C
- Cellular controller/modem (+ Ethernet)
- Change PCI_VENDOR_MASK and PCI_PRODUCT_MASK to unsigned values, to
prevent sign extension of product ID when shifted up into place in
PCI_ID_CODE(). Fixes PR kern/56176.
- Add LCAP & LCAP2 definitions.
- Use PCI-SIG official acronyms for some macros.
- Remove unused shift and mask definitions.
- Fix typo in some messages.
- Fix typo in comments.
- Whitespace fixes.
 1.130.2.9  26-Sep-2019  martin Pull up the following revisions, requested by msaitoh in ticket #1388:

sys/dev/pci/pcireg.h 1.147 via patch
sys/dev/pci/pci_subr.c 1.212, 1.215-1.217 via patch

- Change fast back-to-back "capable" to "enable" in pci_subr.c.
- Print Primary Discard Timer, Secondary Discard Timer, Discard
Timer Status and Discard Timer SERR# Enable bit in pci_subr.c.
- Print some DPC register values not with %04x but with %08x because
those are 32bit.
- Remove whitespace for consistency.
- Use macro.
- Whitespace fixes.
 1.130.2.8  04-Dec-2018  martin Pull up following revision(s) (requested by msaitoh in ticket #1118):

sys/dev/pci/pci_subr.c: revision 1.210
sys/dev/pci/pci_subr.c: revision 1.207
sys/dev/pci/pcireg.h: revision 1.143
sys/dev/pci/pci_subr.c: revision 1.208
sys/dev/pci/pcireg.h: revision 1.144
sys/dev/pci/pci_subr.c: revision 1.209
sys/dev/pci/pcireg.h: revision 1.145
sys/dev/pci/pcireg.h: revision 1.146

Decode PCI Enhanced Allocation.

The register offset of the mask and pending register is depend on the 64bit
address capable bit, so fix the definition of PCI MSI vector mask and pending
register. This problem was not a real bug because PCI_MSI{MASK,PENDING} were
not used from anywhere.

The downstream port of PCIe switch is not a root port, so don't print
root port related register. For example, Intel 63xxESB controller's
downstream port device was printed by pcictl(8) with this bug:
 1.130.2.7  30-Oct-2018  sborrill Pull up the following revisions(s) (requested by msaitoh in ticket #1074):
sys/dev/pci/pci_subr.c: revision 1.204-1.206
sys/dev/pci/pcireg.h: revision 1.141-1.142

Root Complex Event Collector Bus Number Association ECN.
- If capability version is 2 (or greater), decode RCEC Associated Bus Numbers
register.
- Don't print TPH requester's ST Table Size if the ST table location field
is not PCI_TPH_REQ_STTBLLOC_TPHREQ because the size field is only applicable
for PCI_TPH_REQ_STTBLLOC_TPHREQ case.
- Add comment.
 1.130.2.6  23-Sep-2018  martin Pull up following revision(s) (requested by msaitoh in ticket #1028):

sys/dev/pci/pci_subr.c: revision 1.203
sys/dev/pci/pcireg.h: revision 1.140

Add ATS Relaxed Ordering supported bit described in Address Translation
Relaxed Ordering ECN.
 1.130.2.5  26-Jul-2018  snj Pull up following revision(s) (requested by msaitoh in ticket #933):
sys/dev/pci/pci_subr.c: revision 1.202
sys/dev/pci/pcireg.h: revision 1.139
sys/dev/pci/ppbreg.h: revision 1.9
VGA 16 bit decode bit is not bit 3 but bit 4.
--
- Print Power Management Control/status register in 32bit.
- Simplify.
 1.130.2.4  26-Jul-2018  snj Pull up following revision(s) (requested by msaitoh in ticket #930):
sys/dev/pci/pci_subr.c: revision 1.201
sys/dev/pci/pcireg.h: revision 1.138
Fix typo. s/TPL/TLP/
 1.130.2.3  26-Feb-2018  snj Pull up following revision(s) (requested by msaitoh in ticket #576):
sys/dev/pci/pci_subr.c: 1.197-1.200
sys/dev/pci/pcireg.h: 1.136-1.137
sys/dev/pci/ppbreg.h: 1.8
Add VGA 16bit decode bit into the PCI bridge control register. This bit is
defined in PCI-to-PCI Bridge Architecture Specification Revision 1.2. This
bit has meaning if the VGA enable bit or the VGA Palette Snoop Enable bit is
set.
NOTE: sys/arch/x86/pci/pci_ranges.c::mmio_range_extend_by_vga_enable() and/or
some other functions should be modified.
"s/above 300W/greater than 300W/" in pci_conf_print_pcie_power(). From
PCIe Base Spec 3.1a Errata 2017-12-13.
Cleanup:
- Don't pass a capability pointer as a argument of pci_conf_find_cap() and
determine the first pointer in the pci_conf_find_cap() function.
- Don't pass a capability pointer as a argument of pci_conf_find_extcap()
because it's not used.
- Remove unsed code.
- Add PCie Link Activation ECN.
- Use macro.
- KNF.
 1.130.2.2  21-Nov-2017  martin Pull up following revision(s) (requested by msaitoh in ticket #362):
sys/dev/pci/pcireg.h: revision 1.133
sys/dev/pci/pcireg.h: revision 1.134
sys/dev/pci/pcireg.h: revision 1.135
sys/dev/pci/pci_subr.c: revision 1.190
sys/dev/pci/pci_subr.c: revision 1.191
sys/dev/pci/pci_subr.c: revision 1.192
sys/dev/pci/pci_subr.c: revision 1.193
sys/dev/pci/pci_subr.c: revision 1.194
sys/dev/pci/pcireg.h: revision 1.132
- Official shortname of LN Requester is LNR, so change PCI_EXTCAP_LN_REQ
to PCI_EXTCAP_LNR
- Use macro.
- Add PCI_MAPREG_ROM_ADDR_MASK macro and PCI_MAPREG_ROM_ADDR() macro.
- print PCI_MAPREG_ROM_ENABLE bit.
- Decode Expansion ROM Validation ECN.
- Add Native PCIe Enclosure Management ECN's extended capability type.
Not decoded yet.
Decode IOMMU capability of PCI secure device capability. From "AMD I/O
Virtualization Technology(IOMMU) Specification (#48882) Revision 3.00".
IOMMU cap dump fixes:
- Print Capability Register's value.
- Indent output correctly.
- s/cahced/cached/
- Print MSI Message number with 0x%02x
Fix a bug that the TPH ST table is decoded even if it's not in the TPH
Requester extended capability structure.
 1.130.2.1  04-Jul-2017  martin Pull up following revision(s) (requested by msaitoh in ticket #80):
sys/dev/pci/pci_subr.c: revision 1.184
sys/dev/pci/pci_subr.c: revision 1.185
sys/dev/pci/pci_subr.c: revision 1.186
sys/dev/pci/pci_subr.c: revision 1.187
sys/dev/pci/pci_subr.c: revision 1.188
sys/dev/pci/pci_subr.c: revision 1.189
sys/dev/pci/pcireg.h: revision 1.131
Add missing return to print the Slot Power Limit Value correctly.
Fix to print the following bit fields correctly.
- Supported Link Speeds Vector in LCAP2
- Lower SKP OS Generation Supported Speed Vector in LCAP2
- Lower SKP OS Reception Supported Speed Vector in LCAP2
- Enable Lower SKP OS Generation Vector in LCTL3
Note that the above bitfields start from 0 and the follwing bitfields start
from 1:
- Maximum Link Speed in LCAP
- Current Link Speed in LCSR
- Target Link Speed in LCSR2
For the Target Link Speed in LCSR2, 0 is allowed for a device which supports
2.5GT/s only (and this check also works for devices which compliant to
versions of the base specification prior to 3.0.
Tested with BCM5709:
- Target Link Speed: unknown value (0)
+ Target Link Speed: 2.5GT/s
For Attention Indicator Control bit and Power Indicator Control bit, it's
allowed to be a read only value 0 if corresponding capability register bit
is 0.
Fix a bug that LTR's latency in L1 PM Substates capability and Latency
Tolerance Reporting capability isn't printed correctly.
Fix printf format/argument.
 1.137.2.6  26-Dec-2018  pgoyette Sync with HEAD, resolve a few conflicts
 1.137.2.5  26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.137.2.4  20-Oct-2018  pgoyette Sync with head
 1.137.2.3  30-Sep-2018  pgoyette Ssync with HEAD
 1.137.2.2  28-Jul-2018  pgoyette Sync with HEAD
 1.137.2.1  21-May-2018  pgoyette Sync with HEAD
 1.138.2.2  08-Apr-2020  martin Merge changes from current as of 20200406
 1.138.2.1  10-Jun-2019  christos Sync with HEAD
 1.147.4.4  29-Jan-2022  martin Pull up the following revisions, requested by msaitoh in ticket #1412:

sys/dev/pci/pci_subr.c 1.232-1.239 via patch
sys/dev/pci/pcireg.h 1.62-1.63

- Decode link control2's Compliance Preset/De-emphasis more.
- Decode Physical Layer 16.0 GT/s extended capability.
- Decode Lane Margining at the Receiver extended capability.
- Print "reserved" instead of "unknown" when printing equalization
preset. One of them is known to be the default value.
- Fix typo.
 1.147.4.3  03-Dec-2021  martin Pull up the following revisions, requested by msaitoh in ticket #1384:

sys/dev/pci/pcireg.h 1.152-1.154, 1.156-1.161
sys/dev/pci/pci_subr.c 1.222, 1.227-1.232 via patch
sys/dev/pci/nvme_pci.c 1.31
sys/dev/pci/pci.c 1.158, 1.163
sys/dev/pci/ppb.c 1.74

- When parsing Enhanced Allocation entries, use the correct calculation
for finding the next entry.
- Add 32.0GT/s to the list of pcie speeds (PCIe 5.x.).
- Add Some PCI config information:
- Lane Margining at the Receiver
- NVME admin interface
- UFSHCI
- InfiniBand
- Host fabric
- HDA 1.0 with vendor ext
- USB4 HCI
- MIPI I3C
- Cellular controller/modem (+ Ethernet)
- Change PCI_VENDOR_MASK and PCI_PRODUCT_MASK to unsigned values, to
prevent sign extension of product ID when shifted up into place in
PCI_ID_CODE(). Fixes PR kern/56176.
- Add LCAP & LCAP2 definitions.
- Use PCI-SIG official acronyms for some macros.
- Fix typo in some messages.
- Fix typo in comments.
- Whitespace fixes.
 1.147.4.2  19-Mar-2020  martin Pull up following revision(s) (requested by msaitoh in ticket #782):

sys/dev/pci/pcireg.h: revision 1.150
sys/dev/pci/pcireg.h: revision 1.151
sys/dev/pci/pci_subr.c: revision 1.220
sys/dev/pci/pci_subr.c: revision 1.221
sys/dev/pci/pcireg.h: revision 1.149

- Print Bridge Config Retry Enable bit and Retimer Presence Detect Supported
bit.
- Avoid using magic number.

Add PCIe 4.0 stuff a little:
- 10-bit Tag Requester/Completer.
- Add Data link Feature extended capability.
- Add Physical Layer 16.0 GT/s extended capability. Not decode yet.

Remove unused shift and mask definitions.

Add comment.
 1.147.4.1  21-Jan-2020  martin Pull up the following, requested by msaitoh in ticket #629:

sys/dev/pci/pcireg.h 1.148
sys/dev/pci/pci_subr.c 1.218-1.219

- Fix a bug that the virtual channel extended configuration's
arbitration phase register can't be decoded correctly.
- Fix typo.
 1.148.2.2  29-Feb-2020  ad Sync with head.
 1.148.2.1  25-Jan-2020  ad Sync with head.
 1.151.6.1  03-Jan-2021  thorpej Sync w/ HEAD.
 1.153.6.1  31-May-2021  cjep sync with head
 1.153.4.2  01-Aug-2021  thorpej Sync with HEAD.
 1.153.4.1  17-Jun-2021  thorpej Sync w/ HEAD.
 1.168.2.1  22-Jun-2024  martin Pull up following revision(s) (requested by rin in ticket #723):

sys/dev/pci/pcireg.h: revision 1.171

PCI_CLASS_MASK: Use unsigned to avoid undefined behavior. Found by kUBSan.
 1.171.2.1  02-Aug-2025  perseant Sync with HEAD

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