| History log of /src/sys/dev/tprof/tprof_armv8.c |
| Revision | | Date | Author | Comments |
| 1.20 |
| 11-Apr-2023 |
msaitoh | KNF. No functional change.
|
| 1.19 |
| 22-Dec-2022 |
ryo | Even if an overflow interrupt is occured for a counter outside tprof management,
the bit of onverflow status register must be cleared to prevent an interrupt storm.
|
| 1.18 |
| 01-Dec-2022 |
ryo | branches: 1.18.2;
Improve tprof(4)
- Multiple events can now be handled simultaneously.
- Counters should be configured with TPROF_IOC_CONFIGURE_EVENT in advance,
instead of being configured at TPROF_IOC_START.
- The configured counters can be started and stopped repeatedly by
PROF_IOC_START/TPROF_IOC_STOP.
- The value of the performance counter can be obtained at any timing as a 64bit
value with TPROF_IOC_GETCOUNTS.
- Backend common parts are handled in tprof.c as much as possible, and functions
on the tprof_backend side have been reimplemented to be more primitive.
- The reset value of counter overflows for profiling can now be adjusted.
It is calculated by default from the CPU clock (speed of cycle counter) and
TPROF_HZ, but for some events the value may be too large to be sufficient for
profiling. The event counter can be specified as a ratio to the default or as
an absolute value when configuring the event counter.
- Due to overall changes, API and ABI have been changed. TPROF_VERSION and
TPROF_BACKEND_VERSION were updated.
|
| 1.17 |
| 01-Dec-2022 |
ryo | PMCR.E should not be disabled from tprof.
PMCR.E controls not only performance event counters but also the cycle
counter operation, and the cycle counter may be used for cpu_counter.
Similarly, the 31st bit in PMINTENCLR and PMCNTENCLR controls the cycle
counter, not performance event counters, and should not be modified.
|
| 1.16 |
| 10-Nov-2022 |
ryo | revert my previous commit.
since armv8_pmu_init is only called when it is reliably worked by ACPI or fdt,
there is no need for dynamic checks.
pointed out by jmcneill@, thanks
|
| 1.15 |
| 09-Nov-2022 |
ryo | If the hardware does not support PMU, return an error instead of KASSERT.
|
| 1.14 |
| 16-May-2022 |
jmcneill | tprof: armv8: Only attach to known PMU types.
|
| 1.13 |
| 03-Dec-2021 |
skrll | fix the typo that martin spotted.
|
| 1.12 |
| 03-Dec-2021 |
skrll | Add a comment and simplify the code ever so slightly.
|
| 1.11 |
| 03-Dec-2021 |
skrll | Use the first (not second) event counter as there might only be one
available.
|
| 1.10 |
| 26-Nov-2021 |
christos | declare xc
|
| 1.9 |
| 25-Nov-2021 |
skrll | Improve error handling.
Hypervisors can return a PMCR.N of 0.
|
| 1.8 |
| 01-Nov-2021 |
skrll | Trailing whitespace
|
| 1.7 |
| 26-Sep-2021 |
jmcneill | Make sure setup happens on all CPUs.
|
| 1.6 |
| 30-Oct-2020 |
skrll | Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.
|
| 1.5 |
| 30-Mar-2020 |
jmcneill | Enable the cycle counter when a CPU hatches and store an estimate of the
frequency in ci_data.cpu_cc_freq.
|
| 1.4 |
| 17-Jul-2018 |
christos | branches: 1.4.2; 1.4.8;
use PRI?64 instead of ll?
|
| 1.3 |
| 16-Jul-2018 |
jmcneill | Spaces -> tabs
|
| 1.2 |
| 16-Jul-2018 |
jmcneill | RW fields in performance monitor registers are reset to architecturally
UNKNOWN values. Initialize the PMU to a known state - all interrupts and
counters disabled, performance monitor disabled, and user access disabled.
|
| 1.1 |
| 15-Jul-2018 |
jmcneill | Add tprof backend for ARMv8 performance monitors.
|
| 1.4.8.3 |
| 08-Apr-2020 |
martin | Merge changes from current as of 20200406
|
| 1.4.8.2 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.4.8.1 |
| 17-Jul-2018 |
christos | file tprof_armv8.c was added on branch phil-wifi on 2019-06-10 22:07:33 +0000
|
| 1.4.2.2 |
| 28-Jul-2018 |
pgoyette | Sync with HEAD
|
| 1.4.2.1 |
| 17-Jul-2018 |
pgoyette | file tprof_armv8.c was added on branch pgoyette-compat on 2018-07-28 04:37:57 +0000
|
| 1.18.2.2 |
| 21-Jun-2023 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #210):
usr.sbin/tprof/tprof.8: revision 1.30
sys/dev/tprof/tprof_x86_amd.c: revision 1.8
sys/dev/tprof/tprof_armv8.c: revision 1.20
sys/dev/tprof/tprof_types.h: revision 1.7
sys/dev/tprof/tprof_x86_intel.c: revision 1.6
sys/dev/tprof/tprof_x86_intel.c: revision 1.7
sys/dev/tprof/tprof_x86_intel.c: revision 1.8
sys/dev/tprof/tprof.c: revision 1.23
usr.sbin/tprof/tprof.8: revision 1.25
usr.sbin/tprof/tprof.8: revision 1.26
usr.sbin/tprof/arch/tprof_x86.c: revision 1.16
usr.sbin/tprof/tprof.8: revision 1.27
usr.sbin/tprof/arch/tprof_x86.c: revision 1.17
usr.sbin/tprof/tprof.8: revision 1.28
usr.sbin/tprof/tprof.h: revision 1.5
usr.sbin/tprof/tprof.8: revision 1.29
sys/dev/tprof/tprof_armv7.c: revision 1.13
usr.sbin/tprof/tprof_top.c: revision 1.9
usr.sbin/tprof/tprof.c: revision 1.21
Add Cometlake support.
Obtain the number of general counters from CPUID 0xa.
Test cpuid_level in tprof_intel_ncounters().
This function is called before tprof_intel_ident().
KNF. No functional change.
Add two note to the tprof(8)'s manual page.
- "list" command prints the maximum number of counters that can be used
simultaneously.
- multiple -e arguments can be specified.
Use the default counter if -e argument is not specified.
monitor command:
The default counter is selected if -e argument is not specified.
list command:
Print the name of the default counter for monitor and top command.
tprof.8: new sentence, new line
tprof(8): fix markup nits
tprof.8: fix typo, s/speficied/specified/
|
| 1.18.2.1 |
| 23-Dec-2022 |
martin | Pull up following revision(s) (requested by ryo in ticket #20):
sys/arch/arm/arm/cpufunc.c: revision 1.185
sys/dev/tprof/tprof.c: revision 1.22
sys/arch/arm/arm32/arm32_boot.c: revision 1.45
sys/dev/tprof/tprof_armv8.c: revision 1.19
sys/dev/tprof/tprof_armv7.c: revision 1.12
sys/arch/aarch64/aarch64/cpu.c: revision 1.71
sys/arch/aarch64/aarch64/cpu.c: revision 1.72
tprof_lock is not a spin mutex. use mutex_{enter,exit}(). oops
Explicitly disable overflow interrupts before enabling the cycle counter.
PMCR_EL0.LC should be set. ARM deprecates use of PMCR_EL0.LC=0
Even if an overflow interrupt is occured for a counter outside tprof management,
the bit of onverflow status register must be cleared to prevent an interrupt storm.
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