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History log of /src/sys/external/bsd/compiler_rt/dist/lib/builtins/arm/divmodsi4.S
RevisionDateAuthorComments
 1.3  30-Jun-2021  skrll Do previous differently by pushing even number of registers and remove
strange r7 usage.
 1.2  29-Jun-2021  rin Align sp to 8-byte boundary as required by EABI.

This is especially important for non-leaf functions; GCC optimizes codes
based on assumption that sp is aligned properly.

Mostly fix broken earmv5 userland compiled by GCC10 due to alignment
faults in ld.elf_so, where {ld,st}rd are used for [sp, #8x].

No regression for ATF is observed for earmv[67]{,hf}{,eb}.
 1.1  26-Feb-2014  joerg branches: 1.1.1;
Initial revision
 1.1.1.4  27-Feb-2016  joerg branches: 1.1.1.4.22; 1.1.1.4.34;
Import compiler-rt r259194. Primary changes are better support for
128bit long double and a number of refinements in the profiling backend.
 1.1.1.3  10-Aug-2014  joerg branches: 1.1.1.3.4; 1.1.1.3.6;
Import compiler-rt r215309. Extends 128bit IEEE support in soft-float,
uses Thumb mode by default on ARM when available and fixes a bug in the
division code for ARMs with hardware integer division.
 1.1.1.2  16-May-2014  joerg branches: 1.1.1.2.2; 1.1.1.2.4;
Import compiler-rt r208593. Fix a build bug in __clear_cache by not
explicitly forcing the ABI. Add first part of IEEE 754 quad support.
 1.1.1.1  26-Feb-2014  joerg branches: 1.1.1.1.2;
Import compiler-rt r202303. Extend 128bit support to all LP64 platforms.
 1.1.1.4.34.1  01-Aug-2021  thorpej Sync with HEAD.
 1.1.1.4.22.1  08-Aug-2021  martin Pull up following revision(s) (requested by skrll in ticket #1329):

lib/libc/arch/arm/gen/swapcontext.S: revision 1.18
sys/external/bsd/compiler_rt/dist/lib/builtins/arm/divsi3.S: revision 1.2
sys/external/bsd/compiler_rt/dist/lib/builtins/arm/divsi3.S: revision 1.3
sys/external/bsd/compiler_rt/dist/lib/builtins/arm/aeabi_cfcmp.S: revision 1.2
sys/external/bsd/compiler_rt/dist/lib/builtins/arm/aeabi_cfcmp.S: revision 1.3
lib/libc/arch/arm/sys/__clone.S: revision 1.10
lib/libc/arch/arm/sys/__clone.S: revision 1.11
sys/external/bsd/compiler_rt/dist/lib/builtins/arm/modsi3.S: revision 1.2
lib/libc/arch/arm/sys/__clone.S: revision 1.12
sys/external/bsd/compiler_rt/dist/lib/builtins/arm/modsi3.S: revision 1.3
lib/libc/arch/arm/sys/__clone.S: revision 1.13
lib/libc/arch/arm/sys/__clone.S: revision 1.14
sys/external/bsd/compiler_rt/dist/lib/builtins/arm/divmodsi4.S: revision 1.2
sys/external/bsd/compiler_rt/dist/lib/builtins/arm/divmodsi4.S: revision 1.3
lib/libc/arch/arm/gen/swapcontext.S: revision 1.16
lib/libc/arch/arm/gen/swapcontext.S: revision 1.17

Align sp to 8-byte boundary as required by EABI.

This is especially important for non-leaf functions; GCC optimizes codes
based on assumption that sp is aligned properly.

Mostly fix broken earmv5 userland compiled by GCC10 due to alignment
faults in ld.elf_so, where {ld,st}rd are used for [sp, #8x].

No regression for ATF is observed for earmv[67]{,hf}{,eb}.

Align sp to 8-byte boundary as required by EABI.
IIUC, this change only affects libc compiled for ``Thumb-mode userland'',
which we've not officially supported yet.

Fix previous. For Thumb-1:
- sp cannot be manipulated directly
- {add,sub}s should be used instead of {add,sub}

Trailing whitespace

The _INVOKE_CERROR macro deals with thumb so simplify the code (at the
expense of a couple more instructions).

Do previous differently by pushing even number of registers and remove
strange r7 usage.

Do previous differtly by pushing two registers in the same way as the
_INVOKE_CERROR macro
 1.1.1.3.6.1  19-Mar-2016  skrll Sync with HEAD
 1.1.1.3.4.3  03-Dec-2017  jdolecek update from HEAD
 1.1.1.3.4.2  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.1.1.3.4.1  10-Aug-2014  tls file divmodsi4.S was added on branch tls-maxphys on 2014-08-20 00:03:58 +0000
 1.1.1.2.4.2  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.1.1.2.4.1  16-May-2014  yamt file divmodsi4.S was added on branch yamt-pagecache on 2014-05-22 11:40:43 +0000
 1.1.1.2.2.2  18-May-2014  rmind sync with head
 1.1.1.2.2.1  16-May-2014  rmind file divmodsi4.S was added on branch rmind-smpnet on 2014-05-18 17:45:54 +0000
 1.1.1.1.2.1  10-Aug-2014  tls Rebase.

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