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History log of /src/sys/external/bsd/drm2/drm/drm_gem_vm.c
RevisionDateAuthorComments
 1.15  06-Jul-2022  riastradh uvm(9): fo_mmap caller guarantees positive size.

No functional change intended, just sprinkling assertions to make it
clearer.
 1.14  19-Dec-2021  riastradh Make ourselves less dependent on drmP.h, removed upstream.

This causes some trouble as CONFIG_* lines might not be appropriately
defined. A few declarations remain in drmP.h so it's not gone.


Author: Maya Rashish <maya@NetBSD.org>
 1.13  19-Dec-2021  riastradh drm/drm_drv.h for struct drm_device


Author: Maya Rashish <maya@NetBSD.org>
 1.12  19-Dec-2021  riastradh Catch up with function renames

reference -> get, unreference -> put


Author: Maya Rashish <maya@NetBSD.org>
 1.11  19-Dec-2021  riastradh Need <sys/file.h> to dereference struct file.
 1.10  19-Dec-2021  riastradh Pass drm_file, not file, pointer to drm_vma_node_is_allowed.
 1.9  27-Aug-2018  riastradh Rename drm_mmap_* -> drm_legacy_mmap_* like upstream.
 1.8  27-Aug-2018  riastradh Need drm_legacy.h for legacy mmap stuff.
 1.7  27-Aug-2018  riastradh Need to use new <drm/drm_gem.h> for GEM stuff.
 1.6  09-Mar-2015  riastradh branches: 1.6.16; 1.6.18;
Apply access control to gem mmap.
 1.5  26-Jul-2014  riastradh branches: 1.5.2; 1.5.4; 1.5.6;
Let the drm driver decide what part of what object gets mmapped.

Pass the file around too so radeon/ttm can get at it to verify access.

Add drm_gem_or_legacy_mmap_object for drivers to choose the previous
behaviour, like i915.
 1.4  16-Jul-2014  riastradh Make it build and boot on my test machines.

Screen blanks on boot on the Ivy Bridge system with

DRM error in cpt_serr_int_handler: PCH transcoder A FIFO underrun

But after that everything is OK. Appears to be an upstream problem.
To investigate...

I think there's a cache flushing issue somewhere -- there are little
display artefacts on my T60.
 1.3  01-May-2014  riastradh branches: 1.3.2; 1.3.4;
Tweak some DRM GEM page indexing crap.

- Fix order of subtraction in drm_mmap_paddr_locked.
- Address GEM objects' pages from 0, not from the mmap cookie.
- Check page alignment earlier in mmap code paths.
- Sprinkle kasserts throughout.

Still doesn't fix the garbage that is sometimes being scribbled all
over kernel memory!
 1.2  18-Mar-2014  riastradh branches: 1.2.2;
Merge riastradh-drm2 to HEAD.
 1.1  24-Jul-2013  riastradh branches: 1.1.2;
file drm_gem_vm.c was initially added on branch riastradh-drm2.
 1.1.2.5  22-Jan-2014  riastradh Little reference counting fix in drm_mmap.
 1.1.2.4  22-Jan-2014  riastradh Tidy up and reuse the code I had already written for gem mmapping.
 1.1.2.3  08-Sep-2013  riastradh Use the _unlocked variant of unreference in drm_gem_pager_detach.
 1.1.2.2  08-Sep-2013  riastradh Avoid the PAGE_MASK mess in drm_gem_vm.c, drm_scatter.c, & drm_vm.c.
 1.1.2.1  24-Jul-2013  riastradh Add local drm_gem_vm.c, utilities for mapping gem objects into vm.
 1.2.2.1  10-Aug-2014  tls Rebase.
 1.3.4.2  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.3.4.1  01-May-2014  yamt file drm_gem_vm.c was added on branch yamt-pagecache on 2014-05-22 11:40:55 +0000
 1.3.2.2  18-May-2014  rmind sync with head
 1.3.2.1  01-May-2014  rmind file drm_gem_vm.c was added on branch rmind-smpnet on 2014-05-18 17:46:00 +0000
 1.5.6.1  06-Apr-2015  skrll Sync with HEAD
 1.5.4.3  03-Dec-2017  jdolecek update from HEAD
 1.5.4.2  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.5.4.1  26-Jul-2014  tls file drm_gem_vm.c was added on branch tls-maxphys on 2014-08-20 00:04:20 +0000
 1.5.2.1  17-Mar-2015  riz Pull up following revision(s) (requested by snj in ticket #590):
sys/external/bsd/drm2/i915drm/intel_gtt.c: revision 1.5
sys/external/bsd/drm2/drm/drm_drv.c: revision 1.15
sys/external/bsd/drm2/dist/drm/i915/i915_gem.c: revision 1.28
sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_nv50.c: revision 1.3
sys/dev/pci/agp_i810.c: revision 1.115
sys/dev/pci/agp_i810.c: revision 1.116
sys/external/bsd/drm2/include/drm/intel-gtt.h: revision 1.5
sys/dev/pci/agp_i810.c: revision 1.117
sys/external/bsd/drm2/drm/drm_gem_vm.c: revision 1.6
sys/dev/pci/agp_i810var.h: revision 1.6
Issue a write barrier after updating the GTT.
Linux never used to do this...until a month:
<a rel="nofollow" href="https://bugs.freedesktop.org/show_bug.cgi?id=88191">https://bugs.freedesktop.org/show_bug.cgi?id=88191</a>
commit 983d308cb8f602d1920a8c40196eb2ab6cc07bd2
Author: Chris Wilson &lt;chris%chris-wilson.co.uk@localhost&gt;
Date: Mon Jan 26 10:47:10 2015 +0000
agp/intel: Serialise after GTT updates
Include &lt;sys/atomic.h&gt; for membar_producer.
(Why didn't this fail in my build?)
Pass cache-related flags through to the GTT on pre-SNB devices.
I had assumed for ages this would increase the amount of caching and
thereby increase the chance of stale caches leading to rendering
glitches. But apparently I was wrong, and failing to pass these
through was causing all sorts of problems!
Dedup the NetBSD portion of the code (ok Riastradh), no functional change.
Don't return events that are too large and leave them in the list.
Apply access control to gem mmap.
fix gcc is stupid.
 1.6.18.1  10-Jun-2019  christos Sync with HEAD
 1.6.16.1  06-Sep-2018  pgoyette Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)

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