1 /* $NetBSD: exynos_uart.c,v 1.9 2026/11/07 22:20:11 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2013-2021 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry and Jared McNeill. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "locators.h" 33 34 #include <sys/cdefs.h> 35 36 __KERNEL_RCSID(1, "$NetBSD: exynos_uart.c,v 1.9 2026/11/07 22:20:11 thorpej Exp $"); 37 38 #define cn_trap() \ 39 do { \ 40 console_debugger(); \ 41 cn_trapped = 1; \ 42 } while (/* CONSTCOND */ 0) 43 44 #include <sys/param.h> 45 #include <sys/bus.h> 46 #include <sys/device.h> 47 #include <sys/conf.h> 48 #include <sys/intr.h> 49 #include <sys/systm.h> 50 #include <sys/time.h> 51 #include <sys/termios.h> 52 #include <sys/kauth.h> 53 #include <sys/lwp.h> 54 #include <sys/tty.h> 55 56 #include <dev/cons.h> 57 58 #include <dev/fdt/fdtvar.h> 59 #include <dev/fdt/fdt_console.h> 60 61 #include <arm/samsung/sscom_reg.h> 62 63 static int exynos_uart_match(device_t, cfdata_t, void *); 64 static void exynos_uart_attach(device_t, device_t, void *); 65 66 static int exynos_uart_intr(void *); 67 68 static int exynos_uart_cngetc(dev_t); 69 static void exynos_uart_cnputc(dev_t, int); 70 static void exynos_uart_cnpollc(dev_t, int); 71 72 static void exynos_uart_start(struct tty *); 73 static int exynos_uart_param(struct tty *, struct termios *); 74 75 extern struct cfdriver exuart_cd; 76 77 enum exynos_uart_type { 78 EXYNOS_UART_SAMSUNG, 79 EXYNOS_UART_APPLE, 80 }; 81 82 struct exynos_uart_config { 83 enum exynos_uart_type type; 84 uint32_t rxfull; 85 uint32_t txfull; 86 uint32_t rxcount; 87 }; 88 89 struct exynos_uart_softc { 90 device_t sc_dev; 91 bus_space_tag_t sc_bst; 92 bus_space_handle_t sc_bsh; 93 kmutex_t sc_lock; 94 u_int sc_freq; 95 void *sc_ih; 96 97 bool sc_console; 98 struct tty *sc_tty; 99 100 int sc_ospeed; 101 tcflag_t sc_cflag; 102 103 const struct exynos_uart_config *sc_conf; 104 105 u_char sc_buf[1024]; 106 }; 107 108 #define RD4(sc, reg) \ 109 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 110 #define WR4(sc, reg, val) \ 111 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 112 113 static bus_addr_t exynos_uart_consaddr; 114 115 static struct exynos_uart_softc exynos_uart_cnsc; 116 117 static struct cnm_state exynos_uart_cnm_state; 118 119 struct consdev exynos_uart_consdev = { 120 .cn_getc = exynos_uart_cngetc, 121 .cn_putc = exynos_uart_cnputc, 122 .cn_pollc = exynos_uart_cnpollc, 123 .cn_dev = NODEV, 124 .cn_pri = CN_NORMAL, 125 }; 126 127 static dev_type_open(exynos_uart_open); 128 static dev_type_open(exynos_uart_close); 129 static dev_type_read(exynos_uart_read); 130 static dev_type_write(exynos_uart_write); 131 static dev_type_ioctl(exynos_uart_ioctl); 132 static dev_type_tty(exynos_uart_tty); 133 static dev_type_poll(exynos_uart_poll); 134 static dev_type_stop(exynos_uart_stop); 135 136 const struct cdevsw exuart_cdevsw = { 137 .d_open = exynos_uart_open, 138 .d_close = exynos_uart_close, 139 .d_read = exynos_uart_read, 140 .d_write = exynos_uart_write, 141 .d_ioctl = exynos_uart_ioctl, 142 .d_stop = exynos_uart_stop, 143 .d_tty = exynos_uart_tty, 144 .d_poll = exynos_uart_poll, 145 .d_mmap = nommap, 146 .d_kqfilter = ttykqfilter, 147 .d_discard = nodiscard, 148 .d_flag = D_TTY 149 }; 150 151 static int exynos_uart_cmajor = -1; 152 153 static const struct exynos_uart_config exynos_uart_samsung = { 154 .type = EXYNOS_UART_SAMSUNG, 155 .rxfull = UFSTAT_RXFULL, 156 .txfull = UFSTAT_TXFULL, 157 .rxcount = UFSTAT_RXCOUNT, 158 }; 159 160 static const struct exynos_uart_config exynos_uart_apple = { 161 .type = EXYNOS_UART_APPLE, 162 .rxfull = UFSTAT_S5L_RXFULL, 163 .txfull = UFSTAT_S5L_TXFULL, 164 .rxcount = UFSTAT_S5L_RXCOUNT, 165 }; 166 167 static const struct device_compatible_entry compat_data[] = { 168 { .compat = "samsung,exynos4210-uart", .data = &exynos_uart_samsung }, 169 { .compat = "apple,s5l-uart", .data = &exynos_uart_apple }, 170 DEVICE_COMPAT_EOL 171 }; 172 173 CFATTACH_DECL_NEW(exynos_uart, sizeof(struct exynos_uart_softc), 174 exynos_uart_match, exynos_uart_attach, NULL, NULL); 175 176 static int 177 exynos_uart_match(device_t parent, cfdata_t cf, void *aux) 178 { 179 struct fdt_attach_args * const faa = aux; 180 181 return of_compatible_match(faa->faa_phandle, compat_data); 182 } 183 184 static void 185 exynos_uart_attach(device_t parent, device_t self, void *aux) 186 { 187 struct exynos_uart_softc * const sc = device_private(self); 188 struct fdt_attach_args * const faa = aux; 189 const int phandle = faa->faa_phandle; 190 char intrstr[128]; 191 struct clk *clk_uart, *clk_uart_baud0; 192 struct tty *tp; 193 int major, minor; 194 bus_addr_t addr; 195 bus_size_t size; 196 uint32_t ucon; 197 198 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 199 aprint_error(": couldn't get registers\n"); 200 return; 201 } 202 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 203 aprint_error(": failed to decode interrupt\n"); 204 return; 205 } 206 clk_uart = fdtbus_clock_get(phandle, "uart"); 207 if (clk_uart == NULL || clk_enable(clk_uart) != 0) { 208 aprint_error(": failed to enable uart clock\n"); 209 return; 210 } 211 clk_uart_baud0 = fdtbus_clock_get(phandle, "clk_uart_baud0"); 212 if (clk_uart_baud0 == NULL || clk_enable(clk_uart_baud0) != 0) { 213 aprint_error(": failed to enable clk_uart_baud0 clock\n"); 214 return; 215 } 216 217 const bool is_console = exynos_uart_consaddr == addr; 218 219 sc->sc_dev = self; 220 sc->sc_bst = faa->faa_bst; 221 sc->sc_conf = of_compatible_lookup(phandle, compat_data)->data; 222 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 223 sc->sc_console = is_console; 224 if (is_console) { 225 sc->sc_bsh = exynos_uart_cnsc.sc_bsh; 226 } else { 227 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 228 aprint_error(": failed to map registers\n"); 229 return; 230 } 231 } 232 sc->sc_freq = clk_get_rate(clk_uart_baud0); 233 234 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_SERIAL, 235 0, exynos_uart_intr, sc, device_xname(self)); 236 if (sc->sc_ih == NULL) { 237 aprint_error(": failed to establish interrupt on %s\n", 238 intrstr); 239 return; 240 } 241 242 if (exynos_uart_cmajor == -1) { 243 /* allocate a major number */ 244 int bmajor = -1, cmajor = -1; 245 int error = devsw_attach("exuart", NULL, &bmajor, 246 &exuart_cdevsw, &cmajor); 247 if (error) { 248 aprint_error(": couldn't allocate major number\n"); 249 return; 250 } 251 exynos_uart_cmajor = cmajor; 252 } 253 254 major = cdevsw_lookup_major(&exuart_cdevsw); 255 minor = device_unit(self); 256 257 tp = sc->sc_tty = tty_alloc(); 258 tp->t_oproc = exynos_uart_start; 259 tp->t_param = exynos_uart_param; 260 tp->t_dev = makedev(major, minor); 261 tp->t_sc = sc; 262 tty_attach(tp); 263 264 aprint_naive("\n"); 265 if (is_console) { 266 cn_tab->cn_dev = tp->t_dev; 267 aprint_normal(": console"); 268 } 269 aprint_normal("\n"); 270 271 if (is_console) 272 delay(10000); 273 274 /* Initialize device */ 275 WR4(sc, SSCOM_UFCON, 276 __SHIFTIN(2, UFCON_TXTRIGGER) | 277 __SHIFTIN(1, UFCON_RXTRIGGER) | 278 UFCON_TXFIFO_RESET | UFCON_RXFIFO_RESET | 279 UFCON_FIFO_ENABLE); 280 281 /* Configure PIO mode with RX timeout interrupts */ 282 ucon = UCON_TOINT | UCON_ERRINT | 283 UCON_TXMODE_INT | UCON_RXMODE_INT; 284 WR4(sc, SSCOM_UCON, ucon); 285 286 switch (sc->sc_conf->type) { 287 case EXYNOS_UART_SAMSUNG: 288 WR4(sc, SSCOM_UCON, ucon | __SHIFTIN(3, UCON_RXTO)); 289 /* Disable interrupts */ 290 WR4(sc, SSCOM_UINTM, ~0u); 291 break; 292 case EXYNOS_UART_APPLE: 293 break; 294 } 295 296 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 297 } 298 299 static int 300 exynos_uart_cngetc(dev_t dev) 301 { 302 struct exynos_uart_softc * const sc = &exynos_uart_cnsc; 303 uint32_t ufstat; 304 int s, c; 305 306 s = splserial(); 307 308 ufstat = RD4(sc, SSCOM_UFSTAT); 309 if (__SHIFTOUT(ufstat, sc->sc_conf->rxcount) == 0) { 310 splx(s); 311 return -1; 312 } 313 314 c = RD4(sc, SSCOM_URXH); 315 if (!db_active) { 316 int cn_trapped __unused = 0; 317 cn_check_magic(dev, c & 0xff, exynos_uart_cnm_state); 318 } 319 320 splx(s); 321 322 return c & 0xff; 323 } 324 325 static void 326 exynos_uart_cnputc(dev_t dev, int c) 327 { 328 struct exynos_uart_softc * const sc = &exynos_uart_cnsc; 329 int s; 330 331 s = splserial(); 332 while ((RD4(sc, SSCOM_UFSTAT) & sc->sc_conf->txfull) != 0) 333 ; 334 335 WR4(sc, SSCOM_UTXH, c & 0xff); 336 337 splx(s); 338 } 339 340 341 static void 342 exynos_uart_cnpollc(dev_t dev, int on) 343 { 344 } 345 346 static void 347 exynos_uart_cnattach(bus_space_tag_t bst, bus_space_handle_t bsh, 348 int ospeed, tcflag_t cflag, const struct exynos_uart_config *conf) 349 { 350 struct exynos_uart_softc *sc = &exynos_uart_cnsc; 351 352 cn_tab = &exynos_uart_consdev; 353 cn_init_magic(&exynos_uart_cnm_state); 354 cn_set_magic("\047\001"); 355 356 sc->sc_bst = bst; 357 sc->sc_bsh = bsh; 358 sc->sc_ospeed = ospeed; 359 sc->sc_cflag = cflag; 360 sc->sc_conf = conf; 361 } 362 363 static int 364 exynos_uart_open(dev_t dev, int flag, int mode, lwp_t *l) 365 { 366 struct exynos_uart_softc *sc = 367 device_lookup_private(&exuart_cd, minor(dev)); 368 struct tty *tp = sc->sc_tty; 369 uint32_t ucon; 370 371 if (kauth_authorize_device_tty(l->l_cred, 372 KAUTH_DEVICE_TTY_OPEN, tp) != 0) { 373 return EBUSY; 374 } 375 376 mutex_enter(&sc->sc_lock); 377 378 if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) { 379 tp->t_dev = dev; 380 ttychars(tp); 381 tp->t_iflag = TTYDEF_IFLAG; 382 tp->t_oflag = TTYDEF_OFLAG; 383 tp->t_lflag = TTYDEF_LFLAG; 384 if (sc->sc_console) { 385 tp->t_ispeed = tp->t_ospeed = exynos_uart_cnsc.sc_ospeed; 386 tp->t_cflag = exynos_uart_cnsc.sc_cflag; 387 } else { 388 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 389 tp->t_cflag = TTYDEF_CFLAG; 390 } 391 ttsetwater(tp); 392 } 393 tp->t_state |= TS_CARR_ON; 394 395 /* Enable RX and error interrupts */ 396 switch (sc->sc_conf->type) { 397 case EXYNOS_UART_SAMSUNG: 398 WR4(sc, SSCOM_UINTM, ~0u & ~(UINT_RXD|UINT_ERROR)); 399 break; 400 case EXYNOS_UART_APPLE: 401 ucon = RD4(sc, SSCOM_UCON); 402 ucon |= UCON_S5L_RXTHRESH | UCON_S5L_RX_TIMEOUT; 403 WR4(sc, SSCOM_UCON, ucon); 404 break; 405 } 406 407 mutex_exit(&sc->sc_lock); 408 409 return tp->t_linesw->l_open(dev, tp); 410 } 411 412 static int 413 exynos_uart_close(dev_t dev, int flag, int mode, lwp_t *l) 414 { 415 struct exynos_uart_softc *sc = 416 device_lookup_private(&exuart_cd, minor(dev)); 417 struct tty *tp = sc->sc_tty; 418 uint32_t ucon; 419 420 mutex_enter(&sc->sc_lock); 421 422 tp->t_linesw->l_close(tp, flag); 423 ttyclose(tp); 424 425 /* Disable interrupts */ 426 switch (sc->sc_conf->type) { 427 case EXYNOS_UART_SAMSUNG: 428 WR4(sc, SSCOM_UINTM, ~0u); 429 break; 430 case EXYNOS_UART_APPLE: 431 ucon = RD4(sc, SSCOM_UCON); 432 ucon &= ~(UCON_S5L_RXTHRESH | UCON_S5L_RX_TIMEOUT); 433 WR4(sc, SSCOM_UCON, ucon); 434 break; 435 } 436 437 mutex_exit(&sc->sc_lock); 438 439 return 0; 440 } 441 442 static int 443 exynos_uart_read(dev_t dev, struct uio *uio, int flag) 444 { 445 struct exynos_uart_softc *sc = 446 device_lookup_private(&exuart_cd, minor(dev)); 447 struct tty *tp = sc->sc_tty; 448 449 return tp->t_linesw->l_read(tp, uio, flag); 450 } 451 452 static int 453 exynos_uart_write(dev_t dev, struct uio *uio, int flag) 454 { 455 struct exynos_uart_softc *sc = 456 device_lookup_private(&exuart_cd, minor(dev)); 457 struct tty *tp = sc->sc_tty; 458 459 return tp->t_linesw->l_write(tp, uio, flag); 460 } 461 462 static int 463 exynos_uart_poll(dev_t dev, int events, lwp_t *l) 464 { 465 struct exynos_uart_softc *sc = 466 device_lookup_private(&exuart_cd, minor(dev)); 467 struct tty *tp = sc->sc_tty; 468 469 return tp->t_linesw->l_poll(tp, events, l); 470 } 471 472 static int 473 exynos_uart_ioctl(dev_t dev, u_long cmd, void *data, int flag, lwp_t *l) 474 { 475 struct exynos_uart_softc *sc = 476 device_lookup_private(&exuart_cd, minor(dev)); 477 struct tty *tp = sc->sc_tty; 478 int error; 479 480 error = tp->t_linesw->l_ioctl(tp, cmd, data, flag, l); 481 if (error != EPASSTHROUGH) 482 return error; 483 484 return ttioctl(tp, cmd, data, flag, l); 485 } 486 487 static struct tty * 488 exynos_uart_tty(dev_t dev) 489 { 490 struct exynos_uart_softc *sc = 491 device_lookup_private(&exuart_cd, minor(dev)); 492 493 return sc->sc_tty; 494 } 495 496 static void 497 exynos_uart_stop(struct tty *tp, int flag) 498 { 499 } 500 501 static void 502 exynos_uart_start(struct tty *tp) 503 { 504 struct exynos_uart_softc *sc = tp->t_sc; 505 u_char *p = sc->sc_buf; 506 int s, brem; 507 508 s = spltty(); 509 510 if (tp->t_state & (TS_TTSTOP | TS_BUSY | TS_TIMEOUT)) { 511 splx(s); 512 return; 513 } 514 tp->t_state |= TS_BUSY; 515 516 for (brem = q_to_b(&tp->t_outq, sc->sc_buf, sizeof(sc->sc_buf)); 517 brem > 0; 518 brem--, p++) { 519 while ((RD4(sc, SSCOM_UFSTAT) & sc->sc_conf->txfull) != 0) 520 ; 521 522 WR4(sc, SSCOM_UTXH, *p); 523 } 524 525 tp->t_state &= ~TS_BUSY; 526 if (ttypull(tp)) { 527 tp->t_state |= TS_TIMEOUT; 528 callout_schedule(&tp->t_rstrt_ch, 1); 529 } 530 splx(s); 531 } 532 533 static int 534 exynos_uart_param(struct tty *tp, struct termios *t) 535 { 536 struct exynos_uart_softc *sc = tp->t_sc; 537 538 mutex_enter(&sc->sc_lock); 539 540 if (tp->t_cflag != t->c_cflag) { 541 uint32_t ulcon = 0; 542 switch (ISSET(t->c_cflag, CSIZE)) { 543 case CS5: 544 ulcon |= ULCON_LENGTH_5; 545 break; 546 case CS6: 547 ulcon |= ULCON_LENGTH_6; 548 break; 549 case CS7: 550 ulcon |= ULCON_LENGTH_7; 551 break; 552 case CS8: 553 ulcon |= ULCON_LENGTH_8; 554 break; 555 } 556 switch (ISSET(t->c_cflag, PARENB|PARODD)) { 557 case PARENB|PARODD: 558 ulcon |= ULCON_PARITY_ODD; 559 break; 560 case PARENB: 561 ulcon |= ULCON_PARITY_EVEN; 562 break; 563 default: 564 ulcon |= ULCON_PARITY_NONE; 565 break; 566 } 567 if (ISSET(t->c_cflag, CSTOPB)) 568 ulcon |= ULCON_STOP; 569 WR4(sc, SSCOM_ULCON, ulcon); 570 } 571 572 if (tp->t_ospeed != t->c_ospeed) { 573 const uint32_t ubrdiv = (sc->sc_freq / 16) / t->c_ospeed - 1; 574 WR4(sc, SSCOM_UBRDIV, ubrdiv); 575 } 576 577 tp->t_ispeed = t->c_ispeed; 578 tp->t_ospeed = t->c_ospeed; 579 tp->t_cflag = t->c_cflag; 580 581 mutex_exit(&sc->sc_lock); 582 583 return 0; 584 } 585 586 static int 587 exynos_uart_intr(void *priv) 588 { 589 struct exynos_uart_softc *sc = priv; 590 struct tty *tp = sc->sc_tty; 591 uint32_t ack, uerstat, ufstat, c; 592 593 mutex_enter(&sc->sc_lock); 594 595 if (sc->sc_conf->type == EXYNOS_UART_APPLE) { 596 ack = RD4(sc, SSCOM_UTRSTAT); 597 } else { 598 ack = RD4(sc, SSCOM_UINTP); 599 } 600 601 for (;;) { 602 int cn_trapped = 0; 603 604 uerstat = RD4(sc, SSCOM_UERSTAT); 605 if (uerstat & UERSTAT_BREAK) { 606 cn_check_magic(tp->t_dev, CNC_BREAK, 607 exynos_uart_cnm_state); 608 if (cn_trapped) 609 continue; 610 } 611 612 ufstat = RD4(sc, SSCOM_UFSTAT); 613 if (__SHIFTOUT(ufstat, sc->sc_conf->rxcount) == 0) { 614 break; 615 } 616 617 c = RD4(sc, SSCOM_URXH); 618 cn_check_magic(tp->t_dev, c & 0xff, exynos_uart_cnm_state); 619 if (cn_trapped) 620 continue; 621 tp->t_linesw->l_rint(c & 0xff, tp); 622 } 623 624 if (sc->sc_conf->type == EXYNOS_UART_APPLE) { 625 WR4(sc, SSCOM_UTRSTAT, ack); 626 } else { 627 WR4(sc, SSCOM_UINTP, ack); 628 } 629 630 mutex_exit(&sc->sc_lock); 631 632 return 1; 633 } 634 635 /* 636 * Console support 637 */ 638 639 static int 640 exynos_uart_console_match(int phandle) 641 { 642 return of_compatible_match(phandle, compat_data); 643 } 644 645 static void 646 exynos_uart_console_consinit(struct fdt_attach_args *faa, u_int uart_freq) 647 { 648 const int phandle = faa->faa_phandle; 649 bus_space_tag_t bst = faa->faa_bst; 650 bus_space_handle_t bsh; 651 bus_addr_t addr; 652 bus_size_t size; 653 tcflag_t flags; 654 int speed; 655 const struct exynos_uart_config *conf; 656 657 speed = fdtbus_get_stdout_speed(); 658 if (speed < 0) 659 speed = 115200; /* default */ 660 flags = fdtbus_get_stdout_flags(); 661 conf = of_compatible_lookup(phandle, compat_data)->data; 662 663 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) 664 panic("exynos_uart: couldn't get registers"); 665 if (bus_space_map(bst, addr, size, 0, &bsh) != 0) 666 panic("exynos_uart: couldn't map registers"); 667 668 exynos_uart_consaddr = addr; 669 670 exynos_uart_cnattach(bst, bsh, speed, flags, conf); 671 } 672 673 static const struct fdt_console exynos_uart_console = { 674 .match = exynos_uart_console_match, 675 .consinit = exynos_uart_console_consinit, 676 }; 677 678 FDT_CONSOLE(exynos_uart, &exynos_uart_console); 679
Indexes created Sun Nov 08 00:25:27 UTC 2026