1 /* $NetBSD: pgtimer.c,v 1.2 2026/08/07 23:37:46 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2025 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: pgtimer.c,v 1.2 2026/08/07 23:37:46 thorpej Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 41 #include <machine/clockvar.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 struct pgtimer_softc { 46 device_t sc_dev; 47 bus_space_tag_t sc_st; 48 bus_space_handle_t sc_sh; 49 uint32_t sc_reg_shift; 50 void *sc_ih; 51 uint32_t sc_freq; 52 struct clock_if sc_clkif; 53 }; 54 55 #define TIMER_CSR 0 56 #define CSR_ENAB __BIT(0) 57 #define CSR_IPEND __BIT(1) 58 #define TIMER_VAL 1 59 60 #define REG_OFF(sc, r) ((r) << (sc)->sc_reg_shift) 61 62 #define REG_READ(sc, r) \ 63 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, REG_OFF((sc), (r))) 64 #define REG_WRITE(sc, r, v) \ 65 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, REG_OFF((sc), (r)), (v)) 66 67 static const struct device_compatible_entry compat_data[] = { 68 { .compat = "pg68k,ioctl010-timer" }, 69 DEVICE_COMPAT_EOL 70 }; 71 72 static uint32_t 73 pgtimer_us_to_ticks(struct pgtimer_softc *sc, unsigned int interval_us) 74 { 75 const uint32_t tick_ns = 1000000000 / sc->sc_freq; 76 const uint64_t interval_ns = interval_us * 1000; 77 const uint64_t ticks = interval_ns / tick_ns; 78 79 if (ticks == 0 || ticks > 0xffff) { 80 panic("%s: impossible interval %u us (ticks=%llu)", __func__, 81 interval_us, ticks); 82 } 83 84 return (uint32_t)ticks; 85 } 86 87 static int 88 pgtimer_init(struct clock_if *clk, int (*intrfunc)(void *)) 89 { 90 struct pgtimer_softc *sc = 91 container_of(clk, struct pgtimer_softc, sc_clkif); 92 int phandle = devhandle_to_of(device_handle(sc->sc_dev)); 93 char intrstr[128]; 94 95 KASSERT(sc->sc_dev == clk->clk_dev); 96 97 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 98 aprint_error_dev(sc->sc_dev, "failed to decode interrupt\n"); 99 return ENXIO; 100 } 101 102 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_SCHED, 103 FDT_INTR_MPSAFE, intrfunc, NULL, device_xname(sc->sc_dev)); 104 if (sc->sc_ih == NULL) { 105 aprint_error_dev(sc->sc_dev, 106 "failed to establish interrupt at %s\n", intrstr); 107 return ENXIO; 108 } 109 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 110 111 return 0; 112 } 113 114 static int 115 pgtimer_arm(struct clock_if *clk, unsigned int interval_us) 116 { 117 struct pgtimer_softc *sc = 118 container_of(clk, struct pgtimer_softc, sc_clkif); 119 const uint32_t ticks = pgtimer_us_to_ticks(sc, interval_us); 120 121 /* 122 * Changing the counter reload value implicitly disables the 123 * timer. The reload value is set by writing the high byte 124 * followed by the load byte to the Value register. The reload 125 * value is unpredictable until both bytes have been written. 126 */ 127 REG_WRITE(sc, TIMER_VAL, (uint8_t)(ticks >> 8)); 128 REG_WRITE(sc, TIMER_VAL, (uint8_t)ticks); 129 REG_WRITE(sc, TIMER_CSR, CSR_ENAB); 130 131 return 0; 132 } 133 134 static void 135 pgtimer_intr(struct clock_if *clk) 136 { 137 struct pgtimer_softc *sc = 138 container_of(clk, struct pgtimer_softc, sc_clkif); 139 140 /* Clear interrupt condition. */ 141 REG_READ(sc, TIMER_CSR); 142 143 /* Timer auto-reloads. */ 144 } 145 146 static void 147 pgtimer_disarm(struct clock_if *clk) 148 { 149 struct pgtimer_softc *sc = 150 container_of(clk, struct pgtimer_softc, sc_clkif); 151 152 REG_WRITE(sc, TIMER_CSR, 0); 153 } 154 155 static int 156 pgtimer_match(device_t parent, cfdata_t cf, void *aux) 157 { 158 struct fdt_attach_args * const faa = aux; 159 160 return of_compatible_match(faa->faa_phandle, compat_data); 161 } 162 163 static void 164 pgtimer_attach(device_t parent, device_t self, void *aux) 165 { 166 struct pgtimer_softc * const sc = device_private(self); 167 struct fdt_attach_args * const faa = aux; 168 const int phandle = faa->faa_phandle; 169 bus_addr_t addr; 170 bus_size_t size; 171 struct clk *clk; 172 uint32_t clk_div; 173 int error; 174 175 sc->sc_dev = self; 176 sc->sc_st = faa->faa_bst; 177 178 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 179 aprint_error(": couldn't get registers\n"); 180 return; 181 } 182 183 if (of_getprop_uint32(phandle, "reg-shift", &sc->sc_reg_shift)) { 184 /* missing or bad reg-shift property, assume 0 */ 185 sc->sc_reg_shift = 0; 186 } 187 188 error = bus_space_map(sc->sc_st, addr, size, 0, &sc->sc_sh); 189 if (error) { 190 aprint_error(": couldn't map registers (error=%d)\n", error); 191 return; 192 } 193 194 /* Make sure the timer is disabled. */ 195 REG_WRITE(sc, TIMER_CSR, 0); 196 197 clk = fdtbus_clock_get_index(phandle, 0); 198 if (clk == NULL) { 199 aprint_error(": couldn't get clock handle\n"); 200 return; 201 } 202 203 /* 204 * The input to the I/O controller is the main system clock, 205 * which the timer divides itself internally. Firmware will 206 * provide this value in the device tree. 207 */ 208 if (of_getprop_uint32(phandle, "clock-div", &clk_div)) { 209 /* default to divide-by-16 */ 210 clk_div = 16; 211 } 212 213 sc->sc_freq = clk_get_rate(clk) / clk_div; 214 215 aprint_naive("\n"); 216 aprint_normal(": frequency %u Hz\n", sc->sc_freq); 217 218 sc->sc_clkif.clk_dev = self; 219 sc->sc_clkif.clk_init = pgtimer_init; 220 sc->sc_clkif.clk_arm = pgtimer_arm; 221 sc->sc_clkif.clk_intr = pgtimer_intr; 222 sc->sc_clkif.clk_disarm = pgtimer_disarm; 223 clock_attach(&sc->sc_clkif); 224 } 225 226 CFATTACH_DECL_NEW(pgtimer, sizeof(struct pgtimer_softc), 227 pgtimer_match, pgtimer_attach, NULL, NULL); 228
Indexes created Sun Oct 25 00:26:45 UTC 2026