Home | History | Annotate | Download | only in pmap
History log of /src/sys/uvm/pmap/pmap_tlb.h
RevisionDateAuthorComments
 1.17  06-Oct-2023  skrll Support CPUs that might not have ASIDs in the common pmap.
 1.16  26-Oct-2022  skrll MI PMAP hardware page table walker support.

This is based on code given to me by Matt Thomas a long time ago with
many updates and bugs fixes from me.
 1.15  19-Aug-2020  skrll KNF. Add some whitespace to the TLBINV_MAP macro and tlb_invalidate_op
enum.
 1.14  01-Aug-2020  skrll Provide a TLBINFO_OWNED
 1.13  19-Feb-2018  jdolecek convert to use actual __BITMAP_*() macros from <sys/bitops.h>, and make
it possible to override the ASID bitmap length; default to 256 ASIDs as before

XXX NFCI; compile tested only on evbpcc and evbmips, unfortunately didn't
find any combination of port using the MI pmap_tlb.c and working in QEMU
 1.12  19-Feb-2018  jdolecek make it possible to not use the icache evcnts
 1.11  24-Jun-2017  skrll Multiple inclusion protection define consistency
 1.10  26-May-2017  skrll Whitespace
 1.9  11-Jul-2016  matt Changes so that MIPS can use the common pmap.
Change/augment the virtual cache alias callbacks.
 1.8  02-Apr-2015  matt include <sys/evcnt.h>
 1.7  05-Jan-2015  nonaka Use PMAP_TLB_MAX instead of MAXCPUS.
 1.6  03-Apr-2014  matt branches: 1.6.4; 1.6.8; 1.6.10;
Change cpu_tlb_info definition based on PMAP_TLB_MAX instead of MULTIPROCESSOR
 1.5  30-Mar-2014  matt Allow this to handle H/W tlbs. Some ARM allow for a cheap way to flush all
entries using an ASID from the TLB. Add support for taking advantage of it.
Most ARMs don't have an easy way to find out what's in the TLB so make
record_asids can just say all ASIDs are in use. Fix some off by 1 errors.
 1.4  18-Mar-2014  riastradh Merge riastradh-drm2 to HEAD.
 1.3  22-Jul-2013  matt branches: 1.3.2;
If not MULTIPROCESSOR, just make cpu_tlb_info(ci) return &pmap_tlb0_info
 1.2  17-Jul-2013  matt Make this kcpuset_t instead of the private __cpuset_t
Add improvements for single TLB implementation (PPC, ARM).
 1.1  02-Jul-2013  matt branches: 1.1.2;
Split tlb related stuff into pmap_tlb.h so that can be used for ASID mgmt
for non-soft TLB pmaps.
 1.1.2.1  23-Jul-2013  riastradh sync with HEAD
 1.3.2.3  18-May-2014  rmind sync with head
 1.3.2.2  28-Aug-2013  rmind sync with head
 1.3.2.1  22-Jul-2013  rmind file pmap_tlb.h was added on branch rmind-smpnet on 2013-08-28 23:59:38 +0000
 1.6.10.3  28-Aug-2017  skrll Sync with HEAD
 1.6.10.2  05-Oct-2016  skrll Sync with HEAD
 1.6.10.1  06-Apr-2015  skrll Sync with HEAD
 1.6.8.3  03-Dec-2017  jdolecek update from HEAD
 1.6.8.2  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.6.8.1  03-Apr-2014  tls file pmap_tlb.h was added on branch tls-maxphys on 2014-08-20 00:04:45 +0000
 1.6.4.2  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.6.4.1  03-Apr-2014  yamt file pmap_tlb.h was added on branch yamt-pagecache on 2014-05-22 11:41:19 +0000

RSS XML Feed