| History log of /src/tests/kernel/arch/hppa/execregs.c |
| Revision | | Date | Author | Comments |
| 1.2 |
| 28-Feb-2025 |
riastradh | t_execregs: Test some more registers on hppa.
Looks like we're missing zeroing of floating-point registers too, as
well as the carry/borrow and divide step correction bits in the
semi-secret PSW register.
Unfortunately, while investigating this, I discovered that qemu's
hppa implementation doesn't implement fpu traps even if the fpu is
disabled (relevant bits of CR 10 `CCR', Coprocessor Control Register,
are cleared), which breaks fpu switching on NetBSD. So I can't test
properly this myself. We should maybe just change NetBSD from lazy
fpu switching to eager fpu switching anyway to thwart Spectre-class
attacks if there's any hppa hardware out there that does speculative
execution.
PR kern/59084: exec/spawn leaks register content
|
| 1.1 |
| 27-Feb-2025 |
riastradh | Test whether exec/spawn will zero registers.
Currently implemented only for a handful of architectures; should
extend this to all the others, and extend as appropriate if we find
more register content is worth testing (like maybe vector registers,
but they are managed differently anyway and less likely to leak).
VAX test contributed (and tested) by Kalvis Duckmanton, with some
tweaks by me; the others written and tested by me. IA64 skipped,
even though I suspect it _would_ leak if the kernel code ran as is,
because I have no way to test it.
PR kern/59084: exec/spawn leaks register content
|
