Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.

- If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors
can take TSC/core crystal clock ratio but core crystal clock frequency
can't be taken. Intel SDM give us the values for some processors.
- It also required to change lapic_per_second to make LAPIC timer correctly.
- Add new file x86/x86/identcpu_subr.c to share common subroutines between
kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c
will be moved to this file in future.
- Add comment to clarify.

branches: 1.8.8; 1.8.16; 1.8.18;
Define _KERNTYPES for things that need it.

.include <bsd.own.mk> to get MACHINE_CPU

Add arm support for cpuctl identify

branches: 1.5.6; 1.5.12;
Allow WARNS=4 after Christos' fix sys/cdefs.h

Enable WARNS=4 by default, except for:
cpuctl dumplfs hprop ipf iprop-log kadmin kcm kdc kdigest
kimpersonate kstash ktutil makefs ndbootd ntp pppd quot
racoon racoonctl rtadvd sntp sup tcpdchk tcpdmatch tcpdump
traceroute traceroute6 user veriexecgen wsmoused zic
(Mostly third-party applications)

branches: 1.3.2;
Remove 3rd buggy copy of this function and use snprintb(3) instead.
No need to allocate MAXPATHLEN buffers anymore.

branches: 1.2.6;
PR port-amd64/37461 x86 cpu dmesg output is noisy

Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.

branches: 1.1.8; 1.1.10;
Add cpuctl(8). For now this is not much more than a toy for debugging and
benchmarking that allows taking CPUs online/offline.

Remove 3rd buggy copy of this function and use snprintb(3) instead.
No need to allocate MAXPATHLEN buffers anymore.

branches: 1.1.4; 1.1.8;
PR port-amd64/37461 x86 cpu dmesg output is noisy

Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.

cpuctl.8: fix grammar in a sentence

cpuctl(8): note that AMD updates need to be applied on all CPUs at once

Note that checking dmesg(8) after problems might be helpful.
Sort commands.
Bump date.

Unless -v is given, ignore EEXIST errors from the IOC_CPU_UCODE_APPLY ioctl()
used to implement "cpuctl ucode N", which indicates that the microcode
to be loaded already exists in the CPU, and as such, isn't really a
very interesting "error".

branches: 1.20.2; 1.20.10;
cpuctl.8: minor fixes

cpuctl.8: update the URL for AMD microcode, the previous site listed is
apparently defunct.

branches: 1.18.4;
note the default path for ucode updates can be found in sysctl.

branches: 1.17.6;
Sort SEE ALSO.

link back to intrctl(8), it xrefs cpuctl(8)

branches: 1.15.2;
allow most commands to specify more than one cpu. now you can online or
offline (or identify, or intr/nointr) a list of cpus all together.

Bump date. Quote minus with a backslash, for PostScript/PDF output.

Fix manual and usage bug. The ucode command can take [cpuno] argument.

Update URL

Use more common phrasing.

Add verbose flag.
On x86 cpu, cpuctl -v identify dumps the return values of the cpuid
functions. The max levels are taken from CPUID 0 and CPUID 8000_0000.
It's useful for the future CPU.

branches: 1.9.2;
Use Lk macro when dealing with URLs. While here update or remove some
dead URL links. Another part of PR/29238.

branches: 1.8.2;
Sort sections. Uppercase CPU.

Support CPU microcode loading via cpuctl(8).
Implemented and enabled via CPU_UCODE kernel config option
for x86 and Xen Dom0.
Tested on different AMD machines with different
CPU families.

ok wiz@ for the manpages
ok releng@
ok core@ via releng@

branches: 1.6.2;
Bump date for previous. Drop trailing whitespace. Improve formatting.

Add a dumb, mostly Solaris-compatible psrset command. It's missing some
options. Without it there's no easy way to test or use processor sets.

branches: 1.4.2;
PR port-amd64/37461 x86 cpu dmesg output is noisy

Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.

Convert TNF licenses to new 2 clause variant

branches: 1.2.2;
Use cpu index instead of ID for cpuctl; extend listing to provide both
numbers (but now the ID is only informational).

branches: 1.1.8;
Add cpuctl(8). For now this is not much more than a toy for debugging and
benchmarking that allows taking CPUs online/offline.

tabify

cpuctl: be more verbose about problems and diagnosing them

Unless -v is given, ignore EEXIST errors from the IOC_CPU_UCODE_APPLY ioctl()
used to implement "cpuctl ucode N", which indicates that the microcode
to be loaded already exists in the CPU, and as such, isn't really a
very interesting "error".

branches: 1.32.2;
allow "cpuN" as well as "N" to specific a CPU.

update usage to include a change i made from 2015 to allow multiple
CPUs to be operated on at the same time for most commands.

Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.

- If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors
can take TSC/core crystal clock ratio but core crystal clock frequency
can't be taken. Intel SDM give us the values for some processors.
- It also required to change lapic_per_second to make LAPIC timer correctly.
- Add new file x86/x86/identcpu_subr.c to share common subroutines between
kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c
will be moved to this file in future.
- Add comment to clarify.

branches: 1.30.2;
Check the return value of cpuset_set(), to prevent future surprises.

branches: 1.29.4;
implement cpuctl identify for sparc and sparc64.

sparc:
- move enum vactype and struct cacheinfo into cpu.h
- move the cache flags from cpuinfo.flags into CACHEINFO.c_flags
(this allows the new cache_printf_backend() to see them.)
remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA.
- align xmpsg to 64 bytes
- move cache_print() into cache_print.h so it can be shared with
cpuctl. it only depends upon a working printf().
- if found, store the CPU node's "name" into cpu_longname. this
changes the default output to show the local CPU not the
generic CPU family. eg:
cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU
vs the generic "RT620/625" previously shown.
- for each CPU export these things:
- name
- fpuname
- mid
- cloc
- freq
- psr impl and version
- mmu impl, version, and number of contexts
- cacheinfo structure (which changed for the first time ever
with this commit.)

sparc64:
- add a minimal "cacheinfo" structure to export the i/d/e-cache
size and linesize.
- store %ver, cpu node "name" and cacheinfo in cpu_info.
- set cpu_info ver, name and cacheinfo in cpu_attach(), and
export them via sysctl, as well as CPU ID and clock freq

cpuctl:
- add identifycpu_bind() that returns false on !x86 as their
identify routines do not need to run on a particular CPU to
obtain its information, and use it to avoid trying to set
affinity when not needed.
- add sparc and sparc64 cpu identify support using the newly
exported values.

branches: 1.28.8;
allow most commands to specify more than one cpu. now you can online or
offline (or identify, or intr/nointr) a list of cpus all together.

convert getcpuid() to take char* not char**

use stdbool.h

Fix a bug that an unknown command is printed as "(null)".
Reported by Fredrik Pettai.

Fix manual and usage bug. The ucode command can take [cpuno] argument.

branches: 1.23.4;
Add verbose flag.
On x86 cpu, cpuctl -v identify dumps the return values of the cpuid
functions. The max levels are taken from CPUID 0 and CPUID 8000_0000.
It's useful for the future CPU.

Only complain about binding if we have more than 1 cpu. :)
(we always have more than 0).

branches: 1.21.2;
Extend the CPU microcode update framework to support Intel x86 CPUs.
Contrary to the AMD implementation, it doesn't use xcalls to distribute
the update to all CPUs but relies on cpuctl(8) to bind itself to the
right CPU -- to keep it simple and avoid possible problems with
hyperthreading.
Also, it doesn't parse the vendor supplied file to pick the right
part for the present CPU model but relies on userland to prepare
files with specific filenames. I'll commit a pkg for this in a minute
(pkgsrc/sysutils/intel-microcode).
The ioctl interface changed; compatibility is provided (should be
limited to COMPAT_NETBSD6 as soon as this is available).

branches: 1.20.2;
Support CPU microcode loading via cpuctl(8).
Implemented and enabled via CPU_UCODE kernel config option
for x86 and Xen Dom0.
Tested on different AMD machines with different
CPU families.

ok wiz@ for the manpages
ok releng@
ok core@ via releng@

branches: 1.19.2;
Define _PATH_CPUCTL.

Fix wrong err(3) message (no such thing as IOC_CPU_GETINFO).

Add a cs_hwid field to cpustate and use this to store the ci_cpuid (hardware
ID). Report this as the HwID in cpuctl.
OK jruoho@.

static + __dead

Fix -Wsign-compare issue

cpuctl:

- Add interrupt shielding (direct hardware interrupts away from the
specified CPUs). Not documented just yet but will be soon.

- Redo /dev/cpu time_t compat so no kernel changes are needed.

x86:

- Make intr_establish, intr_disestablish safe to use when !cold.

- Distribute hardware interrupts among the CPUs, instead of directing
everything to the boot CPU.

- Add MD code for interrupt sheilding. This works in most cases but there is
a bug where delivery is not accepted by an LAPIC after redistribution. It
also needs re-balancing to make things fair after interrupts are turned
back on for a CPU.

branches: 1.13.2;
cpuctl list: map hardware id after getting state. avoids screwed up display
when ci_cpuid != cpu_index()

redo previous:
check ID in getcpuid(). This way, the other commands (online/offline)
tell the user the real error.

cpu_identify: check ID against number of processors.
Fix for PR/39955.

branches: 1.10.2;
Cosmetic change to previous.

Don't map cpu index to hardware id.

- Add general cpuset macros.
- Use kcpuset name for kernel-only functions.
- Use cpuid_t to specify CPU ID.
- Unify all cpuset users.

API is expected to be stable now.

Sync with the latest cpuset changes.

Clarify output of 'id' column.

branches: 1.5.2;
PR port-amd64/37461 x86 cpu dmesg output is noisy

Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.

Remove clause 3 and 4 from TNF licenses

branches: 1.3.2;
Use cpu index instead of ID for cpuctl; extend listing to provide both
numbers (but now the ID is only informational).

improve usage()

branches: 1.1.2; 1.1.6;
Add cpuctl(8). For now this is not much more than a toy for debugging and
benchmarking that allows taking CPUs online/offline.

Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.

- If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors
can take TSC/core crystal clock ratio but core crystal clock frequency
can't be taken. Intel SDM give us the values for some processors.
- It also required to change lapic_per_second to make LAPIC timer correctly.
- Add new file x86/x86/identcpu_subr.c to share common subroutines between
kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c
will be moved to this file in future.
- Add comment to clarify.

branches: 1.6.4; 1.6.6;
implement cpuctl identify for sparc and sparc64.

sparc:
- move enum vactype and struct cacheinfo into cpu.h
- move the cache flags from cpuinfo.flags into CACHEINFO.c_flags
(this allows the new cache_printf_backend() to see them.)
remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA.
- align xmpsg to 64 bytes
- move cache_print() into cache_print.h so it can be shared with
cpuctl. it only depends upon a working printf().
- if found, store the CPU node's "name" into cpu_longname. this
changes the default output to show the local CPU not the
generic CPU family. eg:
cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU
vs the generic "RT620/625" previously shown.
- for each CPU export these things:
- name
- fpuname
- mid
- cloc
- freq
- psr impl and version
- mmu impl, version, and number of contexts
- cacheinfo structure (which changed for the first time ever
with this commit.)

sparc64:
- add a minimal "cacheinfo" structure to export the i/d/e-cache
size and linesize.
- store %ver, cpu node "name" and cacheinfo in cpu_info.
- set cpu_info ver, name and cacheinfo in cpu_attach(), and
export them via sysctl, as well as CPU ID and clock freq

cpuctl:
- add identifycpu_bind() that returns false on !x86 as their
identify routines do not need to run on a particular CPU to
obtain its information, and use it to avoid trying to set
affinity when not needed.
- add sparc and sparc64 cpu identify support using the newly
exported values.

branches: 1.5.18;
Add verbose flag.
On x86 cpu, cpuctl -v identify dumps the return values of the cpuid
functions. The max levels are taken from CPUID 0 and CPUID 8000_0000.
It's useful for the future CPU.

branches: 1.4.2;
Extend the CPU microcode update framework to support Intel x86 CPUs.
Contrary to the AMD implementation, it doesn't use xcalls to distribute
the update to all CPUs but relies on cpuctl(8) to bind itself to the
right CPU -- to keep it simple and avoid possible problems with
hyperthreading.
Also, it doesn't parse the vendor supplied file to pick the right
part for the present CPU model but relies on userland to prepare
files with specific filenames. I'll commit a pkg for this in a minute
(pkgsrc/sysutils/intel-microcode).
The ioctl interface changed; compatibility is provided (should be
limited to COMPAT_NETBSD6 as soon as this is available).

Add __printflike attribution to use vprintf and friends with an argument
as format string.

branches: 1.2.8; 1.2.10;
Remove 3rd buggy copy of this function and use snprintb(3) instead.
No need to allocate MAXPATHLEN buffers anymore.

branches: 1.1.4; 1.1.8;
PR port-amd64/37461 x86 cpu dmesg output is noisy

Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.

CPU ID strings for Arm Cortex-A710, Neoverse V1, Neoverse N2, and Fujitsu A64FX

add Ampere 1 and 1A

branches: 1.23.2;
Remove ryo@'s mail addresses.

MPIDR is 64bits. Without this AFF3 would always be zero.

Spotted by Cyprien.

branches: 1.21.2;
add CPU_ID_APPLE_M1_ICESTORM and CPU_ID_APPLE_M1_FIRESTORM.

sync cpuids[] to sys/arch/aarch64/aarch64/cpu.c r1.69

display the raw value of each field when -v specified

fix typo

Added more field definitions for ARMv8.x system registers

macroify. NFC.

fix ID_AA64ISAR0_EL1.ATOMIC field definition

Teach cpuctl(8) about some additional aarch64 feature bits.

(Descriptions for CSV3 and CSV2 are not very good, but the blurbs in
the arm arm are an entire paragraph long each. Please fix if you have
a conciser summary!)

branches: 1.14.2;
ID_AA64PFR0_EL1.GIC=0 means that the CPU interface system registers are
not implemented. This does not necessarily mean that there is no GIC in the
system, as GICv2 uses MMIO instead of system registers for the CPU
interface.

While here, add description for GIC=3, which means that the v4.1 system
register interface is supported.

sync cpuids[] of sys/arch/aarch64/aarch64/cpu.c r1.43

Report half-precision FP and SIMD support

(cpuctl/aarch64) Add some more aa64isar0_eli1 flags.

show clidr_el1 and ctr_el0.

Teach cpuctl(8) about ARMv8.5-RNG RNDR/RNDRRS support.

More identification.

add cortex A-76 detection.

Fix mvfr0.fptrap = 0 description

- show detail of debug feature register (ID_AA64DFR0_EL1)
- print raw value of registers when verbose flag is set.
- keep forward compatibility. read kernel's aarch64_sysctl_cpu_id, but avoid unknown system registers.

Add ThunderX IDs

rewrite the CPU identification on arm64:

- publish per-cpu data
- publish a whole bunch of info in struct aarch64_sysctl_cpu_id
instead of various individual nodes (there are 16 total.)
- add MIDR extractor bits
- define ARMv8.2-A id_aa64mmfr2_el1 and id_aa64zfr0_el1 regs,
but avoid using them until we make sure they exist. (these
members are added to aarch64_sysctl_cpu_id to avoid future
compat issues.)

the arm32 and aarch32 version of these need to be adjusted as
well (and aarch32 data published at all.) still trying to
work out how to make the same userland binary running on a
real arm32 or an aarch32 system can work sanely here.

ok ryo@.

branches: 1.2.2; 1.2.4;
TGran64 indication was actually the opposite

add aarch64 support for cpuctl identify.

Simplify previous, pointed out by kre@

Make cpuctl identify print something for old arm where the kernel does
not provide the required data.

branches: 1.6.4;
s/blity/bility/ in various words, mainly in comments.

auxilary -> auxiliary

trailing whitespace

- enlarge buffer to avoid snprintf() truncation

branches: 1.2.4;
implement cpuctl identify for sparc and sparc64.

sparc:
- move enum vactype and struct cacheinfo into cpu.h
- move the cache flags from cpuinfo.flags into CACHEINFO.c_flags
(this allows the new cache_printf_backend() to see them.)
remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA.
- align xmpsg to 64 bytes
- move cache_print() into cache_print.h so it can be shared with
cpuctl. it only depends upon a working printf().
- if found, store the CPU node's "name" into cpu_longname. this
changes the default output to show the local CPU not the
generic CPU family. eg:
cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU
vs the generic "RT620/625" previously shown.
- for each CPU export these things:
- name
- fpuname
- mid
- cloc
- freq
- psr impl and version
- mmu impl, version, and number of contexts
- cacheinfo structure (which changed for the first time ever
with this commit.)

sparc64:
- add a minimal "cacheinfo" structure to export the i/d/e-cache
size and linesize.
- store %ver, cpu node "name" and cacheinfo in cpu_info.
- set cpu_info ver, name and cacheinfo in cpu_attach(), and
export them via sysctl, as well as CPU ID and clock freq

cpuctl:
- add identifycpu_bind() that returns false on !x86 as their
identify routines do not need to run on a particular CPU to
obtain its information, and use it to avoid trying to set
affinity when not needed.
- add sparc and sparc64 cpu identify support using the newly
exported values.

branches: 1.1.4; 1.1.10;
Add arm support for cpuctl identify

Move some common functions into x86/identcpu_subr.c. No functional change.

Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.

- If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors
can take TSC/core crystal clock ratio but core crystal clock frequency
can't be taken. Intel SDM give us the values for some processors.
- It also required to change lapic_per_second to make LAPIC timer correctly.
- Add new file x86/x86/identcpu_subr.c to share common subroutines between
kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c
will be moved to this file in future.
- Add comment to clarify.

branches: 1.4.2;
All MSRs can only be read at privilege level 0. The exact APIC ID cannot
be determined on some AMD CPUs.

Get CPU topology data for AMD processors.

branches: 1.2.2; 1.2.6; 1.2.14; 1.2.28; 1.2.36;
Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually identifies
the cpu is output first.

Change the i386 asm x86_identify() so it returns a value instead of writing
into global data.
Fix a stack alignment fubar that would cause a crash on a cirix 486.
Refactor identify code to common setup for normal identify and ucode
identify - which was missing a memset().

All MSRs can only be read at privilege level 0. The exact APIC ID cannot
be determined on some AMD CPUs.

Fix copy&paste error, the function is named rdmsr().

Found by kre@

Get CPU topology data for AMD processors.

branches: 1.4.16;
xgetbv expects XCR0 to be speficied in %ecx, don't leave %ecx undefined

branches: 1.3.8;
Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually identifies
the cpu is output first.

Change the i386 asm x86_identify() so it returns a value instead of writing
into global data.
Fix a stack alignment fubar that would cause a crash on a cirix 486.
Refactor identify code to common setup for normal identify and ucode
identify - which was missing a memset().

branches: 1.1.4; 1.1.6; 1.1.24; 1.1.28;
PR port-amd64/37461 x86 cpu dmesg output is noisy

Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.

s/padloack/padlock/ in padlock features line.

cpuctl(x86): CPUID_AMDEXT2_L2TLBSIZEX32 also affects 1GB TLB size.

cpuctl(x86): Calculate L2 TLB size using with CPUID_AMDEXT2_L2TLBSIZEX32.

It's required to calculate L2 TLB size correctly on Zen5.

cpuctl(8): Print AMD's hetero workload classification.

branches: 1.144.2;
cpuctl: fix i386 bit descriptions for CPUID_SEF_FLAGS1

warning: non-printing character '\31' in description
'BUS_LOCK_DETECT""b\31' [363]

Fix various typos in comments, log messages and documentation.

Add Meteor Lake and Emerald Rapids.

tabify

cpuctl: be more verbose about problems and diagnosing them

Sort by number. No functional change.

Add Alder Lake-N.

CPU model 0x5a is not Atom E3500 but Atom Z3500.

Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.

Add Raptor Lake and Sapphire Rapids.

Print cpuid 7 sub-leaf 1 %ebx, %edx and sub-leaf 2 %edx.

branches: 1.133.2;
s/features 2/features2/

s/Instruction-Based Sampling/IBS/

Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug.

Add CPUID Fn8000_0021 AMD Extended Features Identification 2.

Print AMD RAS features and Instruction-Based Sampling features.

Modify output of CPUID Fn0000000a.

old:
cpu0: Perfmon-eax 0x8300805<VERSION=0x5,GPCounter=0x8,GPBitwidth=0x30>
cpu0: Perfmon-eax 0x8300805<Vectorlen=0x8>
cpu0: Perfmon-edx 0x8604<FixedFunc=0x4,FFBitwidth=0x30,ANYTHREADDEPR>

new:
cpu0: Perfmon: Ver. 5
cpu0: Perfmon: General: bitwidth 48, 8 counters
cpu0: Perfmon: General: avail 0xff<CORECYCL,INST,REFCYCL,LLCREF,LLCMISS,BRINST>
cpu0: Perfmon: General: avail 0xff<BRMISPR,TOPDOWNSLOT>
cpu0: Perfmon: Fixed: bitwidth 48, 4 counters
cpu0: Perfmon: Fixed: avail 0xf<INST,CLK_CORETHREAD,CLK_REF_TSC,TOPDOWNSLOT>

Decode Intel Hybrid Information Enumeration (CPUID Fn0000_001a).

Remove debug code and simplify. No functional change.

Add Alder Lake, Rocket Lake and Sapphire Rapids. From the latest Intel SDM.

Print 1GB TLB entry at the same leve's line.

Example:
before:
cpu0: ITLB: 128 4KB entries 8-way, 2M/4M: 8 entries
cpu0: DTLB: 64 4KB entries 4-way
cpu0: L2 STLB: 4K/2M: 1024 entries
cpu0: L1 1GB page DTLB: 4 1GB entries 4-way

after:
cpu0: ITLB: 128 4KB entries 8-way, 2M/4M: 8 entries
cpu0: DTLB: 64 4KB entries 4-way, 4 1GB entries 4-way
cpu0: L2 STLB: 4K/2M: 1024 entries

decode SMT parts for AMD family >= 0x17, not just 0x17.

now zen3 systems are properly identified by cpu topology for the
scheduler and cpuctl identify.

Move some common functions into x86/identcpu_subr.c. No functional change.

Improve variable sized TLB's output.

- Fix a bug that STLB is printed as DTLB.
- If a TLB is variable sized, print the max size instead of error message.
XXX This is temporary solution.

Add Load Only TLB and Store Only TLB.

Fix a bug that some TLB related lines were not printed.

Add ':' for readability.

Add 0x96(Elkhart Lake) and 0x9c(Jasper Lake).
Not listed in SDM but listed in those spec update documents.

0x6a and 0x6c are 3rd gen Xeon Scalable (Ice Lake).

- Print CPUID 0x8000008 %ebx on Intel, too. Intel now supports WBNOINVD.
- Print CPUID leaf 7 subleaf 1.

x86: fix several CPUID flags

- Rename: CPUID_PN -> CPUID_PSN
CPUID_CFLUSH -> CPUID_CLFSH
CPUID_SBF -> CPUID_PBE
CPUID_LZCNT -> CPUID_ABM
CPUID_P1GB -> CPUID_PAGE1GB
CPUID2_PCLMUL -> CPUID2_PCLMULQDQ
CPUID2_CID -> CPUID2_CNXTID
CPUID2_xTPR -> CPUID2_XTPR
CPUID2_AES -> CPUID2_AESNI
To match the x86 specification and the other OSes.

- Remove: CPUID_B10, CPUID_B20, CPUID_IA64. They do not exist.

Add 0xa5 and 0xa6 for Comet Lake.

Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.

- If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors
can take TSC/core crystal clock ratio but core crystal clock frequency
can't be taken. Intel SDM give us the values for some processors.
- It also required to change lapic_per_second to make LAPIC timer correctly.
- Add new file x86/x86/identcpu_subr.c to share common subroutines between
kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c
will be moved to this file in future.
- Add comment to clarify.

No functional change:
- Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
ci_max_ext_cpuid to match x86/include/cpu.h though cpuctl/arch/i386.c added
them first.
- Sort some entries.
- Add comment.

Print CPUID 0x80000007 %edx on both Intel and AMD.

Remove ci_max_ext_cpuid because it's the same as ci_cpuid_extlevel.

0x7d and 0x7e are for 10th generation Core (Ice Lake).

- Add definitions of AMD's CPUID Fn8000_001f Encrypted Memory features.
- Add definition of AMD's CPUID Fn8000_000a %edx bit 11 "GMET".
- Define CPUID_AMD_SVM_PFThreshold correctly.
- Modify comment a bit for consistency.

Call cpu_dcp_cacheinfo() only when the cpuid Topology Extension flag is set
on AMD prcessor.

Decode AMD's CPUID Fn8000_0008 %ebx.

branches: 1.104.2;
- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
Intel Deterministic Cache Parameter Leaf(0x04), so make new
cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
common definition.
- KNF.

XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?

White space fix. No functional change.

Update from the latest Intel SDM:
- Add Cascade Lake, Copper Lake
- Add Future Xeon (Cannon Lake)
- Add 06_7DH for another Ice Lake
- Add Coffee Lake based Xeon E

Revert previous (accidentally committed).

Use ETHER_LOCK()/ETHER_UNLOCK() for all ethernet drivers to protect ec_multi*.

All MSRs can only be read at privilege level 0. The exact APIC ID cannot
be determined on some AMD CPUs.

Undo previous. Not needed (and file included isn't installed anyway.

need cpufunc.h for rdmsr

Get CPU topology data for AMD processors.

Add HAXM.

s/TGC/TCG/. Not Tokyo Game Show but Tiny Code Generator.

- Dump CPUID leaf 0x40000000 if available (for -v option).
- Regard "TCGTCGTCGTCG" as QEMU(TGC).

Add Ice Lake and Tremont from the latest Intel SDM.

Handle the NVMM signature.

Print Intel CPUID Architectural Performance Monitoring leaf Fn0000000a.

Decode Intel/AMD MONITOR/MWAIT leaf.

Decode package, core and SMT id if CPUID 0x0b is available on Intel processor.
If the value is different from the kernel value, we should fix the kernel code.

TODO: Use 0x1f if it's available.

- AMD also reports CPUID 7's highest subleaf. Print it.
- Use macro.

- Use ci_feat_val[7] as CPUID 7 %edx to match x86/cpu.h
- AMD also has CPUID 6.
- Remove unused code for coretemp.
- Consistently use descs[] instead of data[].

branches: 1.85.2;
Whitespace fix. No functional change.

From the latest Intel SDM:
- Add Xeon Phi 7215, 7285 and 7295
- Add Coffee Lake

Add yet another Shared L2 TLB (2M/4M pages).

XXX need redesign.

branches: 1.82.2;
Calculate way and number of entries correctly from CPUID leaf 18H.

- Parse the TLB info from `cpuid leaf 18H' on Intel processor. Currently,
this change doesn't decode perfectly. Tested with Gemini Lake. It has
two L2 Shared TLB. One is 4MB and another is 2MB/4MB but former isn't
printed yet:

cpu0: ITLB 1 4KB entries 48-way
cpu0: DTLB 1 4KB entries 32-way
cpu0: L2 STLB 8 4MB entries 4-way

Need some rework for struct x86_cache_info.
- Use aprint_error_dev() for error output.

implement cpuctl identify for sparc and sparc64.

sparc:
- move enum vactype and struct cacheinfo into cpu.h
- move the cache flags from cpuinfo.flags into CACHEINFO.c_flags
(this allows the new cache_printf_backend() to see them.)
remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA.
- align xmpsg to 64 bytes
- move cache_print() into cache_print.h so it can be shared with
cpuctl. it only depends upon a working printf().
- if found, store the CPU node's "name" into cpu_longname. this
changes the default output to show the local CPU not the
generic CPU family. eg:
cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU
vs the generic "RT620/625" previously shown.
- for each CPU export these things:
- name
- fpuname
- mid
- cloc
- freq
- psr impl and version
- mmu impl, version, and number of contexts
- cacheinfo structure (which changed for the first time ever
with this commit.)

sparc64:
- add a minimal "cacheinfo" structure to export the i/d/e-cache
size and linesize.
- store %ver, cpu node "name" and cacheinfo in cpu_info.
- set cpu_info ver, name and cacheinfo in cpu_attach(), and
export them via sysctl, as well as CPU ID and clock freq

cpuctl:
- add identifycpu_bind() that returns false on !x86 as their
identify routines do not need to run on a particular CPU to
obtain its information, and use it to avoid trying to set
affinity when not needed.
- add sparc and sparc64 cpu identify support using the newly
exported values.

Print Intel cpuid 7 %edx.

Example output of cpuctl -v identify 0:

+cpu0: 00000007: 00000000 000027ab 00000000 0c000000
(snip)
+cpu0: SEF edx 0xc000000<IBRS,STIBP>

Update from Intel SDM:
0x55: Xeon Scalable (Skylake)
0x57: Xeon Phi [357]200 (Knights Landing)
0x66: Future Core (Cannon Lake)
0x85: Future Xeon Phi (Knights Mill)

Update from the latest Intel SDM:
0x5c: Atom (Goldmont)
0x5f: Atom (Goldmont, Denverton)
0x7a: Atom (Goldmont Plus)

- Print ci_feat_val[5] (Structured Extended Feature leaf Fn0000_0007 %ebx) on
AMD, too.
- Print ci_feat_val[6] (Fn0000_0007 %ecx) on Intel.

Define CPUID Fn00000001 %ebx bits and use them. No functional change.

branches: 1.74.6;
Update from the latest Intel SDM:
- Denverton
- Future Xeon Phi
- 7th gen Core (Kaby Lake)

Update processor families from the latest Intel SDM:
- 06_4FH: Add Xeon E7 v4 and Core i7-69xx Extreme Edition
- 06_57H: Xeon Phi [357]200

branches: 1.72.2;
Add some name from the latest Intel SDM.
- Quark X1000, Xeon E5 v4 and the future processors.

- Add structure extended feature registers into ci_feat_val[]. The locations
are the same as x86/include/cpu.h. Curreltly those values are not used yet.
- KNF.

From the latest Intel SDM:
- Add Xeon E3-1200 v5
- Change 0x1c from "Atom Family" to "45nm Atom Family"

Model 0x5e is also 6th gen Core or Xeon E3-1500 v5 like model 0x4e.

Add 6th gen Core, Xeon E3-1500 v5 and Xeon D-1500 from the latest Intel SDM.

Add Xeon E5-4600 v3, Xeon E3-1200 v4 etc. from the latest Intel SDM.

Update some Intel CPU models (Sky Lake, Broadwell and Atom X[357]).

Update from Intel SDM:
- Add Atom Z8000, Future gen Xeon (Broadwell), Next gen Xeon Phi and so on.
- Add comments.

Don't print the microcode version if the ioctl failed to not to
print garbage.

Add newline if ci_tsc_freq is 0 to not to break the output.

Move some printf()s from cpu_probe_base_features() to identifycpu().
Those printf()s are used for "identify" command but cpu_probe_base_features()
is shared by ucodeupdate_check(), too. This change fixes a problem that
the "ucode" command print extra output.

kern/49379: Hypervisor's name typo

Add code to detect hypervisor. The code was based from FreeBSD and ported
by Kengo Nakahara.

Update CPUID signature values from the latest Intel SDM.
- Core M-5xxx
- Core i7 extreme
- Future Core (0x4e)
- Future Xeon (0x56)

branches: 1.58.2;
More update:
- Future Atom E3000, Z3000 (0x4a, 0x5a, 0x5d)
- Atom C2000 (0x4d)

Update table for processor families and processor number series from the
latest Intel SDM.
- Atom Z3000 (0x37)
- Core M based on Broadwell (0x3d)
- Next gen Xeon based on Haswell (0x3f)

Exclude descriptor 0xff of CPUID leaf 2. 0xff means the cacheinfo is in leaf 4.

If -v is set and unknown cacheinfo desc is found, print it.

branches: 1.54.2;
- Rename x86_print_cacheinfo() to x86_print_cache_and_tlb_info() because
this function prints TLB info, too.
- Remove an extra printf when verbose flag is set.
- Print the highest extended info level as the basic info level.
- Sort function.

Add verbose flag.
On x86 cpu, cpuctl -v identify dumps the return values of the cpuid
functions. The max levels are taken from CPUID 0 and CPUID 8000_0000.
It's useful for the future CPU.

CPUID leaf 2 and 4 are only for Intel processors.

Add comments. Remove comments. No functional change.

Modify some macros and add some new macros for CPU family and model
to reduce code duplication and to avoid bug.

CPUID_TO_STEPPING(cpuid) (not changed)

CPUID_TO_FAMILY(cpuid) (new)
CPUID_TO_MODEL(cpuid) (new)

Return the display family and the display model.
The macro names are the same as FreeBSD.

CPUID_TO_BASEFAMILY(cpuid) (The old name was CPUID2FAMILY)
CPUID_TO_BASEMODEL(cpuid) (The old name was CPUID2MODEL)

Only for the base field.

CPUID_TO_EXTFAMILY(cpuid) (The old name was CPUID2EXTFAMILY)
CPUID_TO_EXTMODEL(cpuid) (The old name was CPUID2EXTMODEL)

Only for the extended field.

See http://mail-index.netbsd.org/port-amd64/2013/11/12/msg001978.html

Fix typo. From jnemeth.

Update some processor names.

avoid uninitialised variable use.

Support prefetch size.

Check cpuid leaf 4 for newer Intel CPU to know the cache information.

No functional change:
- Add prototypes.
- Make some function static.
- Sort functions.

Fix typo in comment (s/XRC0/XCR0/).

Add shared TLB.
KNF.

Update Intel processors' brand names and model names (e.g. Atom C2000 and
E3000) from the latest document.

Update Intel's Processor Family Names of family == 6 from the latest document.
Add 0x35(Atom), 0x36(Atom S), 0x3f(future Xeon), 0x46(Haswell) and update some
models.

print some more bits

Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually identifies
the cpu is output first.

Use full model number to index name strings - a lot of 256 element arrays
don't matter in usespace.
Update list of intel family 6 model names (all current cpus) to include
everything upto and including sandy bridge and ivy bridge.
My i7 is no longer reported as a random P II.

The Intel and AMD docs (more or less) agree on how the cpuid 'extended
family' and 'extended model' bits are used to create larger values
than the original 16bit value allowed for.
Calculate and save these values 'up-front' and use them throughout.
Untangle the (backwards) nested switch statement for amd 'model 15' cpus.
Works as badly as ever on my i7.

If the IOC_CPU_UCODE_GET_VERSION fails with ENOTTY, try issuing the
request that the amd64 kernel understands.

Change the i386 asm x86_identify() so it returns a value instead of writing
into global data.
Fix a stack alignment fubar that would cause a crash on a cirix 486.
Refactor identify code to common setup for normal identify and ucode
identify - which was missing a memset().

#include sys/ioctl.h

branches: 1.32.2;
Extend the CPU microcode update framework to support Intel x86 CPUs.
Contrary to the AMD implementation, it doesn't use xcalls to distribute
the update to all CPUs but relies on cpuctl(8) to bind itself to the
right CPU -- to keep it simple and avoid possible problems with
hyperthreading.
Also, it doesn't parse the vendor supplied file to pick the right
part for the present CPU model but relies on userland to prepare
files with specific filenames. I'll commit a pkg for this in a minute
(pkgsrc/sysutils/intel-microcode).
The ioctl interface changed; compatibility is provided (should be
limited to COMPAT_NETBSD6 as soon as this is available).

print cpu family for AMD CPU families 0x12 - 0x15

report l3 cache information on AMD Family 10h and newer processors

Print CPU stepping level

Use uintmax_t for freqency computations to avoid differences between
platforms.

branches: 1.27.2;
use a correct macro.
releng@ ok

add info on L2 TLBs and 1GB pages.

branches: 1.25.4;
Identify AMD Family 11h. From PR bin/41188 by FUKAUMI Naoki.

fix printing of padlock features

branches: 1.23.2;
beautify printing of SVM features across multiple lines

check for svm feature flags if cpuid function 0x8000000a is available.

don't call most/all Core2's "(Merom)".

- add newer VIA C7 core and VIA Nano.
- when printing an unknown VIA CPU, default to 'Unknown IDT/VIA' instead of 'C3'

Add a few more processor extended models for Intel Family 6

1. Extend CPU probe of Intel processors to handle extended-models. This
allows us to properly identify new Intel 45nm processors, Core i7,
Atom, and the 45nm Xeon MP.

2. Properly decode several new Intel cache descriptors, as listed in the
most recent (March 2009) edition of Intel's Application Note 485.

3. Convert decode of the various features masks to use the newly added
snprintb_m(3) routine.

Addresses my PR bin/41289
Addresses my PR bin/41290

WARNS=4

Increase size of buffer for humanize_number(3) to print cache sizes
so that it can return 128KB, 256KB and 512KB properly instead of
truncated 0MB or rounded 1MB.

Problem reported by nisimura@ on port-amd64 and port-i386.

print some SVM info if available.

branches: 1.14.2;
Remove 3rd buggy copy of this function and use snprintb(3) instead.
No need to allocate MAXPATHLEN buffers anymore.

branches: 1.13.2;
do correct octal counting and use CPUID_APM_FLAGS in cpuctl

print features4: cpuid fn80000001 %ecx on AMD CPUs.

Add cpuid 0x80000001 %ecx features flags. Rename CPUID_MASK4 to CPUID_INTEL_MASK4 for consistency with new CPUID_AMD_MASK4

1. For non-Intel vendors, don't overload cpuflags with the extended
flags from CPUID 80000001_EDX. Instead, keep the extended flags
separate, in ci_feature3_flags (Intel processors already kept a
separate ci_feature3_flag value).

2. Decode/display ci_feature3_flag in a vendor-specific manner, since
the definitions are vendor-specific.

OK cegger@

change HUMAN_NUMBER back to 5

remove stray `

- fix an amd cache entry.
- merge tables
- support phenom
from Paul Goyette

de-duplicated cacheinfo.h

Print AMD power management features.

branches: 1.4.2;
Sync intel_cpuid_cache_info with src/sys/arch/x86/x86/identcpu.c.

Fix two sizeof(__arraycount()) to not use sizeof when looking up the size
of the array.

This fixes a crash when run on amd phenom under amd64.

Issue reported and inital patch by Paul Goyette.

Report: family, model, extfamily, extmodel

branches: 1.1.2;
PR port-amd64/37461 x86 cpu dmesg output is noisy

Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.

implement cpuctl identify for sparc and sparc64.

sparc:
- move enum vactype and struct cacheinfo into cpu.h
- move the cache flags from cpuinfo.flags into CACHEINFO.c_flags
(this allows the new cache_printf_backend() to see them.)
remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA.
- align xmpsg to 64 bytes
- move cache_print() into cache_print.h so it can be shared with
cpuctl. it only depends upon a working printf().
- if found, store the CPU node's "name" into cpu_longname. this
changes the default output to show the local CPU not the
generic CPU family. eg:
cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU
vs the generic "RT620/625" previously shown.
- for each CPU export these things:
- name
- fpuname
- mid
- cloc
- freq
- psr impl and version
- mmu impl, version, and number of contexts
- cacheinfo structure (which changed for the first time ever
with this commit.)

sparc64:
- add a minimal "cacheinfo" structure to export the i/d/e-cache
size and linesize.
- store %ver, cpu node "name" and cacheinfo in cpu_info.
- set cpu_info ver, name and cacheinfo in cpu_attach(), and
export them via sysctl, as well as CPU ID and clock freq

cpuctl:
- add identifycpu_bind() that returns false on !x86 as their
identify routines do not need to run on a particular CPU to
obtain its information, and use it to avoid trying to set
affinity when not needed.
- add sparc and sparc64 cpu identify support using the newly
exported values.

avoid dummy structure definition, include a system header instead,
looks just cleaner

branches: 1.4.2;
fix for archs w/o cpu ucode driver: add dummy definition

Extend the CPU microcode update framework to support Intel x86 CPUs.
Contrary to the AMD implementation, it doesn't use xcalls to distribute
the update to all CPUs but relies on cpuctl(8) to bind itself to the
right CPU -- to keep it simple and avoid possible problems with
hyperthreading.
Also, it doesn't parse the vendor supplied file to pick the right
part for the present CPU model but relies on userland to prepare
files with specific filenames. I'll commit a pkg for this in a minute
(pkgsrc/sysutils/intel-microcode).
The ioctl interface changed; compatibility is provided (should be
limited to COMPAT_NETBSD6 as soon as this is available).

branches: 1.2.4; 1.2.6;
Make this compile.

PR port-amd64/37461 x86 cpu dmesg output is noisy

Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.

remove clause 3 from all my licenses that aren't conflicting with
another copyright claim line. again. (i did this in 2008 and then
did not update all of my personal templates.)

implement cpuctl identify for sparc and sparc64.

sparc:
- move enum vactype and struct cacheinfo into cpu.h
- move the cache flags from cpuinfo.flags into CACHEINFO.c_flags
(this allows the new cache_printf_backend() to see them.)
remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA.
- align xmpsg to 64 bytes
- move cache_print() into cache_print.h so it can be shared with
cpuctl. it only depends upon a working printf().
- if found, store the CPU node's "name" into cpu_longname. this
changes the default output to show the local CPU not the
generic CPU family. eg:
cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU
vs the generic "RT620/625" previously shown.
- for each CPU export these things:
- name
- fpuname
- mid
- cloc
- freq
- psr impl and version
- mmu impl, version, and number of contexts
- cacheinfo structure (which changed for the first time ever
with this commit.)

sparc64:
- add a minimal "cacheinfo" structure to export the i/d/e-cache
size and linesize.
- store %ver, cpu node "name" and cacheinfo in cpu_info.
- set cpu_info ver, name and cacheinfo in cpu_attach(), and
export them via sysctl, as well as CPU ID and clock freq

cpuctl:
- add identifycpu_bind() that returns false on !x86 as their
identify routines do not need to run on a particular CPU to
obtain its information, and use it to avoid trying to set
affinity when not needed.
- add sparc and sparc64 cpu identify support using the newly
exported values.

remove clause 3 from all my licenses that aren't conflicting with
another copyright claim line. again. (i did this in 2008 and then
did not update all of my personal templates.)

implement cpuctl identify for sparc and sparc64.

sparc:
- move enum vactype and struct cacheinfo into cpu.h
- move the cache flags from cpuinfo.flags into CACHEINFO.c_flags
(this allows the new cache_printf_backend() to see them.)
remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA.
- align xmpsg to 64 bytes
- move cache_print() into cache_print.h so it can be shared with
cpuctl. it only depends upon a working printf().
- if found, store the CPU node's "name" into cpu_longname. this
changes the default output to show the local CPU not the
generic CPU family. eg:
cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU
vs the generic "RT620/625" previously shown.
- for each CPU export these things:
- name
- fpuname
- mid
- cloc
- freq
- psr impl and version
- mmu impl, version, and number of contexts
- cacheinfo structure (which changed for the first time ever
with this commit.)

sparc64:
- add a minimal "cacheinfo" structure to export the i/d/e-cache
size and linesize.
- store %ver, cpu node "name" and cacheinfo in cpu_info.
- set cpu_info ver, name and cacheinfo in cpu_attach(), and
export them via sysctl, as well as CPU ID and clock freq

cpuctl:
- add identifycpu_bind() that returns false on !x86 as their
identify routines do not need to run on a particular CPU to
obtain its information, and use it to avoid trying to set
affinity when not needed.
- add sparc and sparc64 cpu identify support using the newly
exported values.

All MSRs can only be read at privilege level 0. The exact APIC ID cannot
be determined on some AMD CPUs.

Get CPU topology data for AMD processors.

branches: 1.5.16;
xgetbv expects XCR0 to be speficied in %ecx, don't leave %ecx undefined

branches: 1.4.8;
Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually identifies
the cpu is output first.

Fix x86_identify() for amd64

branches: 1.2.18; 1.2.20; 1.2.24;
fix so that we can compile with PIC

branches: 1.1.4;
PR port-amd64/37461 x86 cpu dmesg output is noisy

Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.

branches: 1.1.4;
PR port-amd64/37461 x86 cpu dmesg output is noisy

Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.