| History log of /src/usr.sbin/cpuctl |
| Revision | Date | Author | Comments |
| 1.9 | 21-Apr-2020 |
msaitoh | Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.
- If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors
can take TSC/core crystal clock ratio but core crystal clock frequency
can't be taken. Intel SDM give us the values for some processors.
- It also required to change lapic_per_second to make LAPIC timer correctly.
- Add new file x86/x86/identcpu_subr.c to share common subroutines between
kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c
will be moved to this file in future.
- Add comment to clarify.
|
| 1.8 | 23-Jan-2016 |
christos | branches: 1.8.8; 1.8.16; 1.8.18;
Define _KERNTYPES for things that need it.
|
| 1.7 | 01-Aug-2013 |
matt | .include <bsd.own.mk> to get MACHINE_CPU
|
| 1.6 | 31-Jan-2013 |
matt | Add arm support for cpuctl identify
|
| 1.5 | 23-Apr-2009 |
lukem | branches: 1.5.6; 1.5.12;
Allow WARNS=4 after Christos' fix sys/cdefs.h
|
| 1.4 | 22-Apr-2009 |
lukem | Enable WARNS=4 by default, except for:
cpuctl dumplfs hprop ipf iprop-log kadmin kcm kdc kdigest
kimpersonate kstash ktutil makefs ndbootd ntp pppd quot
racoon racoonctl rtadvd sntp sup tcpdchk tcpdmatch tcpdump
traceroute traceroute6 user veriexecgen wsmoused zic
(Mostly third-party applications)
|
| 1.3 | 16-Dec-2008 |
christos | branches: 1.3.2;
Remove 3rd buggy copy of this function and use snprintb(3) instead.
No need to allocate MAXPATHLEN buffers anymore.
|
| 1.2 | 05-May-2008 |
ad | branches: 1.2.6;
PR port-amd64/37461 x86 cpu dmesg output is noisy
Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.
|
| 1.1 | 04-Aug-2007 |
ad | branches: 1.1.8; 1.1.10;
Add cpuctl(8). For now this is not much more than a toy for debugging and
benchmarking that allows taking CPUs online/offline.
|
| 1.1.10.2 | 04-Aug-2007 |
ad | Add cpuctl(8). For now this is not much more than a toy for debugging and
benchmarking that allows taking CPUs online/offline.
|
| 1.1.10.1 | 04-Aug-2007 |
ad | file Makefile was added on branch matt-mips64 on 2007-08-04 11:03:05 +0000
|
| 1.1.8.1 | 18-May-2008 |
yamt | sync with head.
|
| 1.2.6.1 | 23-Dec-2008 |
snj | Pull up following revision(s) (requested by christos in ticket #193):
usr.sbin/cpuctl/Makefile: revision 1.3
usr.sbin/cpuctl/bitmask.c: file removal
usr.sbin/cpuctl/cpuctl.h: revision 1.2
usr.sbin/cpuctl/arch/i386.c: revision 1.14
Remove 3rd buggy copy of this function and use snprintb(3) instead.
No need to allocate MAXPATHLEN buffers anymore.
|
| 1.3.2.1 | 13-May-2009 |
jym | Sync with HEAD.
Third (and last) commit. See http://mail-index.netbsd.org/source-changes/2009/05/13/msg221222.html
|
| 1.5.12.2 | 20-Aug-2014 |
tls | Rebase to HEAD as of a few days ago.
|
| 1.5.12.1 | 25-Feb-2013 |
tls | resync with head
|
| 1.5.6.1 | 22-May-2014 |
yamt | sync with head.
for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.
this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
|
| 1.8.18.1 | 10-Jul-2020 |
martin | Pull up the following revisions (all via patch) requested by msaitoh in
ticket #995:
usr.sbin/cpuctl/Makefile 1.9
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.5
usr.sbin/cpuctl/arch/i386.c 1.111-1.113
usr.sbin/cpuctl/cpuctl.c 1.31
usr.sbin/cpuctl/cpuctl.h 1.7
sys/arch/x86/x86/identcpu_subr.c 1.1-1.7
- Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel
processors.
- Add 0xa5 and 0xa6 for Comet Lake.
- Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
ci_max_ext_cpuid to match x86/include/cpu.h. No functional change.
- Sort some entries.
- Add comment.
|
| 1.8.16.1 | 21-Apr-2020 |
martin | Sync with HEAD
|
| 1.8.8.1 | 05-Aug-2020 |
martin | Pull up the following revisions, requested by msaitoh in ticket #1585:
usr.sbin/cpuctl/Makefile 1.9
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.5
usr.sbin/cpuctl/arch/i386.c 1.111-1.113 via patch
usr.sbin/cpuctl/cpuctl.c 1.31
usr.sbin/cpuctl/cpuctl.h 1.7
sys/arch/x86/x86/identcpu_subr.c 1.1-1.7
- Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel
processors.
- Add 0xa5 and 0xa6 for Comet Lake.
- Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
ci_max_ext_cpuid to match x86/include/cpu.h. No functional change.
- Sort some entries.
- Add comment.
|
| 1.2 | 16-Dec-2008 |
christos | Remove 3rd buggy copy of this function and use snprintb(3) instead.
No need to allocate MAXPATHLEN buffers anymore.
|
| 1.1 | 05-May-2008 |
ad | branches: 1.1.4; 1.1.8;
PR port-amd64/37461 x86 cpu dmesg output is noisy
Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.
|
| 1.1.8.1 | 23-Dec-2008 |
snj | Pull up following revision(s) (requested by christos in ticket #193):
usr.sbin/cpuctl/Makefile: revision 1.3
usr.sbin/cpuctl/bitmask.c: file removal
usr.sbin/cpuctl/cpuctl.h: revision 1.2
usr.sbin/cpuctl/arch/i386.c: revision 1.14
Remove 3rd buggy copy of this function and use snprintb(3) instead.
No need to allocate MAXPATHLEN buffers anymore.
|
| 1.1.4.2 | 18-May-2008 |
yamt | sync with head.
|
| 1.1.4.1 | 05-May-2008 |
yamt | file bitmask.c was added on branch yamt-pf42 on 2008-05-18 12:36:14 +0000
|
| 1.23 | 19-Mar-2024 |
gutteridge | cpuctl.8: fix grammar in a sentence
|
| 1.22 | 12-Sep-2023 |
wiz | cpuctl(8): note that AMD updates need to be applied on all CPUs at once
Note that checking dmesg(8) after problems might be helpful.
Sort commands.
Bump date.
|
| 1.21 | 06-Mar-2023 |
kre | Unless -v is given, ignore EEXIST errors from the IOC_CPU_UCODE_APPLY ioctl()
used to implement "cpuctl ucode N", which indicates that the microcode
to be loaded already exists in the CPU, and as such, isn't really a
very interesting "error".
|
| 1.20 | 17-May-2019 |
gutteridge | branches: 1.20.2; 1.20.10;
cpuctl.8: minor fixes
|
| 1.19 | 15-Apr-2019 |
gutteridge | cpuctl.8: update the URL for AMD microcode, the previous site listed is
apparently defunct.
|
| 1.18 | 14-Jan-2018 |
mrg | branches: 1.18.4;
note the default path for ucode updates can be found in sysctl.
|
| 1.17 | 17-Sep-2016 |
wiz | branches: 1.17.6;
Sort SEE ALSO.
|
| 1.16 | 17-Sep-2016 |
jdolecek | link back to intrctl(8), it xrefs cpuctl(8)
|
| 1.15 | 16-Nov-2015 |
mrg | branches: 1.15.2;
allow most commands to specify more than one cpu. now you can online or
offline (or identify, or intr/nointr) a list of cpus all together.
|
| 1.14 | 20-Nov-2014 |
wiz | Bump date. Quote minus with a backslash, for PostScript/PDF output.
|
| 1.13 | 20-Nov-2014 |
msaitoh | Fix manual and usage bug. The ucode command can take [cpuno] argument.
|
| 1.12 | 19-Feb-2014 |
szptvlfn | Update URL
|
| 1.11 | 23-Dec-2013 |
wiz | Use more common phrasing.
|
| 1.10 | 23-Dec-2013 |
msaitoh | Add verbose flag.
On x86 cpu, cpuctl -v identify dumps the return values of the cpuid
functions. The max levels are taken from CPUID 0 and CPUID 8000_0000.
It's useful for the future CPU.
|
| 1.9 | 15-Mar-2012 |
njoly | branches: 1.9.2;
Use Lk macro when dealing with URLs. While here update or remove some
dead URL links. Another part of PR/29238.
|
| 1.8 | 14-Jan-2012 |
wiz | branches: 1.8.2;
Sort sections. Uppercase CPU.
|
| 1.7 | 13-Jan-2012 |
cegger | Support CPU microcode loading via cpuctl(8).
Implemented and enabled via CPU_UCODE kernel config option
for x86 and Xen Dom0.
Tested on different AMD machines with different
CPU families.
ok wiz@ for the manpages
ok releng@
ok core@ via releng@
|
| 1.6 | 22-Jun-2008 |
wiz | branches: 1.6.2;
Bump date for previous. Drop trailing whitespace. Improve formatting.
|
| 1.5 | 22-Jun-2008 |
ad | Add a dumb, mostly Solaris-compatible psrset command. It's missing some
options. Without it there's no easy way to test or use processor sets.
|
| 1.4 | 05-May-2008 |
ad | branches: 1.4.2;
PR port-amd64/37461 x86 cpu dmesg output is noisy
Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.
|
| 1.3 | 30-Apr-2008 |
martin | Convert TNF licenses to new 2 clause variant
|
| 1.2 | 25-Mar-2008 |
martin | branches: 1.2.2;
Use cpu index instead of ID for cpuctl; extend listing to provide both
numbers (but now the ID is only informational).
|
| 1.1 | 04-Aug-2007 |
ad | branches: 1.1.8;
Add cpuctl(8). For now this is not much more than a toy for debugging and
benchmarking that allows taking CPUs online/offline.
|
| 1.1.8.2 | 04-Aug-2007 |
ad | Add cpuctl(8). For now this is not much more than a toy for debugging and
benchmarking that allows taking CPUs online/offline.
|
| 1.1.8.1 | 04-Aug-2007 |
ad | file cpuctl.8 was added on branch matt-mips64 on 2007-08-04 11:03:06 +0000
|
| 1.2.2.1 | 18-May-2008 |
yamt | sync with head.
|
| 1.4.2.1 | 23-Jun-2008 |
wrstuden | Sync w/ -current. 34 merge conflicts to follow.
|
| 1.6.2.2 | 22-May-2014 |
yamt | sync with head.
for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.
this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
|
| 1.6.2.1 | 17-Apr-2012 |
yamt | sync with head
|
| 1.8.2.1 | 16-Jan-2015 |
snj | Pull up following revision(s) (requested by msaitoh in ticket #1230):
usr.sbin/cpuctl/cpuctl.8: revisions 1.9-1.12
usr.sbin/cpuctl/cpuctl.c: revisions 1.22-1.23 and 1.25 via patch
usr.sbin/cpuctl/cpuctl.h: revision 1.5 via patch
usr.sbin/cpuctl/arch/cpuctl_i386.h: revisions 1.1-1.2
usr.sbin/cpuctl/arch/i386-asm.S: revisions 1.2-1.3
usr.sbin/cpuctl/arch/i386.c: revisions 1.34, 1.36-1.49, 1.51-1.63 via patch
usr.sbin/cpuctl/arch/x86_64-asm.S: revisions 1.3-1.4
Update cpuctl(8). Microcode and ARM related changes are not included:
- Change the i386 asm x86_identify() so it returns a value instead of
writing into global data. Fix a stack alignment fubar that would
cause a crash on a cirix 486. Refactor identify code to common setup
for normal identify and ucode identify - which was missing a
memset().
- The Intel and AMD docs (more or less) agree on how the cpuid
'extended family' and 'extended model' bits are used to create
larger values than the original 16bit value allowed for.
Calculate and save these values 'up-front' and use them throughout.
Untangle the (backwards) nested switch statement for amd 'model 15'
cpus.
- Use full model number to index name strings - a lot of 256 element
arrays don't matter in usespace.
- Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually
identifies the cpu is output first.
- Only complain about binding if we have more than 1 cpu.
- Check cpuid leaf 4 for newer Intel CPU to know the cache information.
- Support prefetch size.
- Print the highest extended info level as the basic info level.
- Update URL of AMD's web page.
- Add code to detect hypervisor. The code was based from FreeBSD and
ported by Kengo Nakahara.
- Add verbose flag.
- Add newline if ci_tsc_freq is 0 to not to break the output.
- Update Intel's processor family names and models.
- Print some more bits.
- Add shared TLB
- Add prototypes.
- Add comments.
- Make some functions static.
- Sort functions.
- KNF.
|
| 1.9.2.1 | 20-Aug-2014 |
tls | Rebase to HEAD as of a few days ago.
|
| 1.15.2.1 | 04-Nov-2016 |
pgoyette | Sync with HEAD
|
| 1.17.6.2 | 23-Aug-2023 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #1892):
usr.sbin/cpuctl/cpuctl.8: revision 1.21
usr.sbin/cpuctl/cpuctl.c: revision 1.33
Unless -v is given, ignore EEXIST errors from the IOC_CPU_UCODE_APPLY ioctl()
used to implement "cpuctl ucode N", which indicates that the microcode
to be loaded already exists in the CPU, and as such, isn't really a
very interesting "error".
|
| 1.17.6.1 | 11-Apr-2018 |
martin | Pull up following revision(s) (requested by mrg in ticket #734):
usr.sbin/cpuctl/cpuctl.8: revision 1.18
note the default path for ucode updates can be found in sysctl.
|
| 1.18.4.1 | 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.20.10.1 | 23-Aug-2023 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #339):
usr.sbin/cpuctl/cpuctl.8: revision 1.21
usr.sbin/cpuctl/cpuctl.c: revision 1.33
Unless -v is given, ignore EEXIST errors from the IOC_CPU_UCODE_APPLY ioctl()
used to implement "cpuctl ucode N", which indicates that the microcode
to be loaded already exists in the CPU, and as such, isn't really a
very interesting "error".
|
| 1.20.2.1 | 23-Aug-2023 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #1724):
usr.sbin/cpuctl/cpuctl.8: revision 1.21
usr.sbin/cpuctl/cpuctl.c: revision 1.33
Unless -v is given, ignore EEXIST errors from the IOC_CPU_UCODE_APPLY ioctl()
used to implement "cpuctl ucode N", which indicates that the microcode
to be loaded already exists in the CPU, and as such, isn't really a
very interesting "error".
|
| 1.35 | 13-Sep-2023 |
wiz | tabify
|
| 1.34 | 12-Sep-2023 |
wiz | cpuctl: be more verbose about problems and diagnosing them
|
| 1.33 | 06-Mar-2023 |
kre | Unless -v is given, ignore EEXIST errors from the IOC_CPU_UCODE_APPLY ioctl()
used to implement "cpuctl ucode N", which indicates that the microcode
to be loaded already exists in the CPU, and as such, isn't really a
very interesting "error".
|
| 1.32 | 01-Feb-2022 |
mrg | branches: 1.32.2;
allow "cpuN" as well as "N" to specific a CPU.
update usage to include a change i made from 2015 to allow multiple
CPUs to be operated on at the same time for most commands.
|
| 1.31 | 21-Apr-2020 |
msaitoh | Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.
- If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors
can take TSC/core crystal clock ratio but core crystal clock frequency
can't be taken. Intel SDM give us the values for some processors.
- It also required to change lapic_per_second to make LAPIC timer correctly.
- Add new file x86/x86/identcpu_subr.c to share common subroutines between
kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c
will be moved to this file in future.
- Add comment to clarify.
|
| 1.30 | 11-May-2019 |
maxv | branches: 1.30.2;
Check the return value of cpuset_set(), to prevent future surprises.
|
| 1.29 | 16-Jan-2018 |
mrg | branches: 1.29.4;
implement cpuctl identify for sparc and sparc64.
sparc:
- move enum vactype and struct cacheinfo into cpu.h
- move the cache flags from cpuinfo.flags into CACHEINFO.c_flags
(this allows the new cache_printf_backend() to see them.)
remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA.
- align xmpsg to 64 bytes
- move cache_print() into cache_print.h so it can be shared with
cpuctl. it only depends upon a working printf().
- if found, store the CPU node's "name" into cpu_longname. this
changes the default output to show the local CPU not the
generic CPU family. eg:
cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU
vs the generic "RT620/625" previously shown.
- for each CPU export these things:
- name
- fpuname
- mid
- cloc
- freq
- psr impl and version
- mmu impl, version, and number of contexts
- cacheinfo structure (which changed for the first time ever
with this commit.)
sparc64:
- add a minimal "cacheinfo" structure to export the i/d/e-cache
size and linesize.
- store %ver, cpu node "name" and cacheinfo in cpu_info.
- set cpu_info ver, name and cacheinfo in cpu_attach(), and
export them via sysctl, as well as CPU ID and clock freq
cpuctl:
- add identifycpu_bind() that returns false on !x86 as their
identify routines do not need to run on a particular CPU to
obtain its information, and use it to avoid trying to set
affinity when not needed.
- add sparc and sparc64 cpu identify support using the newly
exported values.
|
| 1.28 | 16-Nov-2015 |
mrg | branches: 1.28.8;
allow most commands to specify more than one cpu. now you can online or
offline (or identify, or intr/nointr) a list of cpus all together.
|
| 1.27 | 16-Nov-2015 |
mrg | convert getcpuid() to take char* not char**
|
| 1.26 | 16-Nov-2015 |
mrg | use stdbool.h
|
| 1.25 | 16-Dec-2014 |
msaitoh | Fix a bug that an unknown command is printed as "(null)".
Reported by Fredrik Pettai.
|
| 1.24 | 20-Nov-2014 |
msaitoh | Fix manual and usage bug. The ucode command can take [cpuno] argument.
|
| 1.23 | 23-Dec-2013 |
msaitoh | branches: 1.23.4;
Add verbose flag.
On x86 cpu, cpuctl -v identify dumps the return values of the cpuid
functions. The max levels are taken from CPUID 0 and CPUID 8000_0000.
It's useful for the future CPU.
|
| 1.22 | 31-Jan-2013 |
matt | Only complain about binding if we have more than 1 cpu. :)
(we always have more than 0).
|
| 1.21 | 29-Aug-2012 |
drochner | branches: 1.21.2;
Extend the CPU microcode update framework to support Intel x86 CPUs.
Contrary to the AMD implementation, it doesn't use xcalls to distribute
the update to all CPUs but relies on cpuctl(8) to bind itself to the
right CPU -- to keep it simple and avoid possible problems with
hyperthreading.
Also, it doesn't parse the vendor supplied file to pick the right
part for the present CPU model but relies on userland to prepare
files with specific filenames. I'll commit a pkg for this in a minute
(pkgsrc/sysutils/intel-microcode).
The ioctl interface changed; compatibility is provided (should be
limited to COMPAT_NETBSD6 as soon as this is available).
|
| 1.20 | 13-Jan-2012 |
cegger | branches: 1.20.2;
Support CPU microcode loading via cpuctl(8).
Implemented and enabled via CPU_UCODE kernel config option
for x86 and Xen Dom0.
Tested on different AMD machines with different
CPU families.
ok wiz@ for the manpages
ok releng@
ok core@ via releng@
|
| 1.19 | 27-Sep-2011 |
jruoho | branches: 1.19.2;
Define _PATH_CPUCTL.
|
| 1.18 | 26-Sep-2011 |
jruoho | Fix wrong err(3) message (no such thing as IOC_CPU_GETINFO).
|
| 1.17 | 11-Sep-2011 |
jdc | Add a cs_hwid field to cpustate and use this to store the ci_cpuid (hardware
ID). Report this as the HwID in cpuctl.
OK jruoho@.
|
| 1.16 | 27-Aug-2011 |
joerg | static + __dead
|
| 1.15 | 23-Apr-2009 |
lukem | Fix -Wsign-compare issue
|
| 1.14 | 19-Apr-2009 |
ad | cpuctl:
- Add interrupt shielding (direct hardware interrupts away from the
specified CPUs). Not documented just yet but will be soon.
- Redo /dev/cpu time_t compat so no kernel changes are needed.
x86:
- Make intr_establish, intr_disestablish safe to use when !cold.
- Distribute hardware interrupts among the CPUs, instead of directing
everything to the boot CPU.
- Add MD code for interrupt sheilding. This works in most cases but there is
a bug where delivery is not accepted by an LAPIC after redistribution. It
also needs re-balancing to make things fair after interrupts are turned
back on for a CPU.
|
| 1.13 | 28-Jan-2009 |
ad | branches: 1.13.2;
cpuctl list: map hardware id after getting state. avoids screwed up display
when ci_cpuid != cpu_index()
|
| 1.12 | 19-Nov-2008 |
cegger | redo previous:
check ID in getcpuid(). This way, the other commands (online/offline)
tell the user the real error.
|
| 1.11 | 19-Nov-2008 |
rmind | cpu_identify: check ID against number of processors.
Fix for PR/39955.
|
| 1.10 | 15-Oct-2008 |
ad | branches: 1.10.2;
Cosmetic change to previous.
|
| 1.9 | 15-Oct-2008 |
ad | Don't map cpu index to hardware id.
|
| 1.8 | 16-Jun-2008 |
rmind | - Add general cpuset macros.
- Use kcpuset name for kernel-only functions.
- Use cpuid_t to specify CPU ID.
- Unify all cpuset users.
API is expected to be stable now.
|
| 1.7 | 16-Jun-2008 |
rmind | Sync with the latest cpuset changes.
|
| 1.6 | 12-May-2008 |
ad | Clarify output of 'id' column.
|
| 1.5 | 05-May-2008 |
ad | branches: 1.5.2;
PR port-amd64/37461 x86 cpu dmesg output is noisy
Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.
|
| 1.4 | 28-Apr-2008 |
martin | Remove clause 3 and 4 from TNF licenses
|
| 1.3 | 25-Mar-2008 |
martin | branches: 1.3.2;
Use cpu index instead of ID for cpuctl; extend listing to provide both
numbers (but now the ID is only informational).
|
| 1.2 | 09-Jan-2008 |
tnn | improve usage()
|
| 1.1 | 04-Aug-2007 |
ad | branches: 1.1.2; 1.1.6;
Add cpuctl(8). For now this is not much more than a toy for debugging and
benchmarking that allows taking CPUs online/offline.
|
| 1.1.6.2 | 04-Aug-2007 |
ad | Add cpuctl(8). For now this is not much more than a toy for debugging and
benchmarking that allows taking CPUs online/offline.
|
| 1.1.6.1 | 04-Aug-2007 |
ad | file cpuctl.c was added on branch matt-mips64 on 2007-08-04 11:03:06 +0000
|
| 1.1.2.1 | 23-Mar-2008 |
matt | sync with HEAD
|
| 1.3.2.2 | 17-Jun-2008 |
yamt | sync with head.
|
| 1.3.2.1 | 18-May-2008 |
yamt | sync with head.
|
| 1.5.2.1 | 23-Jun-2008 |
wrstuden | Sync w/ -current. 34 merge conflicts to follow.
|
| 1.10.2.3 | 06-Feb-2009 |
snj | Pull up following revision(s) (requested by rmind in ticket #409):
usr.sbin/cpuctl/cpuctl.c: revision 1.13
cpuctl list: map hardware id after getting state. avoids screwed up display
when ci_cpuid != cpu_index()
|
| 1.10.2.2 | 22-Nov-2008 |
snj | Pull up following revision(s) (requested by cegger in ticket #105):
usr.sbin/cpuctl/cpuctl.c: revision 1.12
redo previous:
check ID in getcpuid(). This way, the other commands (online/offline)
tell the user the real error.
|
| 1.10.2.1 | 22-Nov-2008 |
snj | Pull up following revision(s) (requested by cegger in ticket #105):
usr.sbin/cpuctl/cpuctl.c: revision 1.11
cpu_identify: check ID against number of processors.
Fix for PR/39955.
|
| 1.13.2.1 | 13-May-2009 |
jym | Sync with HEAD.
Third (and last) commit. See http://mail-index.netbsd.org/source-changes/2009/05/13/msg221222.html
|
| 1.19.2.3 | 22-May-2014 |
yamt | sync with head.
for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.
this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
|
| 1.19.2.2 | 30-Oct-2012 |
yamt | sync with head
|
| 1.19.2.1 | 17-Apr-2012 |
yamt | sync with head
|
| 1.20.2.1 | 16-Jan-2015 |
snj | Pull up following revision(s) (requested by msaitoh in ticket #1230):
usr.sbin/cpuctl/cpuctl.8: revisions 1.9-1.12
usr.sbin/cpuctl/cpuctl.c: revisions 1.22-1.23 and 1.25 via patch
usr.sbin/cpuctl/cpuctl.h: revision 1.5 via patch
usr.sbin/cpuctl/arch/cpuctl_i386.h: revisions 1.1-1.2
usr.sbin/cpuctl/arch/i386-asm.S: revisions 1.2-1.3
usr.sbin/cpuctl/arch/i386.c: revisions 1.34, 1.36-1.49, 1.51-1.63 via patch
usr.sbin/cpuctl/arch/x86_64-asm.S: revisions 1.3-1.4
Update cpuctl(8). Microcode and ARM related changes are not included:
- Change the i386 asm x86_identify() so it returns a value instead of
writing into global data. Fix a stack alignment fubar that would
cause a crash on a cirix 486. Refactor identify code to common setup
for normal identify and ucode identify - which was missing a
memset().
- The Intel and AMD docs (more or less) agree on how the cpuid
'extended family' and 'extended model' bits are used to create
larger values than the original 16bit value allowed for.
Calculate and save these values 'up-front' and use them throughout.
Untangle the (backwards) nested switch statement for amd 'model 15'
cpus.
- Use full model number to index name strings - a lot of 256 element
arrays don't matter in usespace.
- Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually
identifies the cpu is output first.
- Only complain about binding if we have more than 1 cpu.
- Check cpuid leaf 4 for newer Intel CPU to know the cache information.
- Support prefetch size.
- Print the highest extended info level as the basic info level.
- Update URL of AMD's web page.
- Add code to detect hypervisor. The code was based from FreeBSD and
ported by Kengo Nakahara.
- Add verbose flag.
- Add newline if ci_tsc_freq is 0 to not to break the output.
- Update Intel's processor family names and models.
- Print some more bits.
- Add shared TLB
- Add prototypes.
- Add comments.
- Make some functions static.
- Sort functions.
- KNF.
|
| 1.21.2.2 | 20-Aug-2014 |
tls | Rebase to HEAD as of a few days ago.
|
| 1.21.2.1 | 25-Feb-2013 |
tls | resync with head
|
| 1.23.4.1 | 21-Dec-2014 |
snj | Pull up following revision(s) (requested by msaitoh in ticket #336):
usr.sbin/cpuctl/cpuctl.c: revision 1.25
Fix a bug that an unknown command is printed as "(null)".
Reported by Fredrik Pettai.
|
| 1.28.8.3 | 23-Aug-2023 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #1892):
usr.sbin/cpuctl/cpuctl.8: revision 1.21
usr.sbin/cpuctl/cpuctl.c: revision 1.33
Unless -v is given, ignore EEXIST errors from the IOC_CPU_UCODE_APPLY ioctl()
used to implement "cpuctl ucode N", which indicates that the microcode
to be loaded already exists in the CPU, and as such, isn't really a
very interesting "error".
|
| 1.28.8.2 | 05-Aug-2020 |
martin | Pull up the following revisions, requested by msaitoh in ticket #1585:
usr.sbin/cpuctl/Makefile 1.9
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.5
usr.sbin/cpuctl/arch/i386.c 1.111-1.113 via patch
usr.sbin/cpuctl/cpuctl.c 1.31
usr.sbin/cpuctl/cpuctl.h 1.7
sys/arch/x86/x86/identcpu_subr.c 1.1-1.7
- Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel
processors.
- Add 0xa5 and 0xa6 for Comet Lake.
- Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
ci_max_ext_cpuid to match x86/include/cpu.h. No functional change.
- Sort some entries.
- Add comment.
|
| 1.28.8.1 | 12-May-2019 |
martin | Pull up following revision(s) (requested by maxv in ticket #1260):
common/lib/libc/sys/cpuset.c: revision 1.21
usr.sbin/cpuctl/cpuctl.c: revision 1.30
Fix bug, the computation of cpuset_nentries was incorrect, we must do +1
to be able to address the last 32 bits.
On a machine with 80 CPUs, this caused "cpuctl identify >64" to return
garbage.
Check the return value of cpuset_set(), to prevent future surprises.
|
| 1.29.4.2 | 21-Apr-2020 |
martin | Sync with HEAD
|
| 1.29.4.1 | 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.30.2.2 | 23-Aug-2023 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #1724):
usr.sbin/cpuctl/cpuctl.8: revision 1.21
usr.sbin/cpuctl/cpuctl.c: revision 1.33
Unless -v is given, ignore EEXIST errors from the IOC_CPU_UCODE_APPLY ioctl()
used to implement "cpuctl ucode N", which indicates that the microcode
to be loaded already exists in the CPU, and as such, isn't really a
very interesting "error".
|
| 1.30.2.1 | 10-Jul-2020 |
martin | Pull up the following revisions (all via patch) requested by msaitoh in
ticket #995:
usr.sbin/cpuctl/Makefile 1.9
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.5
usr.sbin/cpuctl/arch/i386.c 1.111-1.113
usr.sbin/cpuctl/cpuctl.c 1.31
usr.sbin/cpuctl/cpuctl.h 1.7
sys/arch/x86/x86/identcpu_subr.c 1.1-1.7
- Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel
processors.
- Add 0xa5 and 0xa6 for Comet Lake.
- Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
ci_max_ext_cpuid to match x86/include/cpu.h. No functional change.
- Sort some entries.
- Add comment.
|
| 1.32.2.1 | 23-Aug-2023 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #339):
usr.sbin/cpuctl/cpuctl.8: revision 1.21
usr.sbin/cpuctl/cpuctl.c: revision 1.33
Unless -v is given, ignore EEXIST errors from the IOC_CPU_UCODE_APPLY ioctl()
used to implement "cpuctl ucode N", which indicates that the microcode
to be loaded already exists in the CPU, and as such, isn't really a
very interesting "error".
|
| 1.7 | 21-Apr-2020 |
msaitoh | Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.
- If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors
can take TSC/core crystal clock ratio but core crystal clock frequency
can't be taken. Intel SDM give us the values for some processors.
- It also required to change lapic_per_second to make LAPIC timer correctly.
- Add new file x86/x86/identcpu_subr.c to share common subroutines between
kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c
will be moved to this file in future.
- Add comment to clarify.
|
| 1.6 | 16-Jan-2018 |
mrg | branches: 1.6.4; 1.6.6;
implement cpuctl identify for sparc and sparc64.
sparc:
- move enum vactype and struct cacheinfo into cpu.h
- move the cache flags from cpuinfo.flags into CACHEINFO.c_flags
(this allows the new cache_printf_backend() to see them.)
remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA.
- align xmpsg to 64 bytes
- move cache_print() into cache_print.h so it can be shared with
cpuctl. it only depends upon a working printf().
- if found, store the CPU node's "name" into cpu_longname. this
changes the default output to show the local CPU not the
generic CPU family. eg:
cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU
vs the generic "RT620/625" previously shown.
- for each CPU export these things:
- name
- fpuname
- mid
- cloc
- freq
- psr impl and version
- mmu impl, version, and number of contexts
- cacheinfo structure (which changed for the first time ever
with this commit.)
sparc64:
- add a minimal "cacheinfo" structure to export the i/d/e-cache
size and linesize.
- store %ver, cpu node "name" and cacheinfo in cpu_info.
- set cpu_info ver, name and cacheinfo in cpu_attach(), and
export them via sysctl, as well as CPU ID and clock freq
cpuctl:
- add identifycpu_bind() that returns false on !x86 as their
identify routines do not need to run on a particular CPU to
obtain its information, and use it to avoid trying to set
affinity when not needed.
- add sparc and sparc64 cpu identify support using the newly
exported values.
|
| 1.5 | 23-Dec-2013 |
msaitoh | branches: 1.5.18;
Add verbose flag.
On x86 cpu, cpuctl -v identify dumps the return values of the cpuid
functions. The max levels are taken from CPUID 0 and CPUID 8000_0000.
It's useful for the future CPU.
|
| 1.4 | 29-Aug-2012 |
drochner | branches: 1.4.2;
Extend the CPU microcode update framework to support Intel x86 CPUs.
Contrary to the AMD implementation, it doesn't use xcalls to distribute
the update to all CPUs but relies on cpuctl(8) to bind itself to the
right CPU -- to keep it simple and avoid possible problems with
hyperthreading.
Also, it doesn't parse the vendor supplied file to pick the right
part for the present CPU model but relies on userland to prepare
files with specific filenames. I'll commit a pkg for this in a minute
(pkgsrc/sysutils/intel-microcode).
The ioctl interface changed; compatibility is provided (should be
limited to COMPAT_NETBSD6 as soon as this is available).
|
| 1.3 | 15-Mar-2012 |
joerg | Add __printflike attribution to use vprintf and friends with an argument
as format string.
|
| 1.2 | 16-Dec-2008 |
christos | branches: 1.2.8; 1.2.10;
Remove 3rd buggy copy of this function and use snprintb(3) instead.
No need to allocate MAXPATHLEN buffers anymore.
|
| 1.1 | 05-May-2008 |
ad | branches: 1.1.4; 1.1.8;
PR port-amd64/37461 x86 cpu dmesg output is noisy
Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.
|
| 1.1.8.1 | 23-Dec-2008 |
snj | Pull up following revision(s) (requested by christos in ticket #193):
usr.sbin/cpuctl/Makefile: revision 1.3
usr.sbin/cpuctl/bitmask.c: file removal
usr.sbin/cpuctl/cpuctl.h: revision 1.2
usr.sbin/cpuctl/arch/i386.c: revision 1.14
Remove 3rd buggy copy of this function and use snprintb(3) instead.
No need to allocate MAXPATHLEN buffers anymore.
|
| 1.1.4.2 | 18-May-2008 |
yamt | sync with head.
|
| 1.1.4.1 | 05-May-2008 |
yamt | file cpuctl.h was added on branch yamt-pf42 on 2008-05-18 12:36:14 +0000
|
| 1.2.10.1 | 16-Jan-2015 |
snj | Pull up following revision(s) (requested by msaitoh in ticket #1230):
usr.sbin/cpuctl/cpuctl.8: revisions 1.9-1.12
usr.sbin/cpuctl/cpuctl.c: revisions 1.22-1.23 and 1.25 via patch
usr.sbin/cpuctl/cpuctl.h: revision 1.5 via patch
usr.sbin/cpuctl/arch/cpuctl_i386.h: revisions 1.1-1.2
usr.sbin/cpuctl/arch/i386-asm.S: revisions 1.2-1.3
usr.sbin/cpuctl/arch/i386.c: revisions 1.34, 1.36-1.49, 1.51-1.63 via patch
usr.sbin/cpuctl/arch/x86_64-asm.S: revisions 1.3-1.4
Update cpuctl(8). Microcode and ARM related changes are not included:
- Change the i386 asm x86_identify() so it returns a value instead of
writing into global data. Fix a stack alignment fubar that would
cause a crash on a cirix 486. Refactor identify code to common setup
for normal identify and ucode identify - which was missing a
memset().
- The Intel and AMD docs (more or less) agree on how the cpuid
'extended family' and 'extended model' bits are used to create
larger values than the original 16bit value allowed for.
Calculate and save these values 'up-front' and use them throughout.
Untangle the (backwards) nested switch statement for amd 'model 15'
cpus.
- Use full model number to index name strings - a lot of 256 element
arrays don't matter in usespace.
- Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually
identifies the cpu is output first.
- Only complain about binding if we have more than 1 cpu.
- Check cpuid leaf 4 for newer Intel CPU to know the cache information.
- Support prefetch size.
- Print the highest extended info level as the basic info level.
- Update URL of AMD's web page.
- Add code to detect hypervisor. The code was based from FreeBSD and
ported by Kengo Nakahara.
- Add verbose flag.
- Add newline if ci_tsc_freq is 0 to not to break the output.
- Update Intel's processor family names and models.
- Print some more bits.
- Add shared TLB
- Add prototypes.
- Add comments.
- Make some functions static.
- Sort functions.
- KNF.
|
| 1.2.8.3 | 22-May-2014 |
yamt | sync with head.
for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.
this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
|
| 1.2.8.2 | 30-Oct-2012 |
yamt | sync with head
|
| 1.2.8.1 | 17-Apr-2012 |
yamt | sync with head
|
| 1.4.2.1 | 20-Aug-2014 |
tls | Rebase to HEAD as of a few days ago.
|
| 1.5.18.1 | 05-Aug-2020 |
martin | Pull up the following revisions, requested by msaitoh in ticket #1585:
usr.sbin/cpuctl/Makefile 1.9
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.5
usr.sbin/cpuctl/arch/i386.c 1.111-1.113 via patch
usr.sbin/cpuctl/cpuctl.c 1.31
usr.sbin/cpuctl/cpuctl.h 1.7
sys/arch/x86/x86/identcpu_subr.c 1.1-1.7
- Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel
processors.
- Add 0xa5 and 0xa6 for Comet Lake.
- Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
ci_max_ext_cpuid to match x86/include/cpu.h. No functional change.
- Sort some entries.
- Add comment.
|
| 1.6.6.1 | 10-Jul-2020 |
martin | Pull up the following revisions (all via patch) requested by msaitoh in
ticket #995:
usr.sbin/cpuctl/Makefile 1.9
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.5
usr.sbin/cpuctl/arch/i386.c 1.111-1.113
usr.sbin/cpuctl/cpuctl.c 1.31
usr.sbin/cpuctl/cpuctl.h 1.7
sys/arch/x86/x86/identcpu_subr.c 1.1-1.7
- Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel
processors.
- Add 0xa5 and 0xa6 for Comet Lake.
- Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
ci_max_ext_cpuid to match x86/include/cpu.h. No functional change.
- Sort some entries.
- Add comment.
|
| 1.6.4.1 | 21-Apr-2020 |
martin | Sync with HEAD
|
| 1.25 | 07-Oct-2024 |
jakllsch | CPU ID strings for Arm Cortex-A710, Neoverse V1, Neoverse N2, and Fujitsu A64FX
|
| 1.24 | 27-Sep-2024 |
jakllsch | add Ampere 1 and 1A
|
| 1.23 | 07-Feb-2024 |
msaitoh | branches: 1.23.2;
Remove ryo@'s mail addresses.
|
| 1.22 | 03-Feb-2023 |
skrll | MPIDR is 64bits. Without this AFF3 would always be zero.
Spotted by Cyprien.
|
| 1.21 | 30-Apr-2022 |
ryo | branches: 1.21.2;
add CPU_ID_APPLE_M1_ICESTORM and CPU_ID_APPLE_M1_FIRESTORM.
sync cpuids[] to sys/arch/aarch64/aarch64/cpu.c r1.69
|
| 1.20 | 06-Jan-2022 |
ryo | display the raw value of each field when -v specified
|
| 1.19 | 06-Jan-2022 |
ryo | fix typo
|
| 1.18 | 06-Jan-2022 |
ryo | Added more field definitions for ARMv8.x system registers
|
| 1.17 | 06-Jan-2022 |
ryo | macroify. NFC.
|
| 1.16 | 05-Jan-2022 |
ryo | fix ID_AA64ISAR0_EL1.ATOMIC field definition
|
| 1.15 | 17-May-2021 |
riastradh | Teach cpuctl(8) about some additional aarch64 feature bits.
(Descriptions for CSV3 and CSV2 are not very good, but the blurbs in
the arm arm are an entire paragraph long each. Please fix if you have
a conciser summary!)
|
| 1.14 | 16-Jan-2021 |
jmcneill | branches: 1.14.2;
ID_AA64PFR0_EL1.GIC=0 means that the CPU interface system registers are
not implemented. This does not necessarily mean that there is no GIC in the
system, as GICv2 uses MMIO instead of system registers for the CPU
interface.
While here, add description for GIC=3, which means that the v4.1 system
register interface is supported.
|
| 1.13 | 04-Jan-2021 |
ryo | sync cpuids[] of sys/arch/aarch64/aarch64/cpu.c r1.43
|
| 1.12 | 10-Oct-2020 |
jmcneill | Report half-precision FP and SIMD support
|
| 1.11 | 05-Jul-2020 |
riastradh | (cpuctl/aarch64) Add some more aa64isar0_eli1 flags.
|
| 1.10 | 01-Jul-2020 |
ryo | show clidr_el1 and ctr_el0.
|
| 1.9 | 10-May-2020 |
riastradh | Teach cpuctl(8) about ARMv8.5-RNG RNDR/RNDRRS support.
|
| 1.8 | 28-Jan-2020 |
maxv | More identification.
|
| 1.7 | 09-May-2019 |
mrg | add cortex A-76 detection.
|
| 1.6 | 23-Jan-2019 |
skrll | Fix mvfr0.fptrap = 0 description
|
| 1.5 | 20-Dec-2018 |
ryo | - show detail of debug feature register (ID_AA64DFR0_EL1)
- print raw value of registers when verbose flag is set.
- keep forward compatibility. read kernel's aarch64_sysctl_cpu_id, but avoid unknown system registers.
|
| 1.4 | 26-Nov-2018 |
ryo | Add ThunderX IDs
|
| 1.3 | 20-Nov-2018 |
mrg | rewrite the CPU identification on arm64:
- publish per-cpu data
- publish a whole bunch of info in struct aarch64_sysctl_cpu_id
instead of various individual nodes (there are 16 total.)
- add MIDR extractor bits
- define ARMv8.2-A id_aa64mmfr2_el1 and id_aa64zfr0_el1 regs,
but avoid using them until we make sure they exist. (these
members are added to aarch64_sysctl_cpu_id to avoid future
compat issues.)
the arm32 and aarch32 version of these need to be adjusted as
well (and aarch32 data published at all.) still trying to
work out how to make the same userland binary running on a
real arm32 or an aarch32 system can work sanely here.
ok ryo@.
|
| 1.2 | 08-May-2018 |
ryo | branches: 1.2.2; 1.2.4;
TGran64 indication was actually the opposite
|
| 1.1 | 03-May-2018 |
ryo | add aarch64 support for cpuctl identify.
|
| 1.2.4.2 | 08-Apr-2020 |
martin | Merge changes from current as of 20200406
|
| 1.2.4.1 | 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.2.2.5 | 26-Jan-2019 |
pgoyette | Sync with HEAD
|
| 1.2.2.4 | 26-Dec-2018 |
pgoyette | Sync with HEAD, resolve a few conflicts
|
| 1.2.2.3 | 26-Nov-2018 |
pgoyette | Sync with HEAD, resolve a couple of conflicts
|
| 1.2.2.2 | 21-May-2018 |
pgoyette | Sync with HEAD
|
| 1.2.2.1 | 08-May-2018 |
pgoyette | file aarch64.c was added on branch pgoyette-compat on 2018-05-21 04:36:19 +0000
|
| 1.14.2.1 | 31-May-2021 |
cjep | sync with head
|
| 1.21.2.2 | 03-Oct-2024 |
martin | Pull up following revision(s) (requested by jakllsch in ticket #922):
sys/arch/aarch64/aarch64/cpu.c: revision 1.79
sys/arch/arm/include/cputypes.h: revision 1.17
usr.sbin/cpuctl/arch/aarch64.c: revision 1.24
sys/arch/aarch64/aarch64/cpu.c: revision 1.80
Add Ampere 1 and 1A CPU IDs
refine previous
add Ampere 1 and 1A
|
| 1.21.2.1 | 20-Sep-2024 |
martin | Pull up following revision(s) (requested by rin in ticket #869):
usr.sbin/cpuctl/arch/aarch64.c: revision 1.22
sys/arch/aarch64/aarch64/cpu.c: revision 1.73
Remove useless/harmful casts in debug messages. MPIDR AFF3 would not
be printed before.
MPIDR is 64bits. Without this AFF3 would always be zero.
Spotted by Cyprien.
|
| 1.23.2.1 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.8 | 04-Jun-2025 |
martin | Simplify previous, pointed out by kre@
|
| 1.7 | 03-Jun-2025 |
martin | Make cpuctl identify print something for old arm where the kernel does
not provide the required data.
|
| 1.6 | 06-Aug-2022 |
andvar | branches: 1.6.4;
s/blity/bility/ in various words, mainly in comments.
|
| 1.5 | 05-Dec-2021 |
msaitoh | auxilary -> auxiliary
|
| 1.4 | 16-Jan-2021 |
jmcneill | trailing whitespace
|
| 1.3 | 03-Feb-2019 |
mrg | - enlarge buffer to avoid snprintf() truncation
|
| 1.2 | 16-Jan-2018 |
mrg | branches: 1.2.4;
implement cpuctl identify for sparc and sparc64.
sparc:
- move enum vactype and struct cacheinfo into cpu.h
- move the cache flags from cpuinfo.flags into CACHEINFO.c_flags
(this allows the new cache_printf_backend() to see them.)
remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA.
- align xmpsg to 64 bytes
- move cache_print() into cache_print.h so it can be shared with
cpuctl. it only depends upon a working printf().
- if found, store the CPU node's "name" into cpu_longname. this
changes the default output to show the local CPU not the
generic CPU family. eg:
cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU
vs the generic "RT620/625" previously shown.
- for each CPU export these things:
- name
- fpuname
- mid
- cloc
- freq
- psr impl and version
- mmu impl, version, and number of contexts
- cacheinfo structure (which changed for the first time ever
with this commit.)
sparc64:
- add a minimal "cacheinfo" structure to export the i/d/e-cache
size and linesize.
- store %ver, cpu node "name" and cacheinfo in cpu_info.
- set cpu_info ver, name and cacheinfo in cpu_attach(), and
export them via sysctl, as well as CPU ID and clock freq
cpuctl:
- add identifycpu_bind() that returns false on !x86 as their
identify routines do not need to run on a particular CPU to
obtain its information, and use it to avoid trying to set
affinity when not needed.
- add sparc and sparc64 cpu identify support using the newly
exported values.
|
| 1.1 | 31-Jan-2013 |
matt | branches: 1.1.4; 1.1.10;
Add arm support for cpuctl identify
|
| 1.1.10.2 | 22-May-2014 |
yamt | sync with head.
for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.
this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
|
| 1.1.10.1 | 31-Jan-2013 |
yamt | file arm.c was added on branch yamt-pagecache on 2014-05-22 11:43:02 +0000
|
| 1.1.4.2 | 25-Feb-2013 |
tls | resync with head
|
| 1.1.4.1 | 31-Jan-2013 |
tls | file arm.c was added on branch tls-maxphys on 2013-02-25 00:30:42 +0000
|
| 1.2.4.1 | 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.6.4.1 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.6 | 07-Oct-2021 |
msaitoh | Move some common functions into x86/identcpu_subr.c. No functional change.
|
| 1.5 | 21-Apr-2020 |
msaitoh | Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.
- If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors
can take TSC/core crystal clock ratio but core crystal clock frequency
can't be taken. Intel SDM give us the values for some processors.
- It also required to change lapic_per_second to make LAPIC timer correctly.
- Add new file x86/x86/identcpu_subr.c to share common subroutines between
kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c
will be moved to this file in future.
- Add comment to clarify.
|
| 1.4 | 21-May-2019 |
mlelstv | branches: 1.4.2;
All MSRs can only be read at privilege level 0. The exact APIC ID cannot
be determined on some AMD CPUs.
|
| 1.3 | 10-May-2019 |
mlelstv | Get CPU topology data for AMD processors.
|
| 1.2 | 07-Jan-2013 |
dsl | branches: 1.2.2; 1.2.6; 1.2.14; 1.2.28; 1.2.36;
Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually identifies
the cpu is output first.
|
| 1.1 | 05-Jan-2013 |
dsl | Change the i386 asm x86_identify() so it returns a value instead of writing
into global data.
Fix a stack alignment fubar that would cause a crash on a cirix 486.
Refactor identify code to common setup for normal identify and ucode
identify - which was missing a memset().
|
| 1.2.36.2 | 21-Apr-2020 |
martin | Sync with HEAD
|
| 1.2.36.1 | 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.2.28.2 | 24-Dec-2021 |
martin | Pull up the following (all via patch), requested by msaitoh in ticket #1721:
usr.sbin/cpuctl/arch/i386.c 1.118-1.119, 1.121-1.122
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.6
sys/arch/x86/x86/identcpu_subr.c 1.8-1.9
sys/arch/x86/x86/identcpu.c 1.123
sys/arch/x86/include/cacheinfo.h 1.30
sys/arch/x86/include/cpu.h 1.132
- Fix a bug that some TLB related lines were not printed.
- Fix a bug that STLB is printed as DTLB.
- If a TLB is variable sized, print the max size instead of error message.
- Cosmetic changes to improve readability.
|
| 1.2.28.1 | 05-Aug-2020 |
martin | Pull up the following revisions, requested by msaitoh in ticket #1585:
usr.sbin/cpuctl/Makefile 1.9
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.5
usr.sbin/cpuctl/arch/i386.c 1.111-1.113 via patch
usr.sbin/cpuctl/cpuctl.c 1.31
usr.sbin/cpuctl/cpuctl.h 1.7
sys/arch/x86/x86/identcpu_subr.c 1.1-1.7
- Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel
processors.
- Add 0xa5 and 0xa6 for Comet Lake.
- Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
ci_max_ext_cpuid to match x86/include/cpu.h. No functional change.
- Sort some entries.
- Add comment.
|
| 1.2.14.2 | 16-Jan-2015 |
snj | Pull up following revision(s) (requested by msaitoh in ticket #1230):
usr.sbin/cpuctl/cpuctl.8: revisions 1.9-1.12
usr.sbin/cpuctl/cpuctl.c: revisions 1.22-1.23 and 1.25 via patch
usr.sbin/cpuctl/cpuctl.h: revision 1.5 via patch
usr.sbin/cpuctl/arch/cpuctl_i386.h: revisions 1.1-1.2
usr.sbin/cpuctl/arch/i386-asm.S: revisions 1.2-1.3
usr.sbin/cpuctl/arch/i386.c: revisions 1.34, 1.36-1.49, 1.51-1.63 via patch
usr.sbin/cpuctl/arch/x86_64-asm.S: revisions 1.3-1.4
Update cpuctl(8). Microcode and ARM related changes are not included:
- Change the i386 asm x86_identify() so it returns a value instead of
writing into global data. Fix a stack alignment fubar that would
cause a crash on a cirix 486. Refactor identify code to common setup
for normal identify and ucode identify - which was missing a
memset().
- The Intel and AMD docs (more or less) agree on how the cpuid
'extended family' and 'extended model' bits are used to create
larger values than the original 16bit value allowed for.
Calculate and save these values 'up-front' and use them throughout.
Untangle the (backwards) nested switch statement for amd 'model 15'
cpus.
- Use full model number to index name strings - a lot of 256 element
arrays don't matter in usespace.
- Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually
identifies the cpu is output first.
- Only complain about binding if we have more than 1 cpu.
- Check cpuid leaf 4 for newer Intel CPU to know the cache information.
- Support prefetch size.
- Print the highest extended info level as the basic info level.
- Update URL of AMD's web page.
- Add code to detect hypervisor. The code was based from FreeBSD and
ported by Kengo Nakahara.
- Add verbose flag.
- Add newline if ci_tsc_freq is 0 to not to break the output.
- Update Intel's processor family names and models.
- Print some more bits.
- Add shared TLB
- Add prototypes.
- Add comments.
- Make some functions static.
- Sort functions.
- KNF.
|
| 1.2.14.1 | 07-Jan-2013 |
snj | file cpuctl_i386.h was added on branch netbsd-6 on 2015-01-16 08:32:25 +0000
|
| 1.2.6.2 | 25-Feb-2013 |
tls | resync with head
|
| 1.2.6.1 | 07-Jan-2013 |
tls | file cpuctl_i386.h was added on branch tls-maxphys on 2013-02-25 00:30:42 +0000
|
| 1.2.2.2 | 23-Jan-2013 |
yamt | sync with head
|
| 1.2.2.1 | 07-Jan-2013 |
yamt | file cpuctl_i386.h was added on branch yamt-pagecache on 2013-01-23 00:06:41 +0000
|
| 1.4.2.2 | 24-Dec-2021 |
martin | Pull up the following (all via patch), requested by msaitoh in ticket #1396:
usr.sbin/cpuctl/arch/i386.c 1.118-1.119, 1.121-1.122
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.6
sys/arch/x86/x86/identcpu_subr.c 1.8-1.9
sys/arch/x86/x86/identcpu.c 1.123
sys/arch/x86/include/cacheinfo.h 1.30
sys/arch/x86/include/cpu.h 1.132
- Fix a bug that some TLB related lines were not printed.
- Fix a bug that STLB is printed as DTLB.
- If a TLB is variable sized, print the max size instead of error message.
- Cosmetic changes to improve readability.
|
| 1.4.2.1 | 10-Jul-2020 |
martin | Pull up the following revisions (all via patch) requested by msaitoh in
ticket #995:
usr.sbin/cpuctl/Makefile 1.9
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.5
usr.sbin/cpuctl/arch/i386.c 1.111-1.113
usr.sbin/cpuctl/cpuctl.c 1.31
usr.sbin/cpuctl/cpuctl.h 1.7
sys/arch/x86/x86/identcpu_subr.c 1.1-1.7
- Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel
processors.
- Add 0xa5 and 0xa6 for Comet Lake.
- Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
ci_max_ext_cpuid to match x86/include/cpu.h. No functional change.
- Sort some entries.
- Add comment.
|
| 1.7 | 21-May-2019 |
mlelstv | All MSRs can only be read at privilege level 0. The exact APIC ID cannot
be determined on some AMD CPUs.
|
| 1.6 | 11-May-2019 |
mlelstv | Fix copy&paste error, the function is named rdmsr().
Found by kre@
|
| 1.5 | 10-May-2019 |
mlelstv | Get CPU topology data for AMD processors.
|
| 1.4 | 01-Mar-2015 |
tnn | branches: 1.4.16;
xgetbv expects XCR0 to be speficied in %ecx, don't leave %ecx undefined
|
| 1.3 | 07-Jan-2013 |
dsl | branches: 1.3.8;
Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually identifies
the cpu is output first.
|
| 1.2 | 05-Jan-2013 |
dsl | Change the i386 asm x86_identify() so it returns a value instead of writing
into global data.
Fix a stack alignment fubar that would cause a crash on a cirix 486.
Refactor identify code to common setup for normal identify and ucode
identify - which was missing a memset().
|
| 1.1 | 05-May-2008 |
ad | branches: 1.1.4; 1.1.6; 1.1.24; 1.1.28;
PR port-amd64/37461 x86 cpu dmesg output is noisy
Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.
|
| 1.1.28.1 | 25-Feb-2013 |
tls | resync with head
|
| 1.1.24.2 | 24-Mar-2015 |
snj | Pull up following revision(s) (requested by tnn in ticket #1266):
usr.sbin/cpuctl/arch/i386-asm.S: revision 1.4
usr.sbin/cpuctl/arch/x86_64-asm.S: revision 1.5
xgetbv expects XCR0 to be speficied in %ecx, don't leave %ecx undefined
|
| 1.1.24.1 | 16-Jan-2015 |
snj | Pull up following revision(s) (requested by msaitoh in ticket #1230):
usr.sbin/cpuctl/cpuctl.8: revisions 1.9-1.12
usr.sbin/cpuctl/cpuctl.c: revisions 1.22-1.23 and 1.25 via patch
usr.sbin/cpuctl/cpuctl.h: revision 1.5 via patch
usr.sbin/cpuctl/arch/cpuctl_i386.h: revisions 1.1-1.2
usr.sbin/cpuctl/arch/i386-asm.S: revisions 1.2-1.3
usr.sbin/cpuctl/arch/i386.c: revisions 1.34, 1.36-1.49, 1.51-1.63 via patch
usr.sbin/cpuctl/arch/x86_64-asm.S: revisions 1.3-1.4
Update cpuctl(8). Microcode and ARM related changes are not included:
- Change the i386 asm x86_identify() so it returns a value instead of
writing into global data. Fix a stack alignment fubar that would
cause a crash on a cirix 486. Refactor identify code to common setup
for normal identify and ucode identify - which was missing a
memset().
- The Intel and AMD docs (more or less) agree on how the cpuid
'extended family' and 'extended model' bits are used to create
larger values than the original 16bit value allowed for.
Calculate and save these values 'up-front' and use them throughout.
Untangle the (backwards) nested switch statement for amd 'model 15'
cpus.
- Use full model number to index name strings - a lot of 256 element
arrays don't matter in usespace.
- Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually
identifies the cpu is output first.
- Only complain about binding if we have more than 1 cpu.
- Check cpuid leaf 4 for newer Intel CPU to know the cache information.
- Support prefetch size.
- Print the highest extended info level as the basic info level.
- Update URL of AMD's web page.
- Add code to detect hypervisor. The code was based from FreeBSD and
ported by Kengo Nakahara.
- Add verbose flag.
- Add newline if ci_tsc_freq is 0 to not to break the output.
- Update Intel's processor family names and models.
- Print some more bits.
- Add shared TLB
- Add prototypes.
- Add comments.
- Make some functions static.
- Sort functions.
- KNF.
|
| 1.1.6.1 | 23-Jan-2013 |
yamt | sync with head
|
| 1.1.4.2 | 18-May-2008 |
yamt | sync with head.
|
| 1.1.4.1 | 05-May-2008 |
yamt | file i386-asm.S was added on branch yamt-pf42 on 2008-05-18 12:36:14 +0000
|
| 1.3.8.1 | 09-Mar-2015 |
snj | Pull up following revision(s) (requested by tnn in ticket #570):
usr.sbin/cpuctl/arch/i386-asm.S: revision 1.4
usr.sbin/cpuctl/arch/x86_64-asm.S: revision 1.5
xgetbv expects XCR0 to be speficied in %ecx, don't leave %ecx undefined
|
| 1.4.16.1 | 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.148 | 28-May-2025 |
andvar | s/padloack/padlock/ in padlock features line.
|
| 1.147 | 19-Oct-2024 |
msaitoh | cpuctl(x86): CPUID_AMDEXT2_L2TLBSIZEX32 also affects 1GB TLB size.
|
| 1.146 | 19-Oct-2024 |
msaitoh | cpuctl(x86): Calculate L2 TLB size using with CPUID_AMDEXT2_L2TLBSIZEX32.
It's required to calculate L2 TLB size correctly on Zen5.
|
| 1.145 | 19-Oct-2024 |
msaitoh | cpuctl(8): Print AMD's hetero workload classification.
|
| 1.144 | 08-Mar-2024 |
rillig | branches: 1.144.2;
cpuctl: fix i386 bit descriptions for CPUID_SEF_FLAGS1
warning: non-printing character '\31' in description
'BUS_LOCK_DETECT""b\31' [363]
|
| 1.143 | 10-Feb-2024 |
andvar | Fix various typos in comments, log messages and documentation.
|
| 1.142 | 18-Jan-2024 |
msaitoh | Add Meteor Lake and Emerald Rapids.
|
| 1.141 | 13-Sep-2023 |
wiz | tabify
|
| 1.140 | 12-Sep-2023 |
wiz | cpuctl: be more verbose about problems and diagnosing them
|
| 1.139 | 21-Jul-2023 |
msaitoh | Sort by number. No functional change.
|
| 1.138 | 06-Jul-2023 |
msaitoh | Add Alder Lake-N.
|
| 1.137 | 05-Jul-2023 |
msaitoh | CPU model 0x5a is not Atom E3500 but Atom Z3500.
|
| 1.136 | 14-Feb-2023 |
msaitoh | Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.
|
| 1.135 | 30-Dec-2022 |
msaitoh | Add Raptor Lake and Sapphire Rapids.
|
| 1.134 | 30-Dec-2022 |
msaitoh | Print cpuid 7 sub-leaf 1 %ebx, %edx and sub-leaf 2 %edx.
|
| 1.133 | 17-Nov-2022 |
msaitoh | branches: 1.133.2;
s/features 2/features2/
|
| 1.132 | 16-Nov-2022 |
msaitoh | s/Instruction-Based Sampling/IBS/
|
| 1.131 | 16-Nov-2022 |
msaitoh | Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug.
|
| 1.130 | 16-Nov-2022 |
msaitoh | Add CPUID Fn8000_0021 AMD Extended Features Identification 2.
|
| 1.129 | 16-Nov-2022 |
msaitoh | Print AMD RAS features and Instruction-Based Sampling features.
|
| 1.128 | 15-Jun-2022 |
msaitoh | Modify output of CPUID Fn0000000a.
old:
cpu0: Perfmon-eax 0x8300805<VERSION=0x5,GPCounter=0x8,GPBitwidth=0x30>
cpu0: Perfmon-eax 0x8300805<Vectorlen=0x8>
cpu0: Perfmon-edx 0x8604<FixedFunc=0x4,FFBitwidth=0x30,ANYTHREADDEPR>
new:
cpu0: Perfmon: Ver. 5
cpu0: Perfmon: General: bitwidth 48, 8 counters
cpu0: Perfmon: General: avail 0xff<CORECYCL,INST,REFCYCL,LLCREF,LLCMISS,BRINST>
cpu0: Perfmon: General: avail 0xff<BRMISPR,TOPDOWNSLOT>
cpu0: Perfmon: Fixed: bitwidth 48, 4 counters
cpu0: Perfmon: Fixed: avail 0xf<INST,CLK_CORETHREAD,CLK_REF_TSC,TOPDOWNSLOT>
|
| 1.127 | 29-Jan-2022 |
msaitoh | Decode Intel Hybrid Information Enumeration (CPUID Fn0000_001a).
|
| 1.126 | 27-Jan-2022 |
msaitoh | Remove debug code and simplify. No functional change.
|
| 1.125 | 13-Jan-2022 |
msaitoh | Add Alder Lake, Rocket Lake and Sapphire Rapids. From the latest Intel SDM.
|
| 1.124 | 09-Dec-2021 |
msaitoh | Print 1GB TLB entry at the same leve's line.
Example:
before:
cpu0: ITLB: 128 4KB entries 8-way, 2M/4M: 8 entries
cpu0: DTLB: 64 4KB entries 4-way
cpu0: L2 STLB: 4K/2M: 1024 entries
cpu0: L1 1GB page DTLB: 4 1GB entries 4-way
after:
cpu0: ITLB: 128 4KB entries 8-way, 2M/4M: 8 entries
cpu0: DTLB: 64 4KB entries 4-way, 4 1GB entries 4-way
cpu0: L2 STLB: 4K/2M: 1024 entries
|
| 1.123 | 27-Oct-2021 |
mrg | decode SMT parts for AMD family >= 0x17, not just 0x17.
now zen3 systems are properly identified by cpu topology for the
scheduler and cpuctl identify.
|
| 1.122 | 07-Oct-2021 |
msaitoh | Move some common functions into x86/identcpu_subr.c. No functional change.
|
| 1.121 | 27-Sep-2021 |
msaitoh | Improve variable sized TLB's output.
- Fix a bug that STLB is printed as DTLB.
- If a TLB is variable sized, print the max size instead of error message.
XXX This is temporary solution.
|
| 1.120 | 27-Sep-2021 |
msaitoh | Add Load Only TLB and Store Only TLB.
|
| 1.119 | 27-Sep-2021 |
msaitoh | Fix a bug that some TLB related lines were not printed.
|
| 1.118 | 27-Sep-2021 |
msaitoh | Add ':' for readability.
|
| 1.117 | 12-Jul-2021 |
msaitoh | Add 0x96(Elkhart Lake) and 0x9c(Jasper Lake).
Not listed in SDM but listed in those spec update documents.
|
| 1.116 | 10-Jul-2021 |
msaitoh | 0x6a and 0x6c are 3rd gen Xeon Scalable (Ice Lake).
|
| 1.115 | 24-Nov-2020 |
msaitoh | - Print CPUID 0x8000008 %ebx on Intel, too. Intel now supports WBNOINVD.
- Print CPUID leaf 7 subleaf 1.
|
| 1.114 | 05-Sep-2020 |
maxv | x86: fix several CPUID flags
- Rename: CPUID_PN -> CPUID_PSN
CPUID_CFLUSH -> CPUID_CLFSH
CPUID_SBF -> CPUID_PBE
CPUID_LZCNT -> CPUID_ABM
CPUID_P1GB -> CPUID_PAGE1GB
CPUID2_PCLMUL -> CPUID2_PCLMULQDQ
CPUID2_CID -> CPUID2_CNXTID
CPUID2_xTPR -> CPUID2_XTPR
CPUID2_AES -> CPUID2_AESNI
To match the x86 specification and the other OSes.
- Remove: CPUID_B10, CPUID_B20, CPUID_IA64. They do not exist.
|
| 1.113 | 01-Jun-2020 |
msaitoh | Add 0xa5 and 0xa6 for Comet Lake.
|
| 1.112 | 21-Apr-2020 |
msaitoh | Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.
- If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors
can take TSC/core crystal clock ratio but core crystal clock frequency
can't be taken. Intel SDM give us the values for some processors.
- It also required to change lapic_per_second to make LAPIC timer correctly.
- Add new file x86/x86/identcpu_subr.c to share common subroutines between
kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c
will be moved to this file in future.
- Add comment to clarify.
|
| 1.111 | 16-Apr-2020 |
msaitoh | No functional change:
- Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
ci_max_ext_cpuid to match x86/include/cpu.h though cpuctl/arch/i386.c added
them first.
- Sort some entries.
- Add comment.
|
| 1.110 | 06-Apr-2020 |
msaitoh | Print CPUID 0x80000007 %edx on both Intel and AMD.
|
| 1.109 | 06-Apr-2020 |
msaitoh | Remove ci_max_ext_cpuid because it's the same as ci_cpuid_extlevel.
|
| 1.108 | 17-Nov-2019 |
msaitoh | 0x7d and 0x7e are for 10th generation Core (Ice Lake).
|
| 1.107 | 03-Oct-2019 |
msaitoh | - Add definitions of AMD's CPUID Fn8000_001f Encrypted Memory features.
- Add definition of AMD's CPUID Fn8000_000a %edx bit 11 "GMET".
- Define CPUID_AMD_SVM_PFThreshold correctly.
- Modify comment a bit for consistency.
|
| 1.106 | 09-Sep-2019 |
msaitoh | Call cpu_dcp_cacheinfo() only when the cpuid Topology Extension flag is set
on AMD prcessor.
|
| 1.105 | 30-Aug-2019 |
msaitoh | Decode AMD's CPUID Fn8000_0008 %ebx.
|
| 1.104 | 26-Jul-2019 |
msaitoh | branches: 1.104.2;
- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
Intel Deterministic Cache Parameter Leaf(0x04), so make new
cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
common definition.
- KNF.
XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?
|
| 1.103 | 29-May-2019 |
msaitoh | White space fix. No functional change.
|
| 1.102 | 28-May-2019 |
msaitoh | Update from the latest Intel SDM:
- Add Cascade Lake, Copper Lake
- Add Future Xeon (Cannon Lake)
- Add 06_7DH for another Ice Lake
- Add Coffee Lake based Xeon E
|
| 1.101 | 28-May-2019 |
msaitoh | Revert previous (accidentally committed).
|
| 1.100 | 28-May-2019 |
msaitoh | Use ETHER_LOCK()/ETHER_UNLOCK() for all ethernet drivers to protect ec_multi*.
|
| 1.99 | 21-May-2019 |
mlelstv | All MSRs can only be read at privilege level 0. The exact APIC ID cannot
be determined on some AMD CPUs.
|
| 1.98 | 11-May-2019 |
kre | Undo previous. Not needed (and file included isn't installed anyway.
|
| 1.97 | 11-May-2019 |
christos | need cpufunc.h for rdmsr
|
| 1.96 | 10-May-2019 |
mlelstv | Get CPU topology data for AMD processors.
|
| 1.95 | 24-Mar-2019 |
msaitoh | Add HAXM.
|
| 1.94 | 22-Mar-2019 |
msaitoh | s/TGC/TCG/. Not Tokyo Game Show but Tiny Code Generator.
|
| 1.93 | 22-Mar-2019 |
msaitoh | - Dump CPUID leaf 0x40000000 if available (for -v option).
- Regard "TCGTCGTCGTCG" as QEMU(TGC).
|
| 1.92 | 05-Feb-2019 |
msaitoh | Add Ice Lake and Tremont from the latest Intel SDM.
|
| 1.91 | 06-Jan-2019 |
maxv | Handle the NVMM signature.
|
| 1.90 | 26-Nov-2018 |
msaitoh | Print Intel CPUID Architectural Performance Monitoring leaf Fn0000000a.
|
| 1.89 | 22-Nov-2018 |
msaitoh | Decode Intel/AMD MONITOR/MWAIT leaf.
|
| 1.88 | 21-Nov-2018 |
msaitoh | Decode package, core and SMT id if CPUID 0x0b is available on Intel processor.
If the value is different from the kernel value, we should fix the kernel code.
TODO: Use 0x1f if it's available.
|
| 1.87 | 21-Nov-2018 |
msaitoh | - AMD also reports CPUID 7's highest subleaf. Print it.
- Use macro.
|
| 1.86 | 21-Nov-2018 |
msaitoh | - Use ci_feat_val[7] as CPUID 7 %edx to match x86/cpu.h
- AMD also has CPUID 6.
- Remove unused code for coretemp.
- Consistently use descs[] instead of data[].
|
| 1.85 | 20-Jun-2018 |
msaitoh | branches: 1.85.2;
Whitespace fix. No functional change.
|
| 1.84 | 30-Mar-2018 |
msaitoh | From the latest Intel SDM:
- Add Xeon Phi 7215, 7285 and 7295
- Add Coffee Lake
|
| 1.83 | 09-Mar-2018 |
msaitoh | Add yet another Shared L2 TLB (2M/4M pages).
XXX need redesign.
|
| 1.82 | 05-Mar-2018 |
msaitoh | branches: 1.82.2;
Calculate way and number of entries correctly from CPUID leaf 18H.
|
| 1.81 | 05-Mar-2018 |
msaitoh | - Parse the TLB info from `cpuid leaf 18H' on Intel processor. Currently,
this change doesn't decode perfectly. Tested with Gemini Lake. It has
two L2 Shared TLB. One is 4MB and another is 2MB/4MB but former isn't
printed yet:
cpu0: ITLB 1 4KB entries 48-way
cpu0: DTLB 1 4KB entries 32-way
cpu0: L2 STLB 8 4MB entries 4-way
Need some rework for struct x86_cache_info.
- Use aprint_error_dev() for error output.
|
| 1.80 | 16-Jan-2018 |
mrg | implement cpuctl identify for sparc and sparc64.
sparc:
- move enum vactype and struct cacheinfo into cpu.h
- move the cache flags from cpuinfo.flags into CACHEINFO.c_flags
(this allows the new cache_printf_backend() to see them.)
remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA.
- align xmpsg to 64 bytes
- move cache_print() into cache_print.h so it can be shared with
cpuctl. it only depends upon a working printf().
- if found, store the CPU node's "name" into cpu_longname. this
changes the default output to show the local CPU not the
generic CPU family. eg:
cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU
vs the generic "RT620/625" previously shown.
- for each CPU export these things:
- name
- fpuname
- mid
- cloc
- freq
- psr impl and version
- mmu impl, version, and number of contexts
- cacheinfo structure (which changed for the first time ever
with this commit.)
sparc64:
- add a minimal "cacheinfo" structure to export the i/d/e-cache
size and linesize.
- store %ver, cpu node "name" and cacheinfo in cpu_info.
- set cpu_info ver, name and cacheinfo in cpu_attach(), and
export them via sysctl, as well as CPU ID and clock freq
cpuctl:
- add identifycpu_bind() that returns false on !x86 as their
identify routines do not need to run on a particular CPU to
obtain its information, and use it to avoid trying to set
affinity when not needed.
- add sparc and sparc64 cpu identify support using the newly
exported values.
|
| 1.79 | 10-Jan-2018 |
msaitoh | Print Intel cpuid 7 %edx.
Example output of cpuctl -v identify 0:
+cpu0: 00000007: 00000000 000027ab 00000000 0c000000
(snip)
+cpu0: SEF edx 0xc000000<IBRS,STIBP>
|
| 1.78 | 19-Oct-2017 |
msaitoh | Update from Intel SDM:
0x55: Xeon Scalable (Skylake)
0x57: Xeon Phi [357]200 (Knights Landing)
0x66: Future Core (Cannon Lake)
0x85: Future Xeon Phi (Knights Mill)
|
| 1.77 | 17-Oct-2017 |
msaitoh | Update from the latest Intel SDM:
0x5c: Atom (Goldmont)
0x5f: Atom (Goldmont, Denverton)
0x7a: Atom (Goldmont Plus)
|
| 1.76 | 16-Oct-2017 |
msaitoh | - Print ci_feat_val[5] (Structured Extended Feature leaf Fn0000_0007 %ebx) on
AMD, too.
- Print ci_feat_val[6] (Fn0000_0007 %ecx) on Intel.
|
| 1.75 | 07-Sep-2017 |
msaitoh | Define CPUID Fn00000001 %ebx bits and use them. No functional change.
|
| 1.74 | 11-Oct-2016 |
msaitoh | branches: 1.74.6;
Update from the latest Intel SDM:
- Denverton
- Future Xeon Phi
- 7th gen Core (Kaby Lake)
|
| 1.73 | 21-Jul-2016 |
msaitoh | Update processor families from the latest Intel SDM:
- 06_4FH: Add Xeon E7 v4 and Core i7-69xx Extreme Edition
- 06_57H: Xeon Phi [357]200
|
| 1.72 | 27-Apr-2016 |
msaitoh | branches: 1.72.2;
Add some name from the latest Intel SDM.
- Quark X1000, Xeon E5 v4 and the future processors.
|
| 1.71 | 27-Apr-2016 |
msaitoh | - Add structure extended feature registers into ci_feat_val[]. The locations
are the same as x86/include/cpu.h. Curreltly those values are not used yet.
- KNF.
|
| 1.70 | 08-Jan-2016 |
msaitoh | From the latest Intel SDM:
- Add Xeon E3-1200 v5
- Change 0x1c from "Atom Family" to "45nm Atom Family"
|
| 1.69 | 04-Dec-2015 |
msaitoh | Model 0x5e is also 6th gen Core or Xeon E3-1500 v5 like model 0x4e.
|
| 1.68 | 19-Oct-2015 |
msaitoh | Add 6th gen Core, Xeon E3-1500 v5 and Xeon D-1500 from the latest Intel SDM.
|
| 1.67 | 01-Jul-2015 |
msaitoh | Add Xeon E5-4600 v3, Xeon E3-1200 v4 etc. from the latest Intel SDM.
|
| 1.66 | 08-May-2015 |
msaitoh | Update some Intel CPU models (Sky Lake, Broadwell and Atom X[357]).
|
| 1.65 | 27-Mar-2015 |
msaitoh | Update from Intel SDM:
- Add Atom Z8000, Future gen Xeon (Broadwell), Next gen Xeon Phi and so on.
- Add comments.
|
| 1.64 | 11-Dec-2014 |
msaitoh | Don't print the microcode version if the ioctl failed to not to
print garbage.
|
| 1.63 | 11-Dec-2014 |
msaitoh | Add newline if ci_tsc_freq is 0 to not to break the output.
|
| 1.62 | 20-Nov-2014 |
msaitoh | Move some printf()s from cpu_probe_base_features() to identifycpu().
Those printf()s are used for "identify" command but cpu_probe_base_features()
is shared by ucodeupdate_check(), too. This change fixes a problem that
the "ucode" command print extra output.
|
| 1.61 | 11-Nov-2014 |
skrll | kern/49379: Hypervisor's name typo
|
| 1.60 | 07-Nov-2014 |
msaitoh | Add code to detect hypervisor. The code was based from FreeBSD and ported
by Kengo Nakahara.
|
| 1.59 | 09-Sep-2014 |
msaitoh | Update CPUID signature values from the latest Intel SDM.
- Core M-5xxx
- Core i7 extreme
- Future Core (0x4e)
- Future Xeon (0x56)
|
| 1.58 | 25-Jul-2014 |
msaitoh | branches: 1.58.2;
More update:
- Future Atom E3000, Z3000 (0x4a, 0x5a, 0x5d)
- Atom C2000 (0x4d)
|
| 1.57 | 25-Jul-2014 |
msaitoh | Update table for processor families and processor number series from the
latest Intel SDM.
- Atom Z3000 (0x37)
- Core M based on Broadwell (0x3d)
- Next gen Xeon based on Haswell (0x3f)
|
| 1.56 | 03-Jul-2014 |
msaitoh | Exclude descriptor 0xff of CPUID leaf 2. 0xff means the cacheinfo is in leaf 4.
|
| 1.55 | 27-May-2014 |
msaitoh | If -v is set and unknown cacheinfo desc is found, print it.
|
| 1.54 | 04-Jan-2014 |
msaitoh | branches: 1.54.2;
- Rename x86_print_cacheinfo() to x86_print_cache_and_tlb_info() because
this function prints TLB info, too.
- Remove an extra printf when verbose flag is set.
- Print the highest extended info level as the basic info level.
- Sort function.
|
| 1.53 | 23-Dec-2013 |
msaitoh | Add verbose flag.
On x86 cpu, cpuctl -v identify dumps the return values of the cpuid
functions. The max levels are taken from CPUID 0 and CPUID 8000_0000.
It's useful for the future CPU.
|
| 1.52 | 23-Dec-2013 |
msaitoh | CPUID leaf 2 and 4 are only for Intel processors.
|
| 1.51 | 23-Dec-2013 |
msaitoh | Add comments. Remove comments. No functional change.
|
| 1.50 | 15-Nov-2013 |
msaitoh | Modify some macros and add some new macros for CPU family and model
to reduce code duplication and to avoid bug.
CPUID_TO_STEPPING(cpuid) (not changed)
CPUID_TO_FAMILY(cpuid) (new)
CPUID_TO_MODEL(cpuid) (new)
Return the display family and the display model.
The macro names are the same as FreeBSD.
CPUID_TO_BASEFAMILY(cpuid) (The old name was CPUID2FAMILY)
CPUID_TO_BASEMODEL(cpuid) (The old name was CPUID2MODEL)
Only for the base field.
CPUID_TO_EXTFAMILY(cpuid) (The old name was CPUID2EXTFAMILY)
CPUID_TO_EXTMODEL(cpuid) (The old name was CPUID2EXTMODEL)
Only for the extended field.
See http://mail-index.netbsd.org/port-amd64/2013/11/12/msg001978.html
|
| 1.49 | 07-Nov-2013 |
msaitoh | Fix typo. From jnemeth.
|
| 1.48 | 07-Nov-2013 |
msaitoh | Update some processor names.
|
| 1.47 | 30-Oct-2013 |
mrg | avoid uninitialised variable use.
|
| 1.46 | 28-Oct-2013 |
msaitoh | Support prefetch size.
|
| 1.45 | 21-Oct-2013 |
msaitoh | Check cpuid leaf 4 for newer Intel CPU to know the cache information.
|
| 1.44 | 21-Oct-2013 |
msaitoh | No functional change:
- Add prototypes.
- Make some function static.
- Sort functions.
|
| 1.43 | 04-Oct-2013 |
msaitoh | Fix typo in comment (s/XRC0/XCR0/).
|
| 1.42 | 14-Sep-2013 |
msaitoh | Add shared TLB.
KNF.
|
| 1.41 | 13-Sep-2013 |
msaitoh | Update Intel processors' brand names and model names (e.g. Atom C2000 and
E3000) from the latest document.
|
| 1.40 | 16-Jul-2013 |
msaitoh | Update Intel's Processor Family Names of family == 6 from the latest document.
Add 0x35(Atom), 0x36(Atom S), 0x3f(future Xeon), 0x46(Haswell) and update some
models.
|
| 1.39 | 06-Mar-2013 |
yamt | print some more bits
|
| 1.38 | 07-Jan-2013 |
dsl | Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually identifies
the cpu is output first.
|
| 1.37 | 06-Jan-2013 |
dsl | Use full model number to index name strings - a lot of 256 element arrays
don't matter in usespace.
Update list of intel family 6 model names (all current cpus) to include
everything upto and including sandy bridge and ivy bridge.
My i7 is no longer reported as a random P II.
|
| 1.36 | 05-Jan-2013 |
dsl | The Intel and AMD docs (more or less) agree on how the cpuid 'extended
family' and 'extended model' bits are used to create larger values
than the original 16bit value allowed for.
Calculate and save these values 'up-front' and use them throughout.
Untangle the (backwards) nested switch statement for amd 'model 15' cpus.
Works as badly as ever on my i7.
|
| 1.35 | 05-Jan-2013 |
dsl | If the IOC_CPU_UCODE_GET_VERSION fails with ENOTTY, try issuing the
request that the amd64 kernel understands.
|
| 1.34 | 05-Jan-2013 |
dsl | Change the i386 asm x86_identify() so it returns a value instead of writing
into global data.
Fix a stack alignment fubar that would cause a crash on a cirix 486.
Refactor identify code to common setup for normal identify and ucode
identify - which was missing a memset().
|
| 1.33 | 02-Jan-2013 |
dsl | #include sys/ioctl.h
|
| 1.32 | 29-Aug-2012 |
drochner | branches: 1.32.2;
Extend the CPU microcode update framework to support Intel x86 CPUs.
Contrary to the AMD implementation, it doesn't use xcalls to distribute
the update to all CPUs but relies on cpuctl(8) to bind itself to the
right CPU -- to keep it simple and avoid possible problems with
hyperthreading.
Also, it doesn't parse the vendor supplied file to pick the right
part for the present CPU model but relies on userland to prepare
files with specific filenames. I'll commit a pkg for this in a minute
(pkgsrc/sysutils/intel-microcode).
The ioctl interface changed; compatibility is provided (should be
limited to COMPAT_NETBSD6 as soon as this is available).
|
| 1.31 | 17-Apr-2012 |
cegger | print cpu family for AMD CPU families 0x12 - 0x15
|
| 1.30 | 05-Apr-2012 |
cegger | report l3 cache information on AMD Family 10h and newer processors
|
| 1.29 | 02-Mar-2012 |
sborrill | Print CPU stepping level
|
| 1.28 | 29-Feb-2012 |
joerg | Use uintmax_t for freqency computations to avoid differences between
platforms.
|
| 1.27 | 03-Feb-2012 |
yamt | branches: 1.27.2;
use a correct macro.
releng@ ok
|
| 1.26 | 04-Dec-2011 |
chs | add info on L2 TLBs and 1GB pages.
|
| 1.25 | 03-May-2011 |
jruoho | branches: 1.25.4;
Identify AMD Family 11h. From PR bin/41188 by FUKAUMI Naoki.
|
| 1.24 | 19-Feb-2011 |
jmcneill | fix printing of padlock features
|
| 1.23 | 15-Dec-2010 |
cegger | branches: 1.23.2;
beautify printing of SVM features across multiple lines
|
| 1.22 | 23-Feb-2010 |
cegger | check for svm feature flags if cpuid function 0x8000000a is available.
|
| 1.21 | 16-Feb-2010 |
mrg | don't call most/all Core2's "(Merom)".
|
| 1.20 | 02-Oct-2009 |
jmcneill | - add newer VIA C7 core and VIA Nano.
- when printing an unknown VIA CPU, default to 'Unknown IDT/VIA' instead of 'C3'
|
| 1.19 | 14-May-2009 |
pgoyette | Add a few more processor extended models for Intel Family 6
|
| 1.18 | 13-May-2009 |
pgoyette | 1. Extend CPU probe of Intel processors to handle extended-models. This
allows us to properly identify new Intel 45nm processors, Core i7,
Atom, and the 45nm Xeon MP.
2. Properly decode several new Intel cache descriptors, as listed in the
most recent (March 2009) edition of Intel's Application Note 485.
3. Convert decode of the various features masks to use the newly added
snprintb_m(3) routine.
Addresses my PR bin/41289
Addresses my PR bin/41290
|
| 1.17 | 22-Apr-2009 |
christos | WARNS=4
|
| 1.16 | 16-Mar-2009 |
tsutsui | Increase size of buffer for humanize_number(3) to print cache sizes
so that it can return 128KB, 256KB and 512KB properly instead of
truncated 0MB or rounded 1MB.
Problem reported by nisimura@ on port-amd64 and port-i386.
|
| 1.15 | 12-Mar-2009 |
yamt | print some SVM info if available.
|
| 1.14 | 16-Dec-2008 |
christos | branches: 1.14.2;
Remove 3rd buggy copy of this function and use snprintb(3) instead.
No need to allocate MAXPATHLEN buffers anymore.
|
| 1.13 | 14-Oct-2008 |
cegger | branches: 1.13.2;
do correct octal counting and use CPUID_APM_FLAGS in cpuctl
|
| 1.12 | 13-Oct-2008 |
cegger | print features4: cpuid fn80000001 %ecx on AMD CPUs.
|
| 1.11 | 13-Oct-2008 |
cegger | Add cpuid 0x80000001 %ecx features flags. Rename CPUID_MASK4 to CPUID_INTEL_MASK4 for consistency with new CPUID_AMD_MASK4
|
| 1.10 | 24-Aug-2008 |
pgoyette | 1. For non-Intel vendors, don't overload cpuflags with the extended
flags from CPUID 80000001_EDX. Instead, keep the extended flags
separate, in ci_feature3_flags (Intel processors already kept a
separate ci_feature3_flag value).
2. Decode/display ci_feature3_flag in a vendor-specific manner, since
the definitions are vendor-specific.
OK cegger@
|
| 1.9 | 31-May-2008 |
christos | change HUMAN_NUMBER back to 5
|
| 1.8 | 30-May-2008 |
christos | remove stray `
|
| 1.7 | 30-May-2008 |
christos | - fix an amd cache entry.
- merge tables
- support phenom
from Paul Goyette
|
| 1.6 | 30-May-2008 |
christos | de-duplicated cacheinfo.h
|
| 1.5 | 21-May-2008 |
ad | Print AMD power management features.
|
| 1.4 | 17-May-2008 |
tsutsui | branches: 1.4.2;
Sync intel_cpuid_cache_info with src/sys/arch/x86/x86/identcpu.c.
|
| 1.3 | 15-May-2008 |
chris | Fix two sizeof(__arraycount()) to not use sizeof when looking up the size
of the array.
This fixes a crash when run on amd phenom under amd64.
Issue reported and inital patch by Paul Goyette.
|
| 1.2 | 10-May-2008 |
ad | Report: family, model, extfamily, extmodel
|
| 1.1 | 05-May-2008 |
ad | branches: 1.1.2;
PR port-amd64/37461 x86 cpu dmesg output is noisy
Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.
|
| 1.1.2.2 | 18-Sep-2008 |
wrstuden | Sync with wrstuden-revivesa-base-2.
|
| 1.1.2.1 | 23-Jun-2008 |
wrstuden | Sync w/ -current. 34 merge conflicts to follow.
|
| 1.4.2.3 | 04-Jun-2008 |
yamt | sync with head
|
| 1.4.2.2 | 18-May-2008 |
yamt | sync with head.
|
| 1.4.2.1 | 17-May-2008 |
yamt | file i386.c was added on branch yamt-pf42 on 2008-05-18 12:36:14 +0000
|
| 1.13.2.5 | 17-Mar-2012 |
bouyer | Pull up following revision(s) (requested by sborrill in ticket #1735):
usr.sbin/cpuctl/arch/i386.c: revision 1.29
Print CPU stepping level
|
| 1.13.2.4 | 04-Oct-2009 |
snj | Pull up following revision(s) (requested by jmcneill in ticket #1055):
usr.sbin/cpuctl/arch/i386.c: revision 1.20
- add newer VIA C7 core and VIA Nano.
- when printing an unknown VIA CPU, default to 'Unknown IDT/VIA' instead of 'C3'
|
| 1.13.2.3 | 18-May-2009 |
bouyer | Pull up following revision(s) (requested by pgoyette in ticket #761):
sys/arch/x86/include/cacheinfo.h: revisions 1.11, 1.12
usr.sbin/cpuctl/arch/i386.c: revisions 1.18, 1.19 via patch
1. Extend CPU probe of Intel processors to handle extended-models. This
allows us to properly identify new Intel 45nm processors, Core i7,
Atom, and the 45nm Xeon MP.
2. Properly decode several new Intel cache descriptors, as listed in the
most recent (March 2009) edition of Intel's Application Note 485.
Addresses my PR bin/41289
Addresses my PR bin/41290
|
| 1.13.2.2 | 24-Mar-2009 |
snj | branches: 1.13.2.2.4;
Pull up following revision(s) (requested by tsutsui in ticket #594):
usr.sbin/cpuctl/arch/i386.c: revision 1.16
Increase size of buffer for humanize_number(3) to print cache sizes
so that it can return 128KB, 256KB and 512KB properly instead of
truncated 0MB or rounded 1MB.
Problem reported by nisimura@ on port-amd64 and port-i386.
|
| 1.13.2.1 | 23-Dec-2008 |
snj | Pull up following revision(s) (requested by christos in ticket #193):
usr.sbin/cpuctl/Makefile: revision 1.3
usr.sbin/cpuctl/bitmask.c: file removal
usr.sbin/cpuctl/cpuctl.h: revision 1.2
usr.sbin/cpuctl/arch/i386.c: revision 1.14
Remove 3rd buggy copy of this function and use snprintb(3) instead.
No need to allocate MAXPATHLEN buffers anymore.
|
| 1.13.2.2.4.1 | 21-Apr-2010 |
matt | sync to netbsd-5
|
| 1.14.2.1 | 13-May-2009 |
jym | Sync with HEAD.
Third (and last) commit. See http://mail-index.netbsd.org/source-changes/2009/05/13/msg221222.html
|
| 1.23.2.1 | 05-Mar-2011 |
bouyer | Sync with HEAD
|
| 1.25.4.5 | 22-May-2014 |
yamt | sync with head.
for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.
this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
|
| 1.25.4.4 | 23-Jan-2013 |
yamt | sync with head
|
| 1.25.4.3 | 30-Oct-2012 |
yamt | sync with head
|
| 1.25.4.2 | 23-May-2012 |
yamt | sync with head.
|
| 1.25.4.1 | 17-Apr-2012 |
yamt | sync with head
|
| 1.27.2.5 | 16-Jan-2015 |
snj | Pull up following revision(s) (requested by msaitoh in ticket #1230):
usr.sbin/cpuctl/cpuctl.8: revisions 1.9-1.12
usr.sbin/cpuctl/cpuctl.c: revisions 1.22-1.23 and 1.25 via patch
usr.sbin/cpuctl/cpuctl.h: revision 1.5 via patch
usr.sbin/cpuctl/arch/cpuctl_i386.h: revisions 1.1-1.2
usr.sbin/cpuctl/arch/i386-asm.S: revisions 1.2-1.3
usr.sbin/cpuctl/arch/i386.c: revisions 1.34, 1.36-1.49, 1.51-1.63 via patch
usr.sbin/cpuctl/arch/x86_64-asm.S: revisions 1.3-1.4
Update cpuctl(8). Microcode and ARM related changes are not included:
- Change the i386 asm x86_identify() so it returns a value instead of
writing into global data. Fix a stack alignment fubar that would
cause a crash on a cirix 486. Refactor identify code to common setup
for normal identify and ucode identify - which was missing a
memset().
- The Intel and AMD docs (more or less) agree on how the cpuid
'extended family' and 'extended model' bits are used to create
larger values than the original 16bit value allowed for.
Calculate and save these values 'up-front' and use them throughout.
Untangle the (backwards) nested switch statement for amd 'model 15'
cpus.
- Use full model number to index name strings - a lot of 256 element
arrays don't matter in usespace.
- Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually
identifies the cpu is output first.
- Only complain about binding if we have more than 1 cpu.
- Check cpuid leaf 4 for newer Intel CPU to know the cache information.
- Support prefetch size.
- Print the highest extended info level as the basic info level.
- Update URL of AMD's web page.
- Add code to detect hypervisor. The code was based from FreeBSD and
ported by Kengo Nakahara.
- Add verbose flag.
- Add newline if ci_tsc_freq is 0 to not to break the output.
- Update Intel's processor family names and models.
- Print some more bits.
- Add shared TLB
- Add prototypes.
- Add comments.
- Make some functions static.
- Sort functions.
- KNF.
|
| 1.27.2.4 | 19-Apr-2012 |
riz | Pull up following revision(s) (requested by cegger in ticket #187):
usr.sbin/cpuctl/arch/i386.c: revision 1.31
print cpu family for AMD CPU families 0x12 - 0x15
|
| 1.27.2.3 | 06-Apr-2012 |
riz | Pull up following revision(s) (requested by cegger in ticket #163):
usr.sbin/cpuctl/arch/i386.c: revision 1.30
report l3 cache information on AMD Family 10h and newer processors
|
| 1.27.2.2 | 07-Mar-2012 |
riz | Pull up following revision(s) (requested by sborrill in ticket #79):
usr.sbin/cpuctl/arch/i386.c: revision 1.29
Print CPU stepping level
|
| 1.27.2.1 | 05-Mar-2012 |
sborrill | Pull up the following revisions(s) (requested by joerg in ticket #75):
usr.sbin/cpuctl/arch/i386.c: revision 1.28
usr.bin/unifdef/unifdef.c: revision 1.21
usr.bin/ktruss/dump.c: revision 1.40
usr.bin/error/error.h: revision 1.19
usr.bin/error/touch.c: revision 1.27
libexec/httpd/dir-index-bozo.c: revision 1.14
games/dab/algor.cc: revision 1.5
games/dab/board.h: revision 1.4
dist/pf/sbin/pflogd/pflogd.c: revision 1.9
dist/pf/sbin/pflogd/pflogd.h: revision 1.5
Fix various format string mismatches
|
| 1.32.2.3 | 20-Aug-2014 |
tls | Rebase to HEAD as of a few days ago.
|
| 1.32.2.2 | 23-Jun-2013 |
tls | resync from head
|
| 1.32.2.1 | 25-Feb-2013 |
tls | resync with head
|
| 1.54.2.1 | 10-Aug-2014 |
tls | Rebase.
|
| 1.58.2.7 | 09-Oct-2018 |
snj | Pull up following revision(s) (requested by msaitoh in ticket #1636):
sys/arch/x86/include/cacheinfo.h: 1.23-1.26
sys/arch/x86/include/cpu.h: 1.70
sys/arch/x86/include/specialreg.h: 1.91-1.93,1.98,1.100,1.102-1.124,1.126,1.130 via patch
sys/arch/x86/x86/cpu_topology.c: 1.10
sys/arch/x86/x86/identcpu.c: 1.56-1.57,1.70 via patch
usr.sbin/cpuctl/arch/i386.c: 1.71,1.75-1.79,1.81-1.85 via patch
Add some register definitions for x86:
- Add CLWB bit.
- Fix a few (unused) MSR values, and add some bit definitions of
MSR_EFER from Murray Armfield in PR#42861.
- CPUID_CFLUSH bit is not for CFLUSH insn but CLFLUSH insn, so modify
comments and snprintb() string.
- Define CPUID Fn00000001 %ebx bits and use them.
No functional change.
- Add Structured Extended Flags Enumeration Leaf's bit definitions:
AVX512_{IFMA,VBMI2,VNNI,BITALG,VPOPCNTDQ,4VNNIW,4FMAPS},GFNI&VAES.
- Add Turbo Boost Max Technology 3.0 bit.
- Add AMD SVM features definitions.
- Add Intel cpuid 7 %edx IBRS and STIBP bit definitions.
- Fix swapped comments for EFER LME and LMA
- Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
- Add MSR_IA32_ARCH_CAPABILITIES definition.
- Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR.
- Add Intel Deterministic Address Translation Parameter Leaf(0x18)
definitions.
- s/CLFUSH/CLFLUSH/
- Add AMD's Disable Indirect Branch Predictor bit definition.
- Add the MSR bits definitions for IBRS, STIBP and IBPB.
- Add Intel Fn0000_0006 %eax new bit 14-20 (HWP stuff).
- Intel Fn0000_0007 %ecx bit 22 is for both RDPID and IA32_TSC_AUX.
- Add AMD's CPUID Fn80000001 %edx MMX and FXSR bit definitions.
- Add RDCL_NO and IBRS_ALL.
- Add SSBD and RSBA bit definitions.
- Add AMD's SSB bit definitions for F15H, F16H and F17H.
- Add cpuid 7 edx L1D_FLUSH bit.
- Add IA32_ARCH_SKIP_L1DFL_VMENTRY bit.
- Add IA32_FLUSH_CMD MSR.
- Add yet another Shared L2 TLB (2M/4M pages).
- Add 3way and 6way of L2 cache or TLB on AMD CPU.
- AMD L3 cache association bitfield is not 8bit but 4bit like others
association bitfields.
- Sort entries. No functional change.
- Modify comment, fix typo in comment and add comment.
cpuctl(8):
- Add detection for Quark X1000, Xeon E5 v4, E7 v4,
Core i7-69xx Extreme Edition, Xeon Scalable (Skylake),
Xeon Phi [357]200 (Knights Landing), Atom (Goldmont),
Atom (Denverton), Future Core (Cannon Lake), Atom (Goldmont Plus),
Xeon Phi 7215, 7285 and 7295 (Knights Mill) and
7th or 8th gen Core (Kaby Lake, Coffee Lake).
- Print Structured Extended Feature leaf Fn0000_0007 %ebx on AMD,too.
- Print Fn0000_0007 %ecx on Intel.
- Print Intel cpuid 7 %edx.
- Parse the TLB info from `cpuid leaf 18H' on Intel processor.
- Use aprint_error_dev() for error output.
|
| 1.58.2.6 | 08-Dec-2016 |
snj | Pull up following revision(s) (requested by msaitoh in ticket #1285):
sys/arch/x86/include/cacheinfo.h: revision 1.22
sys/arch/x86/include/specialreg.h: revisions 1.87 and 1.90
usr.sbin/cpuctl/arch/i386.c: revisions 1.72-1.74
Changes for x86's cpuctl(8):
- Add Quark X1000, Xeon E[57] v4, Core i7-69xx Extreme, 7th gen Core,
Denverton, Xeon Phi [357]200, Future Xeon and Future Xeon Phi.
- Add SGX, UMIP, RDPID, SGXLC, AVX512DQ, AVX512BW and AVX512VL bit.
- Fix the bit location of CLFLUSHOPT.
- Add new TLB descriptor 0x64 and 0xc4.
|
| 1.58.2.5 | 06-Mar-2016 |
martin | branches: 1.58.2.5.2;
Pull up the following changes, requested by msaitoh in #1117:
sys/arch/x86/include/cacheinfo.h 1.20-1.21
sys/arch/x86/include/specialreg.h 1.83-1.86
usr.sbin/cpuctl/arch/i386.c 1.67-1.70
Changes for x86's cpuctl(8):
- Add some TLB information (index 0x6a-0x6d).
- Add Hardware-Controlled Performance States (HWP) bits, FPU Data
Pointer Updated Only bit and CLFLUSHOPT bit.
- Add some AMD's bit definitions from "BIOS and Kernel Developer(BKDG)
for AMD Family 15h Models 60h-6Fh Processors".
- Add Xeon E5-4600 v3,
- Add Xeon E3-1200 v4 and v5.
- Add 6th gen Core, Xeon E3-1500 v5 and Xeon D-1500.
- Change CPU family 0x1c from "Atom Family" to "45nm Atom Family"
|
| 1.58.2.4 | 09-May-2015 |
snj | Pull up following revision(s) (requested by msaitoh in ticket #739):
sys/arch/x86/include/specialreg.h: revision 1.82
usr.sbin/cpuctl/arch/i386.c: revision 1.66
From Intel SDM:
- Add the Silicon Debug bit in CPUID Fn00000001 %ecx
- Add CPUID Fn0000_0007 %ecx bits
- Add comments.
--
Update some Intel CPU models (Sky Lake, Broadwell and Atom X[357]).
|
| 1.58.2.3 | 19-Apr-2015 |
riz | Pull up following revision(s) (requested by msaitoh in ticket #701):
usr.sbin/cpuctl/arch/i386.c: revision 1.65
Update from Intel SDM:
- Add Atom Z8000, Future gen Xeon (Broadwell), Next gen Xeon Phi and so on.
- Add comments.
|
| 1.58.2.2 | 14-Dec-2014 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #326):
usr.sbin/cpuctl/arch/i386.c: revision 1.60
usr.sbin/cpuctl/arch/i386.c: revision 1.61
usr.sbin/cpuctl/arch/i386.c: revision 1.62
usr.sbin/cpuctl/arch/i386.c: revision 1.63
usr.sbin/cpuctl/arch/i386.c: revision 1.64
Add code to detect hypervisor. The code was based from FreeBSD and ported
by Kengo Nakahara.
kern/49379: Hypervisor's name typo
Move some printf()s from cpu_probe_base_features() to identifycpu().
Those printf()s are used for "identify" command but cpu_probe_base_features()
is shared by ucodeupdate_check(), too. This change fixes a problem that
the "ucode" command print extra output.
Add newline if ci_tsc_freq is 0 to not to break the output.
Don't print the microcode version if the ioctl failed to not to
print garbage.
|
| 1.58.2.1 | 12-Dec-2014 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #310):
sys/arch/x86/include/specialreg.h: revision 1.79-1.80
usr.sbin/cpuctl/arch/i386.c: revision 1.59
sys/arch/x86/include/cacheinfo.h: revision 1.19
Update some cpuid related values:
- Add XSAVECC, XGETBV, XSAVES, SMAP and PQE
- Change XINUSE to XGETBV
- Add new cache descripter value (0xc3)
- Update signatures for the follwing CPUs:
- Core M-5xxx
- Core i7 Extreme
- Future Core (0x4e)
- Future Xeon (0x56)
|
| 1.58.2.5.2.1 | 18-Jan-2017 |
skrll | Sync with netbsd-5
|
| 1.72.2.2 | 04-Nov-2016 |
pgoyette | Sync with HEAD
|
| 1.72.2.1 | 26-Jul-2016 |
pgoyette | Sync with HEAD
|
| 1.74.6.18 | 29-Jul-2023 |
martin | Pull up the following revisions, via patch, requested by msaitoh
in ticket #1854:
usr.sbin/cpuctl/arch/i386.c 1.137-1.139
- CPU model 0x5a is not Atom E3500 but Atom Z3500.
- Add Alder Lake-N.
|
| 1.74.6.17 | 21-Jun-2023 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #1827):
sys/arch/x86/include/specialreg.h: revision 1.202
sys/arch/x86/include/specialreg.h: revision 1.203
usr.sbin/cpuctl/arch/i386.c: revision 1.136
Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.
Add AMD CPUID Fn0000_0008 %ebx bit 3 INVLPGB.
|
| 1.74.6.16 | 23-Jan-2023 |
martin | Pull up the following revisions, requested by msaitoh in ticket #1792:
usr.sbin/cpuctl/arch/i386.c 1.129-1.135
- Print cpuid 7 sub-leaf 1 %ebx, %edx and sub-leaf 2 %edx.
- Add Raptor Lake and Sapphire Rapids.
- Modify messages a little.
|
| 1.74.6.15 | 15-Oct-2022 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #1775):
sys/arch/x86/include/specialreg.h: revision 1.189
usr.sbin/cpuctl/arch/i386.c: revision 1.128
sys/arch/x86/include/specialreg.h: revision 1.190
sys/arch/x86/include/specialreg.h: revision 1.191
sys/arch/x86/include/specialreg.h: revision 1.192
s/shareing/sharing/. No functional change.
Add top-down slots event bit of architectural performance monitoring leaf.
Modify CPUID Fn0000000a %ebx's string. Add new string for %ecx.
Modify output of CPUID Fn0000000a.
old:
cpu0: Perfmon-eax 0x8300805<VERSION=0x5,GPCounter=0x8,GPBitwidth=0x30>
cpu0: Perfmon-eax 0x8300805<Vectorlen=0x8>
cpu0: Perfmon-edx 0x8604<FixedFunc=0x4,FFBitwidth=0x30,ANYTHREADDEPR>
new:
cpu0: Perfmon: Ver. 5
cpu0: Perfmon: General: bitwidth 48, 8 counters
cpu0: Perfmon: General: avail 0xff<CORECYCL,INST,REFCYCL,LLCREF,LLCMISS,BRINST>
cpu0: Perfmon: General: avail 0xff<BRMISPR,TOPDOWNSLOT>
cpu0: Perfmon: Fixed: bitwidth 48, 4 counters
cpu0: Perfmon: Fixed: avail 0xf<INST,CLK_CORETHREAD,CLK_REF_TSC,TOPDOWNSLOT>
Update some AMD CPUID bits:
- Rename FSREP_MOV to FSRM.
- Add Memory Bandwidth Enforcement (MBE)
- Add AMD's PPIN. Rename CPUID_SEF_PPIN to CPUID_SEF_INTEL_PPIN.
- Add Collaborative Processor Performance Control (CPPC).
- Add HOST_MCE_OVERRIDE.
- Add some unknown bits as Bxx.
- Add comments.
- Use __BIT().
|
| 1.74.6.14 | 31-Jan-2022 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #1732):
usr.sbin/cpuctl/arch/i386.c: revision 1.125
usr.sbin/cpuctl/arch/i386.c: revision 1.126
usr.sbin/cpuctl/arch/i386.c: revision 1.127
Add Alder Lake, Rocket Lake and Sapphire Rapids. From the latest Intel SDM.
Remove debug code and simplify. No functional change.
Decode Intel Hybrid Information Enumeration (CPUID Fn0000_001a).
|
| 1.74.6.13 | 24-Dec-2021 |
martin | Pull up the following (all via patch), requested by msaitoh in ticket #1721:
usr.sbin/cpuctl/arch/i386.c 1.118-1.119, 1.121-1.122
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.6
sys/arch/x86/x86/identcpu_subr.c 1.8-1.9
sys/arch/x86/x86/identcpu.c 1.123
sys/arch/x86/include/cacheinfo.h 1.30
sys/arch/x86/include/cpu.h 1.132
- Fix a bug that some TLB related lines were not printed.
- Fix a bug that STLB is printed as DTLB.
- If a TLB is variable sized, print the max size instead of error message.
- Cosmetic changes to improve readability.
|
| 1.74.6.12 | 08-Dec-2021 |
martin | Pull up the following, requested by msaitoh in ticket #1720:
sys/arch/x86/include/specialreg.h 1.146, 1.171,
1.173-1.178 via patch
sys/arch/x86/x86/identcpu.c 1.106, 1.117,
1.122 via patch
sys/arch/x86/x86/pmap.c patch
sys/external/bsd/drm2/drm/drm_cache.c 1.14
usr.sbin/cpuctl/arch/i386.c 1.114-1.117
- Add PT, PKRU, HDC, LA57, PKE, PKS, CET, CET_U, CET_S, HWP, KL,
AVX512_BF16, TME_EN and PCONFIG.
- Rename some macros to match the x86 specification and the other OSes.
- Print CPUID 0x8000008 %ebx on Intel, too.
- Print CPUID leaf 7 subleaf 1.
- Identify Tiger Lake, 3rd gen Xeon Scalable (Ice Lake), Elkhart Lake
and Jasper Lake.
- Remove a few unused MSRs.
- Add comment.
- KNF. Whitespace fix.
|
| 1.74.6.11 | 05-Aug-2020 |
martin | Pull up the following revisions, requested by msaitoh in ticket #1585:
usr.sbin/cpuctl/Makefile 1.9
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.5
usr.sbin/cpuctl/arch/i386.c 1.111-1.113 via patch
usr.sbin/cpuctl/cpuctl.c 1.31
usr.sbin/cpuctl/cpuctl.h 1.7
sys/arch/x86/x86/identcpu_subr.c 1.1-1.7
- Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel
processors.
- Add 0xa5 and 0xa6 for Comet Lake.
- Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
ci_max_ext_cpuid to match x86/include/cpu.h. No functional change.
- Sort some entries.
- Add comment.
|
| 1.74.6.10 | 15-Apr-2020 |
martin | Pull up the following, requested by msaitoh in ticket #1530:
sys/arch/x86/x86/procfs_machdep.c 1.33-1.36
sys/arch/x86/x86/tsc.c 1.40
sys/arch/x86/x86/specialreg.h 1.159-1.161
usr.sbin/cpuctl/arch/i386.c 1.109-1.110 via patch
- Print avx512ifma, cqm_mbm_total, cqm_mbm_local, waitpkg, rdpru,
Fast Short Rep Mov(fsrm), AVX512_VP2INTERSECT, SERIALIZE and
TSXLDTRK.
- Rename CPUID Fn8000_0007 %edx bit 8 from "TSC" to "ITSC"
(Invariant TSC) to avoid confusion.
- Print CPUID 0x80000007 %edx on both Intel and AMD.
- Remove ci_max_ext_cpuid from usr.sbin/cpuctl/arch/i386.c because it's
the same as ci_cpuid_extlevel.
- Use unsigned to avoid undefined behavior in procfs_getonefeatreg().
|
| 1.74.6.9 | 31-Jan-2020 |
martin | Pull up the following, requested by msaitoh in ticket #1494:
sys/arch/x86/include/specialreg.h 1.146, 1.151-1.154, 1.156 via patch
usr.sbin/cpuctl/arch/i386.c 1.105-1.107 via patch
- Add definitions of AMD's CPUID Fn8000_0008 %ebx.
- Add definitions of AMD's CPUID Fn8000_001f Encrypted Memory features.
- Add definition of AMD's CPUID Fn8000_000a %edx bit 11 "GMET".
- Define CPUID_AMD_SVM_PFThreshold correctly.
- Modify comment a bit for consistency.
- Call cpu_dcp_cacheinfo() only when the cpuid Topology Extension flag
is set on AMD processor.
- Fix typos.
|
| 1.74.6.8 | 19-Nov-2019 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #1450):
usr.sbin/cpuctl/arch/i386.c: revision 1.108
sys/arch/x86/include/specialreg.h: revision 1.158
Add the following bit definitions from the latest Intel SDM:
- CET shadow stack
- Fast Short REP MOV
- Hybrid part
- CET Indirect Branch Tracking
0x7d and 0x7e are for 10th generation Core (Ice Lake).
|
| 1.74.6.7 | 16-Aug-2019 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #1338):
usr.sbin/cpuctl/arch/i386.c: revision 1.104
sys/arch/x86/x86/identcpu.c: revision 1.93
sys/arch/x86/include/cacheinfo.h: revision 1.28
sys/arch/x86/include/specialreg.h: revision 1.150
- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
Intel Deterministic Cache Parameter Leaf(0x04), so make new
cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
common definition.
- KNF.
XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?
|
| 1.74.6.6 | 17-Jul-2019 |
martin | Pull up the following revisions (via patch), requested by msaitoh
in ticket #1296:
usr.sbin/cpuctl/arch/i386.c 1.91,1.93-1.95,1.100-1.103
- Handle NVMM and HAXM's signature.
- Regard "TCGTCGTCGTCG" as QEMU(TCG).
- Dump CPUID leaf 0x40000000 if available (for -v option).
- Add Cascade Lake, Copper Lake.
- Add Future Xeon (Cannon Lake)
- Add 06_7DH for another Ice Lake.
- Add Coffee Lake based Xeon E.
- White space fix. No functional change.
|
| 1.74.6.5 | 11-Feb-2019 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #1187):
usr.sbin/cpuctl/arch/i386.c: revision 1.92
sys/arch/x86/include/specialreg.h: revision 1.138
Add new CPUID flags WAITPKG, CLDEMOTE, MOVDIRI, MOVDIR64B and
IA32_CORE_CAPABILITIES from the latest Intel SDM.
Add Ice Lake and Tremont from the latest Intel SDM.
Fix bitstring format of Intel CPUID Architectural Performance Monitoring
Fn0000000a %ebx.
|
| 1.74.6.4 | 04-Dec-2018 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #1120):
usr.sbin/cpuctl/arch/i386.c: revision 1.85
usr.sbin/cpuctl/arch/i386.c: revision 1.86
usr.sbin/cpuctl/arch/i386.c: revision 1.87
usr.sbin/cpuctl/arch/i386.c: revision 1.88
usr.sbin/cpuctl/arch/i386.c: revision 1.89
usr.sbin/cpuctl/arch/i386.c: revision 1.90
sys/arch/x86/include/specialreg.h: revision 1.132
sys/arch/x86/include/specialreg.h: revision 1.133
sys/arch/x86/include/specialreg.h: revision 1.134
sys/arch/x86/include/specialreg.h: revision 1.135
sys/arch/x86/include/specialreg.h: revision 1.136
sys/arch/x86/x86/cpu_topology.c: revision 1.14
Add MAWAU (for BND{LD,ST}X instruction) from the latest Intel SDM.
Whitespace fix. No functional change.
Modify comment. No functional change:
- AMD also has CPUID 0x06 and 0x0d.
- PCOMMIT was obsoleted.
- Use ci_feat_val[7] as CPUID 7 %edx to match x86/cpu.h
- AMD also has CPUID 6.
- Remove unused code for coretemp.
- Consistently use descs[] instead of data[].
- AMD also reports CPUID 7's highest subleaf. Print it.
- Use macro.
Add Intel CPUID Extended Topology Enumeration Fn0000000b definitions.
Decode package, core and SMT id if CPUID 0x0b is available on Intel processor.
If the value is different from the kernel value, we should fix the kernel code.
TODO: Use 0x1f if it's available.
Add Intel/AMD MONITOR/MWAIT leaf.
Decode Intel/AMD MONITOR/MWAIT leaf.
Add Intel CPUID Architectural Performance Monitoring leaf Fn0000000a.
Print Intel CPUID Architectural Performance Monitoring leaf Fn0000000a.
|
| 1.74.6.3 | 09-Apr-2018 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #715):
sys/arch/x86/include/cacheinfo.h: revision 1.24-1.26
usr.sbin/cpuctl/arch/i386.c: revision 1.81-1.84
- Parse the TLB info from `cpuid leaf 18H' on Intel processor. Currently,
this change doesn't decode perfectly. Tested with Gemini Lake. It has
two L2 Shared TLB. One is 4MB and another is 2MB/4MB but former isn't
printed yet:
cpu0: ITLB 1 4KB entries 48-way
cpu0: DTLB 1 4KB entries 32-way
cpu0: L2 STLB 8 4MB entries 4-way
Need some rework for struct x86_cache_info.
- Use aprint_error_dev() for error output.
Calculate way and number of entries correctly from CPUID leaf 18H.
Add yet another Shared L2 TLB (2M/4M pages).
XXX need redesign.
Add 3way and 6way of L2 cache or TLB on AMD CPU.
AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.
From the latest Intel SDM:
- Add Xeon Phi 7215, 7285 and 7295
- Add Coffee Lake
|
| 1.74.6.2 | 16-Mar-2018 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #633):
sys/arch/x86/include/specialreg.h: revision 1.107
sys/arch/x86/include/specialreg.h: revision 1.108
sys/arch/x86/include/specialreg.h: revision 1.109
sys/arch/x86/include/cacheinfo.h: revision 1.23
sys/arch/x86/include/specialreg.h: revision 1.110
sys/arch/x86/include/specialreg.h: revision 1.111
sys/arch/x86/include/specialreg.h: revision 1.112
sys/arch/x86/include/specialreg.h: revision 1.113
sys/arch/x86/include/specialreg.h: revision 1.114
usr.sbin/cpuctl/arch/i386.c: revision 1.79
sys/arch/x86/x86/identcpu.c: revision 1.70
sys/arch/x86/include/specialreg.h: revision 1.106
Add comment.
Add Intel cpuid 7 %edx IBRS(IBPB Speculation Control) and
STIBP(STIBP Speculation Control) from OpenBSD.
Print Intel cpuid 7 %edx.
Example output of cpuctl -v identify 0:
+cpu0: 00000007: 00000000 000027ab 00000000 0c000000
(snip)
+cpu0: SEF edx 0xc000000<IBRS,STIBP>
fix swapped comments for EFER LME and LMA
- Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
- Add comment.
Add MSR_IA32_ARCH_CAPABILITIES definition.
Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR.
Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.
Sort entries. No functional change.
s/CLFUSH/CLFLUSH/
No functional change.
|
| 1.74.6.1 | 21-Nov-2017 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #365):
sys/arch/x86/include/specialreg.h: revision 1.99
usr.sbin/cpuctl/arch/i386.c: revision 1.75
usr.sbin/cpuctl/arch/i386.c: revision 1.76
usr.sbin/cpuctl/arch/i386.c: revision 1.77
usr.sbin/cpuctl/arch/i386.c: revision 1.78
sys/arch/x86/x86/identcpu.c: revision 1.56
sys/arch/x86/x86/identcpu.c: revision 1.57
sys/arch/x86/x86/cpu_topology.c: revision 1.10
sys/arch/x86/include/specialreg.h: revision 1.100
sys/arch/x86/include/specialreg.h: revision 1.101
sys/arch/x86/include/specialreg.h: revision 1.102
sys/arch/x86/include/specialreg.h: revision 1.103
sys/arch/x86/include/specialreg.h: revision 1.104
sys/arch/x86/include/specialreg.h: revision 1.105
Add EFER_TCE. This would be an interesting feature to have, since it
reduces the indirect cost of invlpg; but I'm not convinced the way we
flush upper-levels is correct for this yet.
Fix typo in comment
Add a comment about APICBASE_PHYSADDR. Has to do with PR/42597.
Define CPUID Fn00000001 %ebx bits and use them. No functional change.
Set ci->ci_cflush_lsize correctly. This bug was added in the last commit(1.56).
Add the following instruction bits in Structured Extended Flags Enumeration
Leaf from "Intel Architecture Instruction Set Extensions and Future Features
Programming Reference" (319433-030):
AVX512_IFMA
AVX512_VBMI
AVX512_VBMI2
GFNI
VAES
VPCLMULQDQ
AVX512_VNNI
AVX512_BITALG
AVX512_VPOPCNTDQ
AVX512_4VNNIW
AVX512_4FMAPS
- Print ci_feat_val[5] (Structured Extended Feature leaf Fn0000_0007 %ebx) on
AMD, too.
- Print ci_feat_val[6] (Fn0000_0007 %ecx) on Intel.
Update from the latest Intel SDM:
0x5c: Atom (Goldmont)
0x5f: Atom (Goldmont, Denverton)
0x7a: Atom (Goldmont Plus)
Add Turbo Boost Max Technology 3.0 bit.
Update from Intel SDM:
0x55: Xeon Scalable (Skylake)
0x57: Xeon Phi [357]200 (Knights Landing)
0x66: Future Core (Cannon Lake)
0x85: Future Xeon Phi (Knights Mill)
Add the following bits in AMD Fn8000000a %edx features (SVM features):
PFThreshold (PAUSE filter threshold)
AVIC (AMD virtual interrupt controller)
V_VMSAVE_VMLOAD (virtualized VMSAVE and VMLOAD)
vGIF (virtualized GIF)
|
| 1.82.2.6 | 18-Jan-2019 |
pgoyette | Synch with HEAD
|
| 1.82.2.5 | 26-Dec-2018 |
pgoyette | Sync with HEAD, resolve a few conflicts
|
| 1.82.2.4 | 26-Nov-2018 |
pgoyette | Sync with HEAD, resolve a couple of conflicts
|
| 1.82.2.3 | 25-Jun-2018 |
pgoyette | Sync with HEAD
|
| 1.82.2.2 | 07-Apr-2018 |
pgoyette | Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
|
| 1.82.2.1 | 15-Mar-2018 |
pgoyette | Synch with HEAD
|
| 1.85.2.3 | 21-Apr-2020 |
martin | Sync with HEAD
|
| 1.85.2.2 | 13-Apr-2020 |
martin | Mostly merge changes from HEAD upto 20200411
|
| 1.85.2.1 | 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.104.2.14 | 29-Jul-2023 |
martin | Pull up the following revisions, via patch, requested by msaitoh
in ticket #1670:
usr.sbin/cpuctl/arch/i386.c 1.137-1.139
- CPU model 0x5a is not Atom E3500 but Atom Z3500.
- Add Alder Lake-N.
|
| 1.104.2.13 | 21-Jun-2023 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #1646):
sys/arch/x86/include/specialreg.h: revision 1.202
sys/arch/x86/include/specialreg.h: revision 1.203
usr.sbin/cpuctl/arch/i386.c: revision 1.136
Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.
Add AMD CPUID Fn0000_0008 %ebx bit 3 INVLPGB.
|
| 1.104.2.12 | 23-Jan-2023 |
martin | Pull up the following revisions, requested by msaitoh in ticket #1575:
usr.sbin/cpuctl/arch/i386.c 1.129-1.135 (via patch)
- Print cpuid 7 sub-leaf 1 %ebx, %edx and sub-leaf 2 %edx.
- Add Raptor Lake and Sapphire Rapids.
- Modify messages a little.
|
| 1.104.2.11 | 15-Oct-2022 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #1542):
sys/arch/x86/include/specialreg.h: revision 1.189
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.23
usr.sbin/cpuctl/arch/i386.c: revision 1.128
sys/arch/x86/include/specialreg.h: revision 1.190
sys/arch/x86/include/specialreg.h: revision 1.191
sys/arch/x86/include/specialreg.h: revision 1.192
s/shareing/sharing/. No functional change.
Add top-down slots event bit of architectural performance monitoring leaf.
Modify CPUID Fn0000000a %ebx's string. Add new string for %ecx.
Modify output of CPUID Fn0000000a.
old:
cpu0: Perfmon-eax 0x8300805<VERSION=0x5,GPCounter=0x8,GPBitwidth=0x30>
cpu0: Perfmon-eax 0x8300805<Vectorlen=0x8>
cpu0: Perfmon-edx 0x8604<FixedFunc=0x4,FFBitwidth=0x30,ANYTHREADDEPR>
new:
cpu0: Perfmon: Ver. 5
cpu0: Perfmon: General: bitwidth 48, 8 counters
cpu0: Perfmon: General: avail 0xff<CORECYCL,INST,REFCYCL,LLCREF,LLCMISS,BRINST>
cpu0: Perfmon: General: avail 0xff<BRMISPR,TOPDOWNSLOT>
cpu0: Perfmon: Fixed: bitwidth 48, 4 counters
cpu0: Perfmon: Fixed: avail 0xf<INST,CLK_CORETHREAD,CLK_REF_TSC,TOPDOWNSLOT>
Update some AMD CPUID bits:
- Rename FSREP_MOV to FSRM.
- Add Memory Bandwidth Enforcement (MBE)
- Add AMD's PPIN. Rename CPUID_SEF_PPIN to CPUID_SEF_INTEL_PPIN.
- Add Collaborative Processor Performance Control (CPPC).
- Add HOST_MCE_OVERRIDE.
- Add some unknown bits as Bxx.
- Add comments.
- Use __BIT().
|
| 1.104.2.10 | 31-Jan-2022 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #1418):
usr.sbin/cpuctl/arch/i386.c: revision 1.125
usr.sbin/cpuctl/arch/i386.c: revision 1.126
usr.sbin/cpuctl/arch/i386.c: revision 1.127
Add Alder Lake, Rocket Lake and Sapphire Rapids. From the latest Intel SDM.
Remove debug code and simplify. No functional change.
Decode Intel Hybrid Information Enumeration (CPUID Fn0000_001a).
|
| 1.104.2.9 | 24-Dec-2021 |
martin | Pull up the following (all via patch), requested by msaitoh in ticket #1396:
usr.sbin/cpuctl/arch/i386.c 1.118-1.119, 1.121-1.122
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.6
sys/arch/x86/x86/identcpu_subr.c 1.8-1.9
sys/arch/x86/x86/identcpu.c 1.123
sys/arch/x86/include/cacheinfo.h 1.30
sys/arch/x86/include/cpu.h 1.132
- Fix a bug that some TLB related lines were not printed.
- Fix a bug that STLB is printed as DTLB.
- If a TLB is variable sized, print the max size instead of error message.
- Cosmetic changes to improve readability.
|
| 1.104.2.8 | 08-Dec-2021 |
martin | Pull up the following revisions, requested by msaitoh in ticket #1391:
sys/arch/x86/include/specialreg.h 1.171, 1.173-1.178
sys/arch/x86/x86/identcpu.c 1.106, 1.117,
1.122 via patch
sys/dev/nvmm/x86/nvmm_x86.c 1.18
sys/external/bsd/drm2/drm/drm_cache.c 1.14
sys/external/bsd/drm2/include/asm/cpufeature.h 1.5
usr.sbin/cpuctl/arch/i386.c 1.114-1.117
- Add LA57, PKE, PKS, CET, CET_U, CET_S, HWP, KL, AVX512_BF16, TME_EN
and PCONFIG.
- Rename some macros to match the x86 specification and the other OSes.
- Print CPUID 0x8000008 %ebx on Intel, too.
- Print CPUID leaf 7 subleaf 1.
- Identify Tiger Lake, 3rd gen Xeon Scalable (Ice Lake), Elkhart Lake
and Jasper Lake.
- Add comment.
- KNF. Whitespace fix.
|
| 1.104.2.7 | 22-Nov-2021 |
martin | Pull up following revision(s) (requested by mrg in ticket #1375):
usr.sbin/cpuctl/arch/i386.c: revision 1.123
sys/arch/x86/x86/cpu_topology.c: revision 1.20
decode SMT parts for AMD family >= 0x17, not just 0x17.
now zen3 systems are properly identified by cpu topology for the
scheduler and cpuctl identify.
|
| 1.104.2.6 | 10-Jul-2020 |
martin | Pull up the following revisions (all via patch) requested by msaitoh in
ticket #995:
usr.sbin/cpuctl/Makefile 1.9
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.5
usr.sbin/cpuctl/arch/i386.c 1.111-1.113
usr.sbin/cpuctl/cpuctl.c 1.31
usr.sbin/cpuctl/cpuctl.h 1.7
sys/arch/x86/x86/identcpu_subr.c 1.1-1.7
- Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel
processors.
- Add 0xa5 and 0xa6 for Comet Lake.
- Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
ci_max_ext_cpuid to match x86/include/cpu.h. No functional change.
- Sort some entries.
- Add comment.
|
| 1.104.2.5 | 14-Apr-2020 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #833):
usr.sbin/cpuctl/arch/i386.c: revision 1.109
sys/arch/x86/include/specialreg.h: revision 1.159
usr.sbin/cpuctl/arch/i386.c: revision 1.110
sys/arch/x86/include/specialreg.h: revision 1.160
sys/arch/x86/include/specialreg.h: revision 1.161
sys/arch/x86/x86/tsc.c: revision 1.40
sys/arch/x86/x86/procfs_machdep.c: revision 1.35
sys/arch/x86/x86/procfs_machdep.c: revision 1.36
Add Fast Short Rep Mov(fsrm).
Add AVX512_VP2INTERSECT, SERIALIZE and TSXLDTRK(TSX suspend load addr tracking)
CPUID Fn00000001 %edx bit 8 is printed as "TSC", so rename CPUID Fn8000_0007
%edx bit 8 from "TSC" to "ITSC" (Invariant TSC) to avoid confusion.
Rename CPUID_APM_TSC to CPUID_APM_ITSC. No functional change.
Remove ci_max_ext_cpuid because it's the same as ci_cpuid_extlevel.
Print CPUID 0x80000007 %edx on both Intel and AMD.
|
| 1.104.2.4 | 19-Nov-2019 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #452):
usr.sbin/cpuctl/arch/i386.c: revision 1.108
sys/arch/x86/include/specialreg.h: revision 1.158
Add the following bit definitions from the latest Intel SDM:
- CET shadow stack
- Fast Short REP MOV
- Hybrid part
- CET Indirect Branch Tracking
0x7d and 0x7e are for 10th generation Core (Ice Lake).
|
| 1.104.2.3 | 17-Oct-2019 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #344):
sys/arch/x86/include/specialreg.h: revision 1.154
sys/arch/x86/include/specialreg.h: revision 1.155
usr.sbin/cpuctl/arch/i386.c: revision 1.107
sys/arch/x86/x86/procfs_machdep.c: revision 1.34
- Add definitions of AMD's CPUID Fn8000_001f Encrypted Memory features.
- Add definition of AMD's CPUID Fn8000_000a %edx bit 11 "GMET".
- Define CPUID_AMD_SVM_PFThreshold correctly.
- Modify comment a bit for consistency.
Fix AMD Fn8000_0001f %eax bit 0's name.
Add rdpru.
|
| 1.104.2.2 | 26-Sep-2019 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #242):
usr.sbin/cpuctl/arch/i386.c: revision 1.106
sys/arch/x86/x86/identcpu.c: revision 1.94
Call cpu_dcp_cacheinfo() only when the cpuid Topology Extension flag is set
on AMD processor.
|
| 1.104.2.1 | 26-Sep-2019 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #241):
sys/arch/x86/include/specialreg.h: revision 1.152
sys/arch/x86/include/specialreg.h: revision 1.153
usr.sbin/cpuctl/arch/i386.c: revision 1.105
sys/arch/x86/x86/spectre.c: revision 1.30
sys/arch/x86/include/specialreg.h: revision 1.151
Add definitions of AMD's CPUID Fn8000_0008 %ebx.
Decode AMD's CPUID Fn8000_0008 %ebx.
Use macro.
Add MCOMMIT instruction.
Define CPUID_CAPEX_FLAGS's bit 10 correctly.
|
| 1.133.2.4 | 03-Oct-2024 |
martin | Pull up following revision(s) (requested by rin in ticket #919):
sys/arch/x86/x86/errata.c: revision 1.28
sys/arch/x86/x86/errata.c: revision 1.29
sys/arch/x86/include/specialreg.h: revision 1.209
usr.sbin/cpuctl/arch/i386.c: revision 1.144
sys/arch/x86/x86/errata.c: revision 1.30
sys/arch/x86/x86/errata.c: revision 1.33
sys/arch/x86/x86/errata.c: revision 1.34
sys/arch/x86/x86/errata.c: revision 1.35
sys/arch/x86/include/specialreg.h: revision 1.210
sys/arch/x86/include/specialreg.h: revision 1.211
x86/errata.c: Link to original AMD errata guide.
This one is no longer updated; need to link to newer ones for
individual families too. That's where all the cryptic nomenclature
comes from here.
x86/errata.c: Say what revision we're searching for.
x86/errata.c: Only say the errata revision search for cpu0.
x86: make the CPUID list for errata be far less confusing
the 0x80000001 CPUID result needs some parsing to match against
actual family/model/stepping values. 4-bit 'family' values of
15 or 6 change how to parse the 4-bit extended model and 8-bit
extended family value - for family 6 or 15, the extended model
bits (4) are concatenated with the base 4-bits to create an
8-bit value, and for family 15, the family value is addition
of the family value and the 8-bit extended-family value, giving
a range of 0 to 15 + 0xff aka 270.
use a CPUREV(family, model, stepping) macro that builds the
relevant bit-representation of a CPUID, making it far easier
to understand what each entry means, and to add new ones too.
i have confirmed that the emitted cpurevs[] array has the same
values before/after this change, ie, NFCI or observed.
x86: add names for errata that don't have actual numbers
zenbleed is reported as "erratum 65535" currently, this adds a name
for it, and enables the name for any others as well.
pull logging into a function with a tag message.
x86: handle AMD errata 1474: A CPU core may hang after about 1044 days
from the new comment:
* This requires disabling CC6 power level, which can be a performance
* issue since it stops full turbo in some implementations (eg, half the
* cores must be in CC6 to achieve the highest boost level.) Set a timer
* to fire in 1000 days -- except NetBSD timers end up having a signed
* 32-bit hz-based value, which rolls over in under 25 days with HZ=1000,
* and doing xcall(9) or kthread(9) from a callout is not allowed anyway,
* so just have a kthread wait 1 day for 1000 times.
documented in:
https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/revision-guides/56323-PUB_1_01.pdf
add MSR stuff for AMD errata 1474.
cpuctl: fix i386 bit descriptions for CPUID_SEF_FLAGS1
warning: non-printing character '\31' in description
'BUS_LOCK_DETECT""b\31' [363]
s/RPMQUERY/RMPQUERY/
|
| 1.133.2.3 | 29-Jul-2023 |
martin | Pull up the following revisions, via patch, requested by msaitoh in
ticket #251:
usr.sbin/cpuctl/arch/i386.c 1.137-1.139
- CPU model 0x5a is not Atom E3500 but Atom Z3500.
- Add Alder Lake-N.
|
| 1.133.2.2 | 21-Jun-2023 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #200):
sys/arch/x86/include/specialreg.h: revision 1.202
sys/arch/x86/include/specialreg.h: revision 1.203
usr.sbin/cpuctl/arch/i386.c: revision 1.136
Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.
Add AMD CPUID Fn0000_0008 %ebx bit 3 INVLPGB.
|
| 1.133.2.1 | 23-Jan-2023 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #57):
usr.sbin/cpuctl/arch/i386.c: revision 1.134
usr.sbin/cpuctl/arch/i386.c: revision 1.135
Print cpuid 7 sub-leaf 1 %ebx, %edx and sub-leaf 2 %edx.
Add Raptor Lake and Sapphire Rapids.
|
| 1.144.2.1 | 02-Aug-2025 |
perseant | Sync with HEAD
|
| 1.6 | 16-Jan-2018 |
mrg | implement cpuctl identify for sparc and sparc64.
sparc:
- move enum vactype and struct cacheinfo into cpu.h
- move the cache flags from cpuinfo.flags into CACHEINFO.c_flags
(this allows the new cache_printf_backend() to see them.)
remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA.
- align xmpsg to 64 bytes
- move cache_print() into cache_print.h so it can be shared with
cpuctl. it only depends upon a working printf().
- if found, store the CPU node's "name" into cpu_longname. this
changes the default output to show the local CPU not the
generic CPU family. eg:
cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU
vs the generic "RT620/625" previously shown.
- for each CPU export these things:
- name
- fpuname
- mid
- cloc
- freq
- psr impl and version
- mmu impl, version, and number of contexts
- cacheinfo structure (which changed for the first time ever
with this commit.)
sparc64:
- add a minimal "cacheinfo" structure to export the i/d/e-cache
size and linesize.
- store %ver, cpu node "name" and cacheinfo in cpu_info.
- set cpu_info ver, name and cacheinfo in cpu_attach(), and
export them via sysctl, as well as CPU ID and clock freq
cpuctl:
- add identifycpu_bind() that returns false on !x86 as their
identify routines do not need to run on a particular CPU to
obtain its information, and use it to avoid trying to set
affinity when not needed.
- add sparc and sparc64 cpu identify support using the newly
exported values.
|
| 1.5 | 17-Oct-2012 |
drochner | avoid dummy structure definition, include a system header instead,
looks just cleaner
|
| 1.4 | 31-Aug-2012 |
drochner | branches: 1.4.2;
fix for archs w/o cpu ucode driver: add dummy definition
|
| 1.3 | 29-Aug-2012 |
drochner | Extend the CPU microcode update framework to support Intel x86 CPUs.
Contrary to the AMD implementation, it doesn't use xcalls to distribute
the update to all CPUs but relies on cpuctl(8) to bind itself to the
right CPU -- to keep it simple and avoid possible problems with
hyperthreading.
Also, it doesn't parse the vendor supplied file to pick the right
part for the present CPU model but relies on userland to prepare
files with specific filenames. I'll commit a pkg for this in a minute
(pkgsrc/sysutils/intel-microcode).
The ioctl interface changed; compatibility is provided (should be
limited to COMPAT_NETBSD6 as soon as this is available).
|
| 1.2 | 06-May-2008 |
skrll | branches: 1.2.4; 1.2.6;
Make this compile.
|
| 1.1 | 05-May-2008 |
ad | PR port-amd64/37461 x86 cpu dmesg output is noisy
Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.
|
| 1.2.6.1 | 30-Oct-2012 |
yamt | sync with head
|
| 1.2.4.2 | 18-May-2008 |
yamt | sync with head.
|
| 1.2.4.1 | 06-May-2008 |
yamt | file noarch.c was added on branch yamt-pf42 on 2008-05-18 12:36:14 +0000
|
| 1.4.2.1 | 20-Nov-2012 |
tls | Resync to 2012-11-19 00:00:00 UTC
|
| 1.2 | 11-Dec-2021 |
mrg | remove clause 3 from all my licenses that aren't conflicting with
another copyright claim line. again. (i did this in 2008 and then
did not update all of my personal templates.)
|
| 1.1 | 16-Jan-2018 |
mrg | implement cpuctl identify for sparc and sparc64.
sparc:
- move enum vactype and struct cacheinfo into cpu.h
- move the cache flags from cpuinfo.flags into CACHEINFO.c_flags
(this allows the new cache_printf_backend() to see them.)
remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA.
- align xmpsg to 64 bytes
- move cache_print() into cache_print.h so it can be shared with
cpuctl. it only depends upon a working printf().
- if found, store the CPU node's "name" into cpu_longname. this
changes the default output to show the local CPU not the
generic CPU family. eg:
cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU
vs the generic "RT620/625" previously shown.
- for each CPU export these things:
- name
- fpuname
- mid
- cloc
- freq
- psr impl and version
- mmu impl, version, and number of contexts
- cacheinfo structure (which changed for the first time ever
with this commit.)
sparc64:
- add a minimal "cacheinfo" structure to export the i/d/e-cache
size and linesize.
- store %ver, cpu node "name" and cacheinfo in cpu_info.
- set cpu_info ver, name and cacheinfo in cpu_attach(), and
export them via sysctl, as well as CPU ID and clock freq
cpuctl:
- add identifycpu_bind() that returns false on !x86 as their
identify routines do not need to run on a particular CPU to
obtain its information, and use it to avoid trying to set
affinity when not needed.
- add sparc and sparc64 cpu identify support using the newly
exported values.
|
| 1.2 | 11-Dec-2021 |
mrg | remove clause 3 from all my licenses that aren't conflicting with
another copyright claim line. again. (i did this in 2008 and then
did not update all of my personal templates.)
|
| 1.1 | 16-Jan-2018 |
mrg | implement cpuctl identify for sparc and sparc64.
sparc:
- move enum vactype and struct cacheinfo into cpu.h
- move the cache flags from cpuinfo.flags into CACHEINFO.c_flags
(this allows the new cache_printf_backend() to see them.)
remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA.
- align xmpsg to 64 bytes
- move cache_print() into cache_print.h so it can be shared with
cpuctl. it only depends upon a working printf().
- if found, store the CPU node's "name" into cpu_longname. this
changes the default output to show the local CPU not the
generic CPU family. eg:
cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU
vs the generic "RT620/625" previously shown.
- for each CPU export these things:
- name
- fpuname
- mid
- cloc
- freq
- psr impl and version
- mmu impl, version, and number of contexts
- cacheinfo structure (which changed for the first time ever
with this commit.)
sparc64:
- add a minimal "cacheinfo" structure to export the i/d/e-cache
size and linesize.
- store %ver, cpu node "name" and cacheinfo in cpu_info.
- set cpu_info ver, name and cacheinfo in cpu_attach(), and
export them via sysctl, as well as CPU ID and clock freq
cpuctl:
- add identifycpu_bind() that returns false on !x86 as their
identify routines do not need to run on a particular CPU to
obtain its information, and use it to avoid trying to set
affinity when not needed.
- add sparc and sparc64 cpu identify support using the newly
exported values.
|
| 1.7 | 21-May-2019 |
mlelstv | All MSRs can only be read at privilege level 0. The exact APIC ID cannot
be determined on some AMD CPUs.
|
| 1.6 | 10-May-2019 |
mlelstv | Get CPU topology data for AMD processors.
|
| 1.5 | 01-Mar-2015 |
tnn | branches: 1.5.16;
xgetbv expects XCR0 to be speficied in %ecx, don't leave %ecx undefined
|
| 1.4 | 07-Jan-2013 |
dsl | branches: 1.4.8;
Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually identifies
the cpu is output first.
|
| 1.3 | 05-Jan-2013 |
dsl | Fix x86_identify() for amd64
|
| 1.2 | 19-Oct-2008 |
christos | branches: 1.2.18; 1.2.20; 1.2.24;
fix so that we can compile with PIC
|
| 1.1 | 05-May-2008 |
ad | branches: 1.1.4;
PR port-amd64/37461 x86 cpu dmesg output is noisy
Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.
|
| 1.1.4.2 | 18-May-2008 |
yamt | sync with head.
|
| 1.1.4.1 | 05-May-2008 |
yamt | file x86_64-asm.S was added on branch yamt-pf42 on 2008-05-18 12:36:14 +0000
|
| 1.2.24.1 | 25-Feb-2013 |
tls | resync with head
|
| 1.2.20.2 | 24-Mar-2015 |
snj | Pull up following revision(s) (requested by tnn in ticket #1266):
usr.sbin/cpuctl/arch/i386-asm.S: revision 1.4
usr.sbin/cpuctl/arch/x86_64-asm.S: revision 1.5
xgetbv expects XCR0 to be speficied in %ecx, don't leave %ecx undefined
|
| 1.2.20.1 | 16-Jan-2015 |
snj | Pull up following revision(s) (requested by msaitoh in ticket #1230):
usr.sbin/cpuctl/cpuctl.8: revisions 1.9-1.12
usr.sbin/cpuctl/cpuctl.c: revisions 1.22-1.23 and 1.25 via patch
usr.sbin/cpuctl/cpuctl.h: revision 1.5 via patch
usr.sbin/cpuctl/arch/cpuctl_i386.h: revisions 1.1-1.2
usr.sbin/cpuctl/arch/i386-asm.S: revisions 1.2-1.3
usr.sbin/cpuctl/arch/i386.c: revisions 1.34, 1.36-1.49, 1.51-1.63 via patch
usr.sbin/cpuctl/arch/x86_64-asm.S: revisions 1.3-1.4
Update cpuctl(8). Microcode and ARM related changes are not included:
- Change the i386 asm x86_identify() so it returns a value instead of
writing into global data. Fix a stack alignment fubar that would
cause a crash on a cirix 486. Refactor identify code to common setup
for normal identify and ucode identify - which was missing a
memset().
- The Intel and AMD docs (more or less) agree on how the cpuid
'extended family' and 'extended model' bits are used to create
larger values than the original 16bit value allowed for.
Calculate and save these values 'up-front' and use them throughout.
Untangle the (backwards) nested switch statement for amd 'model 15'
cpus.
- Use full model number to index name strings - a lot of 256 element
arrays don't matter in usespace.
- Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually
identifies the cpu is output first.
- Only complain about binding if we have more than 1 cpu.
- Check cpuid leaf 4 for newer Intel CPU to know the cache information.
- Support prefetch size.
- Print the highest extended info level as the basic info level.
- Update URL of AMD's web page.
- Add code to detect hypervisor. The code was based from FreeBSD and
ported by Kengo Nakahara.
- Add verbose flag.
- Add newline if ci_tsc_freq is 0 to not to break the output.
- Update Intel's processor family names and models.
- Print some more bits.
- Add shared TLB
- Add prototypes.
- Add comments.
- Make some functions static.
- Sort functions.
- KNF.
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| 1.2.18.1 | 23-Jan-2013 |
yamt | sync with head
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| 1.4.8.1 | 09-Mar-2015 |
snj | Pull up following revision(s) (requested by tnn in ticket #570):
usr.sbin/cpuctl/arch/i386-asm.S: revision 1.4
usr.sbin/cpuctl/arch/x86_64-asm.S: revision 1.5
xgetbv expects XCR0 to be speficied in %ecx, don't leave %ecx undefined
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| 1.5.16.1 | 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.1 | 05-May-2008 |
ad | branches: 1.1.4;
PR port-amd64/37461 x86 cpu dmesg output is noisy
Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.
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| 1.1.4.2 | 18-May-2008 |
yamt | sync with head.
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| 1.1.4.1 | 05-May-2008 |
yamt | file x86_64.c was added on branch yamt-pf42 on 2008-05-18 12:36:14 +0000
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