| History log of /src/usr.sbin/cpuctl/arch/cpuctl_i386.h |
| Revision | | Date | Author | Comments |
| 1.6 |
| 07-Oct-2021 |
msaitoh | Move some common functions into x86/identcpu_subr.c. No functional change.
|
| 1.5 |
| 21-Apr-2020 |
msaitoh | Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.
- If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors
can take TSC/core crystal clock ratio but core crystal clock frequency
can't be taken. Intel SDM give us the values for some processors.
- It also required to change lapic_per_second to make LAPIC timer correctly.
- Add new file x86/x86/identcpu_subr.c to share common subroutines between
kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c
will be moved to this file in future.
- Add comment to clarify.
|
| 1.4 |
| 21-May-2019 |
mlelstv | branches: 1.4.2;
All MSRs can only be read at privilege level 0. The exact APIC ID cannot
be determined on some AMD CPUs.
|
| 1.3 |
| 10-May-2019 |
mlelstv | Get CPU topology data for AMD processors.
|
| 1.2 |
| 07-Jan-2013 |
dsl | branches: 1.2.2; 1.2.6; 1.2.14; 1.2.28; 1.2.36;
Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually identifies
the cpu is output first.
|
| 1.1 |
| 05-Jan-2013 |
dsl | Change the i386 asm x86_identify() so it returns a value instead of writing
into global data.
Fix a stack alignment fubar that would cause a crash on a cirix 486.
Refactor identify code to common setup for normal identify and ucode
identify - which was missing a memset().
|
| 1.2.36.2 |
| 21-Apr-2020 |
martin | Sync with HEAD
|
| 1.2.36.1 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.2.28.2 |
| 24-Dec-2021 |
martin | Pull up the following (all via patch), requested by msaitoh in ticket #1721:
usr.sbin/cpuctl/arch/i386.c 1.118-1.119, 1.121-1.122
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.6
sys/arch/x86/x86/identcpu_subr.c 1.8-1.9
sys/arch/x86/x86/identcpu.c 1.123
sys/arch/x86/include/cacheinfo.h 1.30
sys/arch/x86/include/cpu.h 1.132
- Fix a bug that some TLB related lines were not printed.
- Fix a bug that STLB is printed as DTLB.
- If a TLB is variable sized, print the max size instead of error message.
- Cosmetic changes to improve readability.
|
| 1.2.28.1 |
| 05-Aug-2020 |
martin | Pull up the following revisions, requested by msaitoh in ticket #1585:
usr.sbin/cpuctl/Makefile 1.9
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.5
usr.sbin/cpuctl/arch/i386.c 1.111-1.113 via patch
usr.sbin/cpuctl/cpuctl.c 1.31
usr.sbin/cpuctl/cpuctl.h 1.7
sys/arch/x86/x86/identcpu_subr.c 1.1-1.7
- Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel
processors.
- Add 0xa5 and 0xa6 for Comet Lake.
- Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
ci_max_ext_cpuid to match x86/include/cpu.h. No functional change.
- Sort some entries.
- Add comment.
|
| 1.2.14.2 |
| 16-Jan-2015 |
snj | Pull up following revision(s) (requested by msaitoh in ticket #1230):
usr.sbin/cpuctl/cpuctl.8: revisions 1.9-1.12
usr.sbin/cpuctl/cpuctl.c: revisions 1.22-1.23 and 1.25 via patch
usr.sbin/cpuctl/cpuctl.h: revision 1.5 via patch
usr.sbin/cpuctl/arch/cpuctl_i386.h: revisions 1.1-1.2
usr.sbin/cpuctl/arch/i386-asm.S: revisions 1.2-1.3
usr.sbin/cpuctl/arch/i386.c: revisions 1.34, 1.36-1.49, 1.51-1.63 via patch
usr.sbin/cpuctl/arch/x86_64-asm.S: revisions 1.3-1.4
Update cpuctl(8). Microcode and ARM related changes are not included:
- Change the i386 asm x86_identify() so it returns a value instead of
writing into global data. Fix a stack alignment fubar that would
cause a crash on a cirix 486. Refactor identify code to common setup
for normal identify and ucode identify - which was missing a
memset().
- The Intel and AMD docs (more or less) agree on how the cpuid
'extended family' and 'extended model' bits are used to create
larger values than the original 16bit value allowed for.
Calculate and save these values 'up-front' and use them throughout.
Untangle the (backwards) nested switch statement for amd 'model 15'
cpus.
- Use full model number to index name strings - a lot of 256 element
arrays don't matter in usespace.
- Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually
identifies the cpu is output first.
- Only complain about binding if we have more than 1 cpu.
- Check cpuid leaf 4 for newer Intel CPU to know the cache information.
- Support prefetch size.
- Print the highest extended info level as the basic info level.
- Update URL of AMD's web page.
- Add code to detect hypervisor. The code was based from FreeBSD and
ported by Kengo Nakahara.
- Add verbose flag.
- Add newline if ci_tsc_freq is 0 to not to break the output.
- Update Intel's processor family names and models.
- Print some more bits.
- Add shared TLB
- Add prototypes.
- Add comments.
- Make some functions static.
- Sort functions.
- KNF.
|
| 1.2.14.1 |
| 07-Jan-2013 |
snj | file cpuctl_i386.h was added on branch netbsd-6 on 2015-01-16 08:32:25 +0000
|
| 1.2.6.2 |
| 25-Feb-2013 |
tls | resync with head
|
| 1.2.6.1 |
| 07-Jan-2013 |
tls | file cpuctl_i386.h was added on branch tls-maxphys on 2013-02-25 00:30:42 +0000
|
| 1.2.2.2 |
| 23-Jan-2013 |
yamt | sync with head
|
| 1.2.2.1 |
| 07-Jan-2013 |
yamt | file cpuctl_i386.h was added on branch yamt-pagecache on 2013-01-23 00:06:41 +0000
|
| 1.4.2.2 |
| 24-Dec-2021 |
martin | Pull up the following (all via patch), requested by msaitoh in ticket #1396:
usr.sbin/cpuctl/arch/i386.c 1.118-1.119, 1.121-1.122
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.6
sys/arch/x86/x86/identcpu_subr.c 1.8-1.9
sys/arch/x86/x86/identcpu.c 1.123
sys/arch/x86/include/cacheinfo.h 1.30
sys/arch/x86/include/cpu.h 1.132
- Fix a bug that some TLB related lines were not printed.
- Fix a bug that STLB is printed as DTLB.
- If a TLB is variable sized, print the max size instead of error message.
- Cosmetic changes to improve readability.
|
| 1.4.2.1 |
| 10-Jul-2020 |
martin | Pull up the following revisions (all via patch) requested by msaitoh in
ticket #995:
usr.sbin/cpuctl/Makefile 1.9
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.5
usr.sbin/cpuctl/arch/i386.c 1.111-1.113
usr.sbin/cpuctl/cpuctl.c 1.31
usr.sbin/cpuctl/cpuctl.h 1.7
sys/arch/x86/x86/identcpu_subr.c 1.1-1.7
- Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel
processors.
- Add 0xa5 and 0xa6 for Comet Lake.
- Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
ci_max_ext_cpuid to match x86/include/cpu.h. No functional change.
- Sort some entries.
- Add comment.
|
