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Lines Matching refs:phases

287 // affect the phase, starting with the earliest phases, and record which
289 phases::ID Driver::getFinalPhase(const DerivedArgList &DAL,
292 phases::ID FinalPhase;
299 FinalPhase = phases::Preprocess;
303 FinalPhase = phases::Precompile;
315 FinalPhase = phases::Compile;
319 FinalPhase = phases::Backend;
323 FinalPhase = phases::Assemble;
327 FinalPhase = phases::Link;
2390 typedef const llvm::SmallVectorImpl<phases::ID> PhasesTy;
2432 phases::ID CurPhase, phases::ID FinalPhase,
2433 PhasesTy &Phases) {
2796 phases::ID CurPhase, phases::ID FinalPhase,
2797 PhasesTy &Phases) override {
2817 if (CompileDeviceOnly || CurPhase == phases::Backend) {
2822 for (auto Ph : Phases) {
2823 // Skip the phases that were already dealt with.
2833 if (Ph == phases::Assemble)
2879 } else if (CurPhase > phases::Backend) {
2886 assert(CurPhase < phases::Backend && "Generating single CUDA "
2936 phases::ID CurPhase, phases::ID FinalPhase,
2937 PhasesTy &Phases) override {
2939 // backend and assemble phases to output LLVM IR. Except for generating
2945 assert(((CurPhase == phases::Link && Relocatable) ||
2951 if (!Relocatable && CurPhase == phases::Backend && !EmitLLVM &&
2962 // to skip the backend and assemble phases and use lld to link
2973 // compiler phases, including backend and assemble phases.
2976 C, Args, phases::Backend, CudaDeviceActions[I],
2979 C, Args, phases::Assemble, BackendAction,
3018 } else if (CurPhase == phases::Link) {
3103 phases::ID CurPhase, phases::ID FinalPhase,
3104 PhasesTy &Phases) override {
3114 if (CurPhase == phases::Link) {
3319 phases::ID CurPhase, phases::ID FinalPhase,
3320 DeviceActionBuilder::PhasesTy &Phases) {
3342 SB->getDeviceDependences(DDeps, CurPhase, FinalPhase, Phases);
3548 phases::ID FinalPhase = getFinalPhase(Args, &FinalPhaseArg);
3550 if (FinalPhase == phases::Link) {
3558 if (FinalPhase == phases::Preprocess || Args.hasArg(options::OPT__SLASH_Y_)) {
3578 phases::ID InitialPhase = PL[0];
3597 else if (InitialPhase == phases::Compile &&
3616 if (FinalPhase >= phases::Compile) {
3620 for (phases::ID Phase : types::getCompilationPhases(HeaderType))
3636 if (FinalPhase == phases::Link && LastPLSize == 1) {
3717 for (phases::ID Phase : PL) {
3726 if (Phase == phases::Link) {
3737 if (Phase == phases::IfsMerge) {
3747 if (Phase == phases::Precompile && HeaderModuleAction &&
3809 Args.hasArg(options::OPT_c) ? phases::Compile : phases::LastPhase);
3831 case phases::Compile: {
3841 case phases::IfsMerge: {
3884 Compilation &C, const ArgList &Args, phases::ID Phase, Action *Input,
3891 if (Phase == phases::Assemble && Input->getType() != types::TY_PP_Asm)
3896 case phases::Link:
3898 case phases::IfsMerge:
3900 case phases::Preprocess: {
3920 case phases::Precompile: {
3945 case phases::Compile: {
3965 case phases::Backend: {
3981 case phases::Assemble: