Lines Matching refs:X86
25 #include "X86.h"
52 #define DEBUG_TYPE "x86-codegen"
84 StringRef getPassName() const override { return "X86 FP Stackifier"; }
131 static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums");
132 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
133 Mask |= 1 << (Reg - X86::FP0);
195 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
202 /// getSTReg - Return the X86::ST(i) register which contains the specified
205 return StackTop - 1 - getSlot(RegNo) + X86::ST0;
241 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
251 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
295 return X86::RFP80RegClass.contains(DstReg) ||
296 X86::RFP80RegClass.contains(SrcReg);
305 INITIALIZE_PASS_BEGIN(FPS, DEBUG_TYPE, "X86 FP Stackifier",
308 INITIALIZE_PASS_END(FPS, DEBUG_TYPE, "X86 FP Stackifier",
313 /// getFPReg - Return the X86::FPx register number for the specified operand.
314 /// For example, this returns 3 for X86::FP3.
318 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
319 return Reg - X86::FP0;
330 static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
333 if (!MRI.reg_nodbg_empty(X86::FP0 + i)) {
430 X86::RFP80RegClass.contains(MI.getOperand(0).getReg()))
472 static_assert(X86::FP7 - X86::FP0 == 7, "sequential FP regnumbers");
473 if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) {
474 LLVM_DEBUG(dbgs() << "Register FP#" << Reg - X86::FP0 << " is dead!\n");
475 freeStackSlotAfter(I, Reg-X86::FP0);
626 // concrete X86 instruction which uses the register stack.
629 { X86::ABS_Fp32 , X86::ABS_F },
630 { X86::ABS_Fp64 , X86::ABS_F },
631 { X86::ABS_Fp80 , X86::ABS_F },
632 { X86::ADD_Fp32m , X86::ADD_F32m },
633 { X86::ADD_Fp64m , X86::ADD_F64m },
634 { X86::ADD_Fp64m32 , X86::ADD_F32m },
635 { X86::ADD_Fp80m32 , X86::ADD_F32m },
636 { X86::ADD_Fp80m64 , X86::ADD_F64m },
637 { X86::ADD_FpI16m32 , X86::ADD_FI16m },
638 { X86::ADD_FpI16m64 , X86::ADD_FI16m },
639 { X86::ADD_FpI16m80 , X86::ADD_FI16m },
640 { X86::ADD_FpI32m32 , X86::ADD_FI32m },
641 { X86::ADD_FpI32m64 , X86::ADD_FI32m },
642 { X86::ADD_FpI32m80 , X86::ADD_FI32m },
643 { X86::CHS_Fp32 , X86::CHS_F },
644 { X86::CHS_Fp64 , X86::CHS_F },
645 { X86::CHS_Fp80 , X86::CHS_F },
646 { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
647 { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
648 { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
649 { X86::CMOVB_Fp32 , X86::CMOVB_F },
650 { X86::CMOVB_Fp64 , X86::CMOVB_F },
651 { X86::CMOVB_Fp80 , X86::CMOVB_F },
652 { X86::CMOVE_Fp32 , X86::CMOVE_F },
653 { X86::CMOVE_Fp64 , X86::CMOVE_F },
654 { X86::CMOVE_Fp80 , X86::CMOVE_F },
655 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
656 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
657 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
658 { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
659 { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
660 { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
661 { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
662 { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
663 { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
664 { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
665 { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
666 { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
667 { X86::CMOVP_Fp32 , X86::CMOVP_F },
668 { X86::CMOVP_Fp64 , X86::CMOVP_F },
669 { X86::CMOVP_Fp80 , X86::CMOVP_F },
670 { X86::COM_FpIr32 , X86::COM_FIr },
671 { X86::COM_FpIr64 , X86::COM_FIr },
672 { X86::COM_FpIr80 , X86::COM_FIr },
673 { X86::COM_Fpr32 , X86::COM_FST0r },
674 { X86::COM_Fpr64 , X86::COM_FST0r },
675 { X86::COM_Fpr80 , X86::COM_FST0r },
676 { X86::DIVR_Fp32m , X86::DIVR_F32m },
677 { X86::DIVR_Fp64m , X86::DIVR_F64m },
678 { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
679 { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
680 { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
681 { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
682 { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
683 { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
684 { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
685 { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
686 { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
687 { X86::DIV_Fp32m , X86::DIV_F32m },
688 { X86::DIV_Fp64m , X86::DIV_F64m },
689 { X86::DIV_Fp64m32 , X86::DIV_F32m },
690 { X86::DIV_Fp80m32 , X86::DIV_F32m },
691 { X86::DIV_Fp80m64 , X86::DIV_F64m },
692 { X86::DIV_FpI16m32 , X86::DIV_FI16m },
693 { X86::DIV_FpI16m64 , X86::DIV_FI16m },
694 { X86::DIV_FpI16m80 , X86::DIV_FI16m },
695 { X86::DIV_FpI32m32 , X86::DIV_FI32m },
696 { X86::DIV_FpI32m64 , X86::DIV_FI32m },
697 { X86::DIV_FpI32m80 , X86::DIV_FI32m },
698 { X86::ILD_Fp16m32 , X86::ILD_F16m },
699 { X86::ILD_Fp16m64 , X86::ILD_F16m },
700 { X86::ILD_Fp16m80 , X86::ILD_F16m },
701 { X86::ILD_Fp32m32 , X86::ILD_F32m },
702 { X86::ILD_Fp32m64 , X86::ILD_F32m },
703 { X86::ILD_Fp32m80 , X86::ILD_F32m },
704 { X86::ILD_Fp64m32 , X86::ILD_F64m },
705 { X86::ILD_Fp64m64 , X86::ILD_F64m },
706 { X86::ILD_Fp64m80 , X86::ILD_F64m },
707 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
708 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
709 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
710 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
711 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
712 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
713 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
714 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
715 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
716 { X86::IST_Fp16m32 , X86::IST_F16m },
717 { X86::IST_Fp16m64 , X86::IST_F16m },
718 { X86::IST_Fp16m80 , X86::IST_F16m },
719 { X86::IST_Fp32m32 , X86::IST_F32m },
720 { X86::IST_Fp32m64 , X86::IST_F32m },
721 { X86::IST_Fp32m80 , X86::IST_F32m },
722 { X86::IST_Fp64m32 , X86::IST_FP64m },
723 { X86::IST_Fp64m64 , X86::IST_FP64m },
724 { X86::IST_Fp64m80 , X86::IST_FP64m },
725 { X86::LD_Fp032 , X86::LD_F0 },
726 { X86::LD_Fp064 , X86::LD_F0 },
727 { X86::LD_Fp080 , X86::LD_F0 },
728 { X86::LD_Fp132 , X86::LD_F1 },
729 { X86::LD_Fp164 , X86::LD_F1 },
730 { X86::LD_Fp180 , X86::LD_F1 },
731 { X86::LD_Fp32m , X86::LD_F32m },
732 { X86::LD_Fp32m64 , X86::LD_F32m },
733 { X86::LD_Fp32m80 , X86::LD_F32m },
734 { X86::LD_Fp64m , X86::LD_F64m },
735 { X86::LD_Fp64m80 , X86::LD_F64m },
736 { X86::LD_Fp80m , X86::LD_F80m },
737 { X86::MUL_Fp32m , X86::MUL_F32m },
738 { X86::MUL_Fp64m , X86::MUL_F64m },
739 { X86::MUL_Fp64m32 , X86::MUL_F32m },
740 { X86::MUL_Fp80m32 , X86::MUL_F32m },
741 { X86::MUL_Fp80m64 , X86::MUL_F64m },
742 { X86::MUL_FpI16m32 , X86::MUL_FI16m },
743 { X86::MUL_FpI16m64 , X86::MUL_FI16m },
744 { X86::MUL_FpI16m80 , X86::MUL_FI16m },
745 { X86::MUL_FpI32m32 , X86::MUL_FI32m },
746 { X86::MUL_FpI32m64 , X86::MUL_FI32m },
747 { X86::MUL_FpI32m80 , X86::MUL_FI32m },
748 { X86::SQRT_Fp32 , X86::SQRT_F },
749 { X86::SQRT_Fp64 , X86::SQRT_F },
750 { X86::SQRT_Fp80 , X86::SQRT_F },
751 { X86::ST_Fp32m , X86::ST_F32m },
752 { X86::ST_Fp64m , X86::ST_F64m },
753 { X86::ST_Fp64m32 , X86::ST_F32m },
754 { X86::ST_Fp80m32 , X86::ST_F32m },
755 { X86::ST_Fp80m64 , X86::ST_F64m },
756 { X86::ST_FpP80m , X86::ST_FP80m },
757 { X86::SUBR_Fp32m , X86::SUBR_F32m },
758 { X86::SUBR_Fp64m , X86::SUBR_F64m },
759 { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
760 { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
761 { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
762 { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
763 { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
764 { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
765 { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
766 { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
767 { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
768 { X86::SUB_Fp32m , X86::SUB_F32m },
769 { X86::SUB_Fp64m , X86::SUB_F64m },
770 { X86::SUB_Fp64m32 , X86::SUB_F32m },
771 { X86::SUB_Fp80m32 , X86::SUB_F32m },
772 { X86::SUB_Fp80m64 , X86::SUB_F64m },
773 { X86::SUB_FpI16m32 , X86::SUB_FI16m },
774 { X86::SUB_FpI16m64 , X86::SUB_FI16m },
775 { X86::SUB_FpI16m80 , X86::SUB_FI16m },
776 { X86::SUB_FpI32m32 , X86::SUB_FI32m },
777 { X86::SUB_FpI32m64 , X86::SUB_FI32m },
778 { X86::SUB_FpI32m80 , X86::SUB_FI32m },
779 { X86::TST_Fp32 , X86::TST_F },
780 { X86::TST_Fp64 , X86::TST_F },
781 { X86::TST_Fp80 , X86::TST_F },
782 { X86::UCOM_FpIr32 , X86::UCOM_FIr },
783 { X86::UCOM_FpIr64 , X86::UCOM_FIr },
784 { X86::UCOM_FpIr80 , X86::UCOM_FIr },
785 { X86::UCOM_Fpr32 , X86::UCOM_Fr },
786 { X86::UCOM_Fpr64 , X86::UCOM_Fr },
787 { X86::UCOM_Fpr80 , X86::UCOM_Fr },
805 { X86::ADD_FrST0 , X86::ADD_FPrST0 },
807 { X86::COMP_FST0r, X86::FCOMPP },
808 { X86::COM_FIr , X86::COM_FIPr },
809 { X86::COM_FST0r , X86::COMP_FST0r },
811 { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
812 { X86::DIV_FrST0 , X86::DIV_FPrST0 },
814 { X86::IST_F16m , X86::IST_FP16m },
815 { X86::IST_F32m , X86::IST_FP32m },
817 { X86::MUL_FrST0 , X86::MUL_FPrST0 },
819 { X86::ST_F32m , X86::ST_FP32m },
820 { X86::ST_F64m , X86::ST_FP64m },
821 { X86::ST_Frr , X86::ST_FPrr },
823 { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
824 { X86::SUB_FrST0 , X86::SUB_FPrST0 },
826 { X86::UCOM_FIr , X86::UCOM_FIPr },
828 { X86::UCOM_FPr , X86::UCOM_FPPr },
829 { X86::UCOM_Fr , X86::UCOM_FPr },
849 if (Opcode == X86::FCOMPP || Opcode == X86::UCOM_FPPr)
852 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
883 return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr))
941 BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
984 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1025 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1111 MachineOperand::CreateReg(X86::ST0, /*isDef*/ true, /*isImp*/ true));
1122 assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) &&
1127 bool KillsSrc = MI.killsRegister(X86::FP0 + Reg);
1135 if (!KillsSrc && (MI.getOpcode() == X86::IST_Fp64m32 ||
1136 MI.getOpcode() == X86::ISTT_Fp16m32 ||
1137 MI.getOpcode() == X86::ISTT_Fp32m32 ||
1138 MI.getOpcode() == X86::ISTT_Fp64m32 ||
1139 MI.getOpcode() == X86::IST_Fp64m64 ||
1140 MI.getOpcode() == X86::ISTT_Fp16m64 ||
1141 MI.getOpcode() == X86::ISTT_Fp32m64 ||
1142 MI.getOpcode() == X86::ISTT_Fp64m64 ||
1143 MI.getOpcode() == X86::IST_Fp64m80 ||
1144 MI.getOpcode() == X86::ISTT_Fp16m80 ||
1145 MI.getOpcode() == X86::ISTT_Fp32m80 ||
1146 MI.getOpcode() == X86::ISTT_Fp64m80 ||
1147 MI.getOpcode() == X86::ST_FpP80m)) {
1157 MachineOperand::CreateReg(X86::ST0, /*isDef*/ false, /*isImp*/ true));
1159 if (MI.getOpcode() == X86::IST_FP64m || MI.getOpcode() == X86::ISTT_FP16m ||
1160 MI.getOpcode() == X86::ISTT_FP32m || MI.getOpcode() == X86::ISTT_FP64m ||
1161 MI.getOpcode() == X86::ST_FP80m) {
1188 bool KillsSrc = MI.killsRegister(X86::FP0 + Reg);
1217 { X86::ADD_Fp32 , X86::ADD_FST0r },
1218 { X86::ADD_Fp64 , X86::ADD_FST0r },
1219 { X86::ADD_Fp80 , X86::ADD_FST0r },
1220 { X86::DIV_Fp32 , X86::DIV_FST0r },
1221 { X86::DIV_Fp64 , X86::DIV_FST0r },
1222 { X86::DIV_Fp80 , X86::DIV_FST0r },
1223 { X86::MUL_Fp32 , X86::MUL_FST0r },
1224 { X86::MUL_Fp64 , X86::MUL_FST0r },
1225 { X86::MUL_Fp80 , X86::MUL_FST0r },
1226 { X86::SUB_Fp32 , X86::SUB_FST0r },
1227 { X86::SUB_Fp64 , X86::SUB_FST0r },
1228 { X86::SUB_Fp80 , X86::SUB_FST0r },
1233 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
1234 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
1235 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
1236 { X86::DIV_Fp32 , X86::DIVR_FST0r },
1237 { X86::DIV_Fp64 , X86::DIVR_FST0r },
1238 { X86::DIV_Fp80 , X86::DIVR_FST0r },
1239 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
1240 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
1241 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
1242 { X86::SUB_Fp32 , X86::SUBR_FST0r },
1243 { X86::SUB_Fp64 , X86::SUBR_FST0r },
1244 { X86::SUB_Fp80 , X86::SUBR_FST0r },
1249 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
1250 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
1251 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
1252 { X86::DIV_Fp32 , X86::DIVR_FrST0 },
1253 { X86::DIV_Fp64 , X86::DIVR_FrST0 },
1254 { X86::DIV_Fp80 , X86::DIVR_FrST0 },
1255 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
1256 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
1257 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
1258 { X86::SUB_Fp32 , X86::SUBR_FrST0 },
1259 { X86::SUB_Fp64 , X86::SUBR_FrST0 },
1260 { X86::SUB_Fp80 , X86::SUBR_FrST0 },
1265 { X86::ADD_Fp32 , X86::ADD_FrST0 },
1266 { X86::ADD_Fp64 , X86::ADD_FrST0 },
1267 { X86::ADD_Fp80 , X86::ADD_FrST0 },
1268 { X86::DIV_Fp32 , X86::DIV_FrST0 },
1269 { X86::DIV_Fp64 , X86::DIV_FrST0 },
1270 { X86::DIV_Fp80 , X86::DIV_FrST0 },
1271 { X86::MUL_Fp32 , X86::MUL_FrST0 },
1272 { X86::MUL_Fp64 , X86::MUL_FrST0 },
1273 { X86::MUL_Fp80 , X86::MUL_FrST0 },
1274 { X86::SUB_Fp32 , X86::SUB_FrST0 },
1275 { X86::SUB_Fp64 , X86::SUB_FrST0 },
1276 { X86::SUB_Fp80 , X86::SUB_FrST0 },
1298 bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0);
1299 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1396 bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0);
1397 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1422 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1487 unsigned Reg = MI.getOperand(0).getReg() - X86::FP0;
1489 BuildMI(*MBB, Inst, MI.getDebugLoc(), TII->get(X86::LD_F0));
1544 unsigned STReg = MO.getReg() - X86::FP0;
1613 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1642 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1652 Op.setReg(X86::ST0 + FPReg);
1711 unsigned Reg = MO.getReg() - X86::FP0;
Indexes created Wed Apr 22 00:22:44 UTC 2026