Lines Matching refs:CYCLE
47 * detector and automatic threshold corrector. Cycle crossings relative
55 * the reference carrier cycle. A type-II phase-lock loop (PLL) performs
57 * zero crossing of that cycle, which determines the reference
161 #define CYCLE 8 /* samples per bit */
174 * of the first cycle of the second. The IIR baseband filter phase delay
220 double yxing; /* cycle phase */
246 double lastenv[CYCLE]; /* last cycle amplitudes */
247 double lastint[CYCLE]; /* last integrated cycle amplitudes */
262 int pulse; /* cycle counter */
609 * amplitude and phase estimate. We keep one cycle (1 ms) of the
616 carphase = up->envphase % CYCLE;
626 up->zxing += (double)(carphase - 4) / CYCLE;
673 * Synchronous demodulator. There are eight samples in the cycle
Indexes created Sat Oct 24 00:25:45 UTC 2026