Lines Matching defs:prev_insn
2349 unsigned int prev_insn = 0;
2365 prev_insn = bfd_get_16 (abfd, contents + i - 2);
2371 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2374 /* Check if prev_insn is actually the field b of a parallel
2384 prev_op = sh_insn_info (prev_insn);
2387 prev_op = sh_insn_info (prev_insn);
2399 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2404 there is a previous instruction; PREV_INSN is not
2405 itself a load/store instruction, and PREV_INSN and
2418 /* If the instruction before PREV_INSN has a delay
2419 slot--that is, PREV_INSN is in a delay slot--we
2425 /* If the instruction before PREV_INSN is a load,
2427 putting INSN immediately after PREV_INSN will
2469 /* If PREV_INSN is a load, and it sets a register
2471 immediately after PREV_INSN will cause a pipeline
2475 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
Indexes created Sun Jul 19 00:25:04 UTC 2026